1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright 2017 NXP 3 4 /* INTMUX Block Diagram 5 * 6 * ________________ 7 * interrupt source # 0 +---->| | 8 * | | | 9 * interrupt source # 1 +++-->| | 10 * ... | | | channel # 0 |--------->interrupt out # 0 11 * ... | | | | 12 * ... | | | | 13 * interrupt source # X-1 +++-->|________________| 14 * | | | 15 * | | | 16 * | | | ________________ 17 * +---->| | 18 * | | | | | 19 * | +-->| | 20 * | | | | channel # 1 |--------->interrupt out # 1 21 * | | +>| | 22 * | | | | | 23 * | | | |________________| 24 * | | | 25 * | | | 26 * | | | ... 27 * | | | ... 28 * | | | 29 * | | | ________________ 30 * +---->| | 31 * | | | | 32 * +-->| | 33 * | | channel # N |--------->interrupt out # N 34 * +>| | 35 * | | 36 * |________________| 37 * 38 * 39 * N: Interrupt Channel Instance Number (N=7) 40 * X: Interrupt Source Number for each channel (X=32) 41 * 42 * The INTMUX interrupt multiplexer has 8 channels, each channel receives 32 43 * interrupt sources and generates 1 interrupt output. 44 * 45 */ 46 47 #include <linux/clk.h> 48 #include <linux/interrupt.h> 49 #include <linux/irq.h> 50 #include <linux/irqchip/chained_irq.h> 51 #include <linux/irqdomain.h> 52 #include <linux/kernel.h> 53 #include <linux/of_irq.h> 54 #include <linux/of_platform.h> 55 #include <linux/spinlock.h> 56 #include <linux/pm_runtime.h> 57 58 #define CHANIER(n) (0x10 + (0x40 * n)) 59 #define CHANIPR(n) (0x20 + (0x40 * n)) 60 61 #define CHAN_MAX_NUM 0x8 62 63 struct intmux_irqchip_data { 64 u32 saved_reg; 65 int chanidx; 66 int irq; 67 struct irq_domain *domain; 68 }; 69 70 struct intmux_data { 71 raw_spinlock_t lock; 72 void __iomem *regs; 73 struct clk *ipg_clk; 74 int channum; 75 struct intmux_irqchip_data irqchip_data[]; 76 }; 77 78 static void imx_intmux_irq_mask(struct irq_data *d) 79 { 80 struct intmux_irqchip_data *irqchip_data = d->chip_data; 81 int idx = irqchip_data->chanidx; 82 struct intmux_data *data = container_of(irqchip_data, struct intmux_data, 83 irqchip_data[idx]); 84 unsigned long flags; 85 void __iomem *reg; 86 u32 val; 87 88 raw_spin_lock_irqsave(&data->lock, flags); 89 reg = data->regs + CHANIER(idx); 90 val = readl_relaxed(reg); 91 /* disable the interrupt source of this channel */ 92 val &= ~BIT(d->hwirq); 93 writel_relaxed(val, reg); 94 raw_spin_unlock_irqrestore(&data->lock, flags); 95 } 96 97 static void imx_intmux_irq_unmask(struct irq_data *d) 98 { 99 struct intmux_irqchip_data *irqchip_data = d->chip_data; 100 int idx = irqchip_data->chanidx; 101 struct intmux_data *data = container_of(irqchip_data, struct intmux_data, 102 irqchip_data[idx]); 103 unsigned long flags; 104 void __iomem *reg; 105 u32 val; 106 107 raw_spin_lock_irqsave(&data->lock, flags); 108 reg = data->regs + CHANIER(idx); 109 val = readl_relaxed(reg); 110 /* enable the interrupt source of this channel */ 111 val |= BIT(d->hwirq); 112 writel_relaxed(val, reg); 113 raw_spin_unlock_irqrestore(&data->lock, flags); 114 } 115 116 static struct irq_chip imx_intmux_irq_chip __ro_after_init = { 117 .name = "intmux", 118 .irq_mask = imx_intmux_irq_mask, 119 .irq_unmask = imx_intmux_irq_unmask, 120 }; 121 122 static int imx_intmux_irq_map(struct irq_domain *h, unsigned int irq, 123 irq_hw_number_t hwirq) 124 { 125 struct intmux_irqchip_data *data = h->host_data; 126 127 irq_set_chip_data(irq, data); 128 irq_set_chip_and_handler(irq, &imx_intmux_irq_chip, handle_level_irq); 129 130 return 0; 131 } 132 133 static int imx_intmux_irq_xlate(struct irq_domain *d, struct device_node *node, 134 const u32 *intspec, unsigned int intsize, 135 unsigned long *out_hwirq, unsigned int *out_type) 136 { 137 struct intmux_irqchip_data *irqchip_data = d->host_data; 138 int idx = irqchip_data->chanidx; 139 struct intmux_data *data = container_of(irqchip_data, struct intmux_data, 140 irqchip_data[idx]); 141 142 /* 143 * two cells needed in interrupt specifier: 144 * the 1st cell: hw interrupt number 145 * the 2nd cell: channel index 146 */ 147 if (WARN_ON(intsize != 2)) 148 return -EINVAL; 149 150 if (WARN_ON(intspec[1] >= data->channum)) 151 return -EINVAL; 152 153 *out_hwirq = intspec[0]; 154 *out_type = IRQ_TYPE_LEVEL_HIGH; 155 156 return 0; 157 } 158 159 static int imx_intmux_irq_select(struct irq_domain *d, struct irq_fwspec *fwspec, 160 enum irq_domain_bus_token bus_token) 161 { 162 struct intmux_irqchip_data *irqchip_data = d->host_data; 163 164 /* Not for us */ 165 if (fwspec->fwnode != d->fwnode) 166 return false; 167 168 return irqchip_data->chanidx == fwspec->param[1]; 169 } 170 171 static const struct irq_domain_ops imx_intmux_domain_ops = { 172 .map = imx_intmux_irq_map, 173 .xlate = imx_intmux_irq_xlate, 174 .select = imx_intmux_irq_select, 175 }; 176 177 static void imx_intmux_irq_handler(struct irq_desc *desc) 178 { 179 struct intmux_irqchip_data *irqchip_data = irq_desc_get_handler_data(desc); 180 int idx = irqchip_data->chanidx; 181 struct intmux_data *data = container_of(irqchip_data, struct intmux_data, 182 irqchip_data[idx]); 183 unsigned long irqstat; 184 int pos; 185 186 chained_irq_enter(irq_desc_get_chip(desc), desc); 187 188 /* read the interrupt source pending status of this channel */ 189 irqstat = readl_relaxed(data->regs + CHANIPR(idx)); 190 191 for_each_set_bit(pos, &irqstat, 32) 192 generic_handle_domain_irq(irqchip_data->domain, pos); 193 194 chained_irq_exit(irq_desc_get_chip(desc), desc); 195 } 196 197 static int imx_intmux_probe(struct platform_device *pdev) 198 { 199 struct device_node *np = pdev->dev.of_node; 200 struct irq_domain *domain; 201 struct intmux_data *data; 202 int channum; 203 int i, ret; 204 205 channum = platform_irq_count(pdev); 206 if (channum == -EPROBE_DEFER) { 207 return -EPROBE_DEFER; 208 } else if (channum > CHAN_MAX_NUM) { 209 dev_err(&pdev->dev, "supports up to %d multiplex channels\n", 210 CHAN_MAX_NUM); 211 return -EINVAL; 212 } 213 214 data = devm_kzalloc(&pdev->dev, struct_size(data, irqchip_data, channum), GFP_KERNEL); 215 if (!data) 216 return -ENOMEM; 217 218 data->regs = devm_platform_ioremap_resource(pdev, 0); 219 if (IS_ERR(data->regs)) { 220 dev_err(&pdev->dev, "failed to initialize reg\n"); 221 return PTR_ERR(data->regs); 222 } 223 224 data->ipg_clk = devm_clk_get(&pdev->dev, "ipg"); 225 if (IS_ERR(data->ipg_clk)) 226 return dev_err_probe(&pdev->dev, PTR_ERR(data->ipg_clk), 227 "failed to get ipg clk\n"); 228 229 data->channum = channum; 230 raw_spin_lock_init(&data->lock); 231 232 pm_runtime_get_noresume(&pdev->dev); 233 pm_runtime_set_active(&pdev->dev); 234 pm_runtime_enable(&pdev->dev); 235 236 ret = clk_prepare_enable(data->ipg_clk); 237 if (ret) { 238 dev_err(&pdev->dev, "failed to enable ipg clk: %d\n", ret); 239 return ret; 240 } 241 242 for (i = 0; i < channum; i++) { 243 data->irqchip_data[i].chanidx = i; 244 245 data->irqchip_data[i].irq = irq_of_parse_and_map(np, i); 246 if (data->irqchip_data[i].irq <= 0) { 247 ret = -EINVAL; 248 dev_err(&pdev->dev, "failed to get irq\n"); 249 goto out; 250 } 251 252 domain = irq_domain_add_linear(np, 32, &imx_intmux_domain_ops, 253 &data->irqchip_data[i]); 254 if (!domain) { 255 ret = -ENOMEM; 256 dev_err(&pdev->dev, "failed to create IRQ domain\n"); 257 goto out; 258 } 259 data->irqchip_data[i].domain = domain; 260 irq_domain_set_pm_device(domain, &pdev->dev); 261 262 /* disable all interrupt sources of this channel firstly */ 263 writel_relaxed(0, data->regs + CHANIER(i)); 264 265 irq_set_chained_handler_and_data(data->irqchip_data[i].irq, 266 imx_intmux_irq_handler, 267 &data->irqchip_data[i]); 268 } 269 270 platform_set_drvdata(pdev, data); 271 272 /* 273 * Let pm_runtime_put() disable clock. 274 * If CONFIG_PM is not enabled, the clock will stay powered. 275 */ 276 pm_runtime_put(&pdev->dev); 277 278 return 0; 279 out: 280 clk_disable_unprepare(data->ipg_clk); 281 return ret; 282 } 283 284 static int imx_intmux_remove(struct platform_device *pdev) 285 { 286 struct intmux_data *data = platform_get_drvdata(pdev); 287 int i; 288 289 for (i = 0; i < data->channum; i++) { 290 /* disable all interrupt sources of this channel */ 291 writel_relaxed(0, data->regs + CHANIER(i)); 292 293 irq_set_chained_handler_and_data(data->irqchip_data[i].irq, 294 NULL, NULL); 295 296 irq_domain_remove(data->irqchip_data[i].domain); 297 } 298 299 pm_runtime_disable(&pdev->dev); 300 301 return 0; 302 } 303 304 #ifdef CONFIG_PM 305 static int imx_intmux_runtime_suspend(struct device *dev) 306 { 307 struct intmux_data *data = dev_get_drvdata(dev); 308 struct intmux_irqchip_data *irqchip_data; 309 int i; 310 311 for (i = 0; i < data->channum; i++) { 312 irqchip_data = &data->irqchip_data[i]; 313 irqchip_data->saved_reg = readl_relaxed(data->regs + CHANIER(i)); 314 } 315 316 clk_disable_unprepare(data->ipg_clk); 317 318 return 0; 319 } 320 321 static int imx_intmux_runtime_resume(struct device *dev) 322 { 323 struct intmux_data *data = dev_get_drvdata(dev); 324 struct intmux_irqchip_data *irqchip_data; 325 int ret, i; 326 327 ret = clk_prepare_enable(data->ipg_clk); 328 if (ret) { 329 dev_err(dev, "failed to enable ipg clk: %d\n", ret); 330 return ret; 331 } 332 333 for (i = 0; i < data->channum; i++) { 334 irqchip_data = &data->irqchip_data[i]; 335 writel_relaxed(irqchip_data->saved_reg, data->regs + CHANIER(i)); 336 } 337 338 return 0; 339 } 340 #endif 341 342 static const struct dev_pm_ops imx_intmux_pm_ops = { 343 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 344 pm_runtime_force_resume) 345 SET_RUNTIME_PM_OPS(imx_intmux_runtime_suspend, 346 imx_intmux_runtime_resume, NULL) 347 }; 348 349 static const struct of_device_id imx_intmux_id[] = { 350 { .compatible = "fsl,imx-intmux", }, 351 { /* sentinel */ }, 352 }; 353 354 static struct platform_driver imx_intmux_driver = { 355 .driver = { 356 .name = "imx-intmux", 357 .of_match_table = imx_intmux_id, 358 .pm = &imx_intmux_pm_ops, 359 }, 360 .probe = imx_intmux_probe, 361 .remove = imx_intmux_remove, 362 }; 363 builtin_platform_driver(imx_intmux_driver); 364