1 /* 2 * Copyright (C) 2002 ARM Limited, All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 * Interrupt architecture for the GIC: 9 * 10 * o There is one Interrupt Distributor, which receives interrupts 11 * from system devices and sends them to the Interrupt Controllers. 12 * 13 * o There is one CPU Interface per CPU, which sends interrupts sent 14 * by the Distributor, and interrupts generated locally, to the 15 * associated CPU. The base address of the CPU interface is usually 16 * aliased so that the same address points to different chips depending 17 * on the CPU it is accessed from. 18 * 19 * Note that IRQs 0-31 are special - they are local to each CPU. 20 * As such, the enable set/clear, pending set/clear and active bit 21 * registers are banked per-cpu for these sources. 22 */ 23 #include <linux/init.h> 24 #include <linux/kernel.h> 25 #include <linux/err.h> 26 #include <linux/module.h> 27 #include <linux/list.h> 28 #include <linux/smp.h> 29 #include <linux/cpu.h> 30 #include <linux/cpu_pm.h> 31 #include <linux/cpumask.h> 32 #include <linux/io.h> 33 #include <linux/of.h> 34 #include <linux/of_address.h> 35 #include <linux/of_irq.h> 36 #include <linux/irqdomain.h> 37 #include <linux/interrupt.h> 38 #include <linux/percpu.h> 39 #include <linux/slab.h> 40 #include <linux/irqchip/chained_irq.h> 41 #include <linux/irqchip/arm-gic.h> 42 43 #include <asm/cputype.h> 44 #include <asm/irq.h> 45 #include <asm/exception.h> 46 #include <asm/smp_plat.h> 47 48 #include "irq-gic-common.h" 49 #include "irqchip.h" 50 51 union gic_base { 52 void __iomem *common_base; 53 void __percpu * __iomem *percpu_base; 54 }; 55 56 struct gic_chip_data { 57 union gic_base dist_base; 58 union gic_base cpu_base; 59 #ifdef CONFIG_CPU_PM 60 u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)]; 61 u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)]; 62 u32 saved_spi_target[DIV_ROUND_UP(1020, 4)]; 63 u32 __percpu *saved_ppi_enable; 64 u32 __percpu *saved_ppi_conf; 65 #endif 66 struct irq_domain *domain; 67 unsigned int gic_irqs; 68 #ifdef CONFIG_GIC_NON_BANKED 69 void __iomem *(*get_base)(union gic_base *); 70 #endif 71 }; 72 73 static DEFINE_RAW_SPINLOCK(irq_controller_lock); 74 75 /* 76 * The GIC mapping of CPU interfaces does not necessarily match 77 * the logical CPU numbering. Let's use a mapping as returned 78 * by the GIC itself. 79 */ 80 #define NR_GIC_CPU_IF 8 81 static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly; 82 83 /* 84 * Supported arch specific GIC irq extension. 85 * Default make them NULL. 86 */ 87 struct irq_chip gic_arch_extn = { 88 .irq_eoi = NULL, 89 .irq_mask = NULL, 90 .irq_unmask = NULL, 91 .irq_retrigger = NULL, 92 .irq_set_type = NULL, 93 .irq_set_wake = NULL, 94 }; 95 96 #ifndef MAX_GIC_NR 97 #define MAX_GIC_NR 1 98 #endif 99 100 static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly; 101 102 #ifdef CONFIG_GIC_NON_BANKED 103 static void __iomem *gic_get_percpu_base(union gic_base *base) 104 { 105 return raw_cpu_read(*base->percpu_base); 106 } 107 108 static void __iomem *gic_get_common_base(union gic_base *base) 109 { 110 return base->common_base; 111 } 112 113 static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data) 114 { 115 return data->get_base(&data->dist_base); 116 } 117 118 static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data) 119 { 120 return data->get_base(&data->cpu_base); 121 } 122 123 static inline void gic_set_base_accessor(struct gic_chip_data *data, 124 void __iomem *(*f)(union gic_base *)) 125 { 126 data->get_base = f; 127 } 128 #else 129 #define gic_data_dist_base(d) ((d)->dist_base.common_base) 130 #define gic_data_cpu_base(d) ((d)->cpu_base.common_base) 131 #define gic_set_base_accessor(d, f) 132 #endif 133 134 static inline void __iomem *gic_dist_base(struct irq_data *d) 135 { 136 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); 137 return gic_data_dist_base(gic_data); 138 } 139 140 static inline void __iomem *gic_cpu_base(struct irq_data *d) 141 { 142 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); 143 return gic_data_cpu_base(gic_data); 144 } 145 146 static inline unsigned int gic_irq(struct irq_data *d) 147 { 148 return d->hwirq; 149 } 150 151 /* 152 * Routines to acknowledge, disable and enable interrupts 153 */ 154 static void gic_mask_irq(struct irq_data *d) 155 { 156 u32 mask = 1 << (gic_irq(d) % 32); 157 unsigned long flags; 158 159 raw_spin_lock_irqsave(&irq_controller_lock, flags); 160 writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4); 161 if (gic_arch_extn.irq_mask) 162 gic_arch_extn.irq_mask(d); 163 raw_spin_unlock_irqrestore(&irq_controller_lock, flags); 164 } 165 166 static void gic_unmask_irq(struct irq_data *d) 167 { 168 u32 mask = 1 << (gic_irq(d) % 32); 169 unsigned long flags; 170 171 raw_spin_lock_irqsave(&irq_controller_lock, flags); 172 if (gic_arch_extn.irq_unmask) 173 gic_arch_extn.irq_unmask(d); 174 writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4); 175 raw_spin_unlock_irqrestore(&irq_controller_lock, flags); 176 } 177 178 static void gic_eoi_irq(struct irq_data *d) 179 { 180 if (gic_arch_extn.irq_eoi) { 181 raw_spin_lock(&irq_controller_lock); 182 gic_arch_extn.irq_eoi(d); 183 raw_spin_unlock(&irq_controller_lock); 184 } 185 186 writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI); 187 } 188 189 static int gic_set_type(struct irq_data *d, unsigned int type) 190 { 191 void __iomem *base = gic_dist_base(d); 192 unsigned int gicirq = gic_irq(d); 193 unsigned long flags; 194 int ret; 195 196 /* Interrupt configuration for SGIs can't be changed */ 197 if (gicirq < 16) 198 return -EINVAL; 199 200 /* SPIs have restrictions on the supported types */ 201 if (gicirq >= 32 && type != IRQ_TYPE_LEVEL_HIGH && 202 type != IRQ_TYPE_EDGE_RISING) 203 return -EINVAL; 204 205 raw_spin_lock_irqsave(&irq_controller_lock, flags); 206 207 if (gic_arch_extn.irq_set_type) 208 gic_arch_extn.irq_set_type(d, type); 209 210 ret = gic_configure_irq(gicirq, type, base, NULL); 211 212 raw_spin_unlock_irqrestore(&irq_controller_lock, flags); 213 214 return ret; 215 } 216 217 static int gic_retrigger(struct irq_data *d) 218 { 219 if (gic_arch_extn.irq_retrigger) 220 return gic_arch_extn.irq_retrigger(d); 221 222 /* the genirq layer expects 0 if we can't retrigger in hardware */ 223 return 0; 224 } 225 226 #ifdef CONFIG_SMP 227 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, 228 bool force) 229 { 230 void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3); 231 unsigned int cpu, shift = (gic_irq(d) % 4) * 8; 232 u32 val, mask, bit; 233 unsigned long flags; 234 235 if (!force) 236 cpu = cpumask_any_and(mask_val, cpu_online_mask); 237 else 238 cpu = cpumask_first(mask_val); 239 240 if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids) 241 return -EINVAL; 242 243 raw_spin_lock_irqsave(&irq_controller_lock, flags); 244 mask = 0xff << shift; 245 bit = gic_cpu_map[cpu] << shift; 246 val = readl_relaxed(reg) & ~mask; 247 writel_relaxed(val | bit, reg); 248 raw_spin_unlock_irqrestore(&irq_controller_lock, flags); 249 250 return IRQ_SET_MASK_OK; 251 } 252 #endif 253 254 #ifdef CONFIG_PM 255 static int gic_set_wake(struct irq_data *d, unsigned int on) 256 { 257 int ret = -ENXIO; 258 259 if (gic_arch_extn.irq_set_wake) 260 ret = gic_arch_extn.irq_set_wake(d, on); 261 262 return ret; 263 } 264 265 #else 266 #define gic_set_wake NULL 267 #endif 268 269 static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) 270 { 271 u32 irqstat, irqnr; 272 struct gic_chip_data *gic = &gic_data[0]; 273 void __iomem *cpu_base = gic_data_cpu_base(gic); 274 275 do { 276 irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK); 277 irqnr = irqstat & GICC_IAR_INT_ID_MASK; 278 279 if (likely(irqnr > 15 && irqnr < 1021)) { 280 handle_domain_irq(gic->domain, irqnr, regs); 281 continue; 282 } 283 if (irqnr < 16) { 284 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); 285 #ifdef CONFIG_SMP 286 handle_IPI(irqnr, regs); 287 #endif 288 continue; 289 } 290 break; 291 } while (1); 292 } 293 294 static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) 295 { 296 struct gic_chip_data *chip_data = irq_get_handler_data(irq); 297 struct irq_chip *chip = irq_get_chip(irq); 298 unsigned int cascade_irq, gic_irq; 299 unsigned long status; 300 301 chained_irq_enter(chip, desc); 302 303 raw_spin_lock(&irq_controller_lock); 304 status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK); 305 raw_spin_unlock(&irq_controller_lock); 306 307 gic_irq = (status & GICC_IAR_INT_ID_MASK); 308 if (gic_irq == GICC_INT_SPURIOUS) 309 goto out; 310 311 cascade_irq = irq_find_mapping(chip_data->domain, gic_irq); 312 if (unlikely(gic_irq < 32 || gic_irq > 1020)) 313 handle_bad_irq(cascade_irq, desc); 314 else 315 generic_handle_irq(cascade_irq); 316 317 out: 318 chained_irq_exit(chip, desc); 319 } 320 321 static struct irq_chip gic_chip = { 322 .name = "GIC", 323 .irq_mask = gic_mask_irq, 324 .irq_unmask = gic_unmask_irq, 325 .irq_eoi = gic_eoi_irq, 326 .irq_set_type = gic_set_type, 327 .irq_retrigger = gic_retrigger, 328 #ifdef CONFIG_SMP 329 .irq_set_affinity = gic_set_affinity, 330 #endif 331 .irq_set_wake = gic_set_wake, 332 }; 333 334 void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq) 335 { 336 if (gic_nr >= MAX_GIC_NR) 337 BUG(); 338 if (irq_set_handler_data(irq, &gic_data[gic_nr]) != 0) 339 BUG(); 340 irq_set_chained_handler(irq, gic_handle_cascade_irq); 341 } 342 343 static u8 gic_get_cpumask(struct gic_chip_data *gic) 344 { 345 void __iomem *base = gic_data_dist_base(gic); 346 u32 mask, i; 347 348 for (i = mask = 0; i < 32; i += 4) { 349 mask = readl_relaxed(base + GIC_DIST_TARGET + i); 350 mask |= mask >> 16; 351 mask |= mask >> 8; 352 if (mask) 353 break; 354 } 355 356 if (!mask) 357 pr_crit("GIC CPU mask not found - kernel will fail to boot.\n"); 358 359 return mask; 360 } 361 362 static void gic_cpu_if_up(void) 363 { 364 void __iomem *cpu_base = gic_data_cpu_base(&gic_data[0]); 365 u32 bypass = 0; 366 367 /* 368 * Preserve bypass disable bits to be written back later 369 */ 370 bypass = readl(cpu_base + GIC_CPU_CTRL); 371 bypass &= GICC_DIS_BYPASS_MASK; 372 373 writel_relaxed(bypass | GICC_ENABLE, cpu_base + GIC_CPU_CTRL); 374 } 375 376 377 static void __init gic_dist_init(struct gic_chip_data *gic) 378 { 379 unsigned int i; 380 u32 cpumask; 381 unsigned int gic_irqs = gic->gic_irqs; 382 void __iomem *base = gic_data_dist_base(gic); 383 384 writel_relaxed(GICD_DISABLE, base + GIC_DIST_CTRL); 385 386 /* 387 * Set all global interrupts to this CPU only. 388 */ 389 cpumask = gic_get_cpumask(gic); 390 cpumask |= cpumask << 8; 391 cpumask |= cpumask << 16; 392 for (i = 32; i < gic_irqs; i += 4) 393 writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4); 394 395 gic_dist_config(base, gic_irqs, NULL); 396 397 writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL); 398 } 399 400 static void gic_cpu_init(struct gic_chip_data *gic) 401 { 402 void __iomem *dist_base = gic_data_dist_base(gic); 403 void __iomem *base = gic_data_cpu_base(gic); 404 unsigned int cpu_mask, cpu = smp_processor_id(); 405 int i; 406 407 /* 408 * Get what the GIC says our CPU mask is. 409 */ 410 BUG_ON(cpu >= NR_GIC_CPU_IF); 411 cpu_mask = gic_get_cpumask(gic); 412 gic_cpu_map[cpu] = cpu_mask; 413 414 /* 415 * Clear our mask from the other map entries in case they're 416 * still undefined. 417 */ 418 for (i = 0; i < NR_GIC_CPU_IF; i++) 419 if (i != cpu) 420 gic_cpu_map[i] &= ~cpu_mask; 421 422 gic_cpu_config(dist_base, NULL); 423 424 writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK); 425 gic_cpu_if_up(); 426 } 427 428 void gic_cpu_if_down(void) 429 { 430 void __iomem *cpu_base = gic_data_cpu_base(&gic_data[0]); 431 u32 val = 0; 432 433 val = readl(cpu_base + GIC_CPU_CTRL); 434 val &= ~GICC_ENABLE; 435 writel_relaxed(val, cpu_base + GIC_CPU_CTRL); 436 } 437 438 #ifdef CONFIG_CPU_PM 439 /* 440 * Saves the GIC distributor registers during suspend or idle. Must be called 441 * with interrupts disabled but before powering down the GIC. After calling 442 * this function, no interrupts will be delivered by the GIC, and another 443 * platform-specific wakeup source must be enabled. 444 */ 445 static void gic_dist_save(unsigned int gic_nr) 446 { 447 unsigned int gic_irqs; 448 void __iomem *dist_base; 449 int i; 450 451 if (gic_nr >= MAX_GIC_NR) 452 BUG(); 453 454 gic_irqs = gic_data[gic_nr].gic_irqs; 455 dist_base = gic_data_dist_base(&gic_data[gic_nr]); 456 457 if (!dist_base) 458 return; 459 460 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) 461 gic_data[gic_nr].saved_spi_conf[i] = 462 readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); 463 464 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) 465 gic_data[gic_nr].saved_spi_target[i] = 466 readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4); 467 468 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) 469 gic_data[gic_nr].saved_spi_enable[i] = 470 readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); 471 } 472 473 /* 474 * Restores the GIC distributor registers during resume or when coming out of 475 * idle. Must be called before enabling interrupts. If a level interrupt 476 * that occured while the GIC was suspended is still present, it will be 477 * handled normally, but any edge interrupts that occured will not be seen by 478 * the GIC and need to be handled by the platform-specific wakeup source. 479 */ 480 static void gic_dist_restore(unsigned int gic_nr) 481 { 482 unsigned int gic_irqs; 483 unsigned int i; 484 void __iomem *dist_base; 485 486 if (gic_nr >= MAX_GIC_NR) 487 BUG(); 488 489 gic_irqs = gic_data[gic_nr].gic_irqs; 490 dist_base = gic_data_dist_base(&gic_data[gic_nr]); 491 492 if (!dist_base) 493 return; 494 495 writel_relaxed(GICD_DISABLE, dist_base + GIC_DIST_CTRL); 496 497 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) 498 writel_relaxed(gic_data[gic_nr].saved_spi_conf[i], 499 dist_base + GIC_DIST_CONFIG + i * 4); 500 501 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) 502 writel_relaxed(GICD_INT_DEF_PRI_X4, 503 dist_base + GIC_DIST_PRI + i * 4); 504 505 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) 506 writel_relaxed(gic_data[gic_nr].saved_spi_target[i], 507 dist_base + GIC_DIST_TARGET + i * 4); 508 509 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) 510 writel_relaxed(gic_data[gic_nr].saved_spi_enable[i], 511 dist_base + GIC_DIST_ENABLE_SET + i * 4); 512 513 writel_relaxed(GICD_ENABLE, dist_base + GIC_DIST_CTRL); 514 } 515 516 static void gic_cpu_save(unsigned int gic_nr) 517 { 518 int i; 519 u32 *ptr; 520 void __iomem *dist_base; 521 void __iomem *cpu_base; 522 523 if (gic_nr >= MAX_GIC_NR) 524 BUG(); 525 526 dist_base = gic_data_dist_base(&gic_data[gic_nr]); 527 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); 528 529 if (!dist_base || !cpu_base) 530 return; 531 532 ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_enable); 533 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) 534 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); 535 536 ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_conf); 537 for (i = 0; i < DIV_ROUND_UP(32, 16); i++) 538 ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); 539 540 } 541 542 static void gic_cpu_restore(unsigned int gic_nr) 543 { 544 int i; 545 u32 *ptr; 546 void __iomem *dist_base; 547 void __iomem *cpu_base; 548 549 if (gic_nr >= MAX_GIC_NR) 550 BUG(); 551 552 dist_base = gic_data_dist_base(&gic_data[gic_nr]); 553 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); 554 555 if (!dist_base || !cpu_base) 556 return; 557 558 ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_enable); 559 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) 560 writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4); 561 562 ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_conf); 563 for (i = 0; i < DIV_ROUND_UP(32, 16); i++) 564 writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4); 565 566 for (i = 0; i < DIV_ROUND_UP(32, 4); i++) 567 writel_relaxed(GICD_INT_DEF_PRI_X4, 568 dist_base + GIC_DIST_PRI + i * 4); 569 570 writel_relaxed(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK); 571 gic_cpu_if_up(); 572 } 573 574 static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v) 575 { 576 int i; 577 578 for (i = 0; i < MAX_GIC_NR; i++) { 579 #ifdef CONFIG_GIC_NON_BANKED 580 /* Skip over unused GICs */ 581 if (!gic_data[i].get_base) 582 continue; 583 #endif 584 switch (cmd) { 585 case CPU_PM_ENTER: 586 gic_cpu_save(i); 587 break; 588 case CPU_PM_ENTER_FAILED: 589 case CPU_PM_EXIT: 590 gic_cpu_restore(i); 591 break; 592 case CPU_CLUSTER_PM_ENTER: 593 gic_dist_save(i); 594 break; 595 case CPU_CLUSTER_PM_ENTER_FAILED: 596 case CPU_CLUSTER_PM_EXIT: 597 gic_dist_restore(i); 598 break; 599 } 600 } 601 602 return NOTIFY_OK; 603 } 604 605 static struct notifier_block gic_notifier_block = { 606 .notifier_call = gic_notifier, 607 }; 608 609 static void __init gic_pm_init(struct gic_chip_data *gic) 610 { 611 gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4, 612 sizeof(u32)); 613 BUG_ON(!gic->saved_ppi_enable); 614 615 gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4, 616 sizeof(u32)); 617 BUG_ON(!gic->saved_ppi_conf); 618 619 if (gic == &gic_data[0]) 620 cpu_pm_register_notifier(&gic_notifier_block); 621 } 622 #else 623 static void __init gic_pm_init(struct gic_chip_data *gic) 624 { 625 } 626 #endif 627 628 #ifdef CONFIG_SMP 629 static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) 630 { 631 int cpu; 632 unsigned long flags, map = 0; 633 634 raw_spin_lock_irqsave(&irq_controller_lock, flags); 635 636 /* Convert our logical CPU mask into a physical one. */ 637 for_each_cpu(cpu, mask) 638 map |= gic_cpu_map[cpu]; 639 640 /* 641 * Ensure that stores to Normal memory are visible to the 642 * other CPUs before they observe us issuing the IPI. 643 */ 644 dmb(ishst); 645 646 /* this always happens on GIC0 */ 647 writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); 648 649 raw_spin_unlock_irqrestore(&irq_controller_lock, flags); 650 } 651 #endif 652 653 #ifdef CONFIG_BL_SWITCHER 654 /* 655 * gic_send_sgi - send a SGI directly to given CPU interface number 656 * 657 * cpu_id: the ID for the destination CPU interface 658 * irq: the IPI number to send a SGI for 659 */ 660 void gic_send_sgi(unsigned int cpu_id, unsigned int irq) 661 { 662 BUG_ON(cpu_id >= NR_GIC_CPU_IF); 663 cpu_id = 1 << cpu_id; 664 /* this always happens on GIC0 */ 665 writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); 666 } 667 668 /* 669 * gic_get_cpu_id - get the CPU interface ID for the specified CPU 670 * 671 * @cpu: the logical CPU number to get the GIC ID for. 672 * 673 * Return the CPU interface ID for the given logical CPU number, 674 * or -1 if the CPU number is too large or the interface ID is 675 * unknown (more than one bit set). 676 */ 677 int gic_get_cpu_id(unsigned int cpu) 678 { 679 unsigned int cpu_bit; 680 681 if (cpu >= NR_GIC_CPU_IF) 682 return -1; 683 cpu_bit = gic_cpu_map[cpu]; 684 if (cpu_bit & (cpu_bit - 1)) 685 return -1; 686 return __ffs(cpu_bit); 687 } 688 689 /* 690 * gic_migrate_target - migrate IRQs to another CPU interface 691 * 692 * @new_cpu_id: the CPU target ID to migrate IRQs to 693 * 694 * Migrate all peripheral interrupts with a target matching the current CPU 695 * to the interface corresponding to @new_cpu_id. The CPU interface mapping 696 * is also updated. Targets to other CPU interfaces are unchanged. 697 * This must be called with IRQs locally disabled. 698 */ 699 void gic_migrate_target(unsigned int new_cpu_id) 700 { 701 unsigned int cur_cpu_id, gic_irqs, gic_nr = 0; 702 void __iomem *dist_base; 703 int i, ror_val, cpu = smp_processor_id(); 704 u32 val, cur_target_mask, active_mask; 705 706 if (gic_nr >= MAX_GIC_NR) 707 BUG(); 708 709 dist_base = gic_data_dist_base(&gic_data[gic_nr]); 710 if (!dist_base) 711 return; 712 gic_irqs = gic_data[gic_nr].gic_irqs; 713 714 cur_cpu_id = __ffs(gic_cpu_map[cpu]); 715 cur_target_mask = 0x01010101 << cur_cpu_id; 716 ror_val = (cur_cpu_id - new_cpu_id) & 31; 717 718 raw_spin_lock(&irq_controller_lock); 719 720 /* Update the target interface for this logical CPU */ 721 gic_cpu_map[cpu] = 1 << new_cpu_id; 722 723 /* 724 * Find all the peripheral interrupts targetting the current 725 * CPU interface and migrate them to the new CPU interface. 726 * We skip DIST_TARGET 0 to 7 as they are read-only. 727 */ 728 for (i = 8; i < DIV_ROUND_UP(gic_irqs, 4); i++) { 729 val = readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4); 730 active_mask = val & cur_target_mask; 731 if (active_mask) { 732 val &= ~active_mask; 733 val |= ror32(active_mask, ror_val); 734 writel_relaxed(val, dist_base + GIC_DIST_TARGET + i*4); 735 } 736 } 737 738 raw_spin_unlock(&irq_controller_lock); 739 740 /* 741 * Now let's migrate and clear any potential SGIs that might be 742 * pending for us (cur_cpu_id). Since GIC_DIST_SGI_PENDING_SET 743 * is a banked register, we can only forward the SGI using 744 * GIC_DIST_SOFTINT. The original SGI source is lost but Linux 745 * doesn't use that information anyway. 746 * 747 * For the same reason we do not adjust SGI source information 748 * for previously sent SGIs by us to other CPUs either. 749 */ 750 for (i = 0; i < 16; i += 4) { 751 int j; 752 val = readl_relaxed(dist_base + GIC_DIST_SGI_PENDING_SET + i); 753 if (!val) 754 continue; 755 writel_relaxed(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i); 756 for (j = i; j < i + 4; j++) { 757 if (val & 0xff) 758 writel_relaxed((1 << (new_cpu_id + 16)) | j, 759 dist_base + GIC_DIST_SOFTINT); 760 val >>= 8; 761 } 762 } 763 } 764 765 /* 766 * gic_get_sgir_physaddr - get the physical address for the SGI register 767 * 768 * REturn the physical address of the SGI register to be used 769 * by some early assembly code when the kernel is not yet available. 770 */ 771 static unsigned long gic_dist_physaddr; 772 773 unsigned long gic_get_sgir_physaddr(void) 774 { 775 if (!gic_dist_physaddr) 776 return 0; 777 return gic_dist_physaddr + GIC_DIST_SOFTINT; 778 } 779 780 void __init gic_init_physaddr(struct device_node *node) 781 { 782 struct resource res; 783 if (of_address_to_resource(node, 0, &res) == 0) { 784 gic_dist_physaddr = res.start; 785 pr_info("GIC physical location is %#lx\n", gic_dist_physaddr); 786 } 787 } 788 789 #else 790 #define gic_init_physaddr(node) do { } while (0) 791 #endif 792 793 static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, 794 irq_hw_number_t hw) 795 { 796 if (hw < 32) { 797 irq_set_percpu_devid(irq); 798 irq_domain_set_info(d, irq, hw, &gic_chip, d->host_data, 799 handle_percpu_devid_irq, NULL, NULL); 800 set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN); 801 } else { 802 irq_domain_set_info(d, irq, hw, &gic_chip, d->host_data, 803 handle_fasteoi_irq, NULL, NULL); 804 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 805 806 gic_routable_irq_domain_ops->map(d, irq, hw); 807 } 808 return 0; 809 } 810 811 static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq) 812 { 813 gic_routable_irq_domain_ops->unmap(d, irq); 814 } 815 816 static int gic_irq_domain_xlate(struct irq_domain *d, 817 struct device_node *controller, 818 const u32 *intspec, unsigned int intsize, 819 unsigned long *out_hwirq, unsigned int *out_type) 820 { 821 unsigned long ret = 0; 822 823 if (d->of_node != controller) 824 return -EINVAL; 825 if (intsize < 3) 826 return -EINVAL; 827 828 /* Get the interrupt number and add 16 to skip over SGIs */ 829 *out_hwirq = intspec[1] + 16; 830 831 /* For SPIs, we need to add 16 more to get the GIC irq ID number */ 832 if (!intspec[0]) { 833 ret = gic_routable_irq_domain_ops->xlate(d, controller, 834 intspec, 835 intsize, 836 out_hwirq, 837 out_type); 838 839 if (IS_ERR_VALUE(ret)) 840 return ret; 841 } 842 843 *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK; 844 845 return ret; 846 } 847 848 #ifdef CONFIG_SMP 849 static int gic_secondary_init(struct notifier_block *nfb, unsigned long action, 850 void *hcpu) 851 { 852 if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) 853 gic_cpu_init(&gic_data[0]); 854 return NOTIFY_OK; 855 } 856 857 /* 858 * Notifier for enabling the GIC CPU interface. Set an arbitrarily high 859 * priority because the GIC needs to be up before the ARM generic timers. 860 */ 861 static struct notifier_block gic_cpu_notifier = { 862 .notifier_call = gic_secondary_init, 863 .priority = 100, 864 }; 865 #endif 866 867 static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 868 unsigned int nr_irqs, void *arg) 869 { 870 int i, ret; 871 irq_hw_number_t hwirq; 872 unsigned int type = IRQ_TYPE_NONE; 873 struct of_phandle_args *irq_data = arg; 874 875 ret = gic_irq_domain_xlate(domain, irq_data->np, irq_data->args, 876 irq_data->args_count, &hwirq, &type); 877 if (ret) 878 return ret; 879 880 for (i = 0; i < nr_irqs; i++) 881 gic_irq_domain_map(domain, virq + i, hwirq + i); 882 883 return 0; 884 } 885 886 static const struct irq_domain_ops gic_irq_domain_hierarchy_ops = { 887 .xlate = gic_irq_domain_xlate, 888 .alloc = gic_irq_domain_alloc, 889 .free = irq_domain_free_irqs_top, 890 }; 891 892 static const struct irq_domain_ops gic_irq_domain_ops = { 893 .map = gic_irq_domain_map, 894 .unmap = gic_irq_domain_unmap, 895 .xlate = gic_irq_domain_xlate, 896 }; 897 898 /* Default functions for routable irq domain */ 899 static int gic_routable_irq_domain_map(struct irq_domain *d, unsigned int irq, 900 irq_hw_number_t hw) 901 { 902 return 0; 903 } 904 905 static void gic_routable_irq_domain_unmap(struct irq_domain *d, 906 unsigned int irq) 907 { 908 } 909 910 static int gic_routable_irq_domain_xlate(struct irq_domain *d, 911 struct device_node *controller, 912 const u32 *intspec, unsigned int intsize, 913 unsigned long *out_hwirq, 914 unsigned int *out_type) 915 { 916 *out_hwirq += 16; 917 return 0; 918 } 919 920 static const struct irq_domain_ops gic_default_routable_irq_domain_ops = { 921 .map = gic_routable_irq_domain_map, 922 .unmap = gic_routable_irq_domain_unmap, 923 .xlate = gic_routable_irq_domain_xlate, 924 }; 925 926 const struct irq_domain_ops *gic_routable_irq_domain_ops = 927 &gic_default_routable_irq_domain_ops; 928 929 void __init gic_init_bases(unsigned int gic_nr, int irq_start, 930 void __iomem *dist_base, void __iomem *cpu_base, 931 u32 percpu_offset, struct device_node *node) 932 { 933 irq_hw_number_t hwirq_base; 934 struct gic_chip_data *gic; 935 int gic_irqs, irq_base, i; 936 int nr_routable_irqs; 937 938 BUG_ON(gic_nr >= MAX_GIC_NR); 939 940 gic = &gic_data[gic_nr]; 941 #ifdef CONFIG_GIC_NON_BANKED 942 if (percpu_offset) { /* Frankein-GIC without banked registers... */ 943 unsigned int cpu; 944 945 gic->dist_base.percpu_base = alloc_percpu(void __iomem *); 946 gic->cpu_base.percpu_base = alloc_percpu(void __iomem *); 947 if (WARN_ON(!gic->dist_base.percpu_base || 948 !gic->cpu_base.percpu_base)) { 949 free_percpu(gic->dist_base.percpu_base); 950 free_percpu(gic->cpu_base.percpu_base); 951 return; 952 } 953 954 for_each_possible_cpu(cpu) { 955 u32 mpidr = cpu_logical_map(cpu); 956 u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); 957 unsigned long offset = percpu_offset * core_id; 958 *per_cpu_ptr(gic->dist_base.percpu_base, cpu) = dist_base + offset; 959 *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = cpu_base + offset; 960 } 961 962 gic_set_base_accessor(gic, gic_get_percpu_base); 963 } else 964 #endif 965 { /* Normal, sane GIC... */ 966 WARN(percpu_offset, 967 "GIC_NON_BANKED not enabled, ignoring %08x offset!", 968 percpu_offset); 969 gic->dist_base.common_base = dist_base; 970 gic->cpu_base.common_base = cpu_base; 971 gic_set_base_accessor(gic, gic_get_common_base); 972 } 973 974 /* 975 * Initialize the CPU interface map to all CPUs. 976 * It will be refined as each CPU probes its ID. 977 */ 978 for (i = 0; i < NR_GIC_CPU_IF; i++) 979 gic_cpu_map[i] = 0xff; 980 981 /* 982 * Find out how many interrupts are supported. 983 * The GIC only supports up to 1020 interrupt sources. 984 */ 985 gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f; 986 gic_irqs = (gic_irqs + 1) * 32; 987 if (gic_irqs > 1020) 988 gic_irqs = 1020; 989 gic->gic_irqs = gic_irqs; 990 991 if (node) { /* DT case */ 992 const struct irq_domain_ops *ops = &gic_irq_domain_hierarchy_ops; 993 994 if (!of_property_read_u32(node, "arm,routable-irqs", 995 &nr_routable_irqs)) { 996 ops = &gic_irq_domain_ops; 997 gic_irqs = nr_routable_irqs; 998 } 999 1000 gic->domain = irq_domain_add_linear(node, gic_irqs, ops, gic); 1001 } else { /* Non-DT case */ 1002 /* 1003 * For primary GICs, skip over SGIs. 1004 * For secondary GICs, skip over PPIs, too. 1005 */ 1006 if (gic_nr == 0 && (irq_start & 31) > 0) { 1007 hwirq_base = 16; 1008 if (irq_start != -1) 1009 irq_start = (irq_start & ~31) + 16; 1010 } else { 1011 hwirq_base = 32; 1012 } 1013 1014 gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */ 1015 1016 irq_base = irq_alloc_descs(irq_start, 16, gic_irqs, 1017 numa_node_id()); 1018 if (IS_ERR_VALUE(irq_base)) { 1019 WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n", 1020 irq_start); 1021 irq_base = irq_start; 1022 } 1023 1024 gic->domain = irq_domain_add_legacy(node, gic_irqs, irq_base, 1025 hwirq_base, &gic_irq_domain_ops, gic); 1026 } 1027 1028 if (WARN_ON(!gic->domain)) 1029 return; 1030 1031 if (gic_nr == 0) { 1032 #ifdef CONFIG_SMP 1033 set_smp_cross_call(gic_raise_softirq); 1034 register_cpu_notifier(&gic_cpu_notifier); 1035 #endif 1036 set_handle_irq(gic_handle_irq); 1037 } 1038 1039 gic_chip.flags |= gic_arch_extn.flags; 1040 gic_dist_init(gic); 1041 gic_cpu_init(gic); 1042 gic_pm_init(gic); 1043 } 1044 1045 #ifdef CONFIG_OF 1046 static int gic_cnt __initdata; 1047 1048 static int __init 1049 gic_of_init(struct device_node *node, struct device_node *parent) 1050 { 1051 void __iomem *cpu_base; 1052 void __iomem *dist_base; 1053 u32 percpu_offset; 1054 int irq; 1055 1056 if (WARN_ON(!node)) 1057 return -ENODEV; 1058 1059 dist_base = of_iomap(node, 0); 1060 WARN(!dist_base, "unable to map gic dist registers\n"); 1061 1062 cpu_base = of_iomap(node, 1); 1063 WARN(!cpu_base, "unable to map gic cpu registers\n"); 1064 1065 if (of_property_read_u32(node, "cpu-offset", &percpu_offset)) 1066 percpu_offset = 0; 1067 1068 gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset, node); 1069 if (!gic_cnt) 1070 gic_init_physaddr(node); 1071 1072 if (parent) { 1073 irq = irq_of_parse_and_map(node, 0); 1074 gic_cascade_irq(gic_cnt, irq); 1075 } 1076 1077 if (IS_ENABLED(CONFIG_ARM_GIC_V2M)) 1078 gicv2m_of_init(node, gic_data[gic_cnt].domain); 1079 1080 gic_cnt++; 1081 return 0; 1082 } 1083 IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init); 1084 IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init); 1085 IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init); 1086 IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init); 1087 IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init); 1088 IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init); 1089 IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init); 1090 IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init); 1091 1092 #endif 1093