1 /* 2 * Copyright (C) 2002 ARM Limited, All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 * Interrupt architecture for the GIC: 9 * 10 * o There is one Interrupt Distributor, which receives interrupts 11 * from system devices and sends them to the Interrupt Controllers. 12 * 13 * o There is one CPU Interface per CPU, which sends interrupts sent 14 * by the Distributor, and interrupts generated locally, to the 15 * associated CPU. The base address of the CPU interface is usually 16 * aliased so that the same address points to different chips depending 17 * on the CPU it is accessed from. 18 * 19 * Note that IRQs 0-31 are special - they are local to each CPU. 20 * As such, the enable set/clear, pending set/clear and active bit 21 * registers are banked per-cpu for these sources. 22 */ 23 #include <linux/init.h> 24 #include <linux/kernel.h> 25 #include <linux/err.h> 26 #include <linux/module.h> 27 #include <linux/list.h> 28 #include <linux/smp.h> 29 #include <linux/cpu.h> 30 #include <linux/cpu_pm.h> 31 #include <linux/cpumask.h> 32 #include <linux/io.h> 33 #include <linux/of.h> 34 #include <linux/of_address.h> 35 #include <linux/of_irq.h> 36 #include <linux/acpi.h> 37 #include <linux/irqdomain.h> 38 #include <linux/interrupt.h> 39 #include <linux/percpu.h> 40 #include <linux/slab.h> 41 #include <linux/irqchip.h> 42 #include <linux/irqchip/chained_irq.h> 43 #include <linux/irqchip/arm-gic.h> 44 45 #include <asm/cputype.h> 46 #include <asm/irq.h> 47 #include <asm/exception.h> 48 #include <asm/smp_plat.h> 49 #include <asm/virt.h> 50 51 #include "irq-gic-common.h" 52 53 #ifdef CONFIG_ARM64 54 #include <asm/cpufeature.h> 55 56 static void gic_check_cpu_features(void) 57 { 58 WARN_TAINT_ONCE(cpus_have_cap(ARM64_HAS_SYSREG_GIC_CPUIF), 59 TAINT_CPU_OUT_OF_SPEC, 60 "GICv3 system registers enabled, broken firmware!\n"); 61 } 62 #else 63 #define gic_check_cpu_features() do { } while(0) 64 #endif 65 66 union gic_base { 67 void __iomem *common_base; 68 void __percpu * __iomem *percpu_base; 69 }; 70 71 struct gic_chip_data { 72 struct irq_chip chip; 73 union gic_base dist_base; 74 union gic_base cpu_base; 75 #ifdef CONFIG_CPU_PM 76 u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)]; 77 u32 saved_spi_active[DIV_ROUND_UP(1020, 32)]; 78 u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)]; 79 u32 saved_spi_target[DIV_ROUND_UP(1020, 4)]; 80 u32 __percpu *saved_ppi_enable; 81 u32 __percpu *saved_ppi_active; 82 u32 __percpu *saved_ppi_conf; 83 #endif 84 struct irq_domain *domain; 85 unsigned int gic_irqs; 86 #ifdef CONFIG_GIC_NON_BANKED 87 void __iomem *(*get_base)(union gic_base *); 88 #endif 89 }; 90 91 static DEFINE_RAW_SPINLOCK(irq_controller_lock); 92 93 /* 94 * The GIC mapping of CPU interfaces does not necessarily match 95 * the logical CPU numbering. Let's use a mapping as returned 96 * by the GIC itself. 97 */ 98 #define NR_GIC_CPU_IF 8 99 static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly; 100 101 static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE; 102 103 static struct gic_chip_data gic_data[CONFIG_ARM_GIC_MAX_NR] __read_mostly; 104 105 #ifdef CONFIG_GIC_NON_BANKED 106 static void __iomem *gic_get_percpu_base(union gic_base *base) 107 { 108 return raw_cpu_read(*base->percpu_base); 109 } 110 111 static void __iomem *gic_get_common_base(union gic_base *base) 112 { 113 return base->common_base; 114 } 115 116 static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data) 117 { 118 return data->get_base(&data->dist_base); 119 } 120 121 static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data) 122 { 123 return data->get_base(&data->cpu_base); 124 } 125 126 static inline void gic_set_base_accessor(struct gic_chip_data *data, 127 void __iomem *(*f)(union gic_base *)) 128 { 129 data->get_base = f; 130 } 131 #else 132 #define gic_data_dist_base(d) ((d)->dist_base.common_base) 133 #define gic_data_cpu_base(d) ((d)->cpu_base.common_base) 134 #define gic_set_base_accessor(d, f) 135 #endif 136 137 static inline void __iomem *gic_dist_base(struct irq_data *d) 138 { 139 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); 140 return gic_data_dist_base(gic_data); 141 } 142 143 static inline void __iomem *gic_cpu_base(struct irq_data *d) 144 { 145 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); 146 return gic_data_cpu_base(gic_data); 147 } 148 149 static inline unsigned int gic_irq(struct irq_data *d) 150 { 151 return d->hwirq; 152 } 153 154 static inline bool cascading_gic_irq(struct irq_data *d) 155 { 156 void *data = irq_data_get_irq_handler_data(d); 157 158 /* 159 * If handler_data is set, this is a cascading interrupt, and 160 * it cannot possibly be forwarded. 161 */ 162 return data != NULL; 163 } 164 165 /* 166 * Routines to acknowledge, disable and enable interrupts 167 */ 168 static void gic_poke_irq(struct irq_data *d, u32 offset) 169 { 170 u32 mask = 1 << (gic_irq(d) % 32); 171 writel_relaxed(mask, gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4); 172 } 173 174 static int gic_peek_irq(struct irq_data *d, u32 offset) 175 { 176 u32 mask = 1 << (gic_irq(d) % 32); 177 return !!(readl_relaxed(gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4) & mask); 178 } 179 180 static void gic_mask_irq(struct irq_data *d) 181 { 182 gic_poke_irq(d, GIC_DIST_ENABLE_CLEAR); 183 } 184 185 static void gic_eoimode1_mask_irq(struct irq_data *d) 186 { 187 gic_mask_irq(d); 188 /* 189 * When masking a forwarded interrupt, make sure it is 190 * deactivated as well. 191 * 192 * This ensures that an interrupt that is getting 193 * disabled/masked will not get "stuck", because there is 194 * noone to deactivate it (guest is being terminated). 195 */ 196 if (irqd_is_forwarded_to_vcpu(d)) 197 gic_poke_irq(d, GIC_DIST_ACTIVE_CLEAR); 198 } 199 200 static void gic_unmask_irq(struct irq_data *d) 201 { 202 gic_poke_irq(d, GIC_DIST_ENABLE_SET); 203 } 204 205 static void gic_eoi_irq(struct irq_data *d) 206 { 207 writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI); 208 } 209 210 static void gic_eoimode1_eoi_irq(struct irq_data *d) 211 { 212 /* Do not deactivate an IRQ forwarded to a vcpu. */ 213 if (irqd_is_forwarded_to_vcpu(d)) 214 return; 215 216 writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_DEACTIVATE); 217 } 218 219 static int gic_irq_set_irqchip_state(struct irq_data *d, 220 enum irqchip_irq_state which, bool val) 221 { 222 u32 reg; 223 224 switch (which) { 225 case IRQCHIP_STATE_PENDING: 226 reg = val ? GIC_DIST_PENDING_SET : GIC_DIST_PENDING_CLEAR; 227 break; 228 229 case IRQCHIP_STATE_ACTIVE: 230 reg = val ? GIC_DIST_ACTIVE_SET : GIC_DIST_ACTIVE_CLEAR; 231 break; 232 233 case IRQCHIP_STATE_MASKED: 234 reg = val ? GIC_DIST_ENABLE_CLEAR : GIC_DIST_ENABLE_SET; 235 break; 236 237 default: 238 return -EINVAL; 239 } 240 241 gic_poke_irq(d, reg); 242 return 0; 243 } 244 245 static int gic_irq_get_irqchip_state(struct irq_data *d, 246 enum irqchip_irq_state which, bool *val) 247 { 248 switch (which) { 249 case IRQCHIP_STATE_PENDING: 250 *val = gic_peek_irq(d, GIC_DIST_PENDING_SET); 251 break; 252 253 case IRQCHIP_STATE_ACTIVE: 254 *val = gic_peek_irq(d, GIC_DIST_ACTIVE_SET); 255 break; 256 257 case IRQCHIP_STATE_MASKED: 258 *val = !gic_peek_irq(d, GIC_DIST_ENABLE_SET); 259 break; 260 261 default: 262 return -EINVAL; 263 } 264 265 return 0; 266 } 267 268 static int gic_set_type(struct irq_data *d, unsigned int type) 269 { 270 void __iomem *base = gic_dist_base(d); 271 unsigned int gicirq = gic_irq(d); 272 273 /* Interrupt configuration for SGIs can't be changed */ 274 if (gicirq < 16) 275 return -EINVAL; 276 277 /* SPIs have restrictions on the supported types */ 278 if (gicirq >= 32 && type != IRQ_TYPE_LEVEL_HIGH && 279 type != IRQ_TYPE_EDGE_RISING) 280 return -EINVAL; 281 282 return gic_configure_irq(gicirq, type, base, NULL); 283 } 284 285 static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) 286 { 287 /* Only interrupts on the primary GIC can be forwarded to a vcpu. */ 288 if (cascading_gic_irq(d)) 289 return -EINVAL; 290 291 if (vcpu) 292 irqd_set_forwarded_to_vcpu(d); 293 else 294 irqd_clr_forwarded_to_vcpu(d); 295 return 0; 296 } 297 298 #ifdef CONFIG_SMP 299 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, 300 bool force) 301 { 302 void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3); 303 unsigned int cpu, shift = (gic_irq(d) % 4) * 8; 304 u32 val, mask, bit; 305 unsigned long flags; 306 307 if (!force) 308 cpu = cpumask_any_and(mask_val, cpu_online_mask); 309 else 310 cpu = cpumask_first(mask_val); 311 312 if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids) 313 return -EINVAL; 314 315 raw_spin_lock_irqsave(&irq_controller_lock, flags); 316 mask = 0xff << shift; 317 bit = gic_cpu_map[cpu] << shift; 318 val = readl_relaxed(reg) & ~mask; 319 writel_relaxed(val | bit, reg); 320 raw_spin_unlock_irqrestore(&irq_controller_lock, flags); 321 322 return IRQ_SET_MASK_OK; 323 } 324 #endif 325 326 static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) 327 { 328 u32 irqstat, irqnr; 329 struct gic_chip_data *gic = &gic_data[0]; 330 void __iomem *cpu_base = gic_data_cpu_base(gic); 331 332 do { 333 irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK); 334 irqnr = irqstat & GICC_IAR_INT_ID_MASK; 335 336 if (likely(irqnr > 15 && irqnr < 1020)) { 337 if (static_key_true(&supports_deactivate)) 338 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); 339 handle_domain_irq(gic->domain, irqnr, regs); 340 continue; 341 } 342 if (irqnr < 16) { 343 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); 344 if (static_key_true(&supports_deactivate)) 345 writel_relaxed(irqstat, cpu_base + GIC_CPU_DEACTIVATE); 346 #ifdef CONFIG_SMP 347 handle_IPI(irqnr, regs); 348 #endif 349 continue; 350 } 351 break; 352 } while (1); 353 } 354 355 static void gic_handle_cascade_irq(struct irq_desc *desc) 356 { 357 struct gic_chip_data *chip_data = irq_desc_get_handler_data(desc); 358 struct irq_chip *chip = irq_desc_get_chip(desc); 359 unsigned int cascade_irq, gic_irq; 360 unsigned long status; 361 362 chained_irq_enter(chip, desc); 363 364 raw_spin_lock(&irq_controller_lock); 365 status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK); 366 raw_spin_unlock(&irq_controller_lock); 367 368 gic_irq = (status & GICC_IAR_INT_ID_MASK); 369 if (gic_irq == GICC_INT_SPURIOUS) 370 goto out; 371 372 cascade_irq = irq_find_mapping(chip_data->domain, gic_irq); 373 if (unlikely(gic_irq < 32 || gic_irq > 1020)) 374 handle_bad_irq(desc); 375 else 376 generic_handle_irq(cascade_irq); 377 378 out: 379 chained_irq_exit(chip, desc); 380 } 381 382 static struct irq_chip gic_chip = { 383 .irq_mask = gic_mask_irq, 384 .irq_unmask = gic_unmask_irq, 385 .irq_eoi = gic_eoi_irq, 386 .irq_set_type = gic_set_type, 387 #ifdef CONFIG_SMP 388 .irq_set_affinity = gic_set_affinity, 389 #endif 390 .irq_get_irqchip_state = gic_irq_get_irqchip_state, 391 .irq_set_irqchip_state = gic_irq_set_irqchip_state, 392 .flags = IRQCHIP_SET_TYPE_MASKED | 393 IRQCHIP_SKIP_SET_WAKE | 394 IRQCHIP_MASK_ON_SUSPEND, 395 }; 396 397 static struct irq_chip gic_eoimode1_chip = { 398 .name = "GICv2", 399 .irq_mask = gic_eoimode1_mask_irq, 400 .irq_unmask = gic_unmask_irq, 401 .irq_eoi = gic_eoimode1_eoi_irq, 402 .irq_set_type = gic_set_type, 403 #ifdef CONFIG_SMP 404 .irq_set_affinity = gic_set_affinity, 405 #endif 406 .irq_get_irqchip_state = gic_irq_get_irqchip_state, 407 .irq_set_irqchip_state = gic_irq_set_irqchip_state, 408 .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity, 409 .flags = IRQCHIP_SET_TYPE_MASKED | 410 IRQCHIP_SKIP_SET_WAKE | 411 IRQCHIP_MASK_ON_SUSPEND, 412 }; 413 414 void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq) 415 { 416 BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR); 417 irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq, 418 &gic_data[gic_nr]); 419 } 420 421 static u8 gic_get_cpumask(struct gic_chip_data *gic) 422 { 423 void __iomem *base = gic_data_dist_base(gic); 424 u32 mask, i; 425 426 for (i = mask = 0; i < 32; i += 4) { 427 mask = readl_relaxed(base + GIC_DIST_TARGET + i); 428 mask |= mask >> 16; 429 mask |= mask >> 8; 430 if (mask) 431 break; 432 } 433 434 if (!mask && num_possible_cpus() > 1) 435 pr_crit("GIC CPU mask not found - kernel will fail to boot.\n"); 436 437 return mask; 438 } 439 440 static void gic_cpu_if_up(struct gic_chip_data *gic) 441 { 442 void __iomem *cpu_base = gic_data_cpu_base(gic); 443 u32 bypass = 0; 444 u32 mode = 0; 445 446 if (static_key_true(&supports_deactivate)) 447 mode = GIC_CPU_CTRL_EOImodeNS; 448 449 /* 450 * Preserve bypass disable bits to be written back later 451 */ 452 bypass = readl(cpu_base + GIC_CPU_CTRL); 453 bypass &= GICC_DIS_BYPASS_MASK; 454 455 writel_relaxed(bypass | mode | GICC_ENABLE, cpu_base + GIC_CPU_CTRL); 456 } 457 458 459 static void __init gic_dist_init(struct gic_chip_data *gic) 460 { 461 unsigned int i; 462 u32 cpumask; 463 unsigned int gic_irqs = gic->gic_irqs; 464 void __iomem *base = gic_data_dist_base(gic); 465 466 writel_relaxed(GICD_DISABLE, base + GIC_DIST_CTRL); 467 468 /* 469 * Set all global interrupts to this CPU only. 470 */ 471 cpumask = gic_get_cpumask(gic); 472 cpumask |= cpumask << 8; 473 cpumask |= cpumask << 16; 474 for (i = 32; i < gic_irqs; i += 4) 475 writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4); 476 477 gic_dist_config(base, gic_irqs, NULL); 478 479 writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL); 480 } 481 482 static void gic_cpu_init(struct gic_chip_data *gic) 483 { 484 void __iomem *dist_base = gic_data_dist_base(gic); 485 void __iomem *base = gic_data_cpu_base(gic); 486 unsigned int cpu_mask, cpu = smp_processor_id(); 487 int i; 488 489 /* 490 * Setting up the CPU map is only relevant for the primary GIC 491 * because any nested/secondary GICs do not directly interface 492 * with the CPU(s). 493 */ 494 if (gic == &gic_data[0]) { 495 /* 496 * Get what the GIC says our CPU mask is. 497 */ 498 BUG_ON(cpu >= NR_GIC_CPU_IF); 499 cpu_mask = gic_get_cpumask(gic); 500 gic_cpu_map[cpu] = cpu_mask; 501 502 /* 503 * Clear our mask from the other map entries in case they're 504 * still undefined. 505 */ 506 for (i = 0; i < NR_GIC_CPU_IF; i++) 507 if (i != cpu) 508 gic_cpu_map[i] &= ~cpu_mask; 509 } 510 511 gic_cpu_config(dist_base, NULL); 512 513 writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK); 514 gic_cpu_if_up(gic); 515 } 516 517 int gic_cpu_if_down(unsigned int gic_nr) 518 { 519 void __iomem *cpu_base; 520 u32 val = 0; 521 522 if (gic_nr >= CONFIG_ARM_GIC_MAX_NR) 523 return -EINVAL; 524 525 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); 526 val = readl(cpu_base + GIC_CPU_CTRL); 527 val &= ~GICC_ENABLE; 528 writel_relaxed(val, cpu_base + GIC_CPU_CTRL); 529 530 return 0; 531 } 532 533 #ifdef CONFIG_CPU_PM 534 /* 535 * Saves the GIC distributor registers during suspend or idle. Must be called 536 * with interrupts disabled but before powering down the GIC. After calling 537 * this function, no interrupts will be delivered by the GIC, and another 538 * platform-specific wakeup source must be enabled. 539 */ 540 static void gic_dist_save(unsigned int gic_nr) 541 { 542 unsigned int gic_irqs; 543 void __iomem *dist_base; 544 int i; 545 546 BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR); 547 548 gic_irqs = gic_data[gic_nr].gic_irqs; 549 dist_base = gic_data_dist_base(&gic_data[gic_nr]); 550 551 if (!dist_base) 552 return; 553 554 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) 555 gic_data[gic_nr].saved_spi_conf[i] = 556 readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); 557 558 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) 559 gic_data[gic_nr].saved_spi_target[i] = 560 readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4); 561 562 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) 563 gic_data[gic_nr].saved_spi_enable[i] = 564 readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); 565 566 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) 567 gic_data[gic_nr].saved_spi_active[i] = 568 readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4); 569 } 570 571 /* 572 * Restores the GIC distributor registers during resume or when coming out of 573 * idle. Must be called before enabling interrupts. If a level interrupt 574 * that occured while the GIC was suspended is still present, it will be 575 * handled normally, but any edge interrupts that occured will not be seen by 576 * the GIC and need to be handled by the platform-specific wakeup source. 577 */ 578 static void gic_dist_restore(unsigned int gic_nr) 579 { 580 unsigned int gic_irqs; 581 unsigned int i; 582 void __iomem *dist_base; 583 584 BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR); 585 586 gic_irqs = gic_data[gic_nr].gic_irqs; 587 dist_base = gic_data_dist_base(&gic_data[gic_nr]); 588 589 if (!dist_base) 590 return; 591 592 writel_relaxed(GICD_DISABLE, dist_base + GIC_DIST_CTRL); 593 594 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) 595 writel_relaxed(gic_data[gic_nr].saved_spi_conf[i], 596 dist_base + GIC_DIST_CONFIG + i * 4); 597 598 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) 599 writel_relaxed(GICD_INT_DEF_PRI_X4, 600 dist_base + GIC_DIST_PRI + i * 4); 601 602 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) 603 writel_relaxed(gic_data[gic_nr].saved_spi_target[i], 604 dist_base + GIC_DIST_TARGET + i * 4); 605 606 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) { 607 writel_relaxed(GICD_INT_EN_CLR_X32, 608 dist_base + GIC_DIST_ENABLE_CLEAR + i * 4); 609 writel_relaxed(gic_data[gic_nr].saved_spi_enable[i], 610 dist_base + GIC_DIST_ENABLE_SET + i * 4); 611 } 612 613 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) { 614 writel_relaxed(GICD_INT_EN_CLR_X32, 615 dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4); 616 writel_relaxed(gic_data[gic_nr].saved_spi_active[i], 617 dist_base + GIC_DIST_ACTIVE_SET + i * 4); 618 } 619 620 writel_relaxed(GICD_ENABLE, dist_base + GIC_DIST_CTRL); 621 } 622 623 static void gic_cpu_save(unsigned int gic_nr) 624 { 625 int i; 626 u32 *ptr; 627 void __iomem *dist_base; 628 void __iomem *cpu_base; 629 630 BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR); 631 632 dist_base = gic_data_dist_base(&gic_data[gic_nr]); 633 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); 634 635 if (!dist_base || !cpu_base) 636 return; 637 638 ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_enable); 639 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) 640 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); 641 642 ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_active); 643 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) 644 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4); 645 646 ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_conf); 647 for (i = 0; i < DIV_ROUND_UP(32, 16); i++) 648 ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); 649 650 } 651 652 static void gic_cpu_restore(unsigned int gic_nr) 653 { 654 int i; 655 u32 *ptr; 656 void __iomem *dist_base; 657 void __iomem *cpu_base; 658 659 BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR); 660 661 dist_base = gic_data_dist_base(&gic_data[gic_nr]); 662 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); 663 664 if (!dist_base || !cpu_base) 665 return; 666 667 ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_enable); 668 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) { 669 writel_relaxed(GICD_INT_EN_CLR_X32, 670 dist_base + GIC_DIST_ENABLE_CLEAR + i * 4); 671 writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4); 672 } 673 674 ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_active); 675 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) { 676 writel_relaxed(GICD_INT_EN_CLR_X32, 677 dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4); 678 writel_relaxed(ptr[i], dist_base + GIC_DIST_ACTIVE_SET + i * 4); 679 } 680 681 ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_conf); 682 for (i = 0; i < DIV_ROUND_UP(32, 16); i++) 683 writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4); 684 685 for (i = 0; i < DIV_ROUND_UP(32, 4); i++) 686 writel_relaxed(GICD_INT_DEF_PRI_X4, 687 dist_base + GIC_DIST_PRI + i * 4); 688 689 writel_relaxed(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK); 690 gic_cpu_if_up(&gic_data[gic_nr]); 691 } 692 693 static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v) 694 { 695 int i; 696 697 for (i = 0; i < CONFIG_ARM_GIC_MAX_NR; i++) { 698 #ifdef CONFIG_GIC_NON_BANKED 699 /* Skip over unused GICs */ 700 if (!gic_data[i].get_base) 701 continue; 702 #endif 703 switch (cmd) { 704 case CPU_PM_ENTER: 705 gic_cpu_save(i); 706 break; 707 case CPU_PM_ENTER_FAILED: 708 case CPU_PM_EXIT: 709 gic_cpu_restore(i); 710 break; 711 case CPU_CLUSTER_PM_ENTER: 712 gic_dist_save(i); 713 break; 714 case CPU_CLUSTER_PM_ENTER_FAILED: 715 case CPU_CLUSTER_PM_EXIT: 716 gic_dist_restore(i); 717 break; 718 } 719 } 720 721 return NOTIFY_OK; 722 } 723 724 static struct notifier_block gic_notifier_block = { 725 .notifier_call = gic_notifier, 726 }; 727 728 static void __init gic_pm_init(struct gic_chip_data *gic) 729 { 730 gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4, 731 sizeof(u32)); 732 BUG_ON(!gic->saved_ppi_enable); 733 734 gic->saved_ppi_active = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4, 735 sizeof(u32)); 736 BUG_ON(!gic->saved_ppi_active); 737 738 gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4, 739 sizeof(u32)); 740 BUG_ON(!gic->saved_ppi_conf); 741 742 if (gic == &gic_data[0]) 743 cpu_pm_register_notifier(&gic_notifier_block); 744 } 745 #else 746 static void __init gic_pm_init(struct gic_chip_data *gic) 747 { 748 } 749 #endif 750 751 #ifdef CONFIG_SMP 752 static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) 753 { 754 int cpu; 755 unsigned long flags, map = 0; 756 757 raw_spin_lock_irqsave(&irq_controller_lock, flags); 758 759 /* Convert our logical CPU mask into a physical one. */ 760 for_each_cpu(cpu, mask) 761 map |= gic_cpu_map[cpu]; 762 763 /* 764 * Ensure that stores to Normal memory are visible to the 765 * other CPUs before they observe us issuing the IPI. 766 */ 767 dmb(ishst); 768 769 /* this always happens on GIC0 */ 770 writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); 771 772 raw_spin_unlock_irqrestore(&irq_controller_lock, flags); 773 } 774 #endif 775 776 #ifdef CONFIG_BL_SWITCHER 777 /* 778 * gic_send_sgi - send a SGI directly to given CPU interface number 779 * 780 * cpu_id: the ID for the destination CPU interface 781 * irq: the IPI number to send a SGI for 782 */ 783 void gic_send_sgi(unsigned int cpu_id, unsigned int irq) 784 { 785 BUG_ON(cpu_id >= NR_GIC_CPU_IF); 786 cpu_id = 1 << cpu_id; 787 /* this always happens on GIC0 */ 788 writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); 789 } 790 791 /* 792 * gic_get_cpu_id - get the CPU interface ID for the specified CPU 793 * 794 * @cpu: the logical CPU number to get the GIC ID for. 795 * 796 * Return the CPU interface ID for the given logical CPU number, 797 * or -1 if the CPU number is too large or the interface ID is 798 * unknown (more than one bit set). 799 */ 800 int gic_get_cpu_id(unsigned int cpu) 801 { 802 unsigned int cpu_bit; 803 804 if (cpu >= NR_GIC_CPU_IF) 805 return -1; 806 cpu_bit = gic_cpu_map[cpu]; 807 if (cpu_bit & (cpu_bit - 1)) 808 return -1; 809 return __ffs(cpu_bit); 810 } 811 812 /* 813 * gic_migrate_target - migrate IRQs to another CPU interface 814 * 815 * @new_cpu_id: the CPU target ID to migrate IRQs to 816 * 817 * Migrate all peripheral interrupts with a target matching the current CPU 818 * to the interface corresponding to @new_cpu_id. The CPU interface mapping 819 * is also updated. Targets to other CPU interfaces are unchanged. 820 * This must be called with IRQs locally disabled. 821 */ 822 void gic_migrate_target(unsigned int new_cpu_id) 823 { 824 unsigned int cur_cpu_id, gic_irqs, gic_nr = 0; 825 void __iomem *dist_base; 826 int i, ror_val, cpu = smp_processor_id(); 827 u32 val, cur_target_mask, active_mask; 828 829 BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR); 830 831 dist_base = gic_data_dist_base(&gic_data[gic_nr]); 832 if (!dist_base) 833 return; 834 gic_irqs = gic_data[gic_nr].gic_irqs; 835 836 cur_cpu_id = __ffs(gic_cpu_map[cpu]); 837 cur_target_mask = 0x01010101 << cur_cpu_id; 838 ror_val = (cur_cpu_id - new_cpu_id) & 31; 839 840 raw_spin_lock(&irq_controller_lock); 841 842 /* Update the target interface for this logical CPU */ 843 gic_cpu_map[cpu] = 1 << new_cpu_id; 844 845 /* 846 * Find all the peripheral interrupts targetting the current 847 * CPU interface and migrate them to the new CPU interface. 848 * We skip DIST_TARGET 0 to 7 as they are read-only. 849 */ 850 for (i = 8; i < DIV_ROUND_UP(gic_irqs, 4); i++) { 851 val = readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4); 852 active_mask = val & cur_target_mask; 853 if (active_mask) { 854 val &= ~active_mask; 855 val |= ror32(active_mask, ror_val); 856 writel_relaxed(val, dist_base + GIC_DIST_TARGET + i*4); 857 } 858 } 859 860 raw_spin_unlock(&irq_controller_lock); 861 862 /* 863 * Now let's migrate and clear any potential SGIs that might be 864 * pending for us (cur_cpu_id). Since GIC_DIST_SGI_PENDING_SET 865 * is a banked register, we can only forward the SGI using 866 * GIC_DIST_SOFTINT. The original SGI source is lost but Linux 867 * doesn't use that information anyway. 868 * 869 * For the same reason we do not adjust SGI source information 870 * for previously sent SGIs by us to other CPUs either. 871 */ 872 for (i = 0; i < 16; i += 4) { 873 int j; 874 val = readl_relaxed(dist_base + GIC_DIST_SGI_PENDING_SET + i); 875 if (!val) 876 continue; 877 writel_relaxed(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i); 878 for (j = i; j < i + 4; j++) { 879 if (val & 0xff) 880 writel_relaxed((1 << (new_cpu_id + 16)) | j, 881 dist_base + GIC_DIST_SOFTINT); 882 val >>= 8; 883 } 884 } 885 } 886 887 /* 888 * gic_get_sgir_physaddr - get the physical address for the SGI register 889 * 890 * REturn the physical address of the SGI register to be used 891 * by some early assembly code when the kernel is not yet available. 892 */ 893 static unsigned long gic_dist_physaddr; 894 895 unsigned long gic_get_sgir_physaddr(void) 896 { 897 if (!gic_dist_physaddr) 898 return 0; 899 return gic_dist_physaddr + GIC_DIST_SOFTINT; 900 } 901 902 void __init gic_init_physaddr(struct device_node *node) 903 { 904 struct resource res; 905 if (of_address_to_resource(node, 0, &res) == 0) { 906 gic_dist_physaddr = res.start; 907 pr_info("GIC physical location is %#lx\n", gic_dist_physaddr); 908 } 909 } 910 911 #else 912 #define gic_init_physaddr(node) do { } while (0) 913 #endif 914 915 static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, 916 irq_hw_number_t hw) 917 { 918 struct gic_chip_data *gic = d->host_data; 919 920 if (hw < 32) { 921 irq_set_percpu_devid(irq); 922 irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data, 923 handle_percpu_devid_irq, NULL, NULL); 924 irq_set_status_flags(irq, IRQ_NOAUTOEN); 925 } else { 926 irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data, 927 handle_fasteoi_irq, NULL, NULL); 928 irq_set_probe(irq); 929 } 930 return 0; 931 } 932 933 static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq) 934 { 935 } 936 937 static int gic_irq_domain_translate(struct irq_domain *d, 938 struct irq_fwspec *fwspec, 939 unsigned long *hwirq, 940 unsigned int *type) 941 { 942 if (is_of_node(fwspec->fwnode)) { 943 if (fwspec->param_count < 3) 944 return -EINVAL; 945 946 /* Get the interrupt number and add 16 to skip over SGIs */ 947 *hwirq = fwspec->param[1] + 16; 948 949 /* 950 * For SPIs, we need to add 16 more to get the GIC irq 951 * ID number 952 */ 953 if (!fwspec->param[0]) 954 *hwirq += 16; 955 956 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; 957 return 0; 958 } 959 960 if (is_fwnode_irqchip(fwspec->fwnode)) { 961 if(fwspec->param_count != 2) 962 return -EINVAL; 963 964 *hwirq = fwspec->param[0]; 965 *type = fwspec->param[1]; 966 return 0; 967 } 968 969 return -EINVAL; 970 } 971 972 #ifdef CONFIG_SMP 973 static int gic_secondary_init(struct notifier_block *nfb, unsigned long action, 974 void *hcpu) 975 { 976 if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) 977 gic_cpu_init(&gic_data[0]); 978 return NOTIFY_OK; 979 } 980 981 /* 982 * Notifier for enabling the GIC CPU interface. Set an arbitrarily high 983 * priority because the GIC needs to be up before the ARM generic timers. 984 */ 985 static struct notifier_block gic_cpu_notifier = { 986 .notifier_call = gic_secondary_init, 987 .priority = 100, 988 }; 989 #endif 990 991 static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 992 unsigned int nr_irqs, void *arg) 993 { 994 int i, ret; 995 irq_hw_number_t hwirq; 996 unsigned int type = IRQ_TYPE_NONE; 997 struct irq_fwspec *fwspec = arg; 998 999 ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type); 1000 if (ret) 1001 return ret; 1002 1003 for (i = 0; i < nr_irqs; i++) 1004 gic_irq_domain_map(domain, virq + i, hwirq + i); 1005 1006 return 0; 1007 } 1008 1009 static const struct irq_domain_ops gic_irq_domain_hierarchy_ops = { 1010 .translate = gic_irq_domain_translate, 1011 .alloc = gic_irq_domain_alloc, 1012 .free = irq_domain_free_irqs_top, 1013 }; 1014 1015 static const struct irq_domain_ops gic_irq_domain_ops = { 1016 .map = gic_irq_domain_map, 1017 .unmap = gic_irq_domain_unmap, 1018 }; 1019 1020 static void __init __gic_init_bases(unsigned int gic_nr, int irq_start, 1021 void __iomem *dist_base, void __iomem *cpu_base, 1022 u32 percpu_offset, struct fwnode_handle *handle) 1023 { 1024 irq_hw_number_t hwirq_base; 1025 struct gic_chip_data *gic; 1026 int gic_irqs, irq_base, i; 1027 1028 BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR); 1029 1030 gic_check_cpu_features(); 1031 1032 gic = &gic_data[gic_nr]; 1033 1034 /* Initialize irq_chip */ 1035 if (static_key_true(&supports_deactivate) && gic_nr == 0) { 1036 gic->chip = gic_eoimode1_chip; 1037 } else { 1038 gic->chip = gic_chip; 1039 gic->chip.name = kasprintf(GFP_KERNEL, "GIC-%d", gic_nr); 1040 } 1041 1042 #ifdef CONFIG_GIC_NON_BANKED 1043 if (percpu_offset) { /* Frankein-GIC without banked registers... */ 1044 unsigned int cpu; 1045 1046 gic->dist_base.percpu_base = alloc_percpu(void __iomem *); 1047 gic->cpu_base.percpu_base = alloc_percpu(void __iomem *); 1048 if (WARN_ON(!gic->dist_base.percpu_base || 1049 !gic->cpu_base.percpu_base)) { 1050 free_percpu(gic->dist_base.percpu_base); 1051 free_percpu(gic->cpu_base.percpu_base); 1052 return; 1053 } 1054 1055 for_each_possible_cpu(cpu) { 1056 u32 mpidr = cpu_logical_map(cpu); 1057 u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); 1058 unsigned long offset = percpu_offset * core_id; 1059 *per_cpu_ptr(gic->dist_base.percpu_base, cpu) = dist_base + offset; 1060 *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = cpu_base + offset; 1061 } 1062 1063 gic_set_base_accessor(gic, gic_get_percpu_base); 1064 } else 1065 #endif 1066 { /* Normal, sane GIC... */ 1067 WARN(percpu_offset, 1068 "GIC_NON_BANKED not enabled, ignoring %08x offset!", 1069 percpu_offset); 1070 gic->dist_base.common_base = dist_base; 1071 gic->cpu_base.common_base = cpu_base; 1072 gic_set_base_accessor(gic, gic_get_common_base); 1073 } 1074 1075 /* 1076 * Find out how many interrupts are supported. 1077 * The GIC only supports up to 1020 interrupt sources. 1078 */ 1079 gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f; 1080 gic_irqs = (gic_irqs + 1) * 32; 1081 if (gic_irqs > 1020) 1082 gic_irqs = 1020; 1083 gic->gic_irqs = gic_irqs; 1084 1085 if (handle) { /* DT/ACPI */ 1086 gic->domain = irq_domain_create_linear(handle, gic_irqs, 1087 &gic_irq_domain_hierarchy_ops, 1088 gic); 1089 } else { /* Legacy support */ 1090 /* 1091 * For primary GICs, skip over SGIs. 1092 * For secondary GICs, skip over PPIs, too. 1093 */ 1094 if (gic_nr == 0 && (irq_start & 31) > 0) { 1095 hwirq_base = 16; 1096 if (irq_start != -1) 1097 irq_start = (irq_start & ~31) + 16; 1098 } else { 1099 hwirq_base = 32; 1100 } 1101 1102 gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */ 1103 1104 irq_base = irq_alloc_descs(irq_start, 16, gic_irqs, 1105 numa_node_id()); 1106 if (IS_ERR_VALUE(irq_base)) { 1107 WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n", 1108 irq_start); 1109 irq_base = irq_start; 1110 } 1111 1112 gic->domain = irq_domain_add_legacy(NULL, gic_irqs, irq_base, 1113 hwirq_base, &gic_irq_domain_ops, gic); 1114 } 1115 1116 if (WARN_ON(!gic->domain)) 1117 return; 1118 1119 if (gic_nr == 0) { 1120 /* 1121 * Initialize the CPU interface map to all CPUs. 1122 * It will be refined as each CPU probes its ID. 1123 * This is only necessary for the primary GIC. 1124 */ 1125 for (i = 0; i < NR_GIC_CPU_IF; i++) 1126 gic_cpu_map[i] = 0xff; 1127 #ifdef CONFIG_SMP 1128 set_smp_cross_call(gic_raise_softirq); 1129 register_cpu_notifier(&gic_cpu_notifier); 1130 #endif 1131 set_handle_irq(gic_handle_irq); 1132 if (static_key_true(&supports_deactivate)) 1133 pr_info("GIC: Using split EOI/Deactivate mode\n"); 1134 } 1135 1136 gic_dist_init(gic); 1137 gic_cpu_init(gic); 1138 gic_pm_init(gic); 1139 } 1140 1141 void __init gic_init(unsigned int gic_nr, int irq_start, 1142 void __iomem *dist_base, void __iomem *cpu_base) 1143 { 1144 /* 1145 * Non-DT/ACPI systems won't run a hypervisor, so let's not 1146 * bother with these... 1147 */ 1148 static_key_slow_dec(&supports_deactivate); 1149 __gic_init_bases(gic_nr, irq_start, dist_base, cpu_base, 0, NULL); 1150 } 1151 1152 #ifdef CONFIG_OF 1153 static int gic_cnt __initdata; 1154 1155 static bool gic_check_eoimode(struct device_node *node, void __iomem **base) 1156 { 1157 struct resource cpuif_res; 1158 1159 of_address_to_resource(node, 1, &cpuif_res); 1160 1161 if (!is_hyp_mode_available()) 1162 return false; 1163 if (resource_size(&cpuif_res) < SZ_8K) 1164 return false; 1165 if (resource_size(&cpuif_res) == SZ_128K) { 1166 u32 val_low, val_high; 1167 1168 /* 1169 * Verify that we have the first 4kB of a GIC400 1170 * aliased over the first 64kB by checking the 1171 * GICC_IIDR register on both ends. 1172 */ 1173 val_low = readl_relaxed(*base + GIC_CPU_IDENT); 1174 val_high = readl_relaxed(*base + GIC_CPU_IDENT + 0xf000); 1175 if ((val_low & 0xffff0fff) != 0x0202043B || 1176 val_low != val_high) 1177 return false; 1178 1179 /* 1180 * Move the base up by 60kB, so that we have a 8kB 1181 * contiguous region, which allows us to use GICC_DIR 1182 * at its normal offset. Please pass me that bucket. 1183 */ 1184 *base += 0xf000; 1185 cpuif_res.start += 0xf000; 1186 pr_warn("GIC: Adjusting CPU interface base to %pa", 1187 &cpuif_res.start); 1188 } 1189 1190 return true; 1191 } 1192 1193 int __init 1194 gic_of_init(struct device_node *node, struct device_node *parent) 1195 { 1196 void __iomem *cpu_base; 1197 void __iomem *dist_base; 1198 u32 percpu_offset; 1199 int irq; 1200 1201 if (WARN_ON(!node)) 1202 return -ENODEV; 1203 1204 dist_base = of_iomap(node, 0); 1205 WARN(!dist_base, "unable to map gic dist registers\n"); 1206 1207 cpu_base = of_iomap(node, 1); 1208 WARN(!cpu_base, "unable to map gic cpu registers\n"); 1209 1210 /* 1211 * Disable split EOI/Deactivate if either HYP is not available 1212 * or the CPU interface is too small. 1213 */ 1214 if (gic_cnt == 0 && !gic_check_eoimode(node, &cpu_base)) 1215 static_key_slow_dec(&supports_deactivate); 1216 1217 if (of_property_read_u32(node, "cpu-offset", &percpu_offset)) 1218 percpu_offset = 0; 1219 1220 __gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset, 1221 &node->fwnode); 1222 if (!gic_cnt) 1223 gic_init_physaddr(node); 1224 1225 if (parent) { 1226 irq = irq_of_parse_and_map(node, 0); 1227 gic_cascade_irq(gic_cnt, irq); 1228 } 1229 1230 if (IS_ENABLED(CONFIG_ARM_GIC_V2M)) 1231 gicv2m_init(&node->fwnode, gic_data[gic_cnt].domain); 1232 1233 gic_cnt++; 1234 return 0; 1235 } 1236 IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init); 1237 IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init); 1238 IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init); 1239 IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init); 1240 IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init); 1241 IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init); 1242 IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init); 1243 IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init); 1244 IRQCHIP_DECLARE(pl390, "arm,pl390", gic_of_init); 1245 1246 #endif 1247 1248 #ifdef CONFIG_ACPI 1249 static phys_addr_t cpu_phy_base __initdata; 1250 1251 static int __init 1252 gic_acpi_parse_madt_cpu(struct acpi_subtable_header *header, 1253 const unsigned long end) 1254 { 1255 struct acpi_madt_generic_interrupt *processor; 1256 phys_addr_t gic_cpu_base; 1257 static int cpu_base_assigned; 1258 1259 processor = (struct acpi_madt_generic_interrupt *)header; 1260 1261 if (BAD_MADT_GICC_ENTRY(processor, end)) 1262 return -EINVAL; 1263 1264 /* 1265 * There is no support for non-banked GICv1/2 register in ACPI spec. 1266 * All CPU interface addresses have to be the same. 1267 */ 1268 gic_cpu_base = processor->base_address; 1269 if (cpu_base_assigned && gic_cpu_base != cpu_phy_base) 1270 return -EINVAL; 1271 1272 cpu_phy_base = gic_cpu_base; 1273 cpu_base_assigned = 1; 1274 return 0; 1275 } 1276 1277 /* The things you have to do to just *count* something... */ 1278 static int __init acpi_dummy_func(struct acpi_subtable_header *header, 1279 const unsigned long end) 1280 { 1281 return 0; 1282 } 1283 1284 static bool __init acpi_gic_redist_is_present(void) 1285 { 1286 return acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, 1287 acpi_dummy_func, 0) > 0; 1288 } 1289 1290 static bool __init gic_validate_dist(struct acpi_subtable_header *header, 1291 struct acpi_probe_entry *ape) 1292 { 1293 struct acpi_madt_generic_distributor *dist; 1294 dist = (struct acpi_madt_generic_distributor *)header; 1295 1296 return (dist->version == ape->driver_data && 1297 (dist->version != ACPI_MADT_GIC_VERSION_NONE || 1298 !acpi_gic_redist_is_present())); 1299 } 1300 1301 #define ACPI_GICV2_DIST_MEM_SIZE (SZ_4K) 1302 #define ACPI_GIC_CPU_IF_MEM_SIZE (SZ_8K) 1303 1304 static int __init gic_v2_acpi_init(struct acpi_subtable_header *header, 1305 const unsigned long end) 1306 { 1307 struct acpi_madt_generic_distributor *dist; 1308 void __iomem *cpu_base, *dist_base; 1309 struct fwnode_handle *domain_handle; 1310 int count; 1311 1312 /* Collect CPU base addresses */ 1313 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, 1314 gic_acpi_parse_madt_cpu, 0); 1315 if (count <= 0) { 1316 pr_err("No valid GICC entries exist\n"); 1317 return -EINVAL; 1318 } 1319 1320 cpu_base = ioremap(cpu_phy_base, ACPI_GIC_CPU_IF_MEM_SIZE); 1321 if (!cpu_base) { 1322 pr_err("Unable to map GICC registers\n"); 1323 return -ENOMEM; 1324 } 1325 1326 dist = (struct acpi_madt_generic_distributor *)header; 1327 dist_base = ioremap(dist->base_address, ACPI_GICV2_DIST_MEM_SIZE); 1328 if (!dist_base) { 1329 pr_err("Unable to map GICD registers\n"); 1330 iounmap(cpu_base); 1331 return -ENOMEM; 1332 } 1333 1334 /* 1335 * Disable split EOI/Deactivate if HYP is not available. ACPI 1336 * guarantees that we'll always have a GICv2, so the CPU 1337 * interface will always be the right size. 1338 */ 1339 if (!is_hyp_mode_available()) 1340 static_key_slow_dec(&supports_deactivate); 1341 1342 /* 1343 * Initialize GIC instance zero (no multi-GIC support). 1344 */ 1345 domain_handle = irq_domain_alloc_fwnode(dist_base); 1346 if (!domain_handle) { 1347 pr_err("Unable to allocate domain handle\n"); 1348 iounmap(cpu_base); 1349 iounmap(dist_base); 1350 return -ENOMEM; 1351 } 1352 1353 __gic_init_bases(0, -1, dist_base, cpu_base, 0, domain_handle); 1354 1355 acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle); 1356 1357 if (IS_ENABLED(CONFIG_ARM_GIC_V2M)) 1358 gicv2m_init(NULL, gic_data[0].domain); 1359 1360 return 0; 1361 } 1362 IRQCHIP_ACPI_DECLARE(gic_v2, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1363 gic_validate_dist, ACPI_MADT_GIC_VERSION_V2, 1364 gic_v2_acpi_init); 1365 IRQCHIP_ACPI_DECLARE(gic_v2_maybe, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1366 gic_validate_dist, ACPI_MADT_GIC_VERSION_NONE, 1367 gic_v2_acpi_init); 1368 #endif 1369