1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved. 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 */ 6 7 #define pr_fmt(fmt) "GICv3: " fmt 8 9 #include <linux/acpi.h> 10 #include <linux/cpu.h> 11 #include <linux/cpu_pm.h> 12 #include <linux/delay.h> 13 #include <linux/interrupt.h> 14 #include <linux/irqdomain.h> 15 #include <linux/kstrtox.h> 16 #include <linux/of.h> 17 #include <linux/of_address.h> 18 #include <linux/of_irq.h> 19 #include <linux/percpu.h> 20 #include <linux/refcount.h> 21 #include <linux/slab.h> 22 23 #include <linux/irqchip.h> 24 #include <linux/irqchip/arm-gic-common.h> 25 #include <linux/irqchip/arm-gic-v3.h> 26 #include <linux/irqchip/irq-partition-percpu.h> 27 #include <linux/bitfield.h> 28 #include <linux/bits.h> 29 #include <linux/arm-smccc.h> 30 31 #include <asm/cputype.h> 32 #include <asm/exception.h> 33 #include <asm/smp_plat.h> 34 #include <asm/virt.h> 35 36 #include "irq-gic-common.h" 37 38 #define GICD_INT_NMI_PRI (GICD_INT_DEF_PRI & ~0x80) 39 40 #define FLAGS_WORKAROUND_GICR_WAKER_MSM8996 (1ULL << 0) 41 #define FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539 (1ULL << 1) 42 #define FLAGS_WORKAROUND_MTK_GICR_SAVE (1ULL << 2) 43 #define FLAGS_WORKAROUND_ASR_ERRATUM_8601001 (1ULL << 3) 44 45 #define GIC_IRQ_TYPE_PARTITION (GIC_IRQ_TYPE_LPI + 1) 46 47 struct redist_region { 48 void __iomem *redist_base; 49 phys_addr_t phys_base; 50 bool single_redist; 51 }; 52 53 struct gic_chip_data { 54 struct fwnode_handle *fwnode; 55 phys_addr_t dist_phys_base; 56 void __iomem *dist_base; 57 struct redist_region *redist_regions; 58 struct rdists rdists; 59 struct irq_domain *domain; 60 u64 redist_stride; 61 u32 nr_redist_regions; 62 u64 flags; 63 bool has_rss; 64 unsigned int ppi_nr; 65 struct partition_desc **ppi_descs; 66 }; 67 68 #define T241_CHIPS_MAX 4 69 static void __iomem *t241_dist_base_alias[T241_CHIPS_MAX] __read_mostly; 70 static DEFINE_STATIC_KEY_FALSE(gic_nvidia_t241_erratum); 71 72 static DEFINE_STATIC_KEY_FALSE(gic_arm64_2941627_erratum); 73 74 static struct gic_chip_data gic_data __read_mostly; 75 static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key); 76 77 #define GIC_ID_NR (1U << GICD_TYPER_ID_BITS(gic_data.rdists.gicd_typer)) 78 #define GIC_LINE_NR min(GICD_TYPER_SPIS(gic_data.rdists.gicd_typer), 1020U) 79 #define GIC_ESPI_NR GICD_TYPER_ESPIS(gic_data.rdists.gicd_typer) 80 81 /* 82 * There are 16 SGIs, though we only actually use 8 in Linux. The other 8 SGIs 83 * are potentially stolen by the secure side. Some code, especially code dealing 84 * with hwirq IDs, is simplified by accounting for all 16. 85 */ 86 #define SGI_NR 16 87 88 /* 89 * The behaviours of RPR and PMR registers differ depending on the value of 90 * SCR_EL3.FIQ, and the behaviour of non-secure priority registers of the 91 * distributor and redistributors depends on whether security is enabled in the 92 * GIC. 93 * 94 * When security is enabled, non-secure priority values from the (re)distributor 95 * are presented to the GIC CPUIF as follow: 96 * (GIC_(R)DIST_PRI[irq] >> 1) | 0x80; 97 * 98 * If SCR_EL3.FIQ == 1, the values written to/read from PMR and RPR at non-secure 99 * EL1 are subject to a similar operation thus matching the priorities presented 100 * from the (re)distributor when security is enabled. When SCR_EL3.FIQ == 0, 101 * these values are unchanged by the GIC. 102 * 103 * see GICv3/GICv4 Architecture Specification (IHI0069D): 104 * - section 4.8.1 Non-secure accesses to register fields for Secure interrupt 105 * priorities. 106 * - Figure 4-7 Secure read of the priority field for a Non-secure Group 1 107 * interrupt. 108 */ 109 DEFINE_STATIC_KEY_FALSE(supports_pseudo_nmis); 110 111 DEFINE_STATIC_KEY_FALSE(gic_nonsecure_priorities); 112 EXPORT_SYMBOL(gic_nonsecure_priorities); 113 114 /* 115 * When the Non-secure world has access to group 0 interrupts (as a 116 * consequence of SCR_EL3.FIQ == 0), reading the ICC_RPR_EL1 register will 117 * return the Distributor's view of the interrupt priority. 118 * 119 * When GIC security is enabled (GICD_CTLR.DS == 0), the interrupt priority 120 * written by software is moved to the Non-secure range by the Distributor. 121 * 122 * If both are true (which is when gic_nonsecure_priorities gets enabled), 123 * we need to shift down the priority programmed by software to match it 124 * against the value returned by ICC_RPR_EL1. 125 */ 126 #define GICD_INT_RPR_PRI(priority) \ 127 ({ \ 128 u32 __priority = (priority); \ 129 if (static_branch_unlikely(&gic_nonsecure_priorities)) \ 130 __priority = 0x80 | (__priority >> 1); \ 131 \ 132 __priority; \ 133 }) 134 135 /* rdist_nmi_refs[n] == number of cpus having the rdist interrupt n set as NMI */ 136 static refcount_t *rdist_nmi_refs; 137 138 static struct gic_kvm_info gic_v3_kvm_info __initdata; 139 static DEFINE_PER_CPU(bool, has_rss); 140 141 #define MPIDR_RS(mpidr) (((mpidr) & 0xF0UL) >> 4) 142 #define gic_data_rdist() (this_cpu_ptr(gic_data.rdists.rdist)) 143 #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) 144 #define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K) 145 146 /* Our default, arbitrary priority value. Linux only uses one anyway. */ 147 #define DEFAULT_PMR_VALUE 0xf0 148 149 enum gic_intid_range { 150 SGI_RANGE, 151 PPI_RANGE, 152 SPI_RANGE, 153 EPPI_RANGE, 154 ESPI_RANGE, 155 LPI_RANGE, 156 __INVALID_RANGE__ 157 }; 158 159 static enum gic_intid_range __get_intid_range(irq_hw_number_t hwirq) 160 { 161 switch (hwirq) { 162 case 0 ... 15: 163 return SGI_RANGE; 164 case 16 ... 31: 165 return PPI_RANGE; 166 case 32 ... 1019: 167 return SPI_RANGE; 168 case EPPI_BASE_INTID ... (EPPI_BASE_INTID + 63): 169 return EPPI_RANGE; 170 case ESPI_BASE_INTID ... (ESPI_BASE_INTID + 1023): 171 return ESPI_RANGE; 172 case 8192 ... GENMASK(23, 0): 173 return LPI_RANGE; 174 default: 175 return __INVALID_RANGE__; 176 } 177 } 178 179 static enum gic_intid_range get_intid_range(struct irq_data *d) 180 { 181 return __get_intid_range(d->hwirq); 182 } 183 184 static inline unsigned int gic_irq(struct irq_data *d) 185 { 186 return d->hwirq; 187 } 188 189 static inline bool gic_irq_in_rdist(struct irq_data *d) 190 { 191 switch (get_intid_range(d)) { 192 case SGI_RANGE: 193 case PPI_RANGE: 194 case EPPI_RANGE: 195 return true; 196 default: 197 return false; 198 } 199 } 200 201 static inline void __iomem *gic_dist_base_alias(struct irq_data *d) 202 { 203 if (static_branch_unlikely(&gic_nvidia_t241_erratum)) { 204 irq_hw_number_t hwirq = irqd_to_hwirq(d); 205 u32 chip; 206 207 /* 208 * For the erratum T241-FABRIC-4, read accesses to GICD_In{E} 209 * registers are directed to the chip that owns the SPI. The 210 * the alias region can also be used for writes to the 211 * GICD_In{E} except GICD_ICENABLERn. Each chip has support 212 * for 320 {E}SPIs. Mappings for all 4 chips: 213 * Chip0 = 32-351 214 * Chip1 = 352-671 215 * Chip2 = 672-991 216 * Chip3 = 4096-4415 217 */ 218 switch (__get_intid_range(hwirq)) { 219 case SPI_RANGE: 220 chip = (hwirq - 32) / 320; 221 break; 222 case ESPI_RANGE: 223 chip = 3; 224 break; 225 default: 226 unreachable(); 227 } 228 return t241_dist_base_alias[chip]; 229 } 230 231 return gic_data.dist_base; 232 } 233 234 static inline void __iomem *gic_dist_base(struct irq_data *d) 235 { 236 switch (get_intid_range(d)) { 237 case SGI_RANGE: 238 case PPI_RANGE: 239 case EPPI_RANGE: 240 /* SGI+PPI -> SGI_base for this CPU */ 241 return gic_data_rdist_sgi_base(); 242 243 case SPI_RANGE: 244 case ESPI_RANGE: 245 /* SPI -> dist_base */ 246 return gic_data.dist_base; 247 248 default: 249 return NULL; 250 } 251 } 252 253 static void gic_do_wait_for_rwp(void __iomem *base, u32 bit) 254 { 255 u32 count = 1000000; /* 1s! */ 256 257 while (readl_relaxed(base + GICD_CTLR) & bit) { 258 count--; 259 if (!count) { 260 pr_err_ratelimited("RWP timeout, gone fishing\n"); 261 return; 262 } 263 cpu_relax(); 264 udelay(1); 265 } 266 } 267 268 /* Wait for completion of a distributor change */ 269 static void gic_dist_wait_for_rwp(void) 270 { 271 gic_do_wait_for_rwp(gic_data.dist_base, GICD_CTLR_RWP); 272 } 273 274 /* Wait for completion of a redistributor change */ 275 static void gic_redist_wait_for_rwp(void) 276 { 277 gic_do_wait_for_rwp(gic_data_rdist_rd_base(), GICR_CTLR_RWP); 278 } 279 280 static void gic_enable_redist(bool enable) 281 { 282 void __iomem *rbase; 283 u32 count = 1000000; /* 1s! */ 284 u32 val; 285 286 if (gic_data.flags & FLAGS_WORKAROUND_GICR_WAKER_MSM8996) 287 return; 288 289 rbase = gic_data_rdist_rd_base(); 290 291 val = readl_relaxed(rbase + GICR_WAKER); 292 if (enable) 293 /* Wake up this CPU redistributor */ 294 val &= ~GICR_WAKER_ProcessorSleep; 295 else 296 val |= GICR_WAKER_ProcessorSleep; 297 writel_relaxed(val, rbase + GICR_WAKER); 298 299 if (!enable) { /* Check that GICR_WAKER is writeable */ 300 val = readl_relaxed(rbase + GICR_WAKER); 301 if (!(val & GICR_WAKER_ProcessorSleep)) 302 return; /* No PM support in this redistributor */ 303 } 304 305 while (--count) { 306 val = readl_relaxed(rbase + GICR_WAKER); 307 if (enable ^ (bool)(val & GICR_WAKER_ChildrenAsleep)) 308 break; 309 cpu_relax(); 310 udelay(1); 311 } 312 if (!count) 313 pr_err_ratelimited("redistributor failed to %s...\n", 314 enable ? "wakeup" : "sleep"); 315 } 316 317 /* 318 * Routines to disable, enable, EOI and route interrupts 319 */ 320 static u32 convert_offset_index(struct irq_data *d, u32 offset, u32 *index) 321 { 322 switch (get_intid_range(d)) { 323 case SGI_RANGE: 324 case PPI_RANGE: 325 case SPI_RANGE: 326 *index = d->hwirq; 327 return offset; 328 case EPPI_RANGE: 329 /* 330 * Contrary to the ESPI range, the EPPI range is contiguous 331 * to the PPI range in the registers, so let's adjust the 332 * displacement accordingly. Consistency is overrated. 333 */ 334 *index = d->hwirq - EPPI_BASE_INTID + 32; 335 return offset; 336 case ESPI_RANGE: 337 *index = d->hwirq - ESPI_BASE_INTID; 338 switch (offset) { 339 case GICD_ISENABLER: 340 return GICD_ISENABLERnE; 341 case GICD_ICENABLER: 342 return GICD_ICENABLERnE; 343 case GICD_ISPENDR: 344 return GICD_ISPENDRnE; 345 case GICD_ICPENDR: 346 return GICD_ICPENDRnE; 347 case GICD_ISACTIVER: 348 return GICD_ISACTIVERnE; 349 case GICD_ICACTIVER: 350 return GICD_ICACTIVERnE; 351 case GICD_IPRIORITYR: 352 return GICD_IPRIORITYRnE; 353 case GICD_ICFGR: 354 return GICD_ICFGRnE; 355 case GICD_IROUTER: 356 return GICD_IROUTERnE; 357 default: 358 break; 359 } 360 break; 361 default: 362 break; 363 } 364 365 WARN_ON(1); 366 *index = d->hwirq; 367 return offset; 368 } 369 370 static int gic_peek_irq(struct irq_data *d, u32 offset) 371 { 372 void __iomem *base; 373 u32 index, mask; 374 375 offset = convert_offset_index(d, offset, &index); 376 mask = 1 << (index % 32); 377 378 if (gic_irq_in_rdist(d)) 379 base = gic_data_rdist_sgi_base(); 380 else 381 base = gic_dist_base_alias(d); 382 383 return !!(readl_relaxed(base + offset + (index / 32) * 4) & mask); 384 } 385 386 static void gic_poke_irq(struct irq_data *d, u32 offset) 387 { 388 void __iomem *base; 389 u32 index, mask; 390 391 offset = convert_offset_index(d, offset, &index); 392 mask = 1 << (index % 32); 393 394 if (gic_irq_in_rdist(d)) 395 base = gic_data_rdist_sgi_base(); 396 else 397 base = gic_data.dist_base; 398 399 writel_relaxed(mask, base + offset + (index / 32) * 4); 400 } 401 402 static void gic_mask_irq(struct irq_data *d) 403 { 404 gic_poke_irq(d, GICD_ICENABLER); 405 if (gic_irq_in_rdist(d)) 406 gic_redist_wait_for_rwp(); 407 else 408 gic_dist_wait_for_rwp(); 409 } 410 411 static void gic_eoimode1_mask_irq(struct irq_data *d) 412 { 413 gic_mask_irq(d); 414 /* 415 * When masking a forwarded interrupt, make sure it is 416 * deactivated as well. 417 * 418 * This ensures that an interrupt that is getting 419 * disabled/masked will not get "stuck", because there is 420 * noone to deactivate it (guest is being terminated). 421 */ 422 if (irqd_is_forwarded_to_vcpu(d)) 423 gic_poke_irq(d, GICD_ICACTIVER); 424 } 425 426 static void gic_unmask_irq(struct irq_data *d) 427 { 428 gic_poke_irq(d, GICD_ISENABLER); 429 } 430 431 static inline bool gic_supports_nmi(void) 432 { 433 return IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) && 434 static_branch_likely(&supports_pseudo_nmis); 435 } 436 437 static int gic_irq_set_irqchip_state(struct irq_data *d, 438 enum irqchip_irq_state which, bool val) 439 { 440 u32 reg; 441 442 if (d->hwirq >= 8192) /* SGI/PPI/SPI only */ 443 return -EINVAL; 444 445 switch (which) { 446 case IRQCHIP_STATE_PENDING: 447 reg = val ? GICD_ISPENDR : GICD_ICPENDR; 448 break; 449 450 case IRQCHIP_STATE_ACTIVE: 451 reg = val ? GICD_ISACTIVER : GICD_ICACTIVER; 452 break; 453 454 case IRQCHIP_STATE_MASKED: 455 if (val) { 456 gic_mask_irq(d); 457 return 0; 458 } 459 reg = GICD_ISENABLER; 460 break; 461 462 default: 463 return -EINVAL; 464 } 465 466 gic_poke_irq(d, reg); 467 return 0; 468 } 469 470 static int gic_irq_get_irqchip_state(struct irq_data *d, 471 enum irqchip_irq_state which, bool *val) 472 { 473 if (d->hwirq >= 8192) /* PPI/SPI only */ 474 return -EINVAL; 475 476 switch (which) { 477 case IRQCHIP_STATE_PENDING: 478 *val = gic_peek_irq(d, GICD_ISPENDR); 479 break; 480 481 case IRQCHIP_STATE_ACTIVE: 482 *val = gic_peek_irq(d, GICD_ISACTIVER); 483 break; 484 485 case IRQCHIP_STATE_MASKED: 486 *val = !gic_peek_irq(d, GICD_ISENABLER); 487 break; 488 489 default: 490 return -EINVAL; 491 } 492 493 return 0; 494 } 495 496 static void gic_irq_set_prio(struct irq_data *d, u8 prio) 497 { 498 void __iomem *base = gic_dist_base(d); 499 u32 offset, index; 500 501 offset = convert_offset_index(d, GICD_IPRIORITYR, &index); 502 503 writeb_relaxed(prio, base + offset + index); 504 } 505 506 static u32 __gic_get_ppi_index(irq_hw_number_t hwirq) 507 { 508 switch (__get_intid_range(hwirq)) { 509 case PPI_RANGE: 510 return hwirq - 16; 511 case EPPI_RANGE: 512 return hwirq - EPPI_BASE_INTID + 16; 513 default: 514 unreachable(); 515 } 516 } 517 518 static u32 __gic_get_rdist_index(irq_hw_number_t hwirq) 519 { 520 switch (__get_intid_range(hwirq)) { 521 case SGI_RANGE: 522 case PPI_RANGE: 523 return hwirq; 524 case EPPI_RANGE: 525 return hwirq - EPPI_BASE_INTID + 32; 526 default: 527 unreachable(); 528 } 529 } 530 531 static u32 gic_get_rdist_index(struct irq_data *d) 532 { 533 return __gic_get_rdist_index(d->hwirq); 534 } 535 536 static int gic_irq_nmi_setup(struct irq_data *d) 537 { 538 struct irq_desc *desc = irq_to_desc(d->irq); 539 540 if (!gic_supports_nmi()) 541 return -EINVAL; 542 543 if (gic_peek_irq(d, GICD_ISENABLER)) { 544 pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq); 545 return -EINVAL; 546 } 547 548 /* 549 * A secondary irq_chip should be in charge of LPI request, 550 * it should not be possible to get there 551 */ 552 if (WARN_ON(gic_irq(d) >= 8192)) 553 return -EINVAL; 554 555 /* desc lock should already be held */ 556 if (gic_irq_in_rdist(d)) { 557 u32 idx = gic_get_rdist_index(d); 558 559 /* 560 * Setting up a percpu interrupt as NMI, only switch handler 561 * for first NMI 562 */ 563 if (!refcount_inc_not_zero(&rdist_nmi_refs[idx])) { 564 refcount_set(&rdist_nmi_refs[idx], 1); 565 desc->handle_irq = handle_percpu_devid_fasteoi_nmi; 566 } 567 } else { 568 desc->handle_irq = handle_fasteoi_nmi; 569 } 570 571 gic_irq_set_prio(d, GICD_INT_NMI_PRI); 572 573 return 0; 574 } 575 576 static void gic_irq_nmi_teardown(struct irq_data *d) 577 { 578 struct irq_desc *desc = irq_to_desc(d->irq); 579 580 if (WARN_ON(!gic_supports_nmi())) 581 return; 582 583 if (gic_peek_irq(d, GICD_ISENABLER)) { 584 pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq); 585 return; 586 } 587 588 /* 589 * A secondary irq_chip should be in charge of LPI request, 590 * it should not be possible to get there 591 */ 592 if (WARN_ON(gic_irq(d) >= 8192)) 593 return; 594 595 /* desc lock should already be held */ 596 if (gic_irq_in_rdist(d)) { 597 u32 idx = gic_get_rdist_index(d); 598 599 /* Tearing down NMI, only switch handler for last NMI */ 600 if (refcount_dec_and_test(&rdist_nmi_refs[idx])) 601 desc->handle_irq = handle_percpu_devid_irq; 602 } else { 603 desc->handle_irq = handle_fasteoi_irq; 604 } 605 606 gic_irq_set_prio(d, GICD_INT_DEF_PRI); 607 } 608 609 static bool gic_arm64_erratum_2941627_needed(struct irq_data *d) 610 { 611 enum gic_intid_range range; 612 613 if (!static_branch_unlikely(&gic_arm64_2941627_erratum)) 614 return false; 615 616 range = get_intid_range(d); 617 618 /* 619 * The workaround is needed if the IRQ is an SPI and 620 * the target cpu is different from the one we are 621 * executing on. 622 */ 623 return (range == SPI_RANGE || range == ESPI_RANGE) && 624 !cpumask_test_cpu(raw_smp_processor_id(), 625 irq_data_get_effective_affinity_mask(d)); 626 } 627 628 static void gic_eoi_irq(struct irq_data *d) 629 { 630 write_gicreg(gic_irq(d), ICC_EOIR1_EL1); 631 isb(); 632 633 if (gic_arm64_erratum_2941627_needed(d)) { 634 /* 635 * Make sure the GIC stream deactivate packet 636 * issued by ICC_EOIR1_EL1 has completed before 637 * deactivating through GICD_IACTIVER. 638 */ 639 dsb(sy); 640 gic_poke_irq(d, GICD_ICACTIVER); 641 } 642 } 643 644 static void gic_eoimode1_eoi_irq(struct irq_data *d) 645 { 646 /* 647 * No need to deactivate an LPI, or an interrupt that 648 * is is getting forwarded to a vcpu. 649 */ 650 if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d)) 651 return; 652 653 if (!gic_arm64_erratum_2941627_needed(d)) 654 gic_write_dir(gic_irq(d)); 655 else 656 gic_poke_irq(d, GICD_ICACTIVER); 657 } 658 659 static int gic_set_type(struct irq_data *d, unsigned int type) 660 { 661 enum gic_intid_range range; 662 unsigned int irq = gic_irq(d); 663 void __iomem *base; 664 u32 offset, index; 665 int ret; 666 667 range = get_intid_range(d); 668 669 /* Interrupt configuration for SGIs can't be changed */ 670 if (range == SGI_RANGE) 671 return type != IRQ_TYPE_EDGE_RISING ? -EINVAL : 0; 672 673 /* SPIs have restrictions on the supported types */ 674 if ((range == SPI_RANGE || range == ESPI_RANGE) && 675 type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING) 676 return -EINVAL; 677 678 if (gic_irq_in_rdist(d)) 679 base = gic_data_rdist_sgi_base(); 680 else 681 base = gic_dist_base_alias(d); 682 683 offset = convert_offset_index(d, GICD_ICFGR, &index); 684 685 ret = gic_configure_irq(index, type, base + offset, NULL); 686 if (ret && (range == PPI_RANGE || range == EPPI_RANGE)) { 687 /* Misconfigured PPIs are usually not fatal */ 688 pr_warn("GIC: PPI INTID%d is secure or misconfigured\n", irq); 689 ret = 0; 690 } 691 692 return ret; 693 } 694 695 static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) 696 { 697 if (get_intid_range(d) == SGI_RANGE) 698 return -EINVAL; 699 700 if (vcpu) 701 irqd_set_forwarded_to_vcpu(d); 702 else 703 irqd_clr_forwarded_to_vcpu(d); 704 return 0; 705 } 706 707 static u64 gic_cpu_to_affinity(int cpu) 708 { 709 u64 mpidr = cpu_logical_map(cpu); 710 u64 aff; 711 712 /* ASR8601 needs to have its affinities shifted down... */ 713 if (unlikely(gic_data.flags & FLAGS_WORKAROUND_ASR_ERRATUM_8601001)) 714 mpidr = (MPIDR_AFFINITY_LEVEL(mpidr, 1) | 715 (MPIDR_AFFINITY_LEVEL(mpidr, 2) << 8)); 716 717 aff = ((u64)MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 | 718 MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | 719 MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | 720 MPIDR_AFFINITY_LEVEL(mpidr, 0)); 721 722 return aff; 723 } 724 725 static void gic_deactivate_unhandled(u32 irqnr) 726 { 727 if (static_branch_likely(&supports_deactivate_key)) { 728 if (irqnr < 8192) 729 gic_write_dir(irqnr); 730 } else { 731 write_gicreg(irqnr, ICC_EOIR1_EL1); 732 isb(); 733 } 734 } 735 736 /* 737 * Follow a read of the IAR with any HW maintenance that needs to happen prior 738 * to invoking the relevant IRQ handler. We must do two things: 739 * 740 * (1) Ensure instruction ordering between a read of IAR and subsequent 741 * instructions in the IRQ handler using an ISB. 742 * 743 * It is possible for the IAR to report an IRQ which was signalled *after* 744 * the CPU took an IRQ exception as multiple interrupts can race to be 745 * recognized by the GIC, earlier interrupts could be withdrawn, and/or 746 * later interrupts could be prioritized by the GIC. 747 * 748 * For devices which are tightly coupled to the CPU, such as PMUs, a 749 * context synchronization event is necessary to ensure that system 750 * register state is not stale, as these may have been indirectly written 751 * *after* exception entry. 752 * 753 * (2) Deactivate the interrupt when EOI mode 1 is in use. 754 */ 755 static inline void gic_complete_ack(u32 irqnr) 756 { 757 if (static_branch_likely(&supports_deactivate_key)) 758 write_gicreg(irqnr, ICC_EOIR1_EL1); 759 760 isb(); 761 } 762 763 static bool gic_rpr_is_nmi_prio(void) 764 { 765 if (!gic_supports_nmi()) 766 return false; 767 768 return unlikely(gic_read_rpr() == GICD_INT_RPR_PRI(GICD_INT_NMI_PRI)); 769 } 770 771 static bool gic_irqnr_is_special(u32 irqnr) 772 { 773 return irqnr >= 1020 && irqnr <= 1023; 774 } 775 776 static void __gic_handle_irq(u32 irqnr, struct pt_regs *regs) 777 { 778 if (gic_irqnr_is_special(irqnr)) 779 return; 780 781 gic_complete_ack(irqnr); 782 783 if (generic_handle_domain_irq(gic_data.domain, irqnr)) { 784 WARN_ONCE(true, "Unexpected interrupt (irqnr %u)\n", irqnr); 785 gic_deactivate_unhandled(irqnr); 786 } 787 } 788 789 static void __gic_handle_nmi(u32 irqnr, struct pt_regs *regs) 790 { 791 if (gic_irqnr_is_special(irqnr)) 792 return; 793 794 gic_complete_ack(irqnr); 795 796 if (generic_handle_domain_nmi(gic_data.domain, irqnr)) { 797 WARN_ONCE(true, "Unexpected pseudo-NMI (irqnr %u)\n", irqnr); 798 gic_deactivate_unhandled(irqnr); 799 } 800 } 801 802 /* 803 * An exception has been taken from a context with IRQs enabled, and this could 804 * be an IRQ or an NMI. 805 * 806 * The entry code called us with DAIF.IF set to keep NMIs masked. We must clear 807 * DAIF.IF (and update ICC_PMR_EL1 to mask regular IRQs) prior to returning, 808 * after handling any NMI but before handling any IRQ. 809 * 810 * The entry code has performed IRQ entry, and if an NMI is detected we must 811 * perform NMI entry/exit around invoking the handler. 812 */ 813 static void __gic_handle_irq_from_irqson(struct pt_regs *regs) 814 { 815 bool is_nmi; 816 u32 irqnr; 817 818 irqnr = gic_read_iar(); 819 820 is_nmi = gic_rpr_is_nmi_prio(); 821 822 if (is_nmi) { 823 nmi_enter(); 824 __gic_handle_nmi(irqnr, regs); 825 nmi_exit(); 826 } 827 828 if (gic_prio_masking_enabled()) { 829 gic_pmr_mask_irqs(); 830 gic_arch_enable_irqs(); 831 } 832 833 if (!is_nmi) 834 __gic_handle_irq(irqnr, regs); 835 } 836 837 /* 838 * An exception has been taken from a context with IRQs disabled, which can only 839 * be an NMI. 840 * 841 * The entry code called us with DAIF.IF set to keep NMIs masked. We must leave 842 * DAIF.IF (and ICC_PMR_EL1) unchanged. 843 * 844 * The entry code has performed NMI entry. 845 */ 846 static void __gic_handle_irq_from_irqsoff(struct pt_regs *regs) 847 { 848 u64 pmr; 849 u32 irqnr; 850 851 /* 852 * We were in a context with IRQs disabled. However, the 853 * entry code has set PMR to a value that allows any 854 * interrupt to be acknowledged, and not just NMIs. This can 855 * lead to surprising effects if the NMI has been retired in 856 * the meantime, and that there is an IRQ pending. The IRQ 857 * would then be taken in NMI context, something that nobody 858 * wants to debug twice. 859 * 860 * Until we sort this, drop PMR again to a level that will 861 * actually only allow NMIs before reading IAR, and then 862 * restore it to what it was. 863 */ 864 pmr = gic_read_pmr(); 865 gic_pmr_mask_irqs(); 866 isb(); 867 irqnr = gic_read_iar(); 868 gic_write_pmr(pmr); 869 870 __gic_handle_nmi(irqnr, regs); 871 } 872 873 static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) 874 { 875 if (unlikely(gic_supports_nmi() && !interrupts_enabled(regs))) 876 __gic_handle_irq_from_irqsoff(regs); 877 else 878 __gic_handle_irq_from_irqson(regs); 879 } 880 881 static u32 gic_get_pribits(void) 882 { 883 u32 pribits; 884 885 pribits = gic_read_ctlr(); 886 pribits &= ICC_CTLR_EL1_PRI_BITS_MASK; 887 pribits >>= ICC_CTLR_EL1_PRI_BITS_SHIFT; 888 pribits++; 889 890 return pribits; 891 } 892 893 static bool gic_has_group0(void) 894 { 895 u32 val; 896 u32 old_pmr; 897 898 old_pmr = gic_read_pmr(); 899 900 /* 901 * Let's find out if Group0 is under control of EL3 or not by 902 * setting the highest possible, non-zero priority in PMR. 903 * 904 * If SCR_EL3.FIQ is set, the priority gets shifted down in 905 * order for the CPU interface to set bit 7, and keep the 906 * actual priority in the non-secure range. In the process, it 907 * looses the least significant bit and the actual priority 908 * becomes 0x80. Reading it back returns 0, indicating that 909 * we're don't have access to Group0. 910 */ 911 gic_write_pmr(BIT(8 - gic_get_pribits())); 912 val = gic_read_pmr(); 913 914 gic_write_pmr(old_pmr); 915 916 return val != 0; 917 } 918 919 static void __init gic_dist_init(void) 920 { 921 unsigned int i; 922 u64 affinity; 923 void __iomem *base = gic_data.dist_base; 924 u32 val; 925 926 /* Disable the distributor */ 927 writel_relaxed(0, base + GICD_CTLR); 928 gic_dist_wait_for_rwp(); 929 930 /* 931 * Configure SPIs as non-secure Group-1. This will only matter 932 * if the GIC only has a single security state. This will not 933 * do the right thing if the kernel is running in secure mode, 934 * but that's not the intended use case anyway. 935 */ 936 for (i = 32; i < GIC_LINE_NR; i += 32) 937 writel_relaxed(~0, base + GICD_IGROUPR + i / 8); 938 939 /* Extended SPI range, not handled by the GICv2/GICv3 common code */ 940 for (i = 0; i < GIC_ESPI_NR; i += 32) { 941 writel_relaxed(~0U, base + GICD_ICENABLERnE + i / 8); 942 writel_relaxed(~0U, base + GICD_ICACTIVERnE + i / 8); 943 } 944 945 for (i = 0; i < GIC_ESPI_NR; i += 32) 946 writel_relaxed(~0U, base + GICD_IGROUPRnE + i / 8); 947 948 for (i = 0; i < GIC_ESPI_NR; i += 16) 949 writel_relaxed(0, base + GICD_ICFGRnE + i / 4); 950 951 for (i = 0; i < GIC_ESPI_NR; i += 4) 952 writel_relaxed(GICD_INT_DEF_PRI_X4, base + GICD_IPRIORITYRnE + i); 953 954 /* Now do the common stuff */ 955 gic_dist_config(base, GIC_LINE_NR, NULL); 956 957 val = GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1; 958 if (gic_data.rdists.gicd_typer2 & GICD_TYPER2_nASSGIcap) { 959 pr_info("Enabling SGIs without active state\n"); 960 val |= GICD_CTLR_nASSGIreq; 961 } 962 963 /* Enable distributor with ARE, Group1, and wait for it to drain */ 964 writel_relaxed(val, base + GICD_CTLR); 965 gic_dist_wait_for_rwp(); 966 967 /* 968 * Set all global interrupts to the boot CPU only. ARE must be 969 * enabled. 970 */ 971 affinity = gic_cpu_to_affinity(smp_processor_id()); 972 for (i = 32; i < GIC_LINE_NR; i++) 973 gic_write_irouter(affinity, base + GICD_IROUTER + i * 8); 974 975 for (i = 0; i < GIC_ESPI_NR; i++) 976 gic_write_irouter(affinity, base + GICD_IROUTERnE + i * 8); 977 } 978 979 static int gic_iterate_rdists(int (*fn)(struct redist_region *, void __iomem *)) 980 { 981 int ret = -ENODEV; 982 int i; 983 984 for (i = 0; i < gic_data.nr_redist_regions; i++) { 985 void __iomem *ptr = gic_data.redist_regions[i].redist_base; 986 u64 typer; 987 u32 reg; 988 989 reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK; 990 if (reg != GIC_PIDR2_ARCH_GICv3 && 991 reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */ 992 pr_warn("No redistributor present @%p\n", ptr); 993 break; 994 } 995 996 do { 997 typer = gic_read_typer(ptr + GICR_TYPER); 998 ret = fn(gic_data.redist_regions + i, ptr); 999 if (!ret) 1000 return 0; 1001 1002 if (gic_data.redist_regions[i].single_redist) 1003 break; 1004 1005 if (gic_data.redist_stride) { 1006 ptr += gic_data.redist_stride; 1007 } else { 1008 ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */ 1009 if (typer & GICR_TYPER_VLPIS) 1010 ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */ 1011 } 1012 } while (!(typer & GICR_TYPER_LAST)); 1013 } 1014 1015 return ret ? -ENODEV : 0; 1016 } 1017 1018 static int __gic_populate_rdist(struct redist_region *region, void __iomem *ptr) 1019 { 1020 unsigned long mpidr; 1021 u64 typer; 1022 u32 aff; 1023 1024 /* 1025 * Convert affinity to a 32bit value that can be matched to 1026 * GICR_TYPER bits [63:32]. 1027 */ 1028 mpidr = gic_cpu_to_affinity(smp_processor_id()); 1029 1030 aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 | 1031 MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | 1032 MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | 1033 MPIDR_AFFINITY_LEVEL(mpidr, 0)); 1034 1035 typer = gic_read_typer(ptr + GICR_TYPER); 1036 if ((typer >> 32) == aff) { 1037 u64 offset = ptr - region->redist_base; 1038 raw_spin_lock_init(&gic_data_rdist()->rd_lock); 1039 gic_data_rdist_rd_base() = ptr; 1040 gic_data_rdist()->phys_base = region->phys_base + offset; 1041 1042 pr_info("CPU%d: found redistributor %lx region %d:%pa\n", 1043 smp_processor_id(), mpidr, 1044 (int)(region - gic_data.redist_regions), 1045 &gic_data_rdist()->phys_base); 1046 return 0; 1047 } 1048 1049 /* Try next one */ 1050 return 1; 1051 } 1052 1053 static int gic_populate_rdist(void) 1054 { 1055 if (gic_iterate_rdists(__gic_populate_rdist) == 0) 1056 return 0; 1057 1058 /* We couldn't even deal with ourselves... */ 1059 WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n", 1060 smp_processor_id(), 1061 (unsigned long)cpu_logical_map(smp_processor_id())); 1062 return -ENODEV; 1063 } 1064 1065 static int __gic_update_rdist_properties(struct redist_region *region, 1066 void __iomem *ptr) 1067 { 1068 u64 typer = gic_read_typer(ptr + GICR_TYPER); 1069 u32 ctlr = readl_relaxed(ptr + GICR_CTLR); 1070 1071 /* Boot-time cleanup */ 1072 if ((typer & GICR_TYPER_VLPIS) && (typer & GICR_TYPER_RVPEID)) { 1073 u64 val; 1074 1075 /* Deactivate any present vPE */ 1076 val = gicr_read_vpendbaser(ptr + SZ_128K + GICR_VPENDBASER); 1077 if (val & GICR_VPENDBASER_Valid) 1078 gicr_write_vpendbaser(GICR_VPENDBASER_PendingLast, 1079 ptr + SZ_128K + GICR_VPENDBASER); 1080 1081 /* Mark the VPE table as invalid */ 1082 val = gicr_read_vpropbaser(ptr + SZ_128K + GICR_VPROPBASER); 1083 val &= ~GICR_VPROPBASER_4_1_VALID; 1084 gicr_write_vpropbaser(val, ptr + SZ_128K + GICR_VPROPBASER); 1085 } 1086 1087 gic_data.rdists.has_vlpis &= !!(typer & GICR_TYPER_VLPIS); 1088 1089 /* 1090 * TYPER.RVPEID implies some form of DirectLPI, no matter what the 1091 * doc says... :-/ And CTLR.IR implies another subset of DirectLPI 1092 * that the ITS driver can make use of for LPIs (and not VLPIs). 1093 * 1094 * These are 3 different ways to express the same thing, depending 1095 * on the revision of the architecture and its relaxations over 1096 * time. Just group them under the 'direct_lpi' banner. 1097 */ 1098 gic_data.rdists.has_rvpeid &= !!(typer & GICR_TYPER_RVPEID); 1099 gic_data.rdists.has_direct_lpi &= (!!(typer & GICR_TYPER_DirectLPIS) | 1100 !!(ctlr & GICR_CTLR_IR) | 1101 gic_data.rdists.has_rvpeid); 1102 gic_data.rdists.has_vpend_valid_dirty &= !!(typer & GICR_TYPER_DIRTY); 1103 1104 /* Detect non-sensical configurations */ 1105 if (WARN_ON_ONCE(gic_data.rdists.has_rvpeid && !gic_data.rdists.has_vlpis)) { 1106 gic_data.rdists.has_direct_lpi = false; 1107 gic_data.rdists.has_vlpis = false; 1108 gic_data.rdists.has_rvpeid = false; 1109 } 1110 1111 gic_data.ppi_nr = min(GICR_TYPER_NR_PPIS(typer), gic_data.ppi_nr); 1112 1113 return 1; 1114 } 1115 1116 static void gic_update_rdist_properties(void) 1117 { 1118 gic_data.ppi_nr = UINT_MAX; 1119 gic_iterate_rdists(__gic_update_rdist_properties); 1120 if (WARN_ON(gic_data.ppi_nr == UINT_MAX)) 1121 gic_data.ppi_nr = 0; 1122 pr_info("GICv3 features: %d PPIs%s%s\n", 1123 gic_data.ppi_nr, 1124 gic_data.has_rss ? ", RSS" : "", 1125 gic_data.rdists.has_direct_lpi ? ", DirectLPI" : ""); 1126 1127 if (gic_data.rdists.has_vlpis) 1128 pr_info("GICv4 features: %s%s%s\n", 1129 gic_data.rdists.has_direct_lpi ? "DirectLPI " : "", 1130 gic_data.rdists.has_rvpeid ? "RVPEID " : "", 1131 gic_data.rdists.has_vpend_valid_dirty ? "Valid+Dirty " : ""); 1132 } 1133 1134 /* Check whether it's single security state view */ 1135 static inline bool gic_dist_security_disabled(void) 1136 { 1137 return readl_relaxed(gic_data.dist_base + GICD_CTLR) & GICD_CTLR_DS; 1138 } 1139 1140 static void gic_cpu_sys_reg_init(void) 1141 { 1142 int i, cpu = smp_processor_id(); 1143 u64 mpidr = gic_cpu_to_affinity(cpu); 1144 u64 need_rss = MPIDR_RS(mpidr); 1145 bool group0; 1146 u32 pribits; 1147 1148 /* 1149 * Need to check that the SRE bit has actually been set. If 1150 * not, it means that SRE is disabled at EL2. We're going to 1151 * die painfully, and there is nothing we can do about it. 1152 * 1153 * Kindly inform the luser. 1154 */ 1155 if (!gic_enable_sre()) 1156 pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n"); 1157 1158 pribits = gic_get_pribits(); 1159 1160 group0 = gic_has_group0(); 1161 1162 /* Set priority mask register */ 1163 if (!gic_prio_masking_enabled()) { 1164 write_gicreg(DEFAULT_PMR_VALUE, ICC_PMR_EL1); 1165 } else if (gic_supports_nmi()) { 1166 /* 1167 * Mismatch configuration with boot CPU, the system is likely 1168 * to die as interrupt masking will not work properly on all 1169 * CPUs 1170 * 1171 * The boot CPU calls this function before enabling NMI support, 1172 * and as a result we'll never see this warning in the boot path 1173 * for that CPU. 1174 */ 1175 if (static_branch_unlikely(&gic_nonsecure_priorities)) 1176 WARN_ON(!group0 || gic_dist_security_disabled()); 1177 else 1178 WARN_ON(group0 && !gic_dist_security_disabled()); 1179 } 1180 1181 /* 1182 * Some firmwares hand over to the kernel with the BPR changed from 1183 * its reset value (and with a value large enough to prevent 1184 * any pre-emptive interrupts from working at all). Writing a zero 1185 * to BPR restores is reset value. 1186 */ 1187 gic_write_bpr1(0); 1188 1189 if (static_branch_likely(&supports_deactivate_key)) { 1190 /* EOI drops priority only (mode 1) */ 1191 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop); 1192 } else { 1193 /* EOI deactivates interrupt too (mode 0) */ 1194 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir); 1195 } 1196 1197 /* Always whack Group0 before Group1 */ 1198 if (group0) { 1199 switch(pribits) { 1200 case 8: 1201 case 7: 1202 write_gicreg(0, ICC_AP0R3_EL1); 1203 write_gicreg(0, ICC_AP0R2_EL1); 1204 fallthrough; 1205 case 6: 1206 write_gicreg(0, ICC_AP0R1_EL1); 1207 fallthrough; 1208 case 5: 1209 case 4: 1210 write_gicreg(0, ICC_AP0R0_EL1); 1211 } 1212 1213 isb(); 1214 } 1215 1216 switch(pribits) { 1217 case 8: 1218 case 7: 1219 write_gicreg(0, ICC_AP1R3_EL1); 1220 write_gicreg(0, ICC_AP1R2_EL1); 1221 fallthrough; 1222 case 6: 1223 write_gicreg(0, ICC_AP1R1_EL1); 1224 fallthrough; 1225 case 5: 1226 case 4: 1227 write_gicreg(0, ICC_AP1R0_EL1); 1228 } 1229 1230 isb(); 1231 1232 /* ... and let's hit the road... */ 1233 gic_write_grpen1(1); 1234 1235 /* Keep the RSS capability status in per_cpu variable */ 1236 per_cpu(has_rss, cpu) = !!(gic_read_ctlr() & ICC_CTLR_EL1_RSS); 1237 1238 /* Check all the CPUs have capable of sending SGIs to other CPUs */ 1239 for_each_online_cpu(i) { 1240 bool have_rss = per_cpu(has_rss, i) && per_cpu(has_rss, cpu); 1241 1242 need_rss |= MPIDR_RS(gic_cpu_to_affinity(i)); 1243 if (need_rss && (!have_rss)) 1244 pr_crit("CPU%d (%lx) can't SGI CPU%d (%lx), no RSS\n", 1245 cpu, (unsigned long)mpidr, 1246 i, (unsigned long)gic_cpu_to_affinity(i)); 1247 } 1248 1249 /** 1250 * GIC spec says, when ICC_CTLR_EL1.RSS==1 and GICD_TYPER.RSS==0, 1251 * writing ICC_ASGI1R_EL1 register with RS != 0 is a CONSTRAINED 1252 * UNPREDICTABLE choice of : 1253 * - The write is ignored. 1254 * - The RS field is treated as 0. 1255 */ 1256 if (need_rss && (!gic_data.has_rss)) 1257 pr_crit_once("RSS is required but GICD doesn't support it\n"); 1258 } 1259 1260 static bool gicv3_nolpi; 1261 1262 static int __init gicv3_nolpi_cfg(char *buf) 1263 { 1264 return kstrtobool(buf, &gicv3_nolpi); 1265 } 1266 early_param("irqchip.gicv3_nolpi", gicv3_nolpi_cfg); 1267 1268 static int gic_dist_supports_lpis(void) 1269 { 1270 return (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && 1271 !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS) && 1272 !gicv3_nolpi); 1273 } 1274 1275 static void gic_cpu_init(void) 1276 { 1277 void __iomem *rbase; 1278 int i; 1279 1280 /* Register ourselves with the rest of the world */ 1281 if (gic_populate_rdist()) 1282 return; 1283 1284 gic_enable_redist(true); 1285 1286 WARN((gic_data.ppi_nr > 16 || GIC_ESPI_NR != 0) && 1287 !(gic_read_ctlr() & ICC_CTLR_EL1_ExtRange), 1288 "Distributor has extended ranges, but CPU%d doesn't\n", 1289 smp_processor_id()); 1290 1291 rbase = gic_data_rdist_sgi_base(); 1292 1293 /* Configure SGIs/PPIs as non-secure Group-1 */ 1294 for (i = 0; i < gic_data.ppi_nr + SGI_NR; i += 32) 1295 writel_relaxed(~0, rbase + GICR_IGROUPR0 + i / 8); 1296 1297 gic_cpu_config(rbase, gic_data.ppi_nr + SGI_NR, gic_redist_wait_for_rwp); 1298 1299 /* initialise system registers */ 1300 gic_cpu_sys_reg_init(); 1301 } 1302 1303 #ifdef CONFIG_SMP 1304 1305 #define MPIDR_TO_SGI_RS(mpidr) (MPIDR_RS(mpidr) << ICC_SGI1R_RS_SHIFT) 1306 #define MPIDR_TO_SGI_CLUSTER_ID(mpidr) ((mpidr) & ~0xFUL) 1307 1308 static int gic_starting_cpu(unsigned int cpu) 1309 { 1310 gic_cpu_init(); 1311 1312 if (gic_dist_supports_lpis()) 1313 its_cpu_init(); 1314 1315 return 0; 1316 } 1317 1318 static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask, 1319 unsigned long cluster_id) 1320 { 1321 int next_cpu, cpu = *base_cpu; 1322 unsigned long mpidr; 1323 u16 tlist = 0; 1324 1325 mpidr = gic_cpu_to_affinity(cpu); 1326 1327 while (cpu < nr_cpu_ids) { 1328 tlist |= 1 << (mpidr & 0xf); 1329 1330 next_cpu = cpumask_next(cpu, mask); 1331 if (next_cpu >= nr_cpu_ids) 1332 goto out; 1333 cpu = next_cpu; 1334 1335 mpidr = gic_cpu_to_affinity(cpu); 1336 1337 if (cluster_id != MPIDR_TO_SGI_CLUSTER_ID(mpidr)) { 1338 cpu--; 1339 goto out; 1340 } 1341 } 1342 out: 1343 *base_cpu = cpu; 1344 return tlist; 1345 } 1346 1347 #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \ 1348 (MPIDR_AFFINITY_LEVEL(cluster_id, level) \ 1349 << ICC_SGI1R_AFFINITY_## level ##_SHIFT) 1350 1351 static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq) 1352 { 1353 u64 val; 1354 1355 val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3) | 1356 MPIDR_TO_SGI_AFFINITY(cluster_id, 2) | 1357 irq << ICC_SGI1R_SGI_ID_SHIFT | 1358 MPIDR_TO_SGI_AFFINITY(cluster_id, 1) | 1359 MPIDR_TO_SGI_RS(cluster_id) | 1360 tlist << ICC_SGI1R_TARGET_LIST_SHIFT); 1361 1362 pr_devel("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val); 1363 gic_write_sgi1r(val); 1364 } 1365 1366 static void gic_ipi_send_mask(struct irq_data *d, const struct cpumask *mask) 1367 { 1368 int cpu; 1369 1370 if (WARN_ON(d->hwirq >= 16)) 1371 return; 1372 1373 /* 1374 * Ensure that stores to Normal memory are visible to the 1375 * other CPUs before issuing the IPI. 1376 */ 1377 dsb(ishst); 1378 1379 for_each_cpu(cpu, mask) { 1380 u64 cluster_id = MPIDR_TO_SGI_CLUSTER_ID(gic_cpu_to_affinity(cpu)); 1381 u16 tlist; 1382 1383 tlist = gic_compute_target_list(&cpu, mask, cluster_id); 1384 gic_send_sgi(cluster_id, tlist, d->hwirq); 1385 } 1386 1387 /* Force the above writes to ICC_SGI1R_EL1 to be executed */ 1388 isb(); 1389 } 1390 1391 static void __init gic_smp_init(void) 1392 { 1393 struct irq_fwspec sgi_fwspec = { 1394 .fwnode = gic_data.fwnode, 1395 .param_count = 1, 1396 }; 1397 int base_sgi; 1398 1399 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING, 1400 "irqchip/arm/gicv3:starting", 1401 gic_starting_cpu, NULL); 1402 1403 /* Register all 8 non-secure SGIs */ 1404 base_sgi = irq_domain_alloc_irqs(gic_data.domain, 8, NUMA_NO_NODE, &sgi_fwspec); 1405 if (WARN_ON(base_sgi <= 0)) 1406 return; 1407 1408 set_smp_ipi_range(base_sgi, 8); 1409 } 1410 1411 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, 1412 bool force) 1413 { 1414 unsigned int cpu; 1415 u32 offset, index; 1416 void __iomem *reg; 1417 int enabled; 1418 u64 val; 1419 1420 if (force) 1421 cpu = cpumask_first(mask_val); 1422 else 1423 cpu = cpumask_any_and(mask_val, cpu_online_mask); 1424 1425 if (cpu >= nr_cpu_ids) 1426 return -EINVAL; 1427 1428 if (gic_irq_in_rdist(d)) 1429 return -EINVAL; 1430 1431 /* If interrupt was enabled, disable it first */ 1432 enabled = gic_peek_irq(d, GICD_ISENABLER); 1433 if (enabled) 1434 gic_mask_irq(d); 1435 1436 offset = convert_offset_index(d, GICD_IROUTER, &index); 1437 reg = gic_dist_base(d) + offset + (index * 8); 1438 val = gic_cpu_to_affinity(cpu); 1439 1440 gic_write_irouter(val, reg); 1441 1442 /* 1443 * If the interrupt was enabled, enabled it again. Otherwise, 1444 * just wait for the distributor to have digested our changes. 1445 */ 1446 if (enabled) 1447 gic_unmask_irq(d); 1448 1449 irq_data_update_effective_affinity(d, cpumask_of(cpu)); 1450 1451 return IRQ_SET_MASK_OK_DONE; 1452 } 1453 #else 1454 #define gic_set_affinity NULL 1455 #define gic_ipi_send_mask NULL 1456 #define gic_smp_init() do { } while(0) 1457 #endif 1458 1459 static int gic_retrigger(struct irq_data *data) 1460 { 1461 return !gic_irq_set_irqchip_state(data, IRQCHIP_STATE_PENDING, true); 1462 } 1463 1464 #ifdef CONFIG_CPU_PM 1465 static int gic_cpu_pm_notifier(struct notifier_block *self, 1466 unsigned long cmd, void *v) 1467 { 1468 if (cmd == CPU_PM_EXIT) { 1469 if (gic_dist_security_disabled()) 1470 gic_enable_redist(true); 1471 gic_cpu_sys_reg_init(); 1472 } else if (cmd == CPU_PM_ENTER && gic_dist_security_disabled()) { 1473 gic_write_grpen1(0); 1474 gic_enable_redist(false); 1475 } 1476 return NOTIFY_OK; 1477 } 1478 1479 static struct notifier_block gic_cpu_pm_notifier_block = { 1480 .notifier_call = gic_cpu_pm_notifier, 1481 }; 1482 1483 static void gic_cpu_pm_init(void) 1484 { 1485 cpu_pm_register_notifier(&gic_cpu_pm_notifier_block); 1486 } 1487 1488 #else 1489 static inline void gic_cpu_pm_init(void) { } 1490 #endif /* CONFIG_CPU_PM */ 1491 1492 static struct irq_chip gic_chip = { 1493 .name = "GICv3", 1494 .irq_mask = gic_mask_irq, 1495 .irq_unmask = gic_unmask_irq, 1496 .irq_eoi = gic_eoi_irq, 1497 .irq_set_type = gic_set_type, 1498 .irq_set_affinity = gic_set_affinity, 1499 .irq_retrigger = gic_retrigger, 1500 .irq_get_irqchip_state = gic_irq_get_irqchip_state, 1501 .irq_set_irqchip_state = gic_irq_set_irqchip_state, 1502 .irq_nmi_setup = gic_irq_nmi_setup, 1503 .irq_nmi_teardown = gic_irq_nmi_teardown, 1504 .ipi_send_mask = gic_ipi_send_mask, 1505 .flags = IRQCHIP_SET_TYPE_MASKED | 1506 IRQCHIP_SKIP_SET_WAKE | 1507 IRQCHIP_MASK_ON_SUSPEND, 1508 }; 1509 1510 static struct irq_chip gic_eoimode1_chip = { 1511 .name = "GICv3", 1512 .irq_mask = gic_eoimode1_mask_irq, 1513 .irq_unmask = gic_unmask_irq, 1514 .irq_eoi = gic_eoimode1_eoi_irq, 1515 .irq_set_type = gic_set_type, 1516 .irq_set_affinity = gic_set_affinity, 1517 .irq_retrigger = gic_retrigger, 1518 .irq_get_irqchip_state = gic_irq_get_irqchip_state, 1519 .irq_set_irqchip_state = gic_irq_set_irqchip_state, 1520 .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity, 1521 .irq_nmi_setup = gic_irq_nmi_setup, 1522 .irq_nmi_teardown = gic_irq_nmi_teardown, 1523 .ipi_send_mask = gic_ipi_send_mask, 1524 .flags = IRQCHIP_SET_TYPE_MASKED | 1525 IRQCHIP_SKIP_SET_WAKE | 1526 IRQCHIP_MASK_ON_SUSPEND, 1527 }; 1528 1529 static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, 1530 irq_hw_number_t hw) 1531 { 1532 struct irq_chip *chip = &gic_chip; 1533 struct irq_data *irqd = irq_desc_get_irq_data(irq_to_desc(irq)); 1534 1535 if (static_branch_likely(&supports_deactivate_key)) 1536 chip = &gic_eoimode1_chip; 1537 1538 switch (__get_intid_range(hw)) { 1539 case SGI_RANGE: 1540 case PPI_RANGE: 1541 case EPPI_RANGE: 1542 irq_set_percpu_devid(irq); 1543 irq_domain_set_info(d, irq, hw, chip, d->host_data, 1544 handle_percpu_devid_irq, NULL, NULL); 1545 break; 1546 1547 case SPI_RANGE: 1548 case ESPI_RANGE: 1549 irq_domain_set_info(d, irq, hw, chip, d->host_data, 1550 handle_fasteoi_irq, NULL, NULL); 1551 irq_set_probe(irq); 1552 irqd_set_single_target(irqd); 1553 break; 1554 1555 case LPI_RANGE: 1556 if (!gic_dist_supports_lpis()) 1557 return -EPERM; 1558 irq_domain_set_info(d, irq, hw, chip, d->host_data, 1559 handle_fasteoi_irq, NULL, NULL); 1560 break; 1561 1562 default: 1563 return -EPERM; 1564 } 1565 1566 /* Prevents SW retriggers which mess up the ACK/EOI ordering */ 1567 irqd_set_handle_enforce_irqctx(irqd); 1568 return 0; 1569 } 1570 1571 static int gic_irq_domain_translate(struct irq_domain *d, 1572 struct irq_fwspec *fwspec, 1573 unsigned long *hwirq, 1574 unsigned int *type) 1575 { 1576 if (fwspec->param_count == 1 && fwspec->param[0] < 16) { 1577 *hwirq = fwspec->param[0]; 1578 *type = IRQ_TYPE_EDGE_RISING; 1579 return 0; 1580 } 1581 1582 if (is_of_node(fwspec->fwnode)) { 1583 if (fwspec->param_count < 3) 1584 return -EINVAL; 1585 1586 switch (fwspec->param[0]) { 1587 case 0: /* SPI */ 1588 *hwirq = fwspec->param[1] + 32; 1589 break; 1590 case 1: /* PPI */ 1591 *hwirq = fwspec->param[1] + 16; 1592 break; 1593 case 2: /* ESPI */ 1594 *hwirq = fwspec->param[1] + ESPI_BASE_INTID; 1595 break; 1596 case 3: /* EPPI */ 1597 *hwirq = fwspec->param[1] + EPPI_BASE_INTID; 1598 break; 1599 case GIC_IRQ_TYPE_LPI: /* LPI */ 1600 *hwirq = fwspec->param[1]; 1601 break; 1602 case GIC_IRQ_TYPE_PARTITION: 1603 *hwirq = fwspec->param[1]; 1604 if (fwspec->param[1] >= 16) 1605 *hwirq += EPPI_BASE_INTID - 16; 1606 else 1607 *hwirq += 16; 1608 break; 1609 default: 1610 return -EINVAL; 1611 } 1612 1613 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; 1614 1615 /* 1616 * Make it clear that broken DTs are... broken. 1617 * Partitioned PPIs are an unfortunate exception. 1618 */ 1619 WARN_ON(*type == IRQ_TYPE_NONE && 1620 fwspec->param[0] != GIC_IRQ_TYPE_PARTITION); 1621 return 0; 1622 } 1623 1624 if (is_fwnode_irqchip(fwspec->fwnode)) { 1625 if(fwspec->param_count != 2) 1626 return -EINVAL; 1627 1628 if (fwspec->param[0] < 16) { 1629 pr_err(FW_BUG "Illegal GSI%d translation request\n", 1630 fwspec->param[0]); 1631 return -EINVAL; 1632 } 1633 1634 *hwirq = fwspec->param[0]; 1635 *type = fwspec->param[1]; 1636 1637 WARN_ON(*type == IRQ_TYPE_NONE); 1638 return 0; 1639 } 1640 1641 return -EINVAL; 1642 } 1643 1644 static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 1645 unsigned int nr_irqs, void *arg) 1646 { 1647 int i, ret; 1648 irq_hw_number_t hwirq; 1649 unsigned int type = IRQ_TYPE_NONE; 1650 struct irq_fwspec *fwspec = arg; 1651 1652 ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type); 1653 if (ret) 1654 return ret; 1655 1656 for (i = 0; i < nr_irqs; i++) { 1657 ret = gic_irq_domain_map(domain, virq + i, hwirq + i); 1658 if (ret) 1659 return ret; 1660 } 1661 1662 return 0; 1663 } 1664 1665 static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq, 1666 unsigned int nr_irqs) 1667 { 1668 int i; 1669 1670 for (i = 0; i < nr_irqs; i++) { 1671 struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); 1672 irq_set_handler(virq + i, NULL); 1673 irq_domain_reset_irq_data(d); 1674 } 1675 } 1676 1677 static bool fwspec_is_partitioned_ppi(struct irq_fwspec *fwspec, 1678 irq_hw_number_t hwirq) 1679 { 1680 enum gic_intid_range range; 1681 1682 if (!gic_data.ppi_descs) 1683 return false; 1684 1685 if (!is_of_node(fwspec->fwnode)) 1686 return false; 1687 1688 if (fwspec->param_count < 4 || !fwspec->param[3]) 1689 return false; 1690 1691 range = __get_intid_range(hwirq); 1692 if (range != PPI_RANGE && range != EPPI_RANGE) 1693 return false; 1694 1695 return true; 1696 } 1697 1698 static int gic_irq_domain_select(struct irq_domain *d, 1699 struct irq_fwspec *fwspec, 1700 enum irq_domain_bus_token bus_token) 1701 { 1702 unsigned int type, ret, ppi_idx; 1703 irq_hw_number_t hwirq; 1704 1705 /* Not for us */ 1706 if (fwspec->fwnode != d->fwnode) 1707 return 0; 1708 1709 /* If this is not DT, then we have a single domain */ 1710 if (!is_of_node(fwspec->fwnode)) 1711 return 1; 1712 1713 ret = gic_irq_domain_translate(d, fwspec, &hwirq, &type); 1714 if (WARN_ON_ONCE(ret)) 1715 return 0; 1716 1717 if (!fwspec_is_partitioned_ppi(fwspec, hwirq)) 1718 return d == gic_data.domain; 1719 1720 /* 1721 * If this is a PPI and we have a 4th (non-null) parameter, 1722 * then we need to match the partition domain. 1723 */ 1724 ppi_idx = __gic_get_ppi_index(hwirq); 1725 return d == partition_get_domain(gic_data.ppi_descs[ppi_idx]); 1726 } 1727 1728 static const struct irq_domain_ops gic_irq_domain_ops = { 1729 .translate = gic_irq_domain_translate, 1730 .alloc = gic_irq_domain_alloc, 1731 .free = gic_irq_domain_free, 1732 .select = gic_irq_domain_select, 1733 }; 1734 1735 static int partition_domain_translate(struct irq_domain *d, 1736 struct irq_fwspec *fwspec, 1737 unsigned long *hwirq, 1738 unsigned int *type) 1739 { 1740 unsigned long ppi_intid; 1741 struct device_node *np; 1742 unsigned int ppi_idx; 1743 int ret; 1744 1745 if (!gic_data.ppi_descs) 1746 return -ENOMEM; 1747 1748 np = of_find_node_by_phandle(fwspec->param[3]); 1749 if (WARN_ON(!np)) 1750 return -EINVAL; 1751 1752 ret = gic_irq_domain_translate(d, fwspec, &ppi_intid, type); 1753 if (WARN_ON_ONCE(ret)) 1754 return 0; 1755 1756 ppi_idx = __gic_get_ppi_index(ppi_intid); 1757 ret = partition_translate_id(gic_data.ppi_descs[ppi_idx], 1758 of_node_to_fwnode(np)); 1759 if (ret < 0) 1760 return ret; 1761 1762 *hwirq = ret; 1763 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; 1764 1765 return 0; 1766 } 1767 1768 static const struct irq_domain_ops partition_domain_ops = { 1769 .translate = partition_domain_translate, 1770 .select = gic_irq_domain_select, 1771 }; 1772 1773 static bool gic_enable_quirk_msm8996(void *data) 1774 { 1775 struct gic_chip_data *d = data; 1776 1777 d->flags |= FLAGS_WORKAROUND_GICR_WAKER_MSM8996; 1778 1779 return true; 1780 } 1781 1782 static bool gic_enable_quirk_mtk_gicr(void *data) 1783 { 1784 struct gic_chip_data *d = data; 1785 1786 d->flags |= FLAGS_WORKAROUND_MTK_GICR_SAVE; 1787 1788 return true; 1789 } 1790 1791 static bool gic_enable_quirk_cavium_38539(void *data) 1792 { 1793 struct gic_chip_data *d = data; 1794 1795 d->flags |= FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539; 1796 1797 return true; 1798 } 1799 1800 static bool gic_enable_quirk_hip06_07(void *data) 1801 { 1802 struct gic_chip_data *d = data; 1803 1804 /* 1805 * HIP06 GICD_IIDR clashes with GIC-600 product number (despite 1806 * not being an actual ARM implementation). The saving grace is 1807 * that GIC-600 doesn't have ESPI, so nothing to do in that case. 1808 * HIP07 doesn't even have a proper IIDR, and still pretends to 1809 * have ESPI. In both cases, put them right. 1810 */ 1811 if (d->rdists.gicd_typer & GICD_TYPER_ESPI) { 1812 /* Zero both ESPI and the RES0 field next to it... */ 1813 d->rdists.gicd_typer &= ~GENMASK(9, 8); 1814 return true; 1815 } 1816 1817 return false; 1818 } 1819 1820 #define T241_CHIPN_MASK GENMASK_ULL(45, 44) 1821 #define T241_CHIP_GICDA_OFFSET 0x1580000 1822 #define SMCCC_SOC_ID_T241 0x036b0241 1823 1824 static bool gic_enable_quirk_nvidia_t241(void *data) 1825 { 1826 s32 soc_id = arm_smccc_get_soc_id_version(); 1827 unsigned long chip_bmask = 0; 1828 phys_addr_t phys; 1829 u32 i; 1830 1831 /* Check JEP106 code for NVIDIA T241 chip (036b:0241) */ 1832 if ((soc_id < 0) || (soc_id != SMCCC_SOC_ID_T241)) 1833 return false; 1834 1835 /* Find the chips based on GICR regions PHYS addr */ 1836 for (i = 0; i < gic_data.nr_redist_regions; i++) { 1837 chip_bmask |= BIT(FIELD_GET(T241_CHIPN_MASK, 1838 (u64)gic_data.redist_regions[i].phys_base)); 1839 } 1840 1841 if (hweight32(chip_bmask) < 3) 1842 return false; 1843 1844 /* Setup GICD alias regions */ 1845 for (i = 0; i < ARRAY_SIZE(t241_dist_base_alias); i++) { 1846 if (chip_bmask & BIT(i)) { 1847 phys = gic_data.dist_phys_base + T241_CHIP_GICDA_OFFSET; 1848 phys |= FIELD_PREP(T241_CHIPN_MASK, i); 1849 t241_dist_base_alias[i] = ioremap(phys, SZ_64K); 1850 WARN_ON_ONCE(!t241_dist_base_alias[i]); 1851 } 1852 } 1853 static_branch_enable(&gic_nvidia_t241_erratum); 1854 return true; 1855 } 1856 1857 static bool gic_enable_quirk_asr8601(void *data) 1858 { 1859 struct gic_chip_data *d = data; 1860 1861 d->flags |= FLAGS_WORKAROUND_ASR_ERRATUM_8601001; 1862 1863 return true; 1864 } 1865 1866 static bool gic_enable_quirk_arm64_2941627(void *data) 1867 { 1868 static_branch_enable(&gic_arm64_2941627_erratum); 1869 return true; 1870 } 1871 1872 static bool rd_set_non_coherent(void *data) 1873 { 1874 struct gic_chip_data *d = data; 1875 1876 d->rdists.flags |= RDIST_FLAGS_FORCE_NON_SHAREABLE; 1877 return true; 1878 } 1879 1880 static const struct gic_quirk gic_quirks[] = { 1881 { 1882 .desc = "GICv3: Qualcomm MSM8996 broken firmware", 1883 .compatible = "qcom,msm8996-gic-v3", 1884 .init = gic_enable_quirk_msm8996, 1885 }, 1886 { 1887 .desc = "GICv3: ASR erratum 8601001", 1888 .compatible = "asr,asr8601-gic-v3", 1889 .init = gic_enable_quirk_asr8601, 1890 }, 1891 { 1892 .desc = "GICv3: Mediatek Chromebook GICR save problem", 1893 .property = "mediatek,broken-save-restore-fw", 1894 .init = gic_enable_quirk_mtk_gicr, 1895 }, 1896 { 1897 .desc = "GICv3: HIP06 erratum 161010803", 1898 .iidr = 0x0204043b, 1899 .mask = 0xffffffff, 1900 .init = gic_enable_quirk_hip06_07, 1901 }, 1902 { 1903 .desc = "GICv3: HIP07 erratum 161010803", 1904 .iidr = 0x00000000, 1905 .mask = 0xffffffff, 1906 .init = gic_enable_quirk_hip06_07, 1907 }, 1908 { 1909 /* 1910 * Reserved register accesses generate a Synchronous 1911 * External Abort. This erratum applies to: 1912 * - ThunderX: CN88xx 1913 * - OCTEON TX: CN83xx, CN81xx 1914 * - OCTEON TX2: CN93xx, CN96xx, CN98xx, CNF95xx* 1915 */ 1916 .desc = "GICv3: Cavium erratum 38539", 1917 .iidr = 0xa000034c, 1918 .mask = 0xe8f00fff, 1919 .init = gic_enable_quirk_cavium_38539, 1920 }, 1921 { 1922 .desc = "GICv3: NVIDIA erratum T241-FABRIC-4", 1923 .iidr = 0x0402043b, 1924 .mask = 0xffffffff, 1925 .init = gic_enable_quirk_nvidia_t241, 1926 }, 1927 { 1928 /* 1929 * GIC-700: 2941627 workaround - IP variant [0,1] 1930 * 1931 */ 1932 .desc = "GICv3: ARM64 erratum 2941627", 1933 .iidr = 0x0400043b, 1934 .mask = 0xff0e0fff, 1935 .init = gic_enable_quirk_arm64_2941627, 1936 }, 1937 { 1938 /* 1939 * GIC-700: 2941627 workaround - IP variant [2] 1940 */ 1941 .desc = "GICv3: ARM64 erratum 2941627", 1942 .iidr = 0x0402043b, 1943 .mask = 0xff0f0fff, 1944 .init = gic_enable_quirk_arm64_2941627, 1945 }, 1946 { 1947 .desc = "GICv3: non-coherent attribute", 1948 .property = "dma-noncoherent", 1949 .init = rd_set_non_coherent, 1950 }, 1951 { 1952 } 1953 }; 1954 1955 static void gic_enable_nmi_support(void) 1956 { 1957 int i; 1958 1959 if (!gic_prio_masking_enabled()) 1960 return; 1961 1962 if (gic_data.flags & FLAGS_WORKAROUND_MTK_GICR_SAVE) { 1963 pr_warn("Skipping NMI enable due to firmware issues\n"); 1964 return; 1965 } 1966 1967 rdist_nmi_refs = kcalloc(gic_data.ppi_nr + SGI_NR, 1968 sizeof(*rdist_nmi_refs), GFP_KERNEL); 1969 if (!rdist_nmi_refs) 1970 return; 1971 1972 for (i = 0; i < gic_data.ppi_nr + SGI_NR; i++) 1973 refcount_set(&rdist_nmi_refs[i], 0); 1974 1975 pr_info("Pseudo-NMIs enabled using %s ICC_PMR_EL1 synchronisation\n", 1976 gic_has_relaxed_pmr_sync() ? "relaxed" : "forced"); 1977 1978 /* 1979 * How priority values are used by the GIC depends on two things: 1980 * the security state of the GIC (controlled by the GICD_CTRL.DS bit) 1981 * and if Group 0 interrupts can be delivered to Linux in the non-secure 1982 * world as FIQs (controlled by the SCR_EL3.FIQ bit). These affect the 1983 * ICC_PMR_EL1 register and the priority that software assigns to 1984 * interrupts: 1985 * 1986 * GICD_CTRL.DS | SCR_EL3.FIQ | ICC_PMR_EL1 | Group 1 priority 1987 * ----------------------------------------------------------- 1988 * 1 | - | unchanged | unchanged 1989 * ----------------------------------------------------------- 1990 * 0 | 1 | non-secure | non-secure 1991 * ----------------------------------------------------------- 1992 * 0 | 0 | unchanged | non-secure 1993 * 1994 * where non-secure means that the value is right-shifted by one and the 1995 * MSB bit set, to make it fit in the non-secure priority range. 1996 * 1997 * In the first two cases, where ICC_PMR_EL1 and the interrupt priority 1998 * are both either modified or unchanged, we can use the same set of 1999 * priorities. 2000 * 2001 * In the last case, where only the interrupt priorities are modified to 2002 * be in the non-secure range, we use a different PMR value to mask IRQs 2003 * and the rest of the values that we use remain unchanged. 2004 */ 2005 if (gic_has_group0() && !gic_dist_security_disabled()) 2006 static_branch_enable(&gic_nonsecure_priorities); 2007 2008 static_branch_enable(&supports_pseudo_nmis); 2009 2010 if (static_branch_likely(&supports_deactivate_key)) 2011 gic_eoimode1_chip.flags |= IRQCHIP_SUPPORTS_NMI; 2012 else 2013 gic_chip.flags |= IRQCHIP_SUPPORTS_NMI; 2014 } 2015 2016 static int __init gic_init_bases(phys_addr_t dist_phys_base, 2017 void __iomem *dist_base, 2018 struct redist_region *rdist_regs, 2019 u32 nr_redist_regions, 2020 u64 redist_stride, 2021 struct fwnode_handle *handle) 2022 { 2023 u32 typer; 2024 int err; 2025 2026 if (!is_hyp_mode_available()) 2027 static_branch_disable(&supports_deactivate_key); 2028 2029 if (static_branch_likely(&supports_deactivate_key)) 2030 pr_info("GIC: Using split EOI/Deactivate mode\n"); 2031 2032 gic_data.fwnode = handle; 2033 gic_data.dist_phys_base = dist_phys_base; 2034 gic_data.dist_base = dist_base; 2035 gic_data.redist_regions = rdist_regs; 2036 gic_data.nr_redist_regions = nr_redist_regions; 2037 gic_data.redist_stride = redist_stride; 2038 2039 /* 2040 * Find out how many interrupts are supported. 2041 */ 2042 typer = readl_relaxed(gic_data.dist_base + GICD_TYPER); 2043 gic_data.rdists.gicd_typer = typer; 2044 2045 gic_enable_quirks(readl_relaxed(gic_data.dist_base + GICD_IIDR), 2046 gic_quirks, &gic_data); 2047 2048 pr_info("%d SPIs implemented\n", GIC_LINE_NR - 32); 2049 pr_info("%d Extended SPIs implemented\n", GIC_ESPI_NR); 2050 2051 /* 2052 * ThunderX1 explodes on reading GICD_TYPER2, in violation of the 2053 * architecture spec (which says that reserved registers are RES0). 2054 */ 2055 if (!(gic_data.flags & FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539)) 2056 gic_data.rdists.gicd_typer2 = readl_relaxed(gic_data.dist_base + GICD_TYPER2); 2057 2058 gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops, 2059 &gic_data); 2060 gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist)); 2061 if (!static_branch_unlikely(&gic_nvidia_t241_erratum)) { 2062 /* Disable GICv4.x features for the erratum T241-FABRIC-4 */ 2063 gic_data.rdists.has_rvpeid = true; 2064 gic_data.rdists.has_vlpis = true; 2065 gic_data.rdists.has_direct_lpi = true; 2066 gic_data.rdists.has_vpend_valid_dirty = true; 2067 } 2068 2069 if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) { 2070 err = -ENOMEM; 2071 goto out_free; 2072 } 2073 2074 irq_domain_update_bus_token(gic_data.domain, DOMAIN_BUS_WIRED); 2075 2076 gic_data.has_rss = !!(typer & GICD_TYPER_RSS); 2077 2078 if (typer & GICD_TYPER_MBIS) { 2079 err = mbi_init(handle, gic_data.domain); 2080 if (err) 2081 pr_err("Failed to initialize MBIs\n"); 2082 } 2083 2084 set_handle_irq(gic_handle_irq); 2085 2086 gic_update_rdist_properties(); 2087 2088 gic_dist_init(); 2089 gic_cpu_init(); 2090 gic_enable_nmi_support(); 2091 gic_smp_init(); 2092 gic_cpu_pm_init(); 2093 2094 if (gic_dist_supports_lpis()) { 2095 its_init(handle, &gic_data.rdists, gic_data.domain); 2096 its_cpu_init(); 2097 its_lpi_memreserve_init(); 2098 } else { 2099 if (IS_ENABLED(CONFIG_ARM_GIC_V2M)) 2100 gicv2m_init(handle, gic_data.domain); 2101 } 2102 2103 return 0; 2104 2105 out_free: 2106 if (gic_data.domain) 2107 irq_domain_remove(gic_data.domain); 2108 free_percpu(gic_data.rdists.rdist); 2109 return err; 2110 } 2111 2112 static int __init gic_validate_dist_version(void __iomem *dist_base) 2113 { 2114 u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; 2115 2116 if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) 2117 return -ENODEV; 2118 2119 return 0; 2120 } 2121 2122 /* Create all possible partitions at boot time */ 2123 static void __init gic_populate_ppi_partitions(struct device_node *gic_node) 2124 { 2125 struct device_node *parts_node, *child_part; 2126 int part_idx = 0, i; 2127 int nr_parts; 2128 struct partition_affinity *parts; 2129 2130 parts_node = of_get_child_by_name(gic_node, "ppi-partitions"); 2131 if (!parts_node) 2132 return; 2133 2134 gic_data.ppi_descs = kcalloc(gic_data.ppi_nr, sizeof(*gic_data.ppi_descs), GFP_KERNEL); 2135 if (!gic_data.ppi_descs) 2136 goto out_put_node; 2137 2138 nr_parts = of_get_child_count(parts_node); 2139 2140 if (!nr_parts) 2141 goto out_put_node; 2142 2143 parts = kcalloc(nr_parts, sizeof(*parts), GFP_KERNEL); 2144 if (WARN_ON(!parts)) 2145 goto out_put_node; 2146 2147 for_each_child_of_node(parts_node, child_part) { 2148 struct partition_affinity *part; 2149 int n; 2150 2151 part = &parts[part_idx]; 2152 2153 part->partition_id = of_node_to_fwnode(child_part); 2154 2155 pr_info("GIC: PPI partition %pOFn[%d] { ", 2156 child_part, part_idx); 2157 2158 n = of_property_count_elems_of_size(child_part, "affinity", 2159 sizeof(u32)); 2160 WARN_ON(n <= 0); 2161 2162 for (i = 0; i < n; i++) { 2163 int err, cpu; 2164 u32 cpu_phandle; 2165 struct device_node *cpu_node; 2166 2167 err = of_property_read_u32_index(child_part, "affinity", 2168 i, &cpu_phandle); 2169 if (WARN_ON(err)) 2170 continue; 2171 2172 cpu_node = of_find_node_by_phandle(cpu_phandle); 2173 if (WARN_ON(!cpu_node)) 2174 continue; 2175 2176 cpu = of_cpu_node_to_id(cpu_node); 2177 if (WARN_ON(cpu < 0)) { 2178 of_node_put(cpu_node); 2179 continue; 2180 } 2181 2182 pr_cont("%pOF[%d] ", cpu_node, cpu); 2183 2184 cpumask_set_cpu(cpu, &part->mask); 2185 of_node_put(cpu_node); 2186 } 2187 2188 pr_cont("}\n"); 2189 part_idx++; 2190 } 2191 2192 for (i = 0; i < gic_data.ppi_nr; i++) { 2193 unsigned int irq; 2194 struct partition_desc *desc; 2195 struct irq_fwspec ppi_fwspec = { 2196 .fwnode = gic_data.fwnode, 2197 .param_count = 3, 2198 .param = { 2199 [0] = GIC_IRQ_TYPE_PARTITION, 2200 [1] = i, 2201 [2] = IRQ_TYPE_NONE, 2202 }, 2203 }; 2204 2205 irq = irq_create_fwspec_mapping(&ppi_fwspec); 2206 if (WARN_ON(!irq)) 2207 continue; 2208 desc = partition_create_desc(gic_data.fwnode, parts, nr_parts, 2209 irq, &partition_domain_ops); 2210 if (WARN_ON(!desc)) 2211 continue; 2212 2213 gic_data.ppi_descs[i] = desc; 2214 } 2215 2216 out_put_node: 2217 of_node_put(parts_node); 2218 } 2219 2220 static void __init gic_of_setup_kvm_info(struct device_node *node) 2221 { 2222 int ret; 2223 struct resource r; 2224 u32 gicv_idx; 2225 2226 gic_v3_kvm_info.type = GIC_V3; 2227 2228 gic_v3_kvm_info.maint_irq = irq_of_parse_and_map(node, 0); 2229 if (!gic_v3_kvm_info.maint_irq) 2230 return; 2231 2232 if (of_property_read_u32(node, "#redistributor-regions", 2233 &gicv_idx)) 2234 gicv_idx = 1; 2235 2236 gicv_idx += 3; /* Also skip GICD, GICC, GICH */ 2237 ret = of_address_to_resource(node, gicv_idx, &r); 2238 if (!ret) 2239 gic_v3_kvm_info.vcpu = r; 2240 2241 gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis; 2242 gic_v3_kvm_info.has_v4_1 = gic_data.rdists.has_rvpeid; 2243 vgic_set_kvm_info(&gic_v3_kvm_info); 2244 } 2245 2246 static void gic_request_region(resource_size_t base, resource_size_t size, 2247 const char *name) 2248 { 2249 if (!request_mem_region(base, size, name)) 2250 pr_warn_once(FW_BUG "%s region %pa has overlapping address\n", 2251 name, &base); 2252 } 2253 2254 static void __iomem *gic_of_iomap(struct device_node *node, int idx, 2255 const char *name, struct resource *res) 2256 { 2257 void __iomem *base; 2258 int ret; 2259 2260 ret = of_address_to_resource(node, idx, res); 2261 if (ret) 2262 return IOMEM_ERR_PTR(ret); 2263 2264 gic_request_region(res->start, resource_size(res), name); 2265 base = of_iomap(node, idx); 2266 2267 return base ?: IOMEM_ERR_PTR(-ENOMEM); 2268 } 2269 2270 static int __init gic_of_init(struct device_node *node, struct device_node *parent) 2271 { 2272 phys_addr_t dist_phys_base; 2273 void __iomem *dist_base; 2274 struct redist_region *rdist_regs; 2275 struct resource res; 2276 u64 redist_stride; 2277 u32 nr_redist_regions; 2278 int err, i; 2279 2280 dist_base = gic_of_iomap(node, 0, "GICD", &res); 2281 if (IS_ERR(dist_base)) { 2282 pr_err("%pOF: unable to map gic dist registers\n", node); 2283 return PTR_ERR(dist_base); 2284 } 2285 2286 dist_phys_base = res.start; 2287 2288 err = gic_validate_dist_version(dist_base); 2289 if (err) { 2290 pr_err("%pOF: no distributor detected, giving up\n", node); 2291 goto out_unmap_dist; 2292 } 2293 2294 if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions)) 2295 nr_redist_regions = 1; 2296 2297 rdist_regs = kcalloc(nr_redist_regions, sizeof(*rdist_regs), 2298 GFP_KERNEL); 2299 if (!rdist_regs) { 2300 err = -ENOMEM; 2301 goto out_unmap_dist; 2302 } 2303 2304 for (i = 0; i < nr_redist_regions; i++) { 2305 rdist_regs[i].redist_base = gic_of_iomap(node, 1 + i, "GICR", &res); 2306 if (IS_ERR(rdist_regs[i].redist_base)) { 2307 pr_err("%pOF: couldn't map region %d\n", node, i); 2308 err = -ENODEV; 2309 goto out_unmap_rdist; 2310 } 2311 rdist_regs[i].phys_base = res.start; 2312 } 2313 2314 if (of_property_read_u64(node, "redistributor-stride", &redist_stride)) 2315 redist_stride = 0; 2316 2317 gic_enable_of_quirks(node, gic_quirks, &gic_data); 2318 2319 err = gic_init_bases(dist_phys_base, dist_base, rdist_regs, 2320 nr_redist_regions, redist_stride, &node->fwnode); 2321 if (err) 2322 goto out_unmap_rdist; 2323 2324 gic_populate_ppi_partitions(node); 2325 2326 if (static_branch_likely(&supports_deactivate_key)) 2327 gic_of_setup_kvm_info(node); 2328 return 0; 2329 2330 out_unmap_rdist: 2331 for (i = 0; i < nr_redist_regions; i++) 2332 if (rdist_regs[i].redist_base && !IS_ERR(rdist_regs[i].redist_base)) 2333 iounmap(rdist_regs[i].redist_base); 2334 kfree(rdist_regs); 2335 out_unmap_dist: 2336 iounmap(dist_base); 2337 return err; 2338 } 2339 2340 IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init); 2341 2342 #ifdef CONFIG_ACPI 2343 static struct 2344 { 2345 void __iomem *dist_base; 2346 struct redist_region *redist_regs; 2347 u32 nr_redist_regions; 2348 bool single_redist; 2349 int enabled_rdists; 2350 u32 maint_irq; 2351 int maint_irq_mode; 2352 phys_addr_t vcpu_base; 2353 } acpi_data __initdata; 2354 2355 static void __init 2356 gic_acpi_register_redist(phys_addr_t phys_base, void __iomem *redist_base) 2357 { 2358 static int count = 0; 2359 2360 acpi_data.redist_regs[count].phys_base = phys_base; 2361 acpi_data.redist_regs[count].redist_base = redist_base; 2362 acpi_data.redist_regs[count].single_redist = acpi_data.single_redist; 2363 count++; 2364 } 2365 2366 static int __init 2367 gic_acpi_parse_madt_redist(union acpi_subtable_headers *header, 2368 const unsigned long end) 2369 { 2370 struct acpi_madt_generic_redistributor *redist = 2371 (struct acpi_madt_generic_redistributor *)header; 2372 void __iomem *redist_base; 2373 2374 redist_base = ioremap(redist->base_address, redist->length); 2375 if (!redist_base) { 2376 pr_err("Couldn't map GICR region @%llx\n", redist->base_address); 2377 return -ENOMEM; 2378 } 2379 gic_request_region(redist->base_address, redist->length, "GICR"); 2380 2381 gic_acpi_register_redist(redist->base_address, redist_base); 2382 return 0; 2383 } 2384 2385 static int __init 2386 gic_acpi_parse_madt_gicc(union acpi_subtable_headers *header, 2387 const unsigned long end) 2388 { 2389 struct acpi_madt_generic_interrupt *gicc = 2390 (struct acpi_madt_generic_interrupt *)header; 2391 u32 reg = readl_relaxed(acpi_data.dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; 2392 u32 size = reg == GIC_PIDR2_ARCH_GICv4 ? SZ_64K * 4 : SZ_64K * 2; 2393 void __iomem *redist_base; 2394 2395 if (!acpi_gicc_is_usable(gicc)) 2396 return 0; 2397 2398 redist_base = ioremap(gicc->gicr_base_address, size); 2399 if (!redist_base) 2400 return -ENOMEM; 2401 gic_request_region(gicc->gicr_base_address, size, "GICR"); 2402 2403 gic_acpi_register_redist(gicc->gicr_base_address, redist_base); 2404 return 0; 2405 } 2406 2407 static int __init gic_acpi_collect_gicr_base(void) 2408 { 2409 acpi_tbl_entry_handler redist_parser; 2410 enum acpi_madt_type type; 2411 2412 if (acpi_data.single_redist) { 2413 type = ACPI_MADT_TYPE_GENERIC_INTERRUPT; 2414 redist_parser = gic_acpi_parse_madt_gicc; 2415 } else { 2416 type = ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR; 2417 redist_parser = gic_acpi_parse_madt_redist; 2418 } 2419 2420 /* Collect redistributor base addresses in GICR entries */ 2421 if (acpi_table_parse_madt(type, redist_parser, 0) > 0) 2422 return 0; 2423 2424 pr_info("No valid GICR entries exist\n"); 2425 return -ENODEV; 2426 } 2427 2428 static int __init gic_acpi_match_gicr(union acpi_subtable_headers *header, 2429 const unsigned long end) 2430 { 2431 /* Subtable presence means that redist exists, that's it */ 2432 return 0; 2433 } 2434 2435 static int __init gic_acpi_match_gicc(union acpi_subtable_headers *header, 2436 const unsigned long end) 2437 { 2438 struct acpi_madt_generic_interrupt *gicc = 2439 (struct acpi_madt_generic_interrupt *)header; 2440 2441 /* 2442 * If GICC is enabled and has valid gicr base address, then it means 2443 * GICR base is presented via GICC 2444 */ 2445 if (acpi_gicc_is_usable(gicc) && gicc->gicr_base_address) { 2446 acpi_data.enabled_rdists++; 2447 return 0; 2448 } 2449 2450 /* 2451 * It's perfectly valid firmware can pass disabled GICC entry, driver 2452 * should not treat as errors, skip the entry instead of probe fail. 2453 */ 2454 if (!acpi_gicc_is_usable(gicc)) 2455 return 0; 2456 2457 return -ENODEV; 2458 } 2459 2460 static int __init gic_acpi_count_gicr_regions(void) 2461 { 2462 int count; 2463 2464 /* 2465 * Count how many redistributor regions we have. It is not allowed 2466 * to mix redistributor description, GICR and GICC subtables have to be 2467 * mutually exclusive. 2468 */ 2469 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, 2470 gic_acpi_match_gicr, 0); 2471 if (count > 0) { 2472 acpi_data.single_redist = false; 2473 return count; 2474 } 2475 2476 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, 2477 gic_acpi_match_gicc, 0); 2478 if (count > 0) { 2479 acpi_data.single_redist = true; 2480 count = acpi_data.enabled_rdists; 2481 } 2482 2483 return count; 2484 } 2485 2486 static bool __init acpi_validate_gic_table(struct acpi_subtable_header *header, 2487 struct acpi_probe_entry *ape) 2488 { 2489 struct acpi_madt_generic_distributor *dist; 2490 int count; 2491 2492 dist = (struct acpi_madt_generic_distributor *)header; 2493 if (dist->version != ape->driver_data) 2494 return false; 2495 2496 /* We need to do that exercise anyway, the sooner the better */ 2497 count = gic_acpi_count_gicr_regions(); 2498 if (count <= 0) 2499 return false; 2500 2501 acpi_data.nr_redist_regions = count; 2502 return true; 2503 } 2504 2505 static int __init gic_acpi_parse_virt_madt_gicc(union acpi_subtable_headers *header, 2506 const unsigned long end) 2507 { 2508 struct acpi_madt_generic_interrupt *gicc = 2509 (struct acpi_madt_generic_interrupt *)header; 2510 int maint_irq_mode; 2511 static int first_madt = true; 2512 2513 if (!acpi_gicc_is_usable(gicc)) 2514 return 0; 2515 2516 maint_irq_mode = (gicc->flags & ACPI_MADT_VGIC_IRQ_MODE) ? 2517 ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE; 2518 2519 if (first_madt) { 2520 first_madt = false; 2521 2522 acpi_data.maint_irq = gicc->vgic_interrupt; 2523 acpi_data.maint_irq_mode = maint_irq_mode; 2524 acpi_data.vcpu_base = gicc->gicv_base_address; 2525 2526 return 0; 2527 } 2528 2529 /* 2530 * The maintenance interrupt and GICV should be the same for every CPU 2531 */ 2532 if ((acpi_data.maint_irq != gicc->vgic_interrupt) || 2533 (acpi_data.maint_irq_mode != maint_irq_mode) || 2534 (acpi_data.vcpu_base != gicc->gicv_base_address)) 2535 return -EINVAL; 2536 2537 return 0; 2538 } 2539 2540 static bool __init gic_acpi_collect_virt_info(void) 2541 { 2542 int count; 2543 2544 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, 2545 gic_acpi_parse_virt_madt_gicc, 0); 2546 2547 return (count > 0); 2548 } 2549 2550 #define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K) 2551 #define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K) 2552 #define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K) 2553 2554 static void __init gic_acpi_setup_kvm_info(void) 2555 { 2556 int irq; 2557 2558 if (!gic_acpi_collect_virt_info()) { 2559 pr_warn("Unable to get hardware information used for virtualization\n"); 2560 return; 2561 } 2562 2563 gic_v3_kvm_info.type = GIC_V3; 2564 2565 irq = acpi_register_gsi(NULL, acpi_data.maint_irq, 2566 acpi_data.maint_irq_mode, 2567 ACPI_ACTIVE_HIGH); 2568 if (irq <= 0) 2569 return; 2570 2571 gic_v3_kvm_info.maint_irq = irq; 2572 2573 if (acpi_data.vcpu_base) { 2574 struct resource *vcpu = &gic_v3_kvm_info.vcpu; 2575 2576 vcpu->flags = IORESOURCE_MEM; 2577 vcpu->start = acpi_data.vcpu_base; 2578 vcpu->end = vcpu->start + ACPI_GICV2_VCPU_MEM_SIZE - 1; 2579 } 2580 2581 gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis; 2582 gic_v3_kvm_info.has_v4_1 = gic_data.rdists.has_rvpeid; 2583 vgic_set_kvm_info(&gic_v3_kvm_info); 2584 } 2585 2586 static struct fwnode_handle *gsi_domain_handle; 2587 2588 static struct fwnode_handle *gic_v3_get_gsi_domain_id(u32 gsi) 2589 { 2590 return gsi_domain_handle; 2591 } 2592 2593 static int __init 2594 gic_acpi_init(union acpi_subtable_headers *header, const unsigned long end) 2595 { 2596 struct acpi_madt_generic_distributor *dist; 2597 size_t size; 2598 int i, err; 2599 2600 /* Get distributor base address */ 2601 dist = (struct acpi_madt_generic_distributor *)header; 2602 acpi_data.dist_base = ioremap(dist->base_address, 2603 ACPI_GICV3_DIST_MEM_SIZE); 2604 if (!acpi_data.dist_base) { 2605 pr_err("Unable to map GICD registers\n"); 2606 return -ENOMEM; 2607 } 2608 gic_request_region(dist->base_address, ACPI_GICV3_DIST_MEM_SIZE, "GICD"); 2609 2610 err = gic_validate_dist_version(acpi_data.dist_base); 2611 if (err) { 2612 pr_err("No distributor detected at @%p, giving up\n", 2613 acpi_data.dist_base); 2614 goto out_dist_unmap; 2615 } 2616 2617 size = sizeof(*acpi_data.redist_regs) * acpi_data.nr_redist_regions; 2618 acpi_data.redist_regs = kzalloc(size, GFP_KERNEL); 2619 if (!acpi_data.redist_regs) { 2620 err = -ENOMEM; 2621 goto out_dist_unmap; 2622 } 2623 2624 err = gic_acpi_collect_gicr_base(); 2625 if (err) 2626 goto out_redist_unmap; 2627 2628 gsi_domain_handle = irq_domain_alloc_fwnode(&dist->base_address); 2629 if (!gsi_domain_handle) { 2630 err = -ENOMEM; 2631 goto out_redist_unmap; 2632 } 2633 2634 err = gic_init_bases(dist->base_address, acpi_data.dist_base, 2635 acpi_data.redist_regs, acpi_data.nr_redist_regions, 2636 0, gsi_domain_handle); 2637 if (err) 2638 goto out_fwhandle_free; 2639 2640 acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, gic_v3_get_gsi_domain_id); 2641 2642 if (static_branch_likely(&supports_deactivate_key)) 2643 gic_acpi_setup_kvm_info(); 2644 2645 return 0; 2646 2647 out_fwhandle_free: 2648 irq_domain_free_fwnode(gsi_domain_handle); 2649 out_redist_unmap: 2650 for (i = 0; i < acpi_data.nr_redist_regions; i++) 2651 if (acpi_data.redist_regs[i].redist_base) 2652 iounmap(acpi_data.redist_regs[i].redist_base); 2653 kfree(acpi_data.redist_regs); 2654 out_dist_unmap: 2655 iounmap(acpi_data.dist_base); 2656 return err; 2657 } 2658 IRQCHIP_ACPI_DECLARE(gic_v3, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 2659 acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V3, 2660 gic_acpi_init); 2661 IRQCHIP_ACPI_DECLARE(gic_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 2662 acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V4, 2663 gic_acpi_init); 2664 IRQCHIP_ACPI_DECLARE(gic_v3_or_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 2665 acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_NONE, 2666 gic_acpi_init); 2667 #endif 2668