xref: /linux/drivers/irqchip/irq-gic-v2m.c (revision 0883c2c06fb5bcf5b9e008270827e63c09a88c1e) 
1 /*
2  * ARM GIC v2m MSI(-X) support
3  * Support for Message Signaled Interrupts for systems that
4  * implement ARM Generic Interrupt Controller: GICv2m.
5  *
6  * Copyright (C) 2014 Advanced Micro Devices, Inc.
7  * Authors: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
8  *	    Harish Kasiviswanathan <harish.kasiviswanathan@amd.com>
9  *	    Brandon Anderson <brandon.anderson@amd.com>
10  *
11  * This program is free software; you can redistribute it and/or modify it
12  * under the terms of the GNU General Public License version 2 as published
13  * by the Free Software Foundation.
14  */
15 
16 #define pr_fmt(fmt) "GICv2m: " fmt
17 
18 #include <linux/acpi.h>
19 #include <linux/irq.h>
20 #include <linux/irqdomain.h>
21 #include <linux/kernel.h>
22 #include <linux/msi.h>
23 #include <linux/of_address.h>
24 #include <linux/of_pci.h>
25 #include <linux/slab.h>
26 #include <linux/spinlock.h>
27 
28 /*
29 * MSI_TYPER:
30 *     [31:26] Reserved
31 *     [25:16] lowest SPI assigned to MSI
32 *     [15:10] Reserved
33 *     [9:0]   Numer of SPIs assigned to MSI
34 */
35 #define V2M_MSI_TYPER		       0x008
36 #define V2M_MSI_TYPER_BASE_SHIFT       16
37 #define V2M_MSI_TYPER_BASE_MASK	       0x3FF
38 #define V2M_MSI_TYPER_NUM_MASK	       0x3FF
39 #define V2M_MSI_SETSPI_NS	       0x040
40 #define V2M_MIN_SPI		       32
41 #define V2M_MAX_SPI		       1019
42 #define V2M_MSI_IIDR		       0xFCC
43 
44 #define V2M_MSI_TYPER_BASE_SPI(x)      \
45 	       (((x) >> V2M_MSI_TYPER_BASE_SHIFT) & V2M_MSI_TYPER_BASE_MASK)
46 
47 #define V2M_MSI_TYPER_NUM_SPI(x)       ((x) & V2M_MSI_TYPER_NUM_MASK)
48 
49 /* APM X-Gene with GICv2m MSI_IIDR register value */
50 #define XGENE_GICV2M_MSI_IIDR		0x06000170
51 
52 /* Broadcom NS2 GICv2m MSI_IIDR register value */
53 #define BCM_NS2_GICV2M_MSI_IIDR		0x0000013f
54 
55 /* List of flags for specific v2m implementation */
56 #define GICV2M_NEEDS_SPI_OFFSET		0x00000001
57 
58 static LIST_HEAD(v2m_nodes);
59 static DEFINE_SPINLOCK(v2m_lock);
60 
61 struct v2m_data {
62 	struct list_head entry;
63 	struct fwnode_handle *fwnode;
64 	struct resource res;	/* GICv2m resource */
65 	void __iomem *base;	/* GICv2m virt address */
66 	u32 spi_start;		/* The SPI number that MSIs start */
67 	u32 nr_spis;		/* The number of SPIs for MSIs */
68 	u32 spi_offset;		/* offset to be subtracted from SPI number */
69 	unsigned long *bm;	/* MSI vector bitmap */
70 	u32 flags;		/* v2m flags for specific implementation */
71 };
72 
73 static void gicv2m_mask_msi_irq(struct irq_data *d)
74 {
75 	pci_msi_mask_irq(d);
76 	irq_chip_mask_parent(d);
77 }
78 
79 static void gicv2m_unmask_msi_irq(struct irq_data *d)
80 {
81 	pci_msi_unmask_irq(d);
82 	irq_chip_unmask_parent(d);
83 }
84 
85 static struct irq_chip gicv2m_msi_irq_chip = {
86 	.name			= "MSI",
87 	.irq_mask		= gicv2m_mask_msi_irq,
88 	.irq_unmask		= gicv2m_unmask_msi_irq,
89 	.irq_eoi		= irq_chip_eoi_parent,
90 	.irq_write_msi_msg	= pci_msi_domain_write_msg,
91 };
92 
93 static struct msi_domain_info gicv2m_msi_domain_info = {
94 	.flags	= (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
95 		   MSI_FLAG_PCI_MSIX),
96 	.chip	= &gicv2m_msi_irq_chip,
97 };
98 
99 static void gicv2m_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
100 {
101 	struct v2m_data *v2m = irq_data_get_irq_chip_data(data);
102 	phys_addr_t addr = v2m->res.start + V2M_MSI_SETSPI_NS;
103 
104 	msg->address_hi = upper_32_bits(addr);
105 	msg->address_lo = lower_32_bits(addr);
106 	msg->data = data->hwirq;
107 
108 	if (v2m->flags & GICV2M_NEEDS_SPI_OFFSET)
109 		msg->data -= v2m->spi_offset;
110 }
111 
112 static struct irq_chip gicv2m_irq_chip = {
113 	.name			= "GICv2m",
114 	.irq_mask		= irq_chip_mask_parent,
115 	.irq_unmask		= irq_chip_unmask_parent,
116 	.irq_eoi		= irq_chip_eoi_parent,
117 	.irq_set_affinity	= irq_chip_set_affinity_parent,
118 	.irq_compose_msi_msg	= gicv2m_compose_msi_msg,
119 };
120 
121 static int gicv2m_irq_gic_domain_alloc(struct irq_domain *domain,
122 				       unsigned int virq,
123 				       irq_hw_number_t hwirq)
124 {
125 	struct irq_fwspec fwspec;
126 	struct irq_data *d;
127 	int err;
128 
129 	if (is_of_node(domain->parent->fwnode)) {
130 		fwspec.fwnode = domain->parent->fwnode;
131 		fwspec.param_count = 3;
132 		fwspec.param[0] = 0;
133 		fwspec.param[1] = hwirq - 32;
134 		fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
135 	} else if (is_fwnode_irqchip(domain->parent->fwnode)) {
136 		fwspec.fwnode = domain->parent->fwnode;
137 		fwspec.param_count = 2;
138 		fwspec.param[0] = hwirq;
139 		fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
140 	} else {
141 		return -EINVAL;
142 	}
143 
144 	err = irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
145 	if (err)
146 		return err;
147 
148 	/* Configure the interrupt line to be edge */
149 	d = irq_domain_get_irq_data(domain->parent, virq);
150 	d->chip->irq_set_type(d, IRQ_TYPE_EDGE_RISING);
151 	return 0;
152 }
153 
154 static void gicv2m_unalloc_msi(struct v2m_data *v2m, unsigned int hwirq)
155 {
156 	int pos;
157 
158 	pos = hwirq - v2m->spi_start;
159 	if (pos < 0 || pos >= v2m->nr_spis) {
160 		pr_err("Failed to teardown msi. Invalid hwirq %d\n", hwirq);
161 		return;
162 	}
163 
164 	spin_lock(&v2m_lock);
165 	__clear_bit(pos, v2m->bm);
166 	spin_unlock(&v2m_lock);
167 }
168 
169 static int gicv2m_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
170 				   unsigned int nr_irqs, void *args)
171 {
172 	struct v2m_data *v2m = NULL, *tmp;
173 	int hwirq, offset, err = 0;
174 
175 	spin_lock(&v2m_lock);
176 	list_for_each_entry(tmp, &v2m_nodes, entry) {
177 		offset = find_first_zero_bit(tmp->bm, tmp->nr_spis);
178 		if (offset < tmp->nr_spis) {
179 			__set_bit(offset, tmp->bm);
180 			v2m = tmp;
181 			break;
182 		}
183 	}
184 	spin_unlock(&v2m_lock);
185 
186 	if (!v2m)
187 		return -ENOSPC;
188 
189 	hwirq = v2m->spi_start + offset;
190 
191 	err = gicv2m_irq_gic_domain_alloc(domain, virq, hwirq);
192 	if (err) {
193 		gicv2m_unalloc_msi(v2m, hwirq);
194 		return err;
195 	}
196 
197 	irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
198 				      &gicv2m_irq_chip, v2m);
199 
200 	return 0;
201 }
202 
203 static void gicv2m_irq_domain_free(struct irq_domain *domain,
204 				   unsigned int virq, unsigned int nr_irqs)
205 {
206 	struct irq_data *d = irq_domain_get_irq_data(domain, virq);
207 	struct v2m_data *v2m = irq_data_get_irq_chip_data(d);
208 
209 	BUG_ON(nr_irqs != 1);
210 	gicv2m_unalloc_msi(v2m, d->hwirq);
211 	irq_domain_free_irqs_parent(domain, virq, nr_irqs);
212 }
213 
214 static const struct irq_domain_ops gicv2m_domain_ops = {
215 	.alloc			= gicv2m_irq_domain_alloc,
216 	.free			= gicv2m_irq_domain_free,
217 };
218 
219 static bool is_msi_spi_valid(u32 base, u32 num)
220 {
221 	if (base < V2M_MIN_SPI) {
222 		pr_err("Invalid MSI base SPI (base:%u)\n", base);
223 		return false;
224 	}
225 
226 	if ((num == 0) || (base + num > V2M_MAX_SPI)) {
227 		pr_err("Number of SPIs (%u) exceed maximum (%u)\n",
228 		       num, V2M_MAX_SPI - V2M_MIN_SPI + 1);
229 		return false;
230 	}
231 
232 	return true;
233 }
234 
235 static struct irq_chip gicv2m_pmsi_irq_chip = {
236 	.name			= "pMSI",
237 };
238 
239 static struct msi_domain_ops gicv2m_pmsi_ops = {
240 };
241 
242 static struct msi_domain_info gicv2m_pmsi_domain_info = {
243 	.flags	= (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS),
244 	.ops	= &gicv2m_pmsi_ops,
245 	.chip	= &gicv2m_pmsi_irq_chip,
246 };
247 
248 static void gicv2m_teardown(void)
249 {
250 	struct v2m_data *v2m, *tmp;
251 
252 	list_for_each_entry_safe(v2m, tmp, &v2m_nodes, entry) {
253 		list_del(&v2m->entry);
254 		kfree(v2m->bm);
255 		iounmap(v2m->base);
256 		of_node_put(to_of_node(v2m->fwnode));
257 		if (is_fwnode_irqchip(v2m->fwnode))
258 			irq_domain_free_fwnode(v2m->fwnode);
259 		kfree(v2m);
260 	}
261 }
262 
263 static int gicv2m_allocate_domains(struct irq_domain *parent)
264 {
265 	struct irq_domain *inner_domain, *pci_domain, *plat_domain;
266 	struct v2m_data *v2m;
267 
268 	v2m = list_first_entry_or_null(&v2m_nodes, struct v2m_data, entry);
269 	if (!v2m)
270 		return 0;
271 
272 	inner_domain = irq_domain_create_tree(v2m->fwnode,
273 					      &gicv2m_domain_ops, v2m);
274 	if (!inner_domain) {
275 		pr_err("Failed to create GICv2m domain\n");
276 		return -ENOMEM;
277 	}
278 
279 	inner_domain->bus_token = DOMAIN_BUS_NEXUS;
280 	inner_domain->parent = parent;
281 	pci_domain = pci_msi_create_irq_domain(v2m->fwnode,
282 					       &gicv2m_msi_domain_info,
283 					       inner_domain);
284 	plat_domain = platform_msi_create_irq_domain(v2m->fwnode,
285 						     &gicv2m_pmsi_domain_info,
286 						     inner_domain);
287 	if (!pci_domain || !plat_domain) {
288 		pr_err("Failed to create MSI domains\n");
289 		if (plat_domain)
290 			irq_domain_remove(plat_domain);
291 		if (pci_domain)
292 			irq_domain_remove(pci_domain);
293 		irq_domain_remove(inner_domain);
294 		return -ENOMEM;
295 	}
296 
297 	return 0;
298 }
299 
300 static int __init gicv2m_init_one(struct fwnode_handle *fwnode,
301 				  u32 spi_start, u32 nr_spis,
302 				  struct resource *res)
303 {
304 	int ret;
305 	struct v2m_data *v2m;
306 
307 	v2m = kzalloc(sizeof(struct v2m_data), GFP_KERNEL);
308 	if (!v2m) {
309 		pr_err("Failed to allocate struct v2m_data.\n");
310 		return -ENOMEM;
311 	}
312 
313 	INIT_LIST_HEAD(&v2m->entry);
314 	v2m->fwnode = fwnode;
315 
316 	memcpy(&v2m->res, res, sizeof(struct resource));
317 
318 	v2m->base = ioremap(v2m->res.start, resource_size(&v2m->res));
319 	if (!v2m->base) {
320 		pr_err("Failed to map GICv2m resource\n");
321 		ret = -ENOMEM;
322 		goto err_free_v2m;
323 	}
324 
325 	if (spi_start && nr_spis) {
326 		v2m->spi_start = spi_start;
327 		v2m->nr_spis = nr_spis;
328 	} else {
329 		u32 typer = readl_relaxed(v2m->base + V2M_MSI_TYPER);
330 
331 		v2m->spi_start = V2M_MSI_TYPER_BASE_SPI(typer);
332 		v2m->nr_spis = V2M_MSI_TYPER_NUM_SPI(typer);
333 	}
334 
335 	if (!is_msi_spi_valid(v2m->spi_start, v2m->nr_spis)) {
336 		ret = -EINVAL;
337 		goto err_iounmap;
338 	}
339 
340 	/*
341 	 * APM X-Gene GICv2m implementation has an erratum where
342 	 * the MSI data needs to be the offset from the spi_start
343 	 * in order to trigger the correct MSI interrupt. This is
344 	 * different from the standard GICv2m implementation where
345 	 * the MSI data is the absolute value within the range from
346 	 * spi_start to (spi_start + num_spis).
347 	 *
348 	 * Broadom NS2 GICv2m implementation has an erratum where the MSI data
349 	 * is 'spi_number - 32'
350 	 */
351 	switch (readl_relaxed(v2m->base + V2M_MSI_IIDR)) {
352 	case XGENE_GICV2M_MSI_IIDR:
353 		v2m->flags |= GICV2M_NEEDS_SPI_OFFSET;
354 		v2m->spi_offset = v2m->spi_start;
355 		break;
356 	case BCM_NS2_GICV2M_MSI_IIDR:
357 		v2m->flags |= GICV2M_NEEDS_SPI_OFFSET;
358 		v2m->spi_offset = 32;
359 		break;
360 	}
361 
362 	v2m->bm = kzalloc(sizeof(long) * BITS_TO_LONGS(v2m->nr_spis),
363 			  GFP_KERNEL);
364 	if (!v2m->bm) {
365 		ret = -ENOMEM;
366 		goto err_iounmap;
367 	}
368 
369 	list_add_tail(&v2m->entry, &v2m_nodes);
370 
371 	pr_info("range%pR, SPI[%d:%d]\n", res,
372 		v2m->spi_start, (v2m->spi_start + v2m->nr_spis - 1));
373 	return 0;
374 
375 err_iounmap:
376 	iounmap(v2m->base);
377 err_free_v2m:
378 	kfree(v2m);
379 	return ret;
380 }
381 
382 static struct of_device_id gicv2m_device_id[] = {
383 	{	.compatible	= "arm,gic-v2m-frame",	},
384 	{},
385 };
386 
387 static int __init gicv2m_of_init(struct fwnode_handle *parent_handle,
388 				 struct irq_domain *parent)
389 {
390 	int ret = 0;
391 	struct device_node *node = to_of_node(parent_handle);
392 	struct device_node *child;
393 
394 	for (child = of_find_matching_node(node, gicv2m_device_id); child;
395 	     child = of_find_matching_node(child, gicv2m_device_id)) {
396 		u32 spi_start = 0, nr_spis = 0;
397 		struct resource res;
398 
399 		if (!of_find_property(child, "msi-controller", NULL))
400 			continue;
401 
402 		ret = of_address_to_resource(child, 0, &res);
403 		if (ret) {
404 			pr_err("Failed to allocate v2m resource.\n");
405 			break;
406 		}
407 
408 		if (!of_property_read_u32(child, "arm,msi-base-spi",
409 					  &spi_start) &&
410 		    !of_property_read_u32(child, "arm,msi-num-spis", &nr_spis))
411 			pr_info("DT overriding V2M MSI_TYPER (base:%u, num:%u)\n",
412 				spi_start, nr_spis);
413 
414 		ret = gicv2m_init_one(&child->fwnode, spi_start, nr_spis, &res);
415 		if (ret) {
416 			of_node_put(child);
417 			break;
418 		}
419 	}
420 
421 	if (!ret)
422 		ret = gicv2m_allocate_domains(parent);
423 	if (ret)
424 		gicv2m_teardown();
425 	return ret;
426 }
427 
428 #ifdef CONFIG_ACPI
429 static int acpi_num_msi;
430 
431 static struct fwnode_handle *gicv2m_get_fwnode(struct device *dev)
432 {
433 	struct v2m_data *data;
434 
435 	if (WARN_ON(acpi_num_msi <= 0))
436 		return NULL;
437 
438 	/* We only return the fwnode of the first MSI frame. */
439 	data = list_first_entry_or_null(&v2m_nodes, struct v2m_data, entry);
440 	if (!data)
441 		return NULL;
442 
443 	return data->fwnode;
444 }
445 
446 static int __init
447 acpi_parse_madt_msi(struct acpi_subtable_header *header,
448 		    const unsigned long end)
449 {
450 	int ret;
451 	struct resource res;
452 	u32 spi_start = 0, nr_spis = 0;
453 	struct acpi_madt_generic_msi_frame *m;
454 	struct fwnode_handle *fwnode;
455 
456 	m = (struct acpi_madt_generic_msi_frame *)header;
457 	if (BAD_MADT_ENTRY(m, end))
458 		return -EINVAL;
459 
460 	res.start = m->base_address;
461 	res.end = m->base_address + SZ_4K - 1;
462 	res.flags = IORESOURCE_MEM;
463 
464 	if (m->flags & ACPI_MADT_OVERRIDE_SPI_VALUES) {
465 		spi_start = m->spi_base;
466 		nr_spis = m->spi_count;
467 
468 		pr_info("ACPI overriding V2M MSI_TYPER (base:%u, num:%u)\n",
469 			spi_start, nr_spis);
470 	}
471 
472 	fwnode = irq_domain_alloc_fwnode((void *)m->base_address);
473 	if (!fwnode) {
474 		pr_err("Unable to allocate GICv2m domain token\n");
475 		return -EINVAL;
476 	}
477 
478 	ret = gicv2m_init_one(fwnode, spi_start, nr_spis, &res);
479 	if (ret)
480 		irq_domain_free_fwnode(fwnode);
481 
482 	return ret;
483 }
484 
485 static int __init gicv2m_acpi_init(struct irq_domain *parent)
486 {
487 	int ret;
488 
489 	if (acpi_num_msi > 0)
490 		return 0;
491 
492 	acpi_num_msi = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_MSI_FRAME,
493 				      acpi_parse_madt_msi, 0);
494 
495 	if (acpi_num_msi <= 0)
496 		goto err_out;
497 
498 	ret = gicv2m_allocate_domains(parent);
499 	if (ret)
500 		goto err_out;
501 
502 	pci_msi_register_fwnode_provider(&gicv2m_get_fwnode);
503 
504 	return 0;
505 
506 err_out:
507 	gicv2m_teardown();
508 	return -EINVAL;
509 }
510 #else /* CONFIG_ACPI */
511 static int __init gicv2m_acpi_init(struct irq_domain *parent)
512 {
513 	return -EINVAL;
514 }
515 #endif /* CONFIG_ACPI */
516 
517 int __init gicv2m_init(struct fwnode_handle *parent_handle,
518 		       struct irq_domain *parent)
519 {
520 	if (is_of_node(parent_handle))
521 		return gicv2m_of_init(parent_handle, parent);
522 
523 	return gicv2m_acpi_init(parent);
524 }
525