1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2002 ARM Limited, All Rights Reserved. 4 */ 5 6 #include <linux/interrupt.h> 7 #include <linux/io.h> 8 #include <linux/irq.h> 9 #include <linux/irqchip/arm-gic.h> 10 11 #include "irq-gic-common.h" 12 13 static DEFINE_RAW_SPINLOCK(irq_controller_lock); 14 15 static const struct gic_kvm_info *gic_kvm_info; 16 17 const struct gic_kvm_info *gic_get_kvm_info(void) 18 { 19 return gic_kvm_info; 20 } 21 22 void gic_set_kvm_info(const struct gic_kvm_info *info) 23 { 24 BUG_ON(gic_kvm_info != NULL); 25 gic_kvm_info = info; 26 } 27 28 void gic_enable_of_quirks(const struct device_node *np, 29 const struct gic_quirk *quirks, void *data) 30 { 31 for (; quirks->desc; quirks++) { 32 if (!of_device_is_compatible(np, quirks->compatible)) 33 continue; 34 if (quirks->init(data)) 35 pr_info("GIC: enabling workaround for %s\n", 36 quirks->desc); 37 } 38 } 39 40 void gic_enable_quirks(u32 iidr, const struct gic_quirk *quirks, 41 void *data) 42 { 43 for (; quirks->desc; quirks++) { 44 if (quirks->iidr != (quirks->mask & iidr)) 45 continue; 46 if (quirks->init(data)) 47 pr_info("GIC: enabling workaround for %s\n", 48 quirks->desc); 49 } 50 } 51 52 int gic_configure_irq(unsigned int irq, unsigned int type, 53 void __iomem *base, void (*sync_access)(void)) 54 { 55 u32 confmask = 0x2 << ((irq % 16) * 2); 56 u32 confoff = (irq / 16) * 4; 57 u32 val, oldval; 58 int ret = 0; 59 unsigned long flags; 60 61 /* 62 * Read current configuration register, and insert the config 63 * for "irq", depending on "type". 64 */ 65 raw_spin_lock_irqsave(&irq_controller_lock, flags); 66 val = oldval = readl_relaxed(base + GIC_DIST_CONFIG + confoff); 67 if (type & IRQ_TYPE_LEVEL_MASK) 68 val &= ~confmask; 69 else if (type & IRQ_TYPE_EDGE_BOTH) 70 val |= confmask; 71 72 /* If the current configuration is the same, then we are done */ 73 if (val == oldval) { 74 raw_spin_unlock_irqrestore(&irq_controller_lock, flags); 75 return 0; 76 } 77 78 /* 79 * Write back the new configuration, and possibly re-enable 80 * the interrupt. If we fail to write a new configuration for 81 * an SPI then WARN and return an error. If we fail to write the 82 * configuration for a PPI this is most likely because the GIC 83 * does not allow us to set the configuration or we are in a 84 * non-secure mode, and hence it may not be catastrophic. 85 */ 86 writel_relaxed(val, base + GIC_DIST_CONFIG + confoff); 87 if (readl_relaxed(base + GIC_DIST_CONFIG + confoff) != val) { 88 if (WARN_ON(irq >= 32)) 89 ret = -EINVAL; 90 else 91 pr_warn("GIC: PPI%d is secure or misconfigured\n", 92 irq - 16); 93 } 94 raw_spin_unlock_irqrestore(&irq_controller_lock, flags); 95 96 if (sync_access) 97 sync_access(); 98 99 return ret; 100 } 101 102 void gic_dist_config(void __iomem *base, int gic_irqs, 103 void (*sync_access)(void)) 104 { 105 unsigned int i; 106 107 /* 108 * Set all global interrupts to be level triggered, active low. 109 */ 110 for (i = 32; i < gic_irqs; i += 16) 111 writel_relaxed(GICD_INT_ACTLOW_LVLTRIG, 112 base + GIC_DIST_CONFIG + i / 4); 113 114 /* 115 * Set priority on all global interrupts. 116 */ 117 for (i = 32; i < gic_irqs; i += 4) 118 writel_relaxed(GICD_INT_DEF_PRI_X4, base + GIC_DIST_PRI + i); 119 120 /* 121 * Deactivate and disable all SPIs. Leave the PPI and SGIs 122 * alone as they are in the redistributor registers on GICv3. 123 */ 124 for (i = 32; i < gic_irqs; i += 32) { 125 writel_relaxed(GICD_INT_EN_CLR_X32, 126 base + GIC_DIST_ACTIVE_CLEAR + i / 8); 127 writel_relaxed(GICD_INT_EN_CLR_X32, 128 base + GIC_DIST_ENABLE_CLEAR + i / 8); 129 } 130 131 if (sync_access) 132 sync_access(); 133 } 134 135 void gic_cpu_config(void __iomem *base, void (*sync_access)(void)) 136 { 137 int i; 138 139 /* 140 * Deal with the banked PPI and SGI interrupts - disable all 141 * PPI interrupts, ensure all SGI interrupts are enabled. 142 * Make sure everything is deactivated. 143 */ 144 writel_relaxed(GICD_INT_EN_CLR_X32, base + GIC_DIST_ACTIVE_CLEAR); 145 writel_relaxed(GICD_INT_EN_CLR_PPI, base + GIC_DIST_ENABLE_CLEAR); 146 writel_relaxed(GICD_INT_EN_SET_SGI, base + GIC_DIST_ENABLE_SET); 147 148 /* 149 * Set priority on PPI and SGI interrupts 150 */ 151 for (i = 0; i < 32; i += 4) 152 writel_relaxed(GICD_INT_DEF_PRI_X4, 153 base + GIC_DIST_PRI + i * 4 / 4); 154 155 if (sync_access) 156 sync_access(); 157 } 158