1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Generic Broadcom Set Top Box Level 2 Interrupt controller driver 4 * 5 * Copyright (C) 2014-2024 Broadcom 6 */ 7 8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 9 10 #include <linux/init.h> 11 #include <linux/slab.h> 12 #include <linux/module.h> 13 #include <linux/platform_device.h> 14 #include <linux/spinlock.h> 15 #include <linux/of.h> 16 #include <linux/of_irq.h> 17 #include <linux/of_address.h> 18 #include <linux/interrupt.h> 19 #include <linux/irq.h> 20 #include <linux/io.h> 21 #include <linux/irqdomain.h> 22 #include <linux/irqchip.h> 23 #include <linux/irqchip/chained_irq.h> 24 25 struct brcmstb_intc_init_params { 26 irq_flow_handler_t handler; 27 int cpu_status; 28 int cpu_clear; 29 int cpu_mask_status; 30 int cpu_mask_set; 31 int cpu_mask_clear; 32 }; 33 34 /* Register offsets in the L2 latched interrupt controller */ 35 static const struct brcmstb_intc_init_params l2_edge_intc_init = { 36 .handler = handle_edge_irq, 37 .cpu_status = 0x00, 38 .cpu_clear = 0x08, 39 .cpu_mask_status = 0x0c, 40 .cpu_mask_set = 0x10, 41 .cpu_mask_clear = 0x14 42 }; 43 44 /* Register offsets in the L2 level interrupt controller */ 45 static const struct brcmstb_intc_init_params l2_lvl_intc_init = { 46 .handler = handle_level_irq, 47 .cpu_status = 0x00, 48 .cpu_clear = -1, /* Register not present */ 49 .cpu_mask_status = 0x04, 50 .cpu_mask_set = 0x08, 51 .cpu_mask_clear = 0x0C 52 }; 53 54 /* L2 intc private data structure */ 55 struct brcmstb_l2_intc_data { 56 struct irq_domain *domain; 57 struct irq_chip_generic *gc; 58 int status_offset; 59 int mask_offset; 60 bool can_wake; 61 u32 saved_mask; /* for suspend/resume */ 62 }; 63 64 static void brcmstb_l2_intc_irq_handle(struct irq_desc *desc) 65 { 66 struct brcmstb_l2_intc_data *b = irq_desc_get_handler_data(desc); 67 struct irq_chip *chip = irq_desc_get_chip(desc); 68 unsigned int irq; 69 u32 status; 70 71 chained_irq_enter(chip, desc); 72 73 status = irq_reg_readl(b->gc, b->status_offset) & 74 ~(irq_reg_readl(b->gc, b->mask_offset)); 75 76 if (status == 0) { 77 raw_spin_lock(&desc->lock); 78 handle_bad_irq(desc); 79 raw_spin_unlock(&desc->lock); 80 goto out; 81 } 82 83 do { 84 irq = ffs(status) - 1; 85 status &= ~(1 << irq); 86 generic_handle_domain_irq(b->domain, irq); 87 } while (status); 88 out: 89 /* Don't ack parent before all device writes are done */ 90 wmb(); 91 92 chained_irq_exit(chip, desc); 93 } 94 95 static void __brcmstb_l2_intc_suspend(struct irq_data *d, bool save) 96 { 97 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 98 struct irq_chip_type *ct = irq_data_get_chip_type(d); 99 struct brcmstb_l2_intc_data *b = gc->private; 100 101 guard(raw_spinlock_irqsave)(&gc->lock); 102 /* Save the current mask */ 103 if (save) 104 b->saved_mask = irq_reg_readl(gc, ct->regs.mask); 105 106 if (b->can_wake) { 107 /* Program the wakeup mask */ 108 irq_reg_writel(gc, ~gc->wake_active, ct->regs.disable); 109 irq_reg_writel(gc, gc->wake_active, ct->regs.enable); 110 } 111 } 112 113 static void brcmstb_l2_intc_shutdown(struct irq_data *d) 114 { 115 __brcmstb_l2_intc_suspend(d, false); 116 } 117 118 static void brcmstb_l2_intc_suspend(struct irq_data *d) 119 { 120 __brcmstb_l2_intc_suspend(d, true); 121 } 122 123 static void brcmstb_l2_intc_resume(struct irq_data *d) 124 { 125 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 126 struct irq_chip_type *ct = irq_data_get_chip_type(d); 127 struct brcmstb_l2_intc_data *b = gc->private; 128 129 guard(raw_spinlock_irqsave)(&gc->lock); 130 if (ct->chip.irq_ack) { 131 /* Clear unmasked non-wakeup interrupts */ 132 irq_reg_writel(gc, ~b->saved_mask & ~gc->wake_active, 133 ct->regs.ack); 134 } 135 136 /* Restore the saved mask */ 137 irq_reg_writel(gc, b->saved_mask, ct->regs.disable); 138 irq_reg_writel(gc, ~b->saved_mask, ct->regs.enable); 139 } 140 141 static int __init brcmstb_l2_intc_of_init(struct device_node *np, 142 struct device_node *parent, 143 const struct brcmstb_intc_init_params 144 *init_params) 145 { 146 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; 147 unsigned int set = 0; 148 struct brcmstb_l2_intc_data *data; 149 struct irq_chip_type *ct; 150 int ret; 151 unsigned int flags; 152 int parent_irq; 153 void __iomem *base; 154 155 data = kzalloc(sizeof(*data), GFP_KERNEL); 156 if (!data) 157 return -ENOMEM; 158 159 base = of_iomap(np, 0); 160 if (!base) { 161 pr_err("failed to remap intc L2 registers\n"); 162 ret = -ENOMEM; 163 goto out_free; 164 } 165 166 /* Disable all interrupts by default */ 167 writel(0xffffffff, base + init_params->cpu_mask_set); 168 169 /* Wakeup interrupts may be retained from S5 (cold boot) */ 170 data->can_wake = of_property_read_bool(np, "brcm,irq-can-wake"); 171 if (!data->can_wake && (init_params->cpu_clear >= 0)) 172 writel(0xffffffff, base + init_params->cpu_clear); 173 174 parent_irq = irq_of_parse_and_map(np, 0); 175 if (!parent_irq) { 176 pr_err("failed to find parent interrupt\n"); 177 ret = -EINVAL; 178 goto out_unmap; 179 } 180 181 data->domain = irq_domain_create_linear(of_fwnode_handle(np), 32, 182 &irq_generic_chip_ops, NULL); 183 if (!data->domain) { 184 ret = -ENOMEM; 185 goto out_unmap; 186 } 187 188 /* MIPS chips strapped for BE will automagically configure the 189 * peripheral registers for CPU-native byte order. 190 */ 191 flags = 0; 192 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) 193 flags |= IRQ_GC_BE_IO; 194 195 if (init_params->handler == handle_level_irq) 196 set |= IRQ_LEVEL; 197 198 /* Allocate a single Generic IRQ chip for this node */ 199 ret = irq_alloc_domain_generic_chips(data->domain, 32, 1, 200 np->full_name, init_params->handler, clr, set, flags); 201 if (ret) { 202 pr_err("failed to allocate generic irq chip\n"); 203 goto out_free_domain; 204 } 205 206 /* Set the IRQ chaining logic */ 207 irq_set_chained_handler_and_data(parent_irq, 208 brcmstb_l2_intc_irq_handle, data); 209 210 data->gc = irq_get_domain_generic_chip(data->domain, 0); 211 data->gc->reg_base = base; 212 data->gc->private = data; 213 data->status_offset = init_params->cpu_status; 214 data->mask_offset = init_params->cpu_mask_status; 215 216 ct = data->gc->chip_types; 217 218 if (init_params->cpu_clear >= 0) { 219 ct->regs.ack = init_params->cpu_clear; 220 ct->chip.irq_ack = irq_gc_ack_set_bit; 221 ct->chip.irq_mask_ack = irq_gc_mask_disable_and_ack_set; 222 } else { 223 /* No Ack - but still slightly more efficient to define this */ 224 ct->chip.irq_mask_ack = irq_gc_mask_disable_reg; 225 } 226 227 ct->chip.irq_mask = irq_gc_mask_disable_reg; 228 ct->regs.disable = init_params->cpu_mask_set; 229 ct->regs.mask = init_params->cpu_mask_status; 230 231 ct->chip.irq_unmask = irq_gc_unmask_enable_reg; 232 ct->regs.enable = init_params->cpu_mask_clear; 233 234 ct->chip.irq_suspend = brcmstb_l2_intc_suspend; 235 ct->chip.irq_resume = brcmstb_l2_intc_resume; 236 ct->chip.irq_pm_shutdown = brcmstb_l2_intc_shutdown; 237 238 if (data->can_wake) { 239 /* This IRQ chip can wake the system, set all child interrupts 240 * in wake_enabled mask 241 */ 242 data->gc->wake_enabled = 0xffffffff; 243 ct->chip.irq_set_wake = irq_gc_set_wake; 244 enable_irq_wake(parent_irq); 245 } 246 247 pr_info("registered L2 intc (%pOF, parent irq: %d)\n", np, parent_irq); 248 249 return 0; 250 251 out_free_domain: 252 irq_domain_remove(data->domain); 253 out_unmap: 254 iounmap(base); 255 out_free: 256 kfree(data); 257 return ret; 258 } 259 260 static int __init brcmstb_l2_edge_intc_of_init(struct device_node *np, 261 struct device_node *parent) 262 { 263 return brcmstb_l2_intc_of_init(np, parent, &l2_edge_intc_init); 264 } 265 266 static int __init brcmstb_l2_lvl_intc_of_init(struct device_node *np, 267 struct device_node *parent) 268 { 269 return brcmstb_l2_intc_of_init(np, parent, &l2_lvl_intc_init); 270 } 271 272 IRQCHIP_PLATFORM_DRIVER_BEGIN(brcmstb_l2) 273 IRQCHIP_MATCH("brcm,l2-intc", brcmstb_l2_edge_intc_of_init) 274 IRQCHIP_MATCH("brcm,hif-spi-l2-intc", brcmstb_l2_edge_intc_of_init) 275 IRQCHIP_MATCH("brcm,upg-aux-aon-l2-intc", brcmstb_l2_edge_intc_of_init) 276 IRQCHIP_MATCH("brcm,bcm7271-l2-intc", brcmstb_l2_lvl_intc_of_init) 277 IRQCHIP_PLATFORM_DRIVER_END(brcmstb_l2) 278 MODULE_DESCRIPTION("Broadcom STB generic L2 interrupt controller"); 279 MODULE_LICENSE("GPL v2"); 280