1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Generic Broadcom Set Top Box Level 2 Interrupt controller driver 4 * 5 * Copyright (C) 2014-2024 Broadcom 6 */ 7 8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 9 10 #include <linux/init.h> 11 #include <linux/slab.h> 12 #include <linux/module.h> 13 #include <linux/platform_device.h> 14 #include <linux/spinlock.h> 15 #include <linux/of.h> 16 #include <linux/of_irq.h> 17 #include <linux/of_address.h> 18 #include <linux/interrupt.h> 19 #include <linux/irq.h> 20 #include <linux/io.h> 21 #include <linux/irqdomain.h> 22 #include <linux/irqchip.h> 23 #include <linux/irqchip/chained_irq.h> 24 25 struct brcmstb_intc_init_params { 26 irq_flow_handler_t handler; 27 int cpu_status; 28 int cpu_clear; 29 int cpu_mask_status; 30 int cpu_mask_set; 31 int cpu_mask_clear; 32 }; 33 34 /* Register offsets in the L2 latched interrupt controller */ 35 static const struct brcmstb_intc_init_params l2_edge_intc_init = { 36 .handler = handle_edge_irq, 37 .cpu_status = 0x00, 38 .cpu_clear = 0x08, 39 .cpu_mask_status = 0x0c, 40 .cpu_mask_set = 0x10, 41 .cpu_mask_clear = 0x14 42 }; 43 44 /* Register offsets in the L2 level interrupt controller */ 45 static const struct brcmstb_intc_init_params l2_lvl_intc_init = { 46 .handler = handle_level_irq, 47 .cpu_status = 0x00, 48 .cpu_clear = -1, /* Register not present */ 49 .cpu_mask_status = 0x04, 50 .cpu_mask_set = 0x08, 51 .cpu_mask_clear = 0x0C 52 }; 53 54 /* L2 intc private data structure */ 55 struct brcmstb_l2_intc_data { 56 struct irq_domain *domain; 57 struct irq_chip_generic *gc; 58 int status_offset; 59 int mask_offset; 60 bool can_wake; 61 u32 saved_mask; /* for suspend/resume */ 62 }; 63 64 static void brcmstb_l2_intc_irq_handle(struct irq_desc *desc) 65 { 66 struct brcmstb_l2_intc_data *b = irq_desc_get_handler_data(desc); 67 struct irq_chip *chip = irq_desc_get_chip(desc); 68 unsigned int irq; 69 u32 status; 70 71 chained_irq_enter(chip, desc); 72 73 status = irq_reg_readl(b->gc, b->status_offset) & 74 ~(irq_reg_readl(b->gc, b->mask_offset)); 75 76 if (status == 0) { 77 raw_spin_lock(&desc->lock); 78 handle_bad_irq(desc); 79 raw_spin_unlock(&desc->lock); 80 goto out; 81 } 82 83 do { 84 irq = ffs(status) - 1; 85 status &= ~(1 << irq); 86 generic_handle_domain_irq(b->domain, irq); 87 } while (status); 88 out: 89 /* Don't ack parent before all device writes are done */ 90 wmb(); 91 92 chained_irq_exit(chip, desc); 93 } 94 95 static void __brcmstb_l2_intc_suspend(struct irq_data *d, bool save) 96 { 97 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 98 struct irq_chip_type *ct = irq_data_get_chip_type(d); 99 struct brcmstb_l2_intc_data *b = gc->private; 100 unsigned long flags; 101 102 irq_gc_lock_irqsave(gc, flags); 103 /* Save the current mask */ 104 if (save) 105 b->saved_mask = irq_reg_readl(gc, ct->regs.mask); 106 107 if (b->can_wake) { 108 /* Program the wakeup mask */ 109 irq_reg_writel(gc, ~gc->wake_active, ct->regs.disable); 110 irq_reg_writel(gc, gc->wake_active, ct->regs.enable); 111 } 112 irq_gc_unlock_irqrestore(gc, flags); 113 } 114 115 static void brcmstb_l2_intc_shutdown(struct irq_data *d) 116 { 117 __brcmstb_l2_intc_suspend(d, false); 118 } 119 120 static void brcmstb_l2_intc_suspend(struct irq_data *d) 121 { 122 __brcmstb_l2_intc_suspend(d, true); 123 } 124 125 static void brcmstb_l2_intc_resume(struct irq_data *d) 126 { 127 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 128 struct irq_chip_type *ct = irq_data_get_chip_type(d); 129 struct brcmstb_l2_intc_data *b = gc->private; 130 unsigned long flags; 131 132 irq_gc_lock_irqsave(gc, flags); 133 if (ct->chip.irq_ack) { 134 /* Clear unmasked non-wakeup interrupts */ 135 irq_reg_writel(gc, ~b->saved_mask & ~gc->wake_active, 136 ct->regs.ack); 137 } 138 139 /* Restore the saved mask */ 140 irq_reg_writel(gc, b->saved_mask, ct->regs.disable); 141 irq_reg_writel(gc, ~b->saved_mask, ct->regs.enable); 142 irq_gc_unlock_irqrestore(gc, flags); 143 } 144 145 static int __init brcmstb_l2_intc_of_init(struct device_node *np, 146 struct device_node *parent, 147 const struct brcmstb_intc_init_params 148 *init_params) 149 { 150 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; 151 unsigned int set = 0; 152 struct brcmstb_l2_intc_data *data; 153 struct irq_chip_type *ct; 154 int ret; 155 unsigned int flags; 156 int parent_irq; 157 void __iomem *base; 158 159 data = kzalloc(sizeof(*data), GFP_KERNEL); 160 if (!data) 161 return -ENOMEM; 162 163 base = of_iomap(np, 0); 164 if (!base) { 165 pr_err("failed to remap intc L2 registers\n"); 166 ret = -ENOMEM; 167 goto out_free; 168 } 169 170 /* Disable all interrupts by default */ 171 writel(0xffffffff, base + init_params->cpu_mask_set); 172 173 /* Wakeup interrupts may be retained from S5 (cold boot) */ 174 data->can_wake = of_property_read_bool(np, "brcm,irq-can-wake"); 175 if (!data->can_wake && (init_params->cpu_clear >= 0)) 176 writel(0xffffffff, base + init_params->cpu_clear); 177 178 parent_irq = irq_of_parse_and_map(np, 0); 179 if (!parent_irq) { 180 pr_err("failed to find parent interrupt\n"); 181 ret = -EINVAL; 182 goto out_unmap; 183 } 184 185 data->domain = irq_domain_add_linear(np, 32, 186 &irq_generic_chip_ops, NULL); 187 if (!data->domain) { 188 ret = -ENOMEM; 189 goto out_unmap; 190 } 191 192 /* MIPS chips strapped for BE will automagically configure the 193 * peripheral registers for CPU-native byte order. 194 */ 195 flags = 0; 196 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) 197 flags |= IRQ_GC_BE_IO; 198 199 if (init_params->handler == handle_level_irq) 200 set |= IRQ_LEVEL; 201 202 /* Allocate a single Generic IRQ chip for this node */ 203 ret = irq_alloc_domain_generic_chips(data->domain, 32, 1, 204 np->full_name, init_params->handler, clr, set, flags); 205 if (ret) { 206 pr_err("failed to allocate generic irq chip\n"); 207 goto out_free_domain; 208 } 209 210 /* Set the IRQ chaining logic */ 211 irq_set_chained_handler_and_data(parent_irq, 212 brcmstb_l2_intc_irq_handle, data); 213 214 data->gc = irq_get_domain_generic_chip(data->domain, 0); 215 data->gc->reg_base = base; 216 data->gc->private = data; 217 data->status_offset = init_params->cpu_status; 218 data->mask_offset = init_params->cpu_mask_status; 219 220 ct = data->gc->chip_types; 221 222 if (init_params->cpu_clear >= 0) { 223 ct->regs.ack = init_params->cpu_clear; 224 ct->chip.irq_ack = irq_gc_ack_set_bit; 225 ct->chip.irq_mask_ack = irq_gc_mask_disable_and_ack_set; 226 } else { 227 /* No Ack - but still slightly more efficient to define this */ 228 ct->chip.irq_mask_ack = irq_gc_mask_disable_reg; 229 } 230 231 ct->chip.irq_mask = irq_gc_mask_disable_reg; 232 ct->regs.disable = init_params->cpu_mask_set; 233 ct->regs.mask = init_params->cpu_mask_status; 234 235 ct->chip.irq_unmask = irq_gc_unmask_enable_reg; 236 ct->regs.enable = init_params->cpu_mask_clear; 237 238 ct->chip.irq_suspend = brcmstb_l2_intc_suspend; 239 ct->chip.irq_resume = brcmstb_l2_intc_resume; 240 ct->chip.irq_pm_shutdown = brcmstb_l2_intc_shutdown; 241 242 if (data->can_wake) { 243 /* This IRQ chip can wake the system, set all child interrupts 244 * in wake_enabled mask 245 */ 246 data->gc->wake_enabled = 0xffffffff; 247 ct->chip.irq_set_wake = irq_gc_set_wake; 248 enable_irq_wake(parent_irq); 249 } 250 251 pr_info("registered L2 intc (%pOF, parent irq: %d)\n", np, parent_irq); 252 253 return 0; 254 255 out_free_domain: 256 irq_domain_remove(data->domain); 257 out_unmap: 258 iounmap(base); 259 out_free: 260 kfree(data); 261 return ret; 262 } 263 264 static int __init brcmstb_l2_edge_intc_of_init(struct device_node *np, 265 struct device_node *parent) 266 { 267 return brcmstb_l2_intc_of_init(np, parent, &l2_edge_intc_init); 268 } 269 270 static int __init brcmstb_l2_lvl_intc_of_init(struct device_node *np, 271 struct device_node *parent) 272 { 273 return brcmstb_l2_intc_of_init(np, parent, &l2_lvl_intc_init); 274 } 275 276 IRQCHIP_PLATFORM_DRIVER_BEGIN(brcmstb_l2) 277 IRQCHIP_MATCH("brcm,l2-intc", brcmstb_l2_edge_intc_of_init) 278 IRQCHIP_MATCH("brcm,hif-spi-l2-intc", brcmstb_l2_edge_intc_of_init) 279 IRQCHIP_MATCH("brcm,upg-aux-aon-l2-intc", brcmstb_l2_edge_intc_of_init) 280 IRQCHIP_MATCH("brcm,bcm7271-l2-intc", brcmstb_l2_lvl_intc_of_init) 281 IRQCHIP_PLATFORM_DRIVER_END(brcmstb_l2) 282 MODULE_DESCRIPTION("Broadcom STB generic L2 interrupt controller"); 283 MODULE_LICENSE("GPL v2"); 284