1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Broadcom BCM7038 style Level 1 interrupt controller driver 4 * 5 * Copyright (C) 2014 Broadcom Corporation 6 * Author: Kevin Cernekee 7 */ 8 9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 10 11 #include <linux/bitops.h> 12 #include <linux/kernel.h> 13 #include <linux/init.h> 14 #include <linux/interrupt.h> 15 #include <linux/io.h> 16 #include <linux/ioport.h> 17 #include <linux/irq.h> 18 #include <linux/irqdomain.h> 19 #include <linux/module.h> 20 #include <linux/of.h> 21 #include <linux/of_irq.h> 22 #include <linux/of_address.h> 23 #include <linux/platform_device.h> 24 #include <linux/slab.h> 25 #include <linux/smp.h> 26 #include <linux/types.h> 27 #include <linux/irqchip.h> 28 #include <linux/irqchip/chained_irq.h> 29 #include <linux/syscore_ops.h> 30 31 #define IRQS_PER_WORD 32 32 #define REG_BYTES_PER_IRQ_WORD (sizeof(u32) * 4) 33 #define MAX_WORDS 8 34 35 struct bcm7038_l1_cpu; 36 37 struct bcm7038_l1_chip { 38 raw_spinlock_t lock; 39 unsigned int n_words; 40 struct irq_domain *domain; 41 struct bcm7038_l1_cpu *cpus[NR_CPUS]; 42 #ifdef CONFIG_PM_SLEEP 43 struct list_head list; 44 u32 wake_mask[MAX_WORDS]; 45 #endif 46 u32 irq_fwd_mask[MAX_WORDS]; 47 u8 affinity[MAX_WORDS * IRQS_PER_WORD]; 48 }; 49 50 struct bcm7038_l1_cpu { 51 void __iomem *map_base; 52 u32 mask_cache[]; 53 }; 54 55 /* 56 * STATUS/MASK_STATUS/MASK_SET/MASK_CLEAR are packed one right after another: 57 * 58 * 7038: 59 * 0x1000_1400: W0_STATUS 60 * 0x1000_1404: W1_STATUS 61 * 0x1000_1408: W0_MASK_STATUS 62 * 0x1000_140c: W1_MASK_STATUS 63 * 0x1000_1410: W0_MASK_SET 64 * 0x1000_1414: W1_MASK_SET 65 * 0x1000_1418: W0_MASK_CLEAR 66 * 0x1000_141c: W1_MASK_CLEAR 67 * 68 * 7445: 69 * 0xf03e_1500: W0_STATUS 70 * 0xf03e_1504: W1_STATUS 71 * 0xf03e_1508: W2_STATUS 72 * 0xf03e_150c: W3_STATUS 73 * 0xf03e_1510: W4_STATUS 74 * 0xf03e_1514: W0_MASK_STATUS 75 * 0xf03e_1518: W1_MASK_STATUS 76 * [...] 77 */ 78 79 static inline unsigned int reg_status(struct bcm7038_l1_chip *intc, 80 unsigned int word) 81 { 82 return (0 * intc->n_words + word) * sizeof(u32); 83 } 84 85 static inline unsigned int reg_mask_set(struct bcm7038_l1_chip *intc, 86 unsigned int word) 87 { 88 return (2 * intc->n_words + word) * sizeof(u32); 89 } 90 91 static inline unsigned int reg_mask_clr(struct bcm7038_l1_chip *intc, 92 unsigned int word) 93 { 94 return (3 * intc->n_words + word) * sizeof(u32); 95 } 96 97 static inline u32 l1_readl(void __iomem *reg) 98 { 99 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) 100 return ioread32be(reg); 101 else 102 return readl(reg); 103 } 104 105 static inline void l1_writel(u32 val, void __iomem *reg) 106 { 107 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) 108 iowrite32be(val, reg); 109 else 110 writel(val, reg); 111 } 112 113 static void bcm7038_l1_irq_handle(struct irq_desc *desc) 114 { 115 struct bcm7038_l1_chip *intc = irq_desc_get_handler_data(desc); 116 struct bcm7038_l1_cpu *cpu; 117 struct irq_chip *chip = irq_desc_get_chip(desc); 118 unsigned int idx; 119 120 #if defined(CONFIG_SMP) && defined(CONFIG_MIPS) 121 cpu = intc->cpus[cpu_logical_map(smp_processor_id())]; 122 #else 123 cpu = intc->cpus[0]; 124 #endif 125 126 chained_irq_enter(chip, desc); 127 128 for (idx = 0; idx < intc->n_words; idx++) { 129 int base = idx * IRQS_PER_WORD; 130 unsigned long pending, flags; 131 int hwirq; 132 133 raw_spin_lock_irqsave(&intc->lock, flags); 134 pending = l1_readl(cpu->map_base + reg_status(intc, idx)) & 135 ~cpu->mask_cache[idx]; 136 raw_spin_unlock_irqrestore(&intc->lock, flags); 137 138 for_each_set_bit(hwirq, &pending, IRQS_PER_WORD) 139 generic_handle_domain_irq(intc->domain, base + hwirq); 140 } 141 142 chained_irq_exit(chip, desc); 143 } 144 145 static void __bcm7038_l1_unmask(struct irq_data *d, unsigned int cpu_idx) 146 { 147 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d); 148 u32 word = d->hwirq / IRQS_PER_WORD; 149 u32 mask = BIT(d->hwirq % IRQS_PER_WORD); 150 151 intc->cpus[cpu_idx]->mask_cache[word] &= ~mask; 152 l1_writel(mask, intc->cpus[cpu_idx]->map_base + 153 reg_mask_clr(intc, word)); 154 } 155 156 static void __bcm7038_l1_mask(struct irq_data *d, unsigned int cpu_idx) 157 { 158 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d); 159 u32 word = d->hwirq / IRQS_PER_WORD; 160 u32 mask = BIT(d->hwirq % IRQS_PER_WORD); 161 162 intc->cpus[cpu_idx]->mask_cache[word] |= mask; 163 l1_writel(mask, intc->cpus[cpu_idx]->map_base + 164 reg_mask_set(intc, word)); 165 } 166 167 static void bcm7038_l1_unmask(struct irq_data *d) 168 { 169 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d); 170 unsigned long flags; 171 172 raw_spin_lock_irqsave(&intc->lock, flags); 173 __bcm7038_l1_unmask(d, intc->affinity[d->hwirq]); 174 raw_spin_unlock_irqrestore(&intc->lock, flags); 175 } 176 177 static void bcm7038_l1_mask(struct irq_data *d) 178 { 179 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d); 180 unsigned long flags; 181 182 raw_spin_lock_irqsave(&intc->lock, flags); 183 __bcm7038_l1_mask(d, intc->affinity[d->hwirq]); 184 raw_spin_unlock_irqrestore(&intc->lock, flags); 185 } 186 187 #if defined(CONFIG_MIPS) && defined(CONFIG_SMP) 188 static int bcm7038_l1_set_affinity(struct irq_data *d, 189 const struct cpumask *dest, 190 bool force) 191 { 192 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d); 193 unsigned long flags; 194 irq_hw_number_t hw = d->hwirq; 195 u32 word = hw / IRQS_PER_WORD; 196 u32 mask = BIT(hw % IRQS_PER_WORD); 197 unsigned int first_cpu = cpumask_any_and(dest, cpu_online_mask); 198 bool was_disabled; 199 200 raw_spin_lock_irqsave(&intc->lock, flags); 201 202 was_disabled = !!(intc->cpus[intc->affinity[hw]]->mask_cache[word] & 203 mask); 204 __bcm7038_l1_mask(d, intc->affinity[hw]); 205 intc->affinity[hw] = first_cpu; 206 if (!was_disabled) 207 __bcm7038_l1_unmask(d, first_cpu); 208 209 raw_spin_unlock_irqrestore(&intc->lock, flags); 210 irq_data_update_effective_affinity(d, cpumask_of(first_cpu)); 211 212 return 0; 213 } 214 #endif 215 216 static int bcm7038_l1_init_one(struct device_node *dn, unsigned int idx, 217 struct bcm7038_l1_chip *intc) 218 { 219 struct resource res; 220 resource_size_t sz; 221 struct bcm7038_l1_cpu *cpu; 222 unsigned int i, n_words, parent_irq; 223 int ret; 224 225 if (of_address_to_resource(dn, idx, &res)) 226 return -EINVAL; 227 sz = resource_size(&res); 228 n_words = sz / REG_BYTES_PER_IRQ_WORD; 229 230 if (n_words > MAX_WORDS) 231 return -EINVAL; 232 else if (!intc->n_words) 233 intc->n_words = n_words; 234 else if (intc->n_words != n_words) 235 return -EINVAL; 236 237 ret = of_property_read_u32_array(dn , "brcm,int-fwd-mask", 238 intc->irq_fwd_mask, n_words); 239 if (ret != 0 && ret != -EINVAL) { 240 /* property exists but has the wrong number of words */ 241 pr_err("invalid brcm,int-fwd-mask property\n"); 242 return -EINVAL; 243 } 244 245 cpu = intc->cpus[idx] = kzalloc(struct_size(cpu, mask_cache, n_words), 246 GFP_KERNEL); 247 if (!cpu) 248 return -ENOMEM; 249 250 cpu->map_base = ioremap(res.start, sz); 251 if (!cpu->map_base) 252 return -ENOMEM; 253 254 for (i = 0; i < n_words; i++) { 255 l1_writel(~intc->irq_fwd_mask[i], 256 cpu->map_base + reg_mask_set(intc, i)); 257 l1_writel(intc->irq_fwd_mask[i], 258 cpu->map_base + reg_mask_clr(intc, i)); 259 cpu->mask_cache[i] = ~intc->irq_fwd_mask[i]; 260 } 261 262 parent_irq = irq_of_parse_and_map(dn, idx); 263 if (!parent_irq) { 264 pr_err("failed to map parent interrupt %d\n", parent_irq); 265 return -EINVAL; 266 } 267 268 if (of_property_read_bool(dn, "brcm,irq-can-wake")) 269 enable_irq_wake(parent_irq); 270 271 irq_set_chained_handler_and_data(parent_irq, bcm7038_l1_irq_handle, 272 intc); 273 274 return 0; 275 } 276 277 #ifdef CONFIG_PM_SLEEP 278 /* 279 * We keep a list of bcm7038_l1_chip used for suspend/resume. This hack is 280 * used because the struct chip_type suspend/resume hooks are not called 281 * unless chip_type is hooked onto a generic_chip. Since this driver does 282 * not use generic_chip, we need to manually hook our resume/suspend to 283 * syscore_ops. 284 */ 285 static LIST_HEAD(bcm7038_l1_intcs_list); 286 static DEFINE_RAW_SPINLOCK(bcm7038_l1_intcs_lock); 287 288 static int bcm7038_l1_suspend(void) 289 { 290 struct bcm7038_l1_chip *intc; 291 int boot_cpu, word; 292 u32 val; 293 294 /* Wakeup interrupt should only come from the boot cpu */ 295 #if defined(CONFIG_SMP) && defined(CONFIG_MIPS) 296 boot_cpu = cpu_logical_map(0); 297 #else 298 boot_cpu = 0; 299 #endif 300 301 list_for_each_entry(intc, &bcm7038_l1_intcs_list, list) { 302 for (word = 0; word < intc->n_words; word++) { 303 val = intc->wake_mask[word] | intc->irq_fwd_mask[word]; 304 l1_writel(~val, 305 intc->cpus[boot_cpu]->map_base + reg_mask_set(intc, word)); 306 l1_writel(val, 307 intc->cpus[boot_cpu]->map_base + reg_mask_clr(intc, word)); 308 } 309 } 310 311 return 0; 312 } 313 314 static void bcm7038_l1_resume(void) 315 { 316 struct bcm7038_l1_chip *intc; 317 int boot_cpu, word; 318 319 #if defined(CONFIG_SMP) && defined(CONFIG_MIPS) 320 boot_cpu = cpu_logical_map(0); 321 #else 322 boot_cpu = 0; 323 #endif 324 325 list_for_each_entry(intc, &bcm7038_l1_intcs_list, list) { 326 for (word = 0; word < intc->n_words; word++) { 327 l1_writel(intc->cpus[boot_cpu]->mask_cache[word], 328 intc->cpus[boot_cpu]->map_base + reg_mask_set(intc, word)); 329 l1_writel(~intc->cpus[boot_cpu]->mask_cache[word], 330 intc->cpus[boot_cpu]->map_base + reg_mask_clr(intc, word)); 331 } 332 } 333 } 334 335 static struct syscore_ops bcm7038_l1_syscore_ops = { 336 .suspend = bcm7038_l1_suspend, 337 .resume = bcm7038_l1_resume, 338 }; 339 340 static int bcm7038_l1_set_wake(struct irq_data *d, unsigned int on) 341 { 342 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d); 343 unsigned long flags; 344 u32 word = d->hwirq / IRQS_PER_WORD; 345 u32 mask = BIT(d->hwirq % IRQS_PER_WORD); 346 347 raw_spin_lock_irqsave(&intc->lock, flags); 348 if (on) 349 intc->wake_mask[word] |= mask; 350 else 351 intc->wake_mask[word] &= ~mask; 352 raw_spin_unlock_irqrestore(&intc->lock, flags); 353 354 return 0; 355 } 356 #endif 357 358 static struct irq_chip bcm7038_l1_irq_chip = { 359 .name = "bcm7038-l1", 360 .irq_mask = bcm7038_l1_mask, 361 .irq_unmask = bcm7038_l1_unmask, 362 #if defined(CONFIG_SMP) && defined(CONFIG_MIPS) 363 .irq_set_affinity = bcm7038_l1_set_affinity, 364 #endif 365 #ifdef CONFIG_PM_SLEEP 366 .irq_set_wake = bcm7038_l1_set_wake, 367 #endif 368 }; 369 370 static int bcm7038_l1_map(struct irq_domain *d, unsigned int virq, 371 irq_hw_number_t hw_irq) 372 { 373 struct bcm7038_l1_chip *intc = d->host_data; 374 u32 mask = BIT(hw_irq % IRQS_PER_WORD); 375 u32 word = hw_irq / IRQS_PER_WORD; 376 377 if (intc->irq_fwd_mask[word] & mask) 378 return -EPERM; 379 380 irq_set_chip_and_handler(virq, &bcm7038_l1_irq_chip, handle_level_irq); 381 irq_set_chip_data(virq, d->host_data); 382 irqd_set_single_target(irq_get_irq_data(virq)); 383 return 0; 384 } 385 386 static const struct irq_domain_ops bcm7038_l1_domain_ops = { 387 .xlate = irq_domain_xlate_onecell, 388 .map = bcm7038_l1_map, 389 }; 390 391 static int bcm7038_l1_probe(struct platform_device *pdev, struct device_node *parent) 392 { 393 struct device_node *dn = pdev->dev.of_node; 394 struct bcm7038_l1_chip *intc; 395 int idx, ret; 396 397 intc = kzalloc(sizeof(*intc), GFP_KERNEL); 398 if (!intc) 399 return -ENOMEM; 400 401 raw_spin_lock_init(&intc->lock); 402 for_each_possible_cpu(idx) { 403 ret = bcm7038_l1_init_one(dn, idx, intc); 404 if (ret < 0) { 405 if (idx) 406 break; 407 pr_err("failed to remap intc L1 registers\n"); 408 goto out_free; 409 } 410 } 411 412 intc->domain = irq_domain_create_linear(of_fwnode_handle(dn), IRQS_PER_WORD * intc->n_words, 413 &bcm7038_l1_domain_ops, 414 intc); 415 if (!intc->domain) { 416 ret = -ENOMEM; 417 goto out_unmap; 418 } 419 420 #ifdef CONFIG_PM_SLEEP 421 /* Add bcm7038_l1_chip into a list */ 422 raw_spin_lock(&bcm7038_l1_intcs_lock); 423 list_add_tail(&intc->list, &bcm7038_l1_intcs_list); 424 raw_spin_unlock(&bcm7038_l1_intcs_lock); 425 426 if (list_is_singular(&bcm7038_l1_intcs_list)) 427 register_syscore_ops(&bcm7038_l1_syscore_ops); 428 #endif 429 430 pr_info("registered BCM7038 L1 intc (%pOF, IRQs: %d)\n", 431 dn, IRQS_PER_WORD * intc->n_words); 432 433 return 0; 434 435 out_unmap: 436 for_each_possible_cpu(idx) { 437 struct bcm7038_l1_cpu *cpu = intc->cpus[idx]; 438 439 if (cpu) { 440 if (cpu->map_base) 441 iounmap(cpu->map_base); 442 kfree(cpu); 443 } 444 } 445 out_free: 446 kfree(intc); 447 return ret; 448 } 449 450 IRQCHIP_PLATFORM_DRIVER_BEGIN(bcm7038_l1) 451 IRQCHIP_MATCH("brcm,bcm7038-l1-intc", bcm7038_l1_probe) 452 IRQCHIP_PLATFORM_DRIVER_END(bcm7038_l1) 453 MODULE_DESCRIPTION("Broadcom STB 7038-style L1/L2 interrupt controller"); 454 MODULE_LICENSE("GPL v2"); 455