1 /* 2 * Atmel AT91 AIC5 (Advanced Interrupt Controller) driver 3 * 4 * Copyright (C) 2004 SAN People 5 * Copyright (C) 2004 ATMEL 6 * Copyright (C) Rick Bronson 7 * Copyright (C) 2014 Free Electrons 8 * 9 * Author: Boris BREZILLON <boris.brezillon@free-electrons.com> 10 * 11 * This file is licensed under the terms of the GNU General Public 12 * License version 2. This program is licensed "as is" without any 13 * warranty of any kind, whether express or implied. 14 */ 15 16 #include <linux/init.h> 17 #include <linux/module.h> 18 #include <linux/mm.h> 19 #include <linux/bitmap.h> 20 #include <linux/types.h> 21 #include <linux/irq.h> 22 #include <linux/of.h> 23 #include <linux/of_address.h> 24 #include <linux/of_irq.h> 25 #include <linux/irqdomain.h> 26 #include <linux/err.h> 27 #include <linux/slab.h> 28 #include <linux/io.h> 29 30 #include <asm/exception.h> 31 #include <asm/mach/irq.h> 32 33 #include "irq-atmel-aic-common.h" 34 #include "irqchip.h" 35 36 /* Number of irq lines managed by AIC */ 37 #define NR_AIC5_IRQS 128 38 39 #define AT91_AIC5_SSR 0x0 40 #define AT91_AIC5_INTSEL_MSK (0x7f << 0) 41 42 #define AT91_AIC5_SMR 0x4 43 44 #define AT91_AIC5_SVR 0x8 45 #define AT91_AIC5_IVR 0x10 46 #define AT91_AIC5_FVR 0x14 47 #define AT91_AIC5_ISR 0x18 48 49 #define AT91_AIC5_IPR0 0x20 50 #define AT91_AIC5_IPR1 0x24 51 #define AT91_AIC5_IPR2 0x28 52 #define AT91_AIC5_IPR3 0x2c 53 #define AT91_AIC5_IMR 0x30 54 #define AT91_AIC5_CISR 0x34 55 56 #define AT91_AIC5_IECR 0x40 57 #define AT91_AIC5_IDCR 0x44 58 #define AT91_AIC5_ICCR 0x48 59 #define AT91_AIC5_ISCR 0x4c 60 #define AT91_AIC5_EOICR 0x38 61 #define AT91_AIC5_SPU 0x3c 62 #define AT91_AIC5_DCR 0x6c 63 64 #define AT91_AIC5_FFER 0x50 65 #define AT91_AIC5_FFDR 0x54 66 #define AT91_AIC5_FFSR 0x58 67 68 static struct irq_domain *aic5_domain; 69 70 static asmlinkage void __exception_irq_entry 71 aic5_handle(struct pt_regs *regs) 72 { 73 struct irq_domain_chip_generic *dgc = aic5_domain->gc; 74 struct irq_chip_generic *gc = dgc->gc[0]; 75 u32 irqnr; 76 u32 irqstat; 77 78 irqnr = irq_reg_readl(gc->reg_base + AT91_AIC5_IVR); 79 irqstat = irq_reg_readl(gc->reg_base + AT91_AIC5_ISR); 80 81 irqnr = irq_find_mapping(aic5_domain, irqnr); 82 83 if (!irqstat) 84 irq_reg_writel(0, gc->reg_base + AT91_AIC5_EOICR); 85 else 86 handle_IRQ(irqnr, regs); 87 } 88 89 static void aic5_mask(struct irq_data *d) 90 { 91 struct irq_domain *domain = d->domain; 92 struct irq_domain_chip_generic *dgc = domain->gc; 93 struct irq_chip_generic *gc = dgc->gc[0]; 94 95 /* Disable interrupt on AIC5 */ 96 irq_gc_lock(gc); 97 irq_reg_writel(d->hwirq, gc->reg_base + AT91_AIC5_SSR); 98 irq_reg_writel(1, gc->reg_base + AT91_AIC5_IDCR); 99 gc->mask_cache &= ~d->mask; 100 irq_gc_unlock(gc); 101 } 102 103 static void aic5_unmask(struct irq_data *d) 104 { 105 struct irq_domain *domain = d->domain; 106 struct irq_domain_chip_generic *dgc = domain->gc; 107 struct irq_chip_generic *gc = dgc->gc[0]; 108 109 /* Enable interrupt on AIC5 */ 110 irq_gc_lock(gc); 111 irq_reg_writel(d->hwirq, gc->reg_base + AT91_AIC5_SSR); 112 irq_reg_writel(1, gc->reg_base + AT91_AIC5_IECR); 113 gc->mask_cache |= d->mask; 114 irq_gc_unlock(gc); 115 } 116 117 static int aic5_retrigger(struct irq_data *d) 118 { 119 struct irq_domain *domain = d->domain; 120 struct irq_domain_chip_generic *dgc = domain->gc; 121 struct irq_chip_generic *gc = dgc->gc[0]; 122 123 /* Enable interrupt on AIC5 */ 124 irq_gc_lock(gc); 125 irq_reg_writel(d->hwirq, gc->reg_base + AT91_AIC5_SSR); 126 irq_reg_writel(1, gc->reg_base + AT91_AIC5_ISCR); 127 irq_gc_unlock(gc); 128 129 return 0; 130 } 131 132 static int aic5_set_type(struct irq_data *d, unsigned type) 133 { 134 struct irq_domain *domain = d->domain; 135 struct irq_domain_chip_generic *dgc = domain->gc; 136 struct irq_chip_generic *gc = dgc->gc[0]; 137 unsigned int smr; 138 int ret; 139 140 irq_gc_lock(gc); 141 irq_reg_writel(d->hwirq, gc->reg_base + AT91_AIC5_SSR); 142 smr = irq_reg_readl(gc->reg_base + AT91_AIC5_SMR); 143 ret = aic_common_set_type(d, type, &smr); 144 if (!ret) 145 irq_reg_writel(smr, gc->reg_base + AT91_AIC5_SMR); 146 irq_gc_unlock(gc); 147 148 return ret; 149 } 150 151 #ifdef CONFIG_PM 152 static void aic5_suspend(struct irq_data *d) 153 { 154 struct irq_domain *domain = d->domain; 155 struct irq_domain_chip_generic *dgc = domain->gc; 156 struct irq_chip_generic *bgc = dgc->gc[0]; 157 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 158 int i; 159 u32 mask; 160 161 irq_gc_lock(bgc); 162 for (i = 0; i < dgc->irqs_per_chip; i++) { 163 mask = 1 << i; 164 if ((mask & gc->mask_cache) == (mask & gc->wake_active)) 165 continue; 166 167 irq_reg_writel(i + gc->irq_base, 168 bgc->reg_base + AT91_AIC5_SSR); 169 if (mask & gc->wake_active) 170 irq_reg_writel(1, bgc->reg_base + AT91_AIC5_IECR); 171 else 172 irq_reg_writel(1, bgc->reg_base + AT91_AIC5_IDCR); 173 } 174 irq_gc_unlock(bgc); 175 } 176 177 static void aic5_resume(struct irq_data *d) 178 { 179 struct irq_domain *domain = d->domain; 180 struct irq_domain_chip_generic *dgc = domain->gc; 181 struct irq_chip_generic *bgc = dgc->gc[0]; 182 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 183 int i; 184 u32 mask; 185 186 irq_gc_lock(bgc); 187 for (i = 0; i < dgc->irqs_per_chip; i++) { 188 mask = 1 << i; 189 if ((mask & gc->mask_cache) == (mask & gc->wake_active)) 190 continue; 191 192 irq_reg_writel(i + gc->irq_base, 193 bgc->reg_base + AT91_AIC5_SSR); 194 if (mask & gc->mask_cache) 195 irq_reg_writel(1, bgc->reg_base + AT91_AIC5_IECR); 196 else 197 irq_reg_writel(1, bgc->reg_base + AT91_AIC5_IDCR); 198 } 199 irq_gc_unlock(bgc); 200 } 201 202 static void aic5_pm_shutdown(struct irq_data *d) 203 { 204 struct irq_domain *domain = d->domain; 205 struct irq_domain_chip_generic *dgc = domain->gc; 206 struct irq_chip_generic *bgc = dgc->gc[0]; 207 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 208 int i; 209 210 irq_gc_lock(bgc); 211 for (i = 0; i < dgc->irqs_per_chip; i++) { 212 irq_reg_writel(i + gc->irq_base, 213 bgc->reg_base + AT91_AIC5_SSR); 214 irq_reg_writel(1, bgc->reg_base + AT91_AIC5_IDCR); 215 irq_reg_writel(1, bgc->reg_base + AT91_AIC5_ICCR); 216 } 217 irq_gc_unlock(bgc); 218 } 219 #else 220 #define aic5_suspend NULL 221 #define aic5_resume NULL 222 #define aic5_pm_shutdown NULL 223 #endif /* CONFIG_PM */ 224 225 static void __init aic5_hw_init(struct irq_domain *domain) 226 { 227 struct irq_chip_generic *gc = irq_get_domain_generic_chip(domain, 0); 228 int i; 229 230 /* 231 * Perform 8 End Of Interrupt Command to make sure AIC 232 * will not Lock out nIRQ 233 */ 234 for (i = 0; i < 8; i++) 235 irq_reg_writel(0, gc->reg_base + AT91_AIC5_EOICR); 236 237 /* 238 * Spurious Interrupt ID in Spurious Vector Register. 239 * When there is no current interrupt, the IRQ Vector Register 240 * reads the value stored in AIC_SPU 241 */ 242 irq_reg_writel(0xffffffff, gc->reg_base + AT91_AIC5_SPU); 243 244 /* No debugging in AIC: Debug (Protect) Control Register */ 245 irq_reg_writel(0, gc->reg_base + AT91_AIC5_DCR); 246 247 /* Disable and clear all interrupts initially */ 248 for (i = 0; i < domain->revmap_size; i++) { 249 irq_reg_writel(i, gc->reg_base + AT91_AIC5_SSR); 250 irq_reg_writel(i, gc->reg_base + AT91_AIC5_SVR); 251 irq_reg_writel(1, gc->reg_base + AT91_AIC5_IDCR); 252 irq_reg_writel(1, gc->reg_base + AT91_AIC5_ICCR); 253 } 254 } 255 256 static int aic5_irq_domain_xlate(struct irq_domain *d, 257 struct device_node *ctrlr, 258 const u32 *intspec, unsigned int intsize, 259 irq_hw_number_t *out_hwirq, 260 unsigned int *out_type) 261 { 262 struct irq_domain_chip_generic *dgc = d->gc; 263 struct irq_chip_generic *gc; 264 unsigned smr; 265 int ret; 266 267 if (!dgc) 268 return -EINVAL; 269 270 ret = aic_common_irq_domain_xlate(d, ctrlr, intspec, intsize, 271 out_hwirq, out_type); 272 if (ret) 273 return ret; 274 275 gc = dgc->gc[0]; 276 277 irq_gc_lock(gc); 278 irq_reg_writel(*out_hwirq, gc->reg_base + AT91_AIC5_SSR); 279 smr = irq_reg_readl(gc->reg_base + AT91_AIC5_SMR); 280 ret = aic_common_set_priority(intspec[2], &smr); 281 if (!ret) 282 irq_reg_writel(intspec[2] | smr, gc->reg_base + AT91_AIC5_SMR); 283 irq_gc_unlock(gc); 284 285 return ret; 286 } 287 288 static const struct irq_domain_ops aic5_irq_ops = { 289 .map = irq_map_generic_chip, 290 .xlate = aic5_irq_domain_xlate, 291 }; 292 293 static void __init sama5d3_aic_irq_fixup(struct device_node *root) 294 { 295 aic_common_rtc_irq_fixup(root); 296 } 297 298 static const struct of_device_id __initdata aic5_irq_fixups[] = { 299 { .compatible = "atmel,sama5d3", .data = sama5d3_aic_irq_fixup }, 300 { /* sentinel */ }, 301 }; 302 303 static int __init aic5_of_init(struct device_node *node, 304 struct device_node *parent, 305 int nirqs) 306 { 307 struct irq_chip_generic *gc; 308 struct irq_domain *domain; 309 int nchips; 310 int i; 311 312 if (nirqs > NR_AIC5_IRQS) 313 return -EINVAL; 314 315 if (aic5_domain) 316 return -EEXIST; 317 318 domain = aic_common_of_init(node, &aic5_irq_ops, "atmel-aic5", 319 nirqs); 320 if (IS_ERR(domain)) 321 return PTR_ERR(domain); 322 323 aic_common_irq_fixup(aic5_irq_fixups); 324 325 aic5_domain = domain; 326 nchips = aic5_domain->revmap_size / 32; 327 for (i = 0; i < nchips; i++) { 328 gc = irq_get_domain_generic_chip(domain, i * 32); 329 330 gc->chip_types[0].regs.eoi = AT91_AIC5_EOICR; 331 gc->chip_types[0].chip.irq_mask = aic5_mask; 332 gc->chip_types[0].chip.irq_unmask = aic5_unmask; 333 gc->chip_types[0].chip.irq_retrigger = aic5_retrigger; 334 gc->chip_types[0].chip.irq_set_type = aic5_set_type; 335 gc->chip_types[0].chip.irq_suspend = aic5_suspend; 336 gc->chip_types[0].chip.irq_resume = aic5_resume; 337 gc->chip_types[0].chip.irq_pm_shutdown = aic5_pm_shutdown; 338 } 339 340 aic5_hw_init(domain); 341 set_handle_irq(aic5_handle); 342 343 return 0; 344 } 345 346 #define NR_SAMA5D3_IRQS 50 347 348 static int __init sama5d3_aic5_of_init(struct device_node *node, 349 struct device_node *parent) 350 { 351 return aic5_of_init(node, parent, NR_SAMA5D3_IRQS); 352 } 353 IRQCHIP_DECLARE(sama5d3_aic5, "atmel,sama5d3-aic", sama5d3_aic5_of_init); 354