1 /* 2 * Atmel AT91 common AIC (Advanced Interrupt Controller) code shared by 3 * irq-atmel-aic and irq-atmel-aic5 drivers 4 * 5 * Copyright (C) 2004 SAN People 6 * Copyright (C) 2004 ATMEL 7 * Copyright (C) Rick Bronson 8 * Copyright (C) 2014 Free Electrons 9 * 10 * Author: Boris BREZILLON <boris.brezillon@free-electrons.com> 11 * 12 * This file is licensed under the terms of the GNU General Public 13 * License version 2. This program is licensed "as is" without any 14 * warranty of any kind, whether express or implied. 15 */ 16 17 #include <linux/errno.h> 18 #include <linux/io.h> 19 #include <linux/irq.h> 20 #include <linux/irqdomain.h> 21 #include <linux/of.h> 22 #include <linux/of_address.h> 23 #include <linux/slab.h> 24 25 #include "irq-atmel-aic-common.h" 26 27 #define AT91_AIC_PRIOR GENMASK(2, 0) 28 #define AT91_AIC_IRQ_MIN_PRIORITY 0 29 #define AT91_AIC_IRQ_MAX_PRIORITY 7 30 31 #define AT91_AIC_SRCTYPE GENMASK(6, 5) 32 #define AT91_AIC_SRCTYPE_LOW (0 << 5) 33 #define AT91_AIC_SRCTYPE_FALLING (1 << 5) 34 #define AT91_AIC_SRCTYPE_HIGH (2 << 5) 35 #define AT91_AIC_SRCTYPE_RISING (3 << 5) 36 37 struct aic_chip_data { 38 u32 ext_irqs; 39 }; 40 41 static void aic_common_shutdown(struct irq_data *d) 42 { 43 struct irq_chip_type *ct = irq_data_get_chip_type(d); 44 45 ct->chip.irq_mask(d); 46 } 47 48 int aic_common_set_type(struct irq_data *d, unsigned type, unsigned *val) 49 { 50 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 51 struct aic_chip_data *aic = gc->private; 52 unsigned aic_type; 53 54 switch (type) { 55 case IRQ_TYPE_LEVEL_HIGH: 56 aic_type = AT91_AIC_SRCTYPE_HIGH; 57 break; 58 case IRQ_TYPE_EDGE_RISING: 59 aic_type = AT91_AIC_SRCTYPE_RISING; 60 break; 61 case IRQ_TYPE_LEVEL_LOW: 62 if (!(d->mask & aic->ext_irqs)) 63 return -EINVAL; 64 65 aic_type = AT91_AIC_SRCTYPE_LOW; 66 break; 67 case IRQ_TYPE_EDGE_FALLING: 68 if (!(d->mask & aic->ext_irqs)) 69 return -EINVAL; 70 71 aic_type = AT91_AIC_SRCTYPE_FALLING; 72 break; 73 default: 74 return -EINVAL; 75 } 76 77 *val &= ~AT91_AIC_SRCTYPE; 78 *val |= aic_type; 79 80 return 0; 81 } 82 83 void aic_common_set_priority(int priority, unsigned *val) 84 { 85 *val &= ~AT91_AIC_PRIOR; 86 *val |= priority; 87 } 88 89 int aic_common_irq_domain_xlate(struct irq_domain *d, 90 struct device_node *ctrlr, 91 const u32 *intspec, 92 unsigned int intsize, 93 irq_hw_number_t *out_hwirq, 94 unsigned int *out_type) 95 { 96 if (WARN_ON(intsize < 3)) 97 return -EINVAL; 98 99 if (WARN_ON((intspec[2] < AT91_AIC_IRQ_MIN_PRIORITY) || 100 (intspec[2] > AT91_AIC_IRQ_MAX_PRIORITY))) 101 return -EINVAL; 102 103 *out_hwirq = intspec[0]; 104 *out_type = intspec[1] & IRQ_TYPE_SENSE_MASK; 105 106 return 0; 107 } 108 109 static void __init aic_common_ext_irq_of_init(struct irq_domain *domain) 110 { 111 struct device_node *node = irq_domain_get_of_node(domain); 112 struct irq_chip_generic *gc; 113 struct aic_chip_data *aic; 114 struct property *prop; 115 const __be32 *p; 116 u32 hwirq; 117 118 gc = irq_get_domain_generic_chip(domain, 0); 119 120 aic = gc->private; 121 aic->ext_irqs |= 1; 122 123 of_property_for_each_u32(node, "atmel,external-irqs", prop, p, hwirq) { 124 gc = irq_get_domain_generic_chip(domain, hwirq); 125 if (!gc) { 126 pr_warn("AIC: external irq %d >= %d skip it\n", 127 hwirq, domain->revmap_size); 128 continue; 129 } 130 131 aic = gc->private; 132 aic->ext_irqs |= (1 << (hwirq % 32)); 133 } 134 } 135 136 #define AT91_RTC_IDR 0x24 137 #define AT91_RTC_IMR 0x28 138 #define AT91_RTC_IRQ_MASK 0x1f 139 140 void __init aic_common_rtc_irq_fixup(void) 141 { 142 struct device_node *np; 143 void __iomem *regs; 144 145 np = of_find_compatible_node(NULL, NULL, "atmel,at91rm9200-rtc"); 146 if (!np) 147 np = of_find_compatible_node(NULL, NULL, 148 "atmel,at91sam9x5-rtc"); 149 150 if (!np) 151 return; 152 153 regs = of_iomap(np, 0); 154 of_node_put(np); 155 156 if (!regs) 157 return; 158 159 writel(AT91_RTC_IRQ_MASK, regs + AT91_RTC_IDR); 160 161 iounmap(regs); 162 } 163 164 #define AT91_RTT_MR 0x00 /* Real-time Mode Register */ 165 #define AT91_RTT_ALMIEN (1 << 16) /* Alarm Interrupt Enable */ 166 #define AT91_RTT_RTTINCIEN (1 << 17) /* Real Time Timer Increment Interrupt Enable */ 167 168 void __init aic_common_rtt_irq_fixup(void) 169 { 170 struct device_node *np; 171 void __iomem *regs; 172 173 /* 174 * The at91sam9263 SoC has 2 instances of the RTT block, hence we 175 * iterate over the DT to find each occurrence. 176 */ 177 for_each_compatible_node(np, NULL, "atmel,at91sam9260-rtt") { 178 regs = of_iomap(np, 0); 179 if (!regs) 180 continue; 181 182 writel(readl(regs + AT91_RTT_MR) & 183 ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN), 184 regs + AT91_RTT_MR); 185 186 iounmap(regs); 187 } 188 } 189 190 static void __init aic_common_irq_fixup(const struct of_device_id *matches) 191 { 192 struct device_node *root = of_find_node_by_path("/"); 193 const struct of_device_id *match; 194 195 if (!root) 196 return; 197 198 match = of_match_node(matches, root); 199 200 if (match) { 201 void (*fixup)(void) = match->data; 202 fixup(); 203 } 204 205 of_node_put(root); 206 } 207 208 struct irq_domain *__init aic_common_of_init(struct device_node *node, 209 const struct irq_domain_ops *ops, 210 const char *name, int nirqs, 211 const struct of_device_id *matches) 212 { 213 struct irq_chip_generic *gc; 214 struct irq_domain *domain; 215 struct aic_chip_data *aic; 216 void __iomem *reg_base; 217 int nchips; 218 int ret; 219 int i; 220 221 nchips = DIV_ROUND_UP(nirqs, 32); 222 223 reg_base = of_iomap(node, 0); 224 if (!reg_base) 225 return ERR_PTR(-ENOMEM); 226 227 aic = kcalloc(nchips, sizeof(*aic), GFP_KERNEL); 228 if (!aic) { 229 ret = -ENOMEM; 230 goto err_iounmap; 231 } 232 233 domain = irq_domain_add_linear(node, nchips * 32, ops, aic); 234 if (!domain) { 235 ret = -ENOMEM; 236 goto err_free_aic; 237 } 238 239 ret = irq_alloc_domain_generic_chips(domain, 32, 1, name, 240 handle_fasteoi_irq, 241 IRQ_NOREQUEST | IRQ_NOPROBE | 242 IRQ_NOAUTOEN, 0, 0); 243 if (ret) 244 goto err_domain_remove; 245 246 for (i = 0; i < nchips; i++) { 247 gc = irq_get_domain_generic_chip(domain, i * 32); 248 249 gc->reg_base = reg_base; 250 251 gc->unused = 0; 252 gc->wake_enabled = ~0; 253 gc->chip_types[0].type = IRQ_TYPE_SENSE_MASK; 254 gc->chip_types[0].chip.irq_eoi = irq_gc_eoi; 255 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake; 256 gc->chip_types[0].chip.irq_shutdown = aic_common_shutdown; 257 gc->private = &aic[i]; 258 } 259 260 aic_common_ext_irq_of_init(domain); 261 aic_common_irq_fixup(matches); 262 263 return domain; 264 265 err_domain_remove: 266 irq_domain_remove(domain); 267 268 err_free_aic: 269 kfree(aic); 270 271 err_iounmap: 272 iounmap(reg_base); 273 274 return ERR_PTR(ret); 275 } 276