1 /* 2 * Marvell Armada 370 and Armada XP SoC IRQ handling 3 * 4 * Copyright (C) 2012 Marvell 5 * 6 * Lior Amsalem <alior@marvell.com> 7 * Gregory CLEMENT <gregory.clement@free-electrons.com> 8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 9 * Ben Dooks <ben.dooks@codethink.co.uk> 10 * 11 * This file is licensed under the terms of the GNU General Public 12 * License version 2. This program is licensed "as is" without any 13 * warranty of any kind, whether express or implied. 14 */ 15 16 #include <linux/kernel.h> 17 #include <linux/module.h> 18 #include <linux/init.h> 19 #include <linux/irq.h> 20 #include <linux/interrupt.h> 21 #include <linux/irqchip.h> 22 #include <linux/irqchip/chained_irq.h> 23 #include <linux/cpu.h> 24 #include <linux/io.h> 25 #include <linux/of_address.h> 26 #include <linux/of_irq.h> 27 #include <linux/of_pci.h> 28 #include <linux/irqdomain.h> 29 #include <linux/slab.h> 30 #include <linux/syscore_ops.h> 31 #include <linux/msi.h> 32 #include <asm/mach/arch.h> 33 #include <asm/exception.h> 34 #include <asm/smp_plat.h> 35 #include <asm/mach/irq.h> 36 37 /* Interrupt Controller Registers Map */ 38 #define ARMADA_370_XP_INT_SET_MASK_OFFS (0x48) 39 #define ARMADA_370_XP_INT_CLEAR_MASK_OFFS (0x4C) 40 #define ARMADA_370_XP_INT_FABRIC_MASK_OFFS (0x54) 41 #define ARMADA_370_XP_INT_CAUSE_PERF(cpu) (1 << cpu) 42 43 #define ARMADA_370_XP_INT_CONTROL (0x00) 44 #define ARMADA_370_XP_INT_SET_ENABLE_OFFS (0x30) 45 #define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS (0x34) 46 #define ARMADA_370_XP_INT_SOURCE_CTL(irq) (0x100 + irq*4) 47 #define ARMADA_370_XP_INT_SOURCE_CPU_MASK 0xF 48 #define ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid) ((BIT(0) | BIT(8)) << cpuid) 49 50 #define ARMADA_370_XP_CPU_INTACK_OFFS (0x44) 51 #define ARMADA_375_PPI_CAUSE (0x10) 52 53 #define ARMADA_370_XP_SW_TRIG_INT_OFFS (0x4) 54 #define ARMADA_370_XP_IN_DRBEL_MSK_OFFS (0xc) 55 #define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS (0x8) 56 57 #define ARMADA_370_XP_MAX_PER_CPU_IRQS (28) 58 59 #define ARMADA_370_XP_TIMER0_PER_CPU_IRQ (5) 60 #define ARMADA_370_XP_FABRIC_IRQ (3) 61 62 #define IPI_DOORBELL_START (0) 63 #define IPI_DOORBELL_END (8) 64 #define IPI_DOORBELL_MASK 0xFF 65 #define PCI_MSI_DOORBELL_START (16) 66 #define PCI_MSI_DOORBELL_NR (16) 67 #define PCI_MSI_DOORBELL_END (32) 68 #define PCI_MSI_DOORBELL_MASK 0xFFFF0000 69 70 static void __iomem *per_cpu_int_base; 71 static void __iomem *main_int_base; 72 static struct irq_domain *armada_370_xp_mpic_domain; 73 static u32 doorbell_mask_reg; 74 static int parent_irq; 75 #ifdef CONFIG_PCI_MSI 76 static struct irq_domain *armada_370_xp_msi_domain; 77 static DECLARE_BITMAP(msi_used, PCI_MSI_DOORBELL_NR); 78 static DEFINE_MUTEX(msi_used_lock); 79 static phys_addr_t msi_doorbell_addr; 80 #endif 81 82 static inline bool is_percpu_irq(irq_hw_number_t irq) 83 { 84 switch (irq) { 85 case ARMADA_370_XP_TIMER0_PER_CPU_IRQ: 86 case ARMADA_370_XP_FABRIC_IRQ: 87 return true; 88 default: 89 return false; 90 } 91 } 92 93 /* 94 * In SMP mode: 95 * For shared global interrupts, mask/unmask global enable bit 96 * For CPU interrupts, mask/unmask the calling CPU's bit 97 */ 98 static void armada_370_xp_irq_mask(struct irq_data *d) 99 { 100 irq_hw_number_t hwirq = irqd_to_hwirq(d); 101 102 if (!is_percpu_irq(hwirq)) 103 writel(hwirq, main_int_base + 104 ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS); 105 else 106 writel(hwirq, per_cpu_int_base + 107 ARMADA_370_XP_INT_SET_MASK_OFFS); 108 } 109 110 static void armada_370_xp_irq_unmask(struct irq_data *d) 111 { 112 irq_hw_number_t hwirq = irqd_to_hwirq(d); 113 114 if (!is_percpu_irq(hwirq)) 115 writel(hwirq, main_int_base + 116 ARMADA_370_XP_INT_SET_ENABLE_OFFS); 117 else 118 writel(hwirq, per_cpu_int_base + 119 ARMADA_370_XP_INT_CLEAR_MASK_OFFS); 120 } 121 122 #ifdef CONFIG_PCI_MSI 123 124 static int armada_370_xp_alloc_msi(void) 125 { 126 int hwirq; 127 128 mutex_lock(&msi_used_lock); 129 hwirq = find_first_zero_bit(&msi_used, PCI_MSI_DOORBELL_NR); 130 if (hwirq >= PCI_MSI_DOORBELL_NR) 131 hwirq = -ENOSPC; 132 else 133 set_bit(hwirq, msi_used); 134 mutex_unlock(&msi_used_lock); 135 136 return hwirq; 137 } 138 139 static void armada_370_xp_free_msi(int hwirq) 140 { 141 mutex_lock(&msi_used_lock); 142 if (!test_bit(hwirq, msi_used)) 143 pr_err("trying to free unused MSI#%d\n", hwirq); 144 else 145 clear_bit(hwirq, msi_used); 146 mutex_unlock(&msi_used_lock); 147 } 148 149 static int armada_370_xp_setup_msi_irq(struct msi_controller *chip, 150 struct pci_dev *pdev, 151 struct msi_desc *desc) 152 { 153 struct msi_msg msg; 154 int virq, hwirq; 155 156 /* We support MSI, but not MSI-X */ 157 if (desc->msi_attrib.is_msix) 158 return -EINVAL; 159 160 hwirq = armada_370_xp_alloc_msi(); 161 if (hwirq < 0) 162 return hwirq; 163 164 virq = irq_create_mapping(armada_370_xp_msi_domain, hwirq); 165 if (!virq) { 166 armada_370_xp_free_msi(hwirq); 167 return -EINVAL; 168 } 169 170 irq_set_msi_desc(virq, desc); 171 172 msg.address_lo = msi_doorbell_addr; 173 msg.address_hi = 0; 174 msg.data = 0xf00 | (hwirq + 16); 175 176 pci_write_msi_msg(virq, &msg); 177 return 0; 178 } 179 180 static void armada_370_xp_teardown_msi_irq(struct msi_controller *chip, 181 unsigned int irq) 182 { 183 struct irq_data *d = irq_get_irq_data(irq); 184 unsigned long hwirq = d->hwirq; 185 186 irq_dispose_mapping(irq); 187 armada_370_xp_free_msi(hwirq); 188 } 189 190 static struct irq_chip armada_370_xp_msi_irq_chip = { 191 .name = "armada_370_xp_msi_irq", 192 .irq_enable = pci_msi_unmask_irq, 193 .irq_disable = pci_msi_mask_irq, 194 .irq_mask = pci_msi_mask_irq, 195 .irq_unmask = pci_msi_unmask_irq, 196 }; 197 198 static int armada_370_xp_msi_map(struct irq_domain *domain, unsigned int virq, 199 irq_hw_number_t hw) 200 { 201 irq_set_chip_and_handler(virq, &armada_370_xp_msi_irq_chip, 202 handle_simple_irq); 203 204 return 0; 205 } 206 207 static const struct irq_domain_ops armada_370_xp_msi_irq_ops = { 208 .map = armada_370_xp_msi_map, 209 }; 210 211 static int armada_370_xp_msi_init(struct device_node *node, 212 phys_addr_t main_int_phys_base) 213 { 214 struct msi_controller *msi_chip; 215 u32 reg; 216 int ret; 217 218 msi_doorbell_addr = main_int_phys_base + 219 ARMADA_370_XP_SW_TRIG_INT_OFFS; 220 221 msi_chip = kzalloc(sizeof(*msi_chip), GFP_KERNEL); 222 if (!msi_chip) 223 return -ENOMEM; 224 225 msi_chip->setup_irq = armada_370_xp_setup_msi_irq; 226 msi_chip->teardown_irq = armada_370_xp_teardown_msi_irq; 227 msi_chip->of_node = node; 228 229 armada_370_xp_msi_domain = 230 irq_domain_add_linear(NULL, PCI_MSI_DOORBELL_NR, 231 &armada_370_xp_msi_irq_ops, 232 NULL); 233 if (!armada_370_xp_msi_domain) { 234 kfree(msi_chip); 235 return -ENOMEM; 236 } 237 238 ret = of_pci_msi_chip_add(msi_chip); 239 if (ret < 0) { 240 irq_domain_remove(armada_370_xp_msi_domain); 241 kfree(msi_chip); 242 return ret; 243 } 244 245 reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS) 246 | PCI_MSI_DOORBELL_MASK; 247 248 writel(reg, per_cpu_int_base + 249 ARMADA_370_XP_IN_DRBEL_MSK_OFFS); 250 251 /* Unmask IPI interrupt */ 252 writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); 253 254 return 0; 255 } 256 #else 257 static inline int armada_370_xp_msi_init(struct device_node *node, 258 phys_addr_t main_int_phys_base) 259 { 260 return 0; 261 } 262 #endif 263 264 #ifdef CONFIG_SMP 265 static DEFINE_RAW_SPINLOCK(irq_controller_lock); 266 267 static int armada_xp_set_affinity(struct irq_data *d, 268 const struct cpumask *mask_val, bool force) 269 { 270 irq_hw_number_t hwirq = irqd_to_hwirq(d); 271 unsigned long reg, mask; 272 int cpu; 273 274 /* Select a single core from the affinity mask which is online */ 275 cpu = cpumask_any_and(mask_val, cpu_online_mask); 276 mask = 1UL << cpu_logical_map(cpu); 277 278 raw_spin_lock(&irq_controller_lock); 279 reg = readl(main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq)); 280 reg = (reg & (~ARMADA_370_XP_INT_SOURCE_CPU_MASK)) | mask; 281 writel(reg, main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq)); 282 raw_spin_unlock(&irq_controller_lock); 283 284 return IRQ_SET_MASK_OK; 285 } 286 #endif 287 288 static struct irq_chip armada_370_xp_irq_chip = { 289 .name = "armada_370_xp_irq", 290 .irq_mask = armada_370_xp_irq_mask, 291 .irq_mask_ack = armada_370_xp_irq_mask, 292 .irq_unmask = armada_370_xp_irq_unmask, 293 #ifdef CONFIG_SMP 294 .irq_set_affinity = armada_xp_set_affinity, 295 #endif 296 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND, 297 }; 298 299 static int armada_370_xp_mpic_irq_map(struct irq_domain *h, 300 unsigned int virq, irq_hw_number_t hw) 301 { 302 armada_370_xp_irq_mask(irq_get_irq_data(virq)); 303 if (!is_percpu_irq(hw)) 304 writel(hw, per_cpu_int_base + 305 ARMADA_370_XP_INT_CLEAR_MASK_OFFS); 306 else 307 writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS); 308 irq_set_status_flags(virq, IRQ_LEVEL); 309 310 if (is_percpu_irq(hw)) { 311 irq_set_percpu_devid(virq); 312 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip, 313 handle_percpu_devid_irq); 314 315 } else { 316 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip, 317 handle_level_irq); 318 } 319 irq_set_probe(virq); 320 irq_clear_status_flags(virq, IRQ_NOAUTOEN); 321 322 return 0; 323 } 324 325 static void armada_xp_mpic_smp_cpu_init(void) 326 { 327 u32 control; 328 int nr_irqs, i; 329 330 control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL); 331 nr_irqs = (control >> 2) & 0x3ff; 332 333 for (i = 0; i < nr_irqs; i++) 334 writel(i, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS); 335 336 /* Clear pending IPIs */ 337 writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS); 338 339 /* Enable first 8 IPIs */ 340 writel(IPI_DOORBELL_MASK, per_cpu_int_base + 341 ARMADA_370_XP_IN_DRBEL_MSK_OFFS); 342 343 /* Unmask IPI interrupt */ 344 writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); 345 } 346 347 static void armada_xp_mpic_perf_init(void) 348 { 349 unsigned long cpuid = cpu_logical_map(smp_processor_id()); 350 351 /* Enable Performance Counter Overflow interrupts */ 352 writel(ARMADA_370_XP_INT_CAUSE_PERF(cpuid), 353 per_cpu_int_base + ARMADA_370_XP_INT_FABRIC_MASK_OFFS); 354 } 355 356 #ifdef CONFIG_SMP 357 static void armada_mpic_send_doorbell(const struct cpumask *mask, 358 unsigned int irq) 359 { 360 int cpu; 361 unsigned long map = 0; 362 363 /* Convert our logical CPU mask into a physical one. */ 364 for_each_cpu(cpu, mask) 365 map |= 1 << cpu_logical_map(cpu); 366 367 /* 368 * Ensure that stores to Normal memory are visible to the 369 * other CPUs before issuing the IPI. 370 */ 371 dsb(); 372 373 /* submit softirq */ 374 writel((map << 8) | irq, main_int_base + 375 ARMADA_370_XP_SW_TRIG_INT_OFFS); 376 } 377 378 static int armada_xp_mpic_secondary_init(struct notifier_block *nfb, 379 unsigned long action, void *hcpu) 380 { 381 if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) { 382 armada_xp_mpic_perf_init(); 383 armada_xp_mpic_smp_cpu_init(); 384 } 385 386 return NOTIFY_OK; 387 } 388 389 static struct notifier_block armada_370_xp_mpic_cpu_notifier = { 390 .notifier_call = armada_xp_mpic_secondary_init, 391 .priority = 100, 392 }; 393 394 static int mpic_cascaded_secondary_init(struct notifier_block *nfb, 395 unsigned long action, void *hcpu) 396 { 397 if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) { 398 armada_xp_mpic_perf_init(); 399 enable_percpu_irq(parent_irq, IRQ_TYPE_NONE); 400 } 401 402 return NOTIFY_OK; 403 } 404 405 static struct notifier_block mpic_cascaded_cpu_notifier = { 406 .notifier_call = mpic_cascaded_secondary_init, 407 .priority = 100, 408 }; 409 #endif /* CONFIG_SMP */ 410 411 static const struct irq_domain_ops armada_370_xp_mpic_irq_ops = { 412 .map = armada_370_xp_mpic_irq_map, 413 .xlate = irq_domain_xlate_onecell, 414 }; 415 416 #ifdef CONFIG_PCI_MSI 417 static void armada_370_xp_handle_msi_irq(struct pt_regs *regs, bool is_chained) 418 { 419 u32 msimask, msinr; 420 421 msimask = readl_relaxed(per_cpu_int_base + 422 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS) 423 & PCI_MSI_DOORBELL_MASK; 424 425 writel(~msimask, per_cpu_int_base + 426 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS); 427 428 for (msinr = PCI_MSI_DOORBELL_START; 429 msinr < PCI_MSI_DOORBELL_END; msinr++) { 430 int irq; 431 432 if (!(msimask & BIT(msinr))) 433 continue; 434 435 if (is_chained) { 436 irq = irq_find_mapping(armada_370_xp_msi_domain, 437 msinr - 16); 438 generic_handle_irq(irq); 439 } else { 440 irq = msinr - 16; 441 handle_domain_irq(armada_370_xp_msi_domain, 442 irq, regs); 443 } 444 } 445 } 446 #else 447 static void armada_370_xp_handle_msi_irq(struct pt_regs *r, bool b) {} 448 #endif 449 450 static void armada_370_xp_mpic_handle_cascade_irq(struct irq_desc *desc) 451 { 452 struct irq_chip *chip = irq_desc_get_chip(desc); 453 unsigned long irqmap, irqn, irqsrc, cpuid; 454 unsigned int cascade_irq; 455 456 chained_irq_enter(chip, desc); 457 458 irqmap = readl_relaxed(per_cpu_int_base + ARMADA_375_PPI_CAUSE); 459 cpuid = cpu_logical_map(smp_processor_id()); 460 461 for_each_set_bit(irqn, &irqmap, BITS_PER_LONG) { 462 irqsrc = readl_relaxed(main_int_base + 463 ARMADA_370_XP_INT_SOURCE_CTL(irqn)); 464 465 /* Check if the interrupt is not masked on current CPU. 466 * Test IRQ (0-1) and FIQ (8-9) mask bits. 467 */ 468 if (!(irqsrc & ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid))) 469 continue; 470 471 if (irqn == 1) { 472 armada_370_xp_handle_msi_irq(NULL, true); 473 continue; 474 } 475 476 cascade_irq = irq_find_mapping(armada_370_xp_mpic_domain, irqn); 477 generic_handle_irq(cascade_irq); 478 } 479 480 chained_irq_exit(chip, desc); 481 } 482 483 static void __exception_irq_entry 484 armada_370_xp_handle_irq(struct pt_regs *regs) 485 { 486 u32 irqstat, irqnr; 487 488 do { 489 irqstat = readl_relaxed(per_cpu_int_base + 490 ARMADA_370_XP_CPU_INTACK_OFFS); 491 irqnr = irqstat & 0x3FF; 492 493 if (irqnr > 1022) 494 break; 495 496 if (irqnr > 1) { 497 handle_domain_irq(armada_370_xp_mpic_domain, 498 irqnr, regs); 499 continue; 500 } 501 502 /* MSI handling */ 503 if (irqnr == 1) 504 armada_370_xp_handle_msi_irq(regs, false); 505 506 #ifdef CONFIG_SMP 507 /* IPI Handling */ 508 if (irqnr == 0) { 509 u32 ipimask, ipinr; 510 511 ipimask = readl_relaxed(per_cpu_int_base + 512 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS) 513 & IPI_DOORBELL_MASK; 514 515 writel(~ipimask, per_cpu_int_base + 516 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS); 517 518 /* Handle all pending doorbells */ 519 for (ipinr = IPI_DOORBELL_START; 520 ipinr < IPI_DOORBELL_END; ipinr++) { 521 if (ipimask & (0x1 << ipinr)) 522 handle_IPI(ipinr, regs); 523 } 524 continue; 525 } 526 #endif 527 528 } while (1); 529 } 530 531 static int armada_370_xp_mpic_suspend(void) 532 { 533 doorbell_mask_reg = readl(per_cpu_int_base + 534 ARMADA_370_XP_IN_DRBEL_MSK_OFFS); 535 return 0; 536 } 537 538 static void armada_370_xp_mpic_resume(void) 539 { 540 int nirqs; 541 irq_hw_number_t irq; 542 543 /* Re-enable interrupts */ 544 nirqs = (readl(main_int_base + ARMADA_370_XP_INT_CONTROL) >> 2) & 0x3ff; 545 for (irq = 0; irq < nirqs; irq++) { 546 struct irq_data *data; 547 int virq; 548 549 virq = irq_linear_revmap(armada_370_xp_mpic_domain, irq); 550 if (virq == 0) 551 continue; 552 553 if (irq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ) 554 writel(irq, per_cpu_int_base + 555 ARMADA_370_XP_INT_CLEAR_MASK_OFFS); 556 else 557 writel(irq, main_int_base + 558 ARMADA_370_XP_INT_SET_ENABLE_OFFS); 559 560 data = irq_get_irq_data(virq); 561 if (!irqd_irq_disabled(data)) 562 armada_370_xp_irq_unmask(data); 563 } 564 565 /* Reconfigure doorbells for IPIs and MSIs */ 566 writel(doorbell_mask_reg, 567 per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS); 568 if (doorbell_mask_reg & IPI_DOORBELL_MASK) 569 writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); 570 if (doorbell_mask_reg & PCI_MSI_DOORBELL_MASK) 571 writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); 572 } 573 574 struct syscore_ops armada_370_xp_mpic_syscore_ops = { 575 .suspend = armada_370_xp_mpic_suspend, 576 .resume = armada_370_xp_mpic_resume, 577 }; 578 579 static int __init armada_370_xp_mpic_of_init(struct device_node *node, 580 struct device_node *parent) 581 { 582 struct resource main_int_res, per_cpu_int_res; 583 int nr_irqs, i; 584 u32 control; 585 586 BUG_ON(of_address_to_resource(node, 0, &main_int_res)); 587 BUG_ON(of_address_to_resource(node, 1, &per_cpu_int_res)); 588 589 BUG_ON(!request_mem_region(main_int_res.start, 590 resource_size(&main_int_res), 591 node->full_name)); 592 BUG_ON(!request_mem_region(per_cpu_int_res.start, 593 resource_size(&per_cpu_int_res), 594 node->full_name)); 595 596 main_int_base = ioremap(main_int_res.start, 597 resource_size(&main_int_res)); 598 BUG_ON(!main_int_base); 599 600 per_cpu_int_base = ioremap(per_cpu_int_res.start, 601 resource_size(&per_cpu_int_res)); 602 BUG_ON(!per_cpu_int_base); 603 604 control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL); 605 nr_irqs = (control >> 2) & 0x3ff; 606 607 for (i = 0; i < nr_irqs; i++) 608 writel(i, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS); 609 610 armada_370_xp_mpic_domain = 611 irq_domain_add_linear(node, nr_irqs, 612 &armada_370_xp_mpic_irq_ops, NULL); 613 614 BUG_ON(!armada_370_xp_mpic_domain); 615 616 /* Setup for the boot CPU */ 617 armada_xp_mpic_perf_init(); 618 armada_xp_mpic_smp_cpu_init(); 619 620 armada_370_xp_msi_init(node, main_int_res.start); 621 622 parent_irq = irq_of_parse_and_map(node, 0); 623 if (parent_irq <= 0) { 624 irq_set_default_host(armada_370_xp_mpic_domain); 625 set_handle_irq(armada_370_xp_handle_irq); 626 #ifdef CONFIG_SMP 627 set_smp_cross_call(armada_mpic_send_doorbell); 628 register_cpu_notifier(&armada_370_xp_mpic_cpu_notifier); 629 #endif 630 } else { 631 #ifdef CONFIG_SMP 632 register_cpu_notifier(&mpic_cascaded_cpu_notifier); 633 #endif 634 irq_set_chained_handler(parent_irq, 635 armada_370_xp_mpic_handle_cascade_irq); 636 } 637 638 register_syscore_ops(&armada_370_xp_mpic_syscore_ops); 639 640 return 0; 641 } 642 643 IRQCHIP_DECLARE(armada_370_xp_mpic, "marvell,mpic", armada_370_xp_mpic_of_init); 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