1 /* 2 * Marvell Armada 370 and Armada XP SoC IRQ handling 3 * 4 * Copyright (C) 2012 Marvell 5 * 6 * Lior Amsalem <alior@marvell.com> 7 * Gregory CLEMENT <gregory.clement@free-electrons.com> 8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 9 * Ben Dooks <ben.dooks@codethink.co.uk> 10 * 11 * This file is licensed under the terms of the GNU General Public 12 * License version 2. This program is licensed "as is" without any 13 * warranty of any kind, whether express or implied. 14 */ 15 16 #include <linux/bits.h> 17 #include <linux/kernel.h> 18 #include <linux/module.h> 19 #include <linux/init.h> 20 #include <linux/irq.h> 21 #include <linux/interrupt.h> 22 #include <linux/irqchip.h> 23 #include <linux/irqchip/chained_irq.h> 24 #include <linux/cpu.h> 25 #include <linux/io.h> 26 #include <linux/of_address.h> 27 #include <linux/of_irq.h> 28 #include <linux/of_pci.h> 29 #include <linux/irqdomain.h> 30 #include <linux/slab.h> 31 #include <linux/syscore_ops.h> 32 #include <linux/msi.h> 33 #include <linux/types.h> 34 #include <asm/mach/arch.h> 35 #include <asm/exception.h> 36 #include <asm/smp_plat.h> 37 #include <asm/mach/irq.h> 38 39 /* 40 * Overall diagram of the Armada XP interrupt controller: 41 * 42 * To CPU 0 To CPU 1 43 * 44 * /\ /\ 45 * || || 46 * +---------------+ +---------------+ 47 * | | | | 48 * | per-CPU | | per-CPU | 49 * | mask/unmask | | mask/unmask | 50 * | CPU0 | | CPU1 | 51 * | | | | 52 * +---------------+ +---------------+ 53 * /\ /\ 54 * || || 55 * \\_______________________// 56 * || 57 * +-------------------+ 58 * | | 59 * | Global interrupt | 60 * | mask/unmask | 61 * | | 62 * +-------------------+ 63 * /\ 64 * || 65 * interrupt from 66 * device 67 * 68 * The "global interrupt mask/unmask" is modified using the 69 * ARMADA_370_XP_INT_SET_ENABLE_OFFS and 70 * ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS registers, which are relative 71 * to "main_int_base". 72 * 73 * The "per-CPU mask/unmask" is modified using the 74 * ARMADA_370_XP_INT_SET_MASK_OFFS and 75 * ARMADA_370_XP_INT_CLEAR_MASK_OFFS registers, which are relative to 76 * "per_cpu_int_base". This base address points to a special address, 77 * which automatically accesses the registers of the current CPU. 78 * 79 * The per-CPU mask/unmask can also be adjusted using the global 80 * per-interrupt ARMADA_370_XP_INT_SOURCE_CTL register, which we use 81 * to configure interrupt affinity. 82 * 83 * Due to this model, all interrupts need to be mask/unmasked at two 84 * different levels: at the global level and at the per-CPU level. 85 * 86 * This driver takes the following approach to deal with this: 87 * 88 * - For global interrupts: 89 * 90 * At ->map() time, a global interrupt is unmasked at the per-CPU 91 * mask/unmask level. It is therefore unmasked at this level for 92 * the current CPU, running the ->map() code. This allows to have 93 * the interrupt unmasked at this level in non-SMP 94 * configurations. In SMP configurations, the ->set_affinity() 95 * callback is called, which using the 96 * ARMADA_370_XP_INT_SOURCE_CTL() readjusts the per-CPU mask/unmask 97 * for the interrupt. 98 * 99 * The ->mask() and ->unmask() operations only mask/unmask the 100 * interrupt at the "global" level. 101 * 102 * So, a global interrupt is enabled at the per-CPU level as soon 103 * as it is mapped. At run time, the masking/unmasking takes place 104 * at the global level. 105 * 106 * - For per-CPU interrupts 107 * 108 * At ->map() time, a per-CPU interrupt is unmasked at the global 109 * mask/unmask level. 110 * 111 * The ->mask() and ->unmask() operations mask/unmask the interrupt 112 * at the per-CPU level. 113 * 114 * So, a per-CPU interrupt is enabled at the global level as soon 115 * as it is mapped. At run time, the masking/unmasking takes place 116 * at the per-CPU level. 117 */ 118 119 /* Registers relative to main_int_base */ 120 #define ARMADA_370_XP_INT_CONTROL (0x00) 121 #define ARMADA_370_XP_SW_TRIG_INT_OFFS (0x04) 122 #define ARMADA_370_XP_INT_SET_ENABLE_OFFS (0x30) 123 #define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS (0x34) 124 #define ARMADA_370_XP_INT_SOURCE_CTL(irq) (0x100 + irq*4) 125 #define ARMADA_370_XP_INT_SOURCE_CPU_MASK 0xF 126 #define ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid) ((BIT(0) | BIT(8)) << cpuid) 127 128 /* Registers relative to per_cpu_int_base */ 129 #define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS (0x08) 130 #define ARMADA_370_XP_IN_DRBEL_MSK_OFFS (0x0c) 131 #define ARMADA_375_PPI_CAUSE (0x10) 132 #define ARMADA_370_XP_CPU_INTACK_OFFS (0x44) 133 #define ARMADA_370_XP_INT_SET_MASK_OFFS (0x48) 134 #define ARMADA_370_XP_INT_CLEAR_MASK_OFFS (0x4C) 135 #define ARMADA_370_XP_INT_FABRIC_MASK_OFFS (0x54) 136 #define ARMADA_370_XP_INT_CAUSE_PERF(cpu) (1 << cpu) 137 138 #define ARMADA_370_XP_MAX_PER_CPU_IRQS (28) 139 140 /* IPI and MSI interrupt definitions for IPI platforms */ 141 #define IPI_DOORBELL_START (0) 142 #define IPI_DOORBELL_END (8) 143 #define IPI_DOORBELL_MASK 0xFF 144 #define PCI_MSI_DOORBELL_START (16) 145 #define PCI_MSI_DOORBELL_NR (16) 146 #define PCI_MSI_DOORBELL_END (32) 147 #define PCI_MSI_DOORBELL_MASK 0xFFFF0000 148 149 /* MSI interrupt definitions for non-IPI platforms */ 150 #define PCI_MSI_FULL_DOORBELL_START 0 151 #define PCI_MSI_FULL_DOORBELL_NR 32 152 #define PCI_MSI_FULL_DOORBELL_END 32 153 #define PCI_MSI_FULL_DOORBELL_MASK GENMASK(31, 0) 154 #define PCI_MSI_FULL_DOORBELL_SRC0_MASK GENMASK(15, 0) 155 #define PCI_MSI_FULL_DOORBELL_SRC1_MASK GENMASK(31, 16) 156 157 static void __iomem *per_cpu_int_base; 158 static void __iomem *main_int_base; 159 static struct irq_domain *armada_370_xp_mpic_domain; 160 static u32 doorbell_mask_reg; 161 static int parent_irq; 162 #ifdef CONFIG_PCI_MSI 163 static struct irq_domain *armada_370_xp_msi_domain; 164 static struct irq_domain *armada_370_xp_msi_inner_domain; 165 static DECLARE_BITMAP(msi_used, PCI_MSI_FULL_DOORBELL_NR); 166 static DEFINE_MUTEX(msi_used_lock); 167 static phys_addr_t msi_doorbell_addr; 168 #endif 169 170 static inline bool is_ipi_available(void) 171 { 172 /* 173 * We distinguish IPI availability in the IC by the IC not having a 174 * parent irq defined. If a parent irq is defined, there is a parent 175 * interrupt controller (e.g. GIC) that takes care of inter-processor 176 * interrupts. 177 */ 178 return parent_irq <= 0; 179 } 180 181 static inline u32 msi_doorbell_mask(void) 182 { 183 return is_ipi_available() ? PCI_MSI_DOORBELL_MASK : 184 PCI_MSI_FULL_DOORBELL_MASK; 185 } 186 187 static inline unsigned int msi_doorbell_start(void) 188 { 189 return is_ipi_available() ? PCI_MSI_DOORBELL_START : 190 PCI_MSI_FULL_DOORBELL_START; 191 } 192 193 static inline unsigned int msi_doorbell_size(void) 194 { 195 return is_ipi_available() ? PCI_MSI_DOORBELL_NR : 196 PCI_MSI_FULL_DOORBELL_NR; 197 } 198 199 static inline unsigned int msi_doorbell_end(void) 200 { 201 return is_ipi_available() ? PCI_MSI_DOORBELL_END : 202 PCI_MSI_FULL_DOORBELL_END; 203 } 204 205 static inline bool is_percpu_irq(irq_hw_number_t irq) 206 { 207 if (irq <= ARMADA_370_XP_MAX_PER_CPU_IRQS) 208 return true; 209 210 return false; 211 } 212 213 /* 214 * In SMP mode: 215 * For shared global interrupts, mask/unmask global enable bit 216 * For CPU interrupts, mask/unmask the calling CPU's bit 217 */ 218 static void armada_370_xp_irq_mask(struct irq_data *d) 219 { 220 irq_hw_number_t hwirq = irqd_to_hwirq(d); 221 222 if (!is_percpu_irq(hwirq)) 223 writel(hwirq, main_int_base + 224 ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS); 225 else 226 writel(hwirq, per_cpu_int_base + 227 ARMADA_370_XP_INT_SET_MASK_OFFS); 228 } 229 230 static void armada_370_xp_irq_unmask(struct irq_data *d) 231 { 232 irq_hw_number_t hwirq = irqd_to_hwirq(d); 233 234 if (!is_percpu_irq(hwirq)) 235 writel(hwirq, main_int_base + 236 ARMADA_370_XP_INT_SET_ENABLE_OFFS); 237 else 238 writel(hwirq, per_cpu_int_base + 239 ARMADA_370_XP_INT_CLEAR_MASK_OFFS); 240 } 241 242 #ifdef CONFIG_PCI_MSI 243 244 static struct irq_chip armada_370_xp_msi_irq_chip = { 245 .name = "MPIC MSI", 246 .irq_mask = pci_msi_mask_irq, 247 .irq_unmask = pci_msi_unmask_irq, 248 }; 249 250 static struct msi_domain_info armada_370_xp_msi_domain_info = { 251 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 252 MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX), 253 .chip = &armada_370_xp_msi_irq_chip, 254 }; 255 256 static void armada_370_xp_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) 257 { 258 unsigned int cpu = cpumask_first(irq_data_get_effective_affinity_mask(data)); 259 260 msg->address_lo = lower_32_bits(msi_doorbell_addr); 261 msg->address_hi = upper_32_bits(msi_doorbell_addr); 262 msg->data = BIT(cpu + 8) | (data->hwirq + msi_doorbell_start()); 263 } 264 265 static int armada_370_xp_msi_set_affinity(struct irq_data *irq_data, 266 const struct cpumask *mask, bool force) 267 { 268 unsigned int cpu; 269 270 if (!force) 271 cpu = cpumask_any_and(mask, cpu_online_mask); 272 else 273 cpu = cpumask_first(mask); 274 275 if (cpu >= nr_cpu_ids) 276 return -EINVAL; 277 278 irq_data_update_effective_affinity(irq_data, cpumask_of(cpu)); 279 280 return IRQ_SET_MASK_OK; 281 } 282 283 static struct irq_chip armada_370_xp_msi_bottom_irq_chip = { 284 .name = "MPIC MSI", 285 .irq_compose_msi_msg = armada_370_xp_compose_msi_msg, 286 .irq_set_affinity = armada_370_xp_msi_set_affinity, 287 }; 288 289 static int armada_370_xp_msi_alloc(struct irq_domain *domain, unsigned int virq, 290 unsigned int nr_irqs, void *args) 291 { 292 int hwirq, i; 293 294 mutex_lock(&msi_used_lock); 295 hwirq = bitmap_find_free_region(msi_used, msi_doorbell_size(), 296 order_base_2(nr_irqs)); 297 mutex_unlock(&msi_used_lock); 298 299 if (hwirq < 0) 300 return -ENOSPC; 301 302 for (i = 0; i < nr_irqs; i++) { 303 irq_domain_set_info(domain, virq + i, hwirq + i, 304 &armada_370_xp_msi_bottom_irq_chip, 305 domain->host_data, handle_simple_irq, 306 NULL, NULL); 307 } 308 309 return 0; 310 } 311 312 static void armada_370_xp_msi_free(struct irq_domain *domain, 313 unsigned int virq, unsigned int nr_irqs) 314 { 315 struct irq_data *d = irq_domain_get_irq_data(domain, virq); 316 317 mutex_lock(&msi_used_lock); 318 bitmap_release_region(msi_used, d->hwirq, order_base_2(nr_irqs)); 319 mutex_unlock(&msi_used_lock); 320 } 321 322 static const struct irq_domain_ops armada_370_xp_msi_domain_ops = { 323 .alloc = armada_370_xp_msi_alloc, 324 .free = armada_370_xp_msi_free, 325 }; 326 327 static void armada_370_xp_msi_reenable_percpu(void) 328 { 329 u32 reg; 330 331 /* Enable MSI doorbell mask and combined cpu local interrupt */ 332 reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS); 333 reg |= msi_doorbell_mask(); 334 writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS); 335 336 /* Unmask local doorbell interrupt */ 337 writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); 338 } 339 340 static int armada_370_xp_msi_init(struct device_node *node, 341 phys_addr_t main_int_phys_base) 342 { 343 msi_doorbell_addr = main_int_phys_base + 344 ARMADA_370_XP_SW_TRIG_INT_OFFS; 345 346 armada_370_xp_msi_inner_domain = 347 irq_domain_add_linear(NULL, msi_doorbell_size(), 348 &armada_370_xp_msi_domain_ops, NULL); 349 if (!armada_370_xp_msi_inner_domain) 350 return -ENOMEM; 351 352 armada_370_xp_msi_domain = 353 pci_msi_create_irq_domain(of_node_to_fwnode(node), 354 &armada_370_xp_msi_domain_info, 355 armada_370_xp_msi_inner_domain); 356 if (!armada_370_xp_msi_domain) { 357 irq_domain_remove(armada_370_xp_msi_inner_domain); 358 return -ENOMEM; 359 } 360 361 armada_370_xp_msi_reenable_percpu(); 362 363 /* Unmask low 16 MSI irqs on non-IPI platforms */ 364 if (!is_ipi_available()) 365 writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); 366 367 return 0; 368 } 369 #else 370 static __maybe_unused void armada_370_xp_msi_reenable_percpu(void) {} 371 372 static inline int armada_370_xp_msi_init(struct device_node *node, 373 phys_addr_t main_int_phys_base) 374 { 375 return 0; 376 } 377 #endif 378 379 static void armada_xp_mpic_perf_init(void) 380 { 381 unsigned long cpuid; 382 383 /* 384 * This Performance Counter Overflow interrupt is specific for 385 * Armada 370 and XP. It is not available on Armada 375, 38x and 39x. 386 */ 387 if (!of_machine_is_compatible("marvell,armada-370-xp")) 388 return; 389 390 cpuid = cpu_logical_map(smp_processor_id()); 391 392 /* Enable Performance Counter Overflow interrupts */ 393 writel(ARMADA_370_XP_INT_CAUSE_PERF(cpuid), 394 per_cpu_int_base + ARMADA_370_XP_INT_FABRIC_MASK_OFFS); 395 } 396 397 #ifdef CONFIG_SMP 398 static struct irq_domain *ipi_domain; 399 400 static void armada_370_xp_ipi_mask(struct irq_data *d) 401 { 402 u32 reg; 403 reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS); 404 reg &= ~BIT(d->hwirq); 405 writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS); 406 } 407 408 static void armada_370_xp_ipi_unmask(struct irq_data *d) 409 { 410 u32 reg; 411 reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS); 412 reg |= BIT(d->hwirq); 413 writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS); 414 } 415 416 static void armada_370_xp_ipi_send_mask(struct irq_data *d, 417 const struct cpumask *mask) 418 { 419 unsigned long map = 0; 420 int cpu; 421 422 /* Convert our logical CPU mask into a physical one. */ 423 for_each_cpu(cpu, mask) 424 map |= 1 << cpu_logical_map(cpu); 425 426 /* 427 * Ensure that stores to Normal memory are visible to the 428 * other CPUs before issuing the IPI. 429 */ 430 dsb(); 431 432 /* submit softirq */ 433 writel((map << 8) | d->hwirq, main_int_base + 434 ARMADA_370_XP_SW_TRIG_INT_OFFS); 435 } 436 437 static void armada_370_xp_ipi_ack(struct irq_data *d) 438 { 439 writel(~BIT(d->hwirq), per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS); 440 } 441 442 static struct irq_chip ipi_irqchip = { 443 .name = "IPI", 444 .irq_ack = armada_370_xp_ipi_ack, 445 .irq_mask = armada_370_xp_ipi_mask, 446 .irq_unmask = armada_370_xp_ipi_unmask, 447 .ipi_send_mask = armada_370_xp_ipi_send_mask, 448 }; 449 450 static int armada_370_xp_ipi_alloc(struct irq_domain *d, 451 unsigned int virq, 452 unsigned int nr_irqs, void *args) 453 { 454 int i; 455 456 for (i = 0; i < nr_irqs; i++) { 457 irq_set_percpu_devid(virq + i); 458 irq_domain_set_info(d, virq + i, i, &ipi_irqchip, 459 d->host_data, 460 handle_percpu_devid_irq, 461 NULL, NULL); 462 } 463 464 return 0; 465 } 466 467 static void armada_370_xp_ipi_free(struct irq_domain *d, 468 unsigned int virq, 469 unsigned int nr_irqs) 470 { 471 /* Not freeing IPIs */ 472 } 473 474 static const struct irq_domain_ops ipi_domain_ops = { 475 .alloc = armada_370_xp_ipi_alloc, 476 .free = armada_370_xp_ipi_free, 477 }; 478 479 static void ipi_resume(void) 480 { 481 int i; 482 483 for (i = 0; i < IPI_DOORBELL_END; i++) { 484 int irq; 485 486 irq = irq_find_mapping(ipi_domain, i); 487 if (irq <= 0) 488 continue; 489 if (irq_percpu_is_enabled(irq)) { 490 struct irq_data *d; 491 d = irq_domain_get_irq_data(ipi_domain, irq); 492 armada_370_xp_ipi_unmask(d); 493 } 494 } 495 } 496 497 static __init void armada_xp_ipi_init(struct device_node *node) 498 { 499 int base_ipi; 500 501 ipi_domain = irq_domain_create_linear(of_node_to_fwnode(node), 502 IPI_DOORBELL_END, 503 &ipi_domain_ops, NULL); 504 if (WARN_ON(!ipi_domain)) 505 return; 506 507 irq_domain_update_bus_token(ipi_domain, DOMAIN_BUS_IPI); 508 base_ipi = irq_domain_alloc_irqs(ipi_domain, IPI_DOORBELL_END, NUMA_NO_NODE, NULL); 509 if (WARN_ON(!base_ipi)) 510 return; 511 512 set_smp_ipi_range(base_ipi, IPI_DOORBELL_END); 513 } 514 515 static int armada_xp_set_affinity(struct irq_data *d, 516 const struct cpumask *mask_val, bool force) 517 { 518 irq_hw_number_t hwirq = irqd_to_hwirq(d); 519 int cpu; 520 521 /* Select a single core from the affinity mask which is online */ 522 cpu = cpumask_any_and(mask_val, cpu_online_mask); 523 524 atomic_io_modify(main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq), 525 ARMADA_370_XP_INT_SOURCE_CPU_MASK, 526 BIT(cpu_logical_map(cpu))); 527 528 irq_data_update_effective_affinity(d, cpumask_of(cpu)); 529 530 return IRQ_SET_MASK_OK; 531 } 532 533 static void armada_xp_mpic_smp_cpu_init(void) 534 { 535 u32 control; 536 int nr_irqs, i; 537 538 control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL); 539 nr_irqs = (control >> 2) & 0x3ff; 540 541 for (i = 0; i < nr_irqs; i++) 542 writel(i, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS); 543 544 if (!is_ipi_available()) 545 return; 546 547 /* Disable all IPIs */ 548 writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS); 549 550 /* Clear pending IPIs */ 551 writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS); 552 553 /* Unmask IPI interrupt */ 554 writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); 555 } 556 557 static void armada_xp_mpic_reenable_percpu(void) 558 { 559 unsigned int irq; 560 561 /* Re-enable per-CPU interrupts that were enabled before suspend */ 562 for (irq = 0; irq < ARMADA_370_XP_MAX_PER_CPU_IRQS; irq++) { 563 struct irq_data *data; 564 int virq; 565 566 virq = irq_linear_revmap(armada_370_xp_mpic_domain, irq); 567 if (virq == 0) 568 continue; 569 570 data = irq_get_irq_data(virq); 571 572 if (!irq_percpu_is_enabled(virq)) 573 continue; 574 575 armada_370_xp_irq_unmask(data); 576 } 577 578 if (is_ipi_available()) 579 ipi_resume(); 580 581 armada_370_xp_msi_reenable_percpu(); 582 } 583 584 static int armada_xp_mpic_starting_cpu(unsigned int cpu) 585 { 586 armada_xp_mpic_perf_init(); 587 armada_xp_mpic_smp_cpu_init(); 588 armada_xp_mpic_reenable_percpu(); 589 return 0; 590 } 591 592 static int mpic_cascaded_starting_cpu(unsigned int cpu) 593 { 594 armada_xp_mpic_perf_init(); 595 armada_xp_mpic_reenable_percpu(); 596 enable_percpu_irq(parent_irq, IRQ_TYPE_NONE); 597 return 0; 598 } 599 #else 600 static void armada_xp_mpic_smp_cpu_init(void) {} 601 static void ipi_resume(void) {} 602 #endif 603 604 static struct irq_chip armada_370_xp_irq_chip = { 605 .name = "MPIC", 606 .irq_mask = armada_370_xp_irq_mask, 607 .irq_mask_ack = armada_370_xp_irq_mask, 608 .irq_unmask = armada_370_xp_irq_unmask, 609 #ifdef CONFIG_SMP 610 .irq_set_affinity = armada_xp_set_affinity, 611 #endif 612 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND, 613 }; 614 615 static int armada_370_xp_mpic_irq_map(struct irq_domain *h, 616 unsigned int virq, irq_hw_number_t hw) 617 { 618 /* IRQs 0 and 1 cannot be mapped, they are handled internally */ 619 if (hw <= 1) 620 return -EINVAL; 621 622 armada_370_xp_irq_mask(irq_get_irq_data(virq)); 623 if (!is_percpu_irq(hw)) 624 writel(hw, per_cpu_int_base + 625 ARMADA_370_XP_INT_CLEAR_MASK_OFFS); 626 else 627 writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS); 628 irq_set_status_flags(virq, IRQ_LEVEL); 629 630 if (is_percpu_irq(hw)) { 631 irq_set_percpu_devid(virq); 632 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip, 633 handle_percpu_devid_irq); 634 } else { 635 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip, 636 handle_level_irq); 637 irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq))); 638 } 639 irq_set_probe(virq); 640 641 return 0; 642 } 643 644 static const struct irq_domain_ops armada_370_xp_mpic_irq_ops = { 645 .map = armada_370_xp_mpic_irq_map, 646 .xlate = irq_domain_xlate_onecell, 647 }; 648 649 #ifdef CONFIG_PCI_MSI 650 static void armada_370_xp_handle_msi_irq(struct pt_regs *regs, bool is_chained) 651 { 652 u32 msimask, msinr; 653 654 msimask = readl_relaxed(per_cpu_int_base + 655 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS); 656 msimask &= msi_doorbell_mask(); 657 658 writel(~msimask, per_cpu_int_base + 659 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS); 660 661 for (msinr = msi_doorbell_start(); 662 msinr < msi_doorbell_end(); msinr++) { 663 unsigned int irq; 664 665 if (!(msimask & BIT(msinr))) 666 continue; 667 668 irq = msinr - msi_doorbell_start(); 669 670 generic_handle_domain_irq(armada_370_xp_msi_inner_domain, irq); 671 } 672 } 673 #else 674 static void armada_370_xp_handle_msi_irq(struct pt_regs *r, bool b) {} 675 #endif 676 677 static void armada_370_xp_mpic_handle_cascade_irq(struct irq_desc *desc) 678 { 679 struct irq_chip *chip = irq_desc_get_chip(desc); 680 unsigned long irqmap, irqn, irqsrc, cpuid; 681 682 chained_irq_enter(chip, desc); 683 684 irqmap = readl_relaxed(per_cpu_int_base + ARMADA_375_PPI_CAUSE); 685 cpuid = cpu_logical_map(smp_processor_id()); 686 687 for_each_set_bit(irqn, &irqmap, BITS_PER_LONG) { 688 irqsrc = readl_relaxed(main_int_base + 689 ARMADA_370_XP_INT_SOURCE_CTL(irqn)); 690 691 /* Check if the interrupt is not masked on current CPU. 692 * Test IRQ (0-1) and FIQ (8-9) mask bits. 693 */ 694 if (!(irqsrc & ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid))) 695 continue; 696 697 if (irqn == 0 || irqn == 1) { 698 armada_370_xp_handle_msi_irq(NULL, true); 699 continue; 700 } 701 702 generic_handle_domain_irq(armada_370_xp_mpic_domain, irqn); 703 } 704 705 chained_irq_exit(chip, desc); 706 } 707 708 static void __exception_irq_entry 709 armada_370_xp_handle_irq(struct pt_regs *regs) 710 { 711 u32 irqstat, irqnr; 712 713 do { 714 irqstat = readl_relaxed(per_cpu_int_base + 715 ARMADA_370_XP_CPU_INTACK_OFFS); 716 irqnr = irqstat & 0x3FF; 717 718 if (irqnr > 1022) 719 break; 720 721 if (irqnr > 1) { 722 generic_handle_domain_irq(armada_370_xp_mpic_domain, 723 irqnr); 724 continue; 725 } 726 727 /* MSI handling */ 728 if (irqnr == 1) 729 armada_370_xp_handle_msi_irq(regs, false); 730 731 #ifdef CONFIG_SMP 732 /* IPI Handling */ 733 if (irqnr == 0) { 734 unsigned long ipimask; 735 int ipi; 736 737 ipimask = readl_relaxed(per_cpu_int_base + 738 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS) 739 & IPI_DOORBELL_MASK; 740 741 for_each_set_bit(ipi, &ipimask, IPI_DOORBELL_END) 742 generic_handle_domain_irq(ipi_domain, ipi); 743 } 744 #endif 745 746 } while (1); 747 } 748 749 static int armada_370_xp_mpic_suspend(void) 750 { 751 doorbell_mask_reg = readl(per_cpu_int_base + 752 ARMADA_370_XP_IN_DRBEL_MSK_OFFS); 753 return 0; 754 } 755 756 static void armada_370_xp_mpic_resume(void) 757 { 758 bool src0, src1; 759 int nirqs; 760 irq_hw_number_t irq; 761 762 /* Re-enable interrupts */ 763 nirqs = (readl(main_int_base + ARMADA_370_XP_INT_CONTROL) >> 2) & 0x3ff; 764 for (irq = 0; irq < nirqs; irq++) { 765 struct irq_data *data; 766 int virq; 767 768 virq = irq_linear_revmap(armada_370_xp_mpic_domain, irq); 769 if (virq == 0) 770 continue; 771 772 data = irq_get_irq_data(virq); 773 774 if (!is_percpu_irq(irq)) { 775 /* Non per-CPU interrupts */ 776 writel(irq, per_cpu_int_base + 777 ARMADA_370_XP_INT_CLEAR_MASK_OFFS); 778 if (!irqd_irq_disabled(data)) 779 armada_370_xp_irq_unmask(data); 780 } else { 781 /* Per-CPU interrupts */ 782 writel(irq, main_int_base + 783 ARMADA_370_XP_INT_SET_ENABLE_OFFS); 784 785 /* 786 * Re-enable on the current CPU, 787 * armada_xp_mpic_reenable_percpu() will take 788 * care of secondary CPUs when they come up. 789 */ 790 if (irq_percpu_is_enabled(virq)) 791 armada_370_xp_irq_unmask(data); 792 } 793 } 794 795 /* Reconfigure doorbells for IPIs and MSIs */ 796 writel(doorbell_mask_reg, 797 per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS); 798 799 if (is_ipi_available()) { 800 src0 = doorbell_mask_reg & IPI_DOORBELL_MASK; 801 src1 = doorbell_mask_reg & PCI_MSI_DOORBELL_MASK; 802 } else { 803 src0 = doorbell_mask_reg & PCI_MSI_FULL_DOORBELL_SRC0_MASK; 804 src1 = doorbell_mask_reg & PCI_MSI_FULL_DOORBELL_SRC1_MASK; 805 } 806 807 if (src0) 808 writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); 809 if (src1) 810 writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); 811 812 if (is_ipi_available()) 813 ipi_resume(); 814 } 815 816 static struct syscore_ops armada_370_xp_mpic_syscore_ops = { 817 .suspend = armada_370_xp_mpic_suspend, 818 .resume = armada_370_xp_mpic_resume, 819 }; 820 821 static int __init armada_370_xp_mpic_of_init(struct device_node *node, 822 struct device_node *parent) 823 { 824 struct resource main_int_res, per_cpu_int_res; 825 int nr_irqs, i; 826 u32 control; 827 828 BUG_ON(of_address_to_resource(node, 0, &main_int_res)); 829 BUG_ON(of_address_to_resource(node, 1, &per_cpu_int_res)); 830 831 BUG_ON(!request_mem_region(main_int_res.start, 832 resource_size(&main_int_res), 833 node->full_name)); 834 BUG_ON(!request_mem_region(per_cpu_int_res.start, 835 resource_size(&per_cpu_int_res), 836 node->full_name)); 837 838 main_int_base = ioremap(main_int_res.start, 839 resource_size(&main_int_res)); 840 BUG_ON(!main_int_base); 841 842 per_cpu_int_base = ioremap(per_cpu_int_res.start, 843 resource_size(&per_cpu_int_res)); 844 BUG_ON(!per_cpu_int_base); 845 846 control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL); 847 nr_irqs = (control >> 2) & 0x3ff; 848 849 for (i = 0; i < nr_irqs; i++) 850 writel(i, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS); 851 852 armada_370_xp_mpic_domain = 853 irq_domain_add_linear(node, nr_irqs, 854 &armada_370_xp_mpic_irq_ops, NULL); 855 BUG_ON(!armada_370_xp_mpic_domain); 856 irq_domain_update_bus_token(armada_370_xp_mpic_domain, DOMAIN_BUS_WIRED); 857 858 /* 859 * Initialize parent_irq before calling any other functions, since it is 860 * used to distinguish between IPI and non-IPI platforms. 861 */ 862 parent_irq = irq_of_parse_and_map(node, 0); 863 864 /* Setup for the boot CPU */ 865 armada_xp_mpic_perf_init(); 866 armada_xp_mpic_smp_cpu_init(); 867 868 armada_370_xp_msi_init(node, main_int_res.start); 869 870 if (parent_irq <= 0) { 871 irq_set_default_host(armada_370_xp_mpic_domain); 872 set_handle_irq(armada_370_xp_handle_irq); 873 #ifdef CONFIG_SMP 874 armada_xp_ipi_init(node); 875 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_ARMADA_XP_STARTING, 876 "irqchip/armada/ipi:starting", 877 armada_xp_mpic_starting_cpu, NULL); 878 #endif 879 } else { 880 #ifdef CONFIG_SMP 881 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_ARMADA_XP_STARTING, 882 "irqchip/armada/cascade:starting", 883 mpic_cascaded_starting_cpu, NULL); 884 #endif 885 irq_set_chained_handler(parent_irq, 886 armada_370_xp_mpic_handle_cascade_irq); 887 } 888 889 register_syscore_ops(&armada_370_xp_mpic_syscore_ops); 890 891 return 0; 892 } 893 894 IRQCHIP_DECLARE(armada_370_xp_mpic, "marvell,mpic", armada_370_xp_mpic_of_init); 895