1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright The Asahi Linux Contributors 4 * 5 * Based on irq-lpc32xx: 6 * Copyright 2015-2016 Vladimir Zapolskiy <vz@mleia.com> 7 * Based on irq-bcm2836: 8 * Copyright 2015 Broadcom 9 */ 10 11 /* 12 * AIC is a fairly simple interrupt controller with the following features: 13 * 14 * - 896 level-triggered hardware IRQs 15 * - Single mask bit per IRQ 16 * - Per-IRQ affinity setting 17 * - Automatic masking on event delivery (auto-ack) 18 * - Software triggering (ORed with hw line) 19 * - 2 per-CPU IPIs (meant as "self" and "other", but they are 20 * interchangeable if not symmetric) 21 * - Automatic prioritization (single event/ack register per CPU, lower IRQs = 22 * higher priority) 23 * - Automatic masking on ack 24 * - Default "this CPU" register view and explicit per-CPU views 25 * 26 * In addition, this driver also handles FIQs, as these are routed to the same 27 * IRQ vector. These are used for Fast IPIs, the ARMv8 timer IRQs, and 28 * performance counters (TODO). 29 * 30 * Implementation notes: 31 * 32 * - This driver creates two IRQ domains, one for HW IRQs and internal FIQs, 33 * and one for IPIs. 34 * - Since Linux needs more than 2 IPIs, we implement a software IRQ controller 35 * and funnel all IPIs into one per-CPU IPI (the second "self" IPI is unused). 36 * - FIQ hwirq numbers are assigned after true hwirqs, and are per-cpu. 37 * - DT bindings use 3-cell form (like GIC): 38 * - <0 nr flags> - hwirq #nr 39 * - <1 nr flags> - FIQ #nr 40 * - nr=0 Physical HV timer 41 * - nr=1 Virtual HV timer 42 * - nr=2 Physical guest timer 43 * - nr=3 Virtual guest timer 44 */ 45 46 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 47 48 #include <linux/bits.h> 49 #include <linux/bitfield.h> 50 #include <linux/cpuhotplug.h> 51 #include <linux/io.h> 52 #include <linux/irqchip.h> 53 #include <linux/irqchip/arm-vgic-info.h> 54 #include <linux/irqdomain.h> 55 #include <linux/jump_label.h> 56 #include <linux/limits.h> 57 #include <linux/of_address.h> 58 #include <linux/slab.h> 59 #include <asm/apple_m1_pmu.h> 60 #include <asm/cputype.h> 61 #include <asm/exception.h> 62 #include <asm/sysreg.h> 63 #include <asm/virt.h> 64 65 #include <dt-bindings/interrupt-controller/apple-aic.h> 66 67 /* 68 * AIC v1 registers (MMIO) 69 */ 70 71 #define AIC_INFO 0x0004 72 #define AIC_INFO_NR_IRQ GENMASK(15, 0) 73 74 #define AIC_CONFIG 0x0010 75 76 #define AIC_WHOAMI 0x2000 77 #define AIC_EVENT 0x2004 78 #define AIC_EVENT_DIE GENMASK(31, 24) 79 #define AIC_EVENT_TYPE GENMASK(23, 16) 80 #define AIC_EVENT_NUM GENMASK(15, 0) 81 82 #define AIC_EVENT_TYPE_FIQ 0 /* Software use */ 83 #define AIC_EVENT_TYPE_IRQ 1 84 #define AIC_EVENT_TYPE_IPI 4 85 #define AIC_EVENT_IPI_OTHER 1 86 #define AIC_EVENT_IPI_SELF 2 87 88 #define AIC_IPI_SEND 0x2008 89 #define AIC_IPI_ACK 0x200c 90 #define AIC_IPI_MASK_SET 0x2024 91 #define AIC_IPI_MASK_CLR 0x2028 92 93 #define AIC_IPI_SEND_CPU(cpu) BIT(cpu) 94 95 #define AIC_IPI_OTHER BIT(0) 96 #define AIC_IPI_SELF BIT(31) 97 98 #define AIC_TARGET_CPU 0x3000 99 100 #define AIC_CPU_IPI_SET(cpu) (0x5008 + ((cpu) << 7)) 101 #define AIC_CPU_IPI_CLR(cpu) (0x500c + ((cpu) << 7)) 102 #define AIC_CPU_IPI_MASK_SET(cpu) (0x5024 + ((cpu) << 7)) 103 #define AIC_CPU_IPI_MASK_CLR(cpu) (0x5028 + ((cpu) << 7)) 104 105 #define AIC_MAX_IRQ 0x400 106 107 /* 108 * AIC v2 registers (MMIO) 109 */ 110 111 #define AIC2_VERSION 0x0000 112 #define AIC2_VERSION_VER GENMASK(7, 0) 113 114 #define AIC2_INFO1 0x0004 115 #define AIC2_INFO1_NR_IRQ GENMASK(15, 0) 116 #define AIC2_INFO1_LAST_DIE GENMASK(27, 24) 117 118 #define AIC2_INFO2 0x0008 119 120 #define AIC2_INFO3 0x000c 121 #define AIC2_INFO3_MAX_IRQ GENMASK(15, 0) 122 #define AIC2_INFO3_MAX_DIE GENMASK(27, 24) 123 124 #define AIC2_RESET 0x0010 125 #define AIC2_RESET_RESET BIT(0) 126 127 #define AIC2_CONFIG 0x0014 128 #define AIC2_CONFIG_ENABLE BIT(0) 129 #define AIC2_CONFIG_PREFER_PCPU BIT(28) 130 131 #define AIC2_TIMEOUT 0x0028 132 #define AIC2_CLUSTER_PRIO 0x0030 133 #define AIC2_DELAY_GROUPS 0x0100 134 135 #define AIC2_IRQ_CFG 0x2000 136 137 /* 138 * AIC2 registers are laid out like this, starting at AIC2_IRQ_CFG: 139 * 140 * Repeat for each die: 141 * IRQ_CFG: u32 * MAX_IRQS 142 * SW_SET: u32 * (MAX_IRQS / 32) 143 * SW_CLR: u32 * (MAX_IRQS / 32) 144 * MASK_SET: u32 * (MAX_IRQS / 32) 145 * MASK_CLR: u32 * (MAX_IRQS / 32) 146 * HW_STATE: u32 * (MAX_IRQS / 32) 147 * 148 * This is followed by a set of event registers, each 16K page aligned. 149 * The first one is the AP event register we will use. Unfortunately, 150 * the actual implemented die count is not specified anywhere in the 151 * capability registers, so we have to explicitly specify the event 152 * register as a second reg entry in the device tree to remain 153 * forward-compatible. 154 */ 155 156 #define AIC2_IRQ_CFG_TARGET GENMASK(3, 0) 157 #define AIC2_IRQ_CFG_DELAY_IDX GENMASK(7, 5) 158 159 #define MASK_REG(x) (4 * ((x) >> 5)) 160 #define MASK_BIT(x) BIT((x) & GENMASK(4, 0)) 161 162 /* 163 * IMP-DEF sysregs that control FIQ sources 164 */ 165 166 /* IPI request registers */ 167 #define SYS_IMP_APL_IPI_RR_LOCAL_EL1 sys_reg(3, 5, 15, 0, 0) 168 #define SYS_IMP_APL_IPI_RR_GLOBAL_EL1 sys_reg(3, 5, 15, 0, 1) 169 #define IPI_RR_CPU GENMASK(7, 0) 170 /* Cluster only used for the GLOBAL register */ 171 #define IPI_RR_CLUSTER GENMASK(23, 16) 172 #define IPI_RR_TYPE GENMASK(29, 28) 173 #define IPI_RR_IMMEDIATE 0 174 #define IPI_RR_RETRACT 1 175 #define IPI_RR_DEFERRED 2 176 #define IPI_RR_NOWAKE 3 177 178 /* IPI status register */ 179 #define SYS_IMP_APL_IPI_SR_EL1 sys_reg(3, 5, 15, 1, 1) 180 #define IPI_SR_PENDING BIT(0) 181 182 /* Guest timer FIQ enable register */ 183 #define SYS_IMP_APL_VM_TMR_FIQ_ENA_EL2 sys_reg(3, 5, 15, 1, 3) 184 #define VM_TMR_FIQ_ENABLE_V BIT(0) 185 #define VM_TMR_FIQ_ENABLE_P BIT(1) 186 187 /* Deferred IPI countdown register */ 188 #define SYS_IMP_APL_IPI_CR_EL1 sys_reg(3, 5, 15, 3, 1) 189 190 /* Uncore PMC control register */ 191 #define SYS_IMP_APL_UPMCR0_EL1 sys_reg(3, 7, 15, 0, 4) 192 #define UPMCR0_IMODE GENMASK(18, 16) 193 #define UPMCR0_IMODE_OFF 0 194 #define UPMCR0_IMODE_AIC 2 195 #define UPMCR0_IMODE_HALT 3 196 #define UPMCR0_IMODE_FIQ 4 197 198 /* Uncore PMC status register */ 199 #define SYS_IMP_APL_UPMSR_EL1 sys_reg(3, 7, 15, 6, 4) 200 #define UPMSR_IACT BIT(0) 201 202 /* MPIDR fields */ 203 #define MPIDR_CPU(x) MPIDR_AFFINITY_LEVEL(x, 0) 204 #define MPIDR_CLUSTER(x) MPIDR_AFFINITY_LEVEL(x, 1) 205 206 #define AIC_IRQ_HWIRQ(die, irq) (FIELD_PREP(AIC_EVENT_DIE, die) | \ 207 FIELD_PREP(AIC_EVENT_TYPE, AIC_EVENT_TYPE_IRQ) | \ 208 FIELD_PREP(AIC_EVENT_NUM, irq)) 209 #define AIC_FIQ_HWIRQ(x) (FIELD_PREP(AIC_EVENT_TYPE, AIC_EVENT_TYPE_FIQ) | \ 210 FIELD_PREP(AIC_EVENT_NUM, x)) 211 #define AIC_HWIRQ_IRQ(x) FIELD_GET(AIC_EVENT_NUM, x) 212 #define AIC_HWIRQ_DIE(x) FIELD_GET(AIC_EVENT_DIE, x) 213 #define AIC_NR_SWIPI 32 214 215 /* 216 * FIQ hwirq index definitions: FIQ sources use the DT binding defines 217 * directly, except that timers are special. At the irqchip level, the 218 * two timer types are represented by their access method: _EL0 registers 219 * or _EL02 registers. In the DT binding, the timers are represented 220 * by their purpose (HV or guest). This mapping is for when the kernel is 221 * running at EL2 (with VHE). When the kernel is running at EL1, the 222 * mapping differs and aic_irq_domain_translate() performs the remapping. 223 */ 224 enum fiq_hwirq { 225 /* Must be ordered as in apple-aic.h */ 226 AIC_TMR_EL0_PHYS = AIC_TMR_HV_PHYS, 227 AIC_TMR_EL0_VIRT = AIC_TMR_HV_VIRT, 228 AIC_TMR_EL02_PHYS = AIC_TMR_GUEST_PHYS, 229 AIC_TMR_EL02_VIRT = AIC_TMR_GUEST_VIRT, 230 AIC_CPU_PMU_Effi = AIC_CPU_PMU_E, 231 AIC_CPU_PMU_Perf = AIC_CPU_PMU_P, 232 /* No need for this to be discovered from DT */ 233 AIC_VGIC_MI, 234 AIC_NR_FIQ 235 }; 236 237 /* True if UNCORE/UNCORE2 and Sn_... IPI registers are present and used (A11+) */ 238 static DEFINE_STATIC_KEY_TRUE(use_fast_ipi); 239 /* True if SYS_IMP_APL_IPI_RR_LOCAL_EL1 exists for local fast IPIs (M1+) */ 240 static DEFINE_STATIC_KEY_TRUE(use_local_fast_ipi); 241 242 struct aic_info { 243 int version; 244 245 /* Register offsets */ 246 u32 event; 247 u32 target_cpu; 248 u32 irq_cfg; 249 u32 sw_set; 250 u32 sw_clr; 251 u32 mask_set; 252 u32 mask_clr; 253 254 u32 die_stride; 255 256 /* Features */ 257 bool fast_ipi; 258 bool local_fast_ipi; 259 }; 260 261 static const struct aic_info aic1_info __initconst = { 262 .version = 1, 263 264 .event = AIC_EVENT, 265 .target_cpu = AIC_TARGET_CPU, 266 }; 267 268 static const struct aic_info aic1_fipi_info __initconst = { 269 .version = 1, 270 271 .event = AIC_EVENT, 272 .target_cpu = AIC_TARGET_CPU, 273 274 .fast_ipi = true, 275 }; 276 277 static const struct aic_info aic1_local_fipi_info __initconst = { 278 .version = 1, 279 280 .event = AIC_EVENT, 281 .target_cpu = AIC_TARGET_CPU, 282 283 .fast_ipi = true, 284 .local_fast_ipi = true, 285 }; 286 287 static const struct aic_info aic2_info __initconst = { 288 .version = 2, 289 290 .irq_cfg = AIC2_IRQ_CFG, 291 292 .fast_ipi = true, 293 .local_fast_ipi = true, 294 }; 295 296 static const struct of_device_id aic_info_match[] = { 297 { 298 .compatible = "apple,t8103-aic", 299 .data = &aic1_local_fipi_info, 300 }, 301 { 302 .compatible = "apple,t8015-aic", 303 .data = &aic1_fipi_info, 304 }, 305 { 306 .compatible = "apple,aic", 307 .data = &aic1_info, 308 }, 309 { 310 .compatible = "apple,aic2", 311 .data = &aic2_info, 312 }, 313 {} 314 }; 315 316 struct aic_irq_chip { 317 void __iomem *base; 318 void __iomem *event; 319 struct irq_domain *hw_domain; 320 struct { 321 cpumask_t aff; 322 } *fiq_aff[AIC_NR_FIQ]; 323 324 int nr_irq; 325 int max_irq; 326 int nr_die; 327 int max_die; 328 329 struct aic_info info; 330 }; 331 332 static DEFINE_PER_CPU(uint32_t, aic_fiq_unmasked); 333 334 static struct aic_irq_chip *aic_irqc; 335 336 static void aic_handle_ipi(struct pt_regs *regs); 337 338 static u32 aic_ic_read(struct aic_irq_chip *ic, u32 reg) 339 { 340 return readl_relaxed(ic->base + reg); 341 } 342 343 static void aic_ic_write(struct aic_irq_chip *ic, u32 reg, u32 val) 344 { 345 writel_relaxed(val, ic->base + reg); 346 } 347 348 /* 349 * IRQ irqchip 350 */ 351 352 static void aic_irq_mask(struct irq_data *d) 353 { 354 irq_hw_number_t hwirq = irqd_to_hwirq(d); 355 struct aic_irq_chip *ic = irq_data_get_irq_chip_data(d); 356 357 u32 off = AIC_HWIRQ_DIE(hwirq) * ic->info.die_stride; 358 u32 irq = AIC_HWIRQ_IRQ(hwirq); 359 360 aic_ic_write(ic, ic->info.mask_set + off + MASK_REG(irq), MASK_BIT(irq)); 361 } 362 363 static void aic_irq_unmask(struct irq_data *d) 364 { 365 irq_hw_number_t hwirq = irqd_to_hwirq(d); 366 struct aic_irq_chip *ic = irq_data_get_irq_chip_data(d); 367 368 u32 off = AIC_HWIRQ_DIE(hwirq) * ic->info.die_stride; 369 u32 irq = AIC_HWIRQ_IRQ(hwirq); 370 371 aic_ic_write(ic, ic->info.mask_clr + off + MASK_REG(irq), MASK_BIT(irq)); 372 } 373 374 static void aic_irq_eoi(struct irq_data *d) 375 { 376 /* 377 * Reading the interrupt reason automatically acknowledges and masks 378 * the IRQ, so we just unmask it here if needed. 379 */ 380 if (!irqd_irq_masked(d)) 381 aic_irq_unmask(d); 382 } 383 384 static void __exception_irq_entry aic_handle_irq(struct pt_regs *regs) 385 { 386 struct aic_irq_chip *ic = aic_irqc; 387 u32 event, type, irq; 388 389 do { 390 /* 391 * We cannot use a relaxed read here, as reads from DMA buffers 392 * need to be ordered after the IRQ fires. 393 */ 394 event = readl(ic->event + ic->info.event); 395 type = FIELD_GET(AIC_EVENT_TYPE, event); 396 irq = FIELD_GET(AIC_EVENT_NUM, event); 397 398 if (type == AIC_EVENT_TYPE_IRQ) 399 generic_handle_domain_irq(aic_irqc->hw_domain, event); 400 else if (type == AIC_EVENT_TYPE_IPI && irq == 1) 401 aic_handle_ipi(regs); 402 else if (event != 0) 403 pr_err_ratelimited("Unknown IRQ event %d, %d\n", type, irq); 404 } while (event); 405 406 /* 407 * vGIC maintenance interrupts end up here too, so we need to check 408 * for them separately. It should however only trigger when NV is 409 * in use, and be cleared when coming back from the handler. 410 */ 411 if (is_kernel_in_hyp_mode() && 412 (read_sysreg_s(SYS_ICH_HCR_EL2) & ICH_HCR_EL2_En) && 413 read_sysreg_s(SYS_ICH_MISR_EL2) != 0) { 414 generic_handle_domain_irq(aic_irqc->hw_domain, 415 AIC_FIQ_HWIRQ(AIC_VGIC_MI)); 416 417 if (unlikely((read_sysreg_s(SYS_ICH_HCR_EL2) & ICH_HCR_EL2_En) && 418 read_sysreg_s(SYS_ICH_MISR_EL2))) { 419 pr_err_ratelimited("vGIC IRQ fired and not handled by KVM, disabling.\n"); 420 sysreg_clear_set_s(SYS_ICH_HCR_EL2, ICH_HCR_EL2_En, 0); 421 } 422 } 423 } 424 425 static int aic_irq_set_affinity(struct irq_data *d, 426 const struct cpumask *mask_val, bool force) 427 { 428 irq_hw_number_t hwirq = irqd_to_hwirq(d); 429 struct aic_irq_chip *ic = irq_data_get_irq_chip_data(d); 430 int cpu; 431 432 BUG_ON(!ic->info.target_cpu); 433 434 if (force) 435 cpu = cpumask_first(mask_val); 436 else 437 cpu = cpumask_any_and(mask_val, cpu_online_mask); 438 439 aic_ic_write(ic, ic->info.target_cpu + AIC_HWIRQ_IRQ(hwirq) * 4, BIT(cpu)); 440 irq_data_update_effective_affinity(d, cpumask_of(cpu)); 441 442 return IRQ_SET_MASK_OK; 443 } 444 445 static int aic_irq_set_type(struct irq_data *d, unsigned int type) 446 { 447 /* 448 * Some IRQs (e.g. MSIs) implicitly have edge semantics, and we don't 449 * have a way to find out the type of any given IRQ, so just allow both. 450 */ 451 return (type == IRQ_TYPE_LEVEL_HIGH || type == IRQ_TYPE_EDGE_RISING) ? 0 : -EINVAL; 452 } 453 454 static struct irq_chip aic_chip = { 455 .name = "AIC", 456 .irq_mask = aic_irq_mask, 457 .irq_unmask = aic_irq_unmask, 458 .irq_eoi = aic_irq_eoi, 459 .irq_set_affinity = aic_irq_set_affinity, 460 .irq_set_type = aic_irq_set_type, 461 }; 462 463 static struct irq_chip aic2_chip = { 464 .name = "AIC2", 465 .irq_mask = aic_irq_mask, 466 .irq_unmask = aic_irq_unmask, 467 .irq_eoi = aic_irq_eoi, 468 .irq_set_type = aic_irq_set_type, 469 }; 470 471 /* 472 * FIQ irqchip 473 */ 474 475 static unsigned long aic_fiq_get_idx(struct irq_data *d) 476 { 477 return AIC_HWIRQ_IRQ(irqd_to_hwirq(d)); 478 } 479 480 static void aic_fiq_set_mask(struct irq_data *d) 481 { 482 /* Only the guest timers have real mask bits, unfortunately. */ 483 switch (aic_fiq_get_idx(d)) { 484 case AIC_TMR_EL02_PHYS: 485 sysreg_clear_set_s(SYS_IMP_APL_VM_TMR_FIQ_ENA_EL2, VM_TMR_FIQ_ENABLE_P, 0); 486 isb(); 487 break; 488 case AIC_TMR_EL02_VIRT: 489 sysreg_clear_set_s(SYS_IMP_APL_VM_TMR_FIQ_ENA_EL2, VM_TMR_FIQ_ENABLE_V, 0); 490 isb(); 491 break; 492 default: 493 break; 494 } 495 } 496 497 static void aic_fiq_clear_mask(struct irq_data *d) 498 { 499 switch (aic_fiq_get_idx(d)) { 500 case AIC_TMR_EL02_PHYS: 501 sysreg_clear_set_s(SYS_IMP_APL_VM_TMR_FIQ_ENA_EL2, 0, VM_TMR_FIQ_ENABLE_P); 502 isb(); 503 break; 504 case AIC_TMR_EL02_VIRT: 505 sysreg_clear_set_s(SYS_IMP_APL_VM_TMR_FIQ_ENA_EL2, 0, VM_TMR_FIQ_ENABLE_V); 506 isb(); 507 break; 508 default: 509 break; 510 } 511 } 512 513 static void aic_fiq_mask(struct irq_data *d) 514 { 515 aic_fiq_set_mask(d); 516 __this_cpu_and(aic_fiq_unmasked, ~BIT(aic_fiq_get_idx(d))); 517 } 518 519 static void aic_fiq_unmask(struct irq_data *d) 520 { 521 aic_fiq_clear_mask(d); 522 __this_cpu_or(aic_fiq_unmasked, BIT(aic_fiq_get_idx(d))); 523 } 524 525 static void aic_fiq_eoi(struct irq_data *d) 526 { 527 /* We mask to ack (where we can), so we need to unmask at EOI. */ 528 if (__this_cpu_read(aic_fiq_unmasked) & BIT(aic_fiq_get_idx(d))) 529 aic_fiq_clear_mask(d); 530 } 531 532 #define TIMER_FIRING(x) \ 533 (((x) & (ARCH_TIMER_CTRL_ENABLE | ARCH_TIMER_CTRL_IT_MASK | \ 534 ARCH_TIMER_CTRL_IT_STAT)) == \ 535 (ARCH_TIMER_CTRL_ENABLE | ARCH_TIMER_CTRL_IT_STAT)) 536 537 static void __exception_irq_entry aic_handle_fiq(struct pt_regs *regs) 538 { 539 /* 540 * It would be really nice if we had a system register that lets us get 541 * the FIQ source state without having to peek down into sources... 542 * but such a register does not seem to exist. 543 * 544 * So, we have these potential sources to test for: 545 * - Fast IPIs (not yet used) 546 * - The 4 timers (CNTP, CNTV for each of HV and guest) 547 * - Per-core PMCs (not yet supported) 548 * - Per-cluster uncore PMCs (not yet supported) 549 * 550 * Since not dealing with any of these results in a FIQ storm, 551 * we check for everything here, even things we don't support yet. 552 */ 553 554 if (static_branch_likely(&use_fast_ipi) && 555 (read_sysreg_s(SYS_IMP_APL_IPI_SR_EL1) & IPI_SR_PENDING)) 556 aic_handle_ipi(regs); 557 558 if (TIMER_FIRING(read_sysreg(cntp_ctl_el0))) 559 generic_handle_domain_irq(aic_irqc->hw_domain, 560 AIC_FIQ_HWIRQ(AIC_TMR_EL0_PHYS)); 561 562 if (TIMER_FIRING(read_sysreg(cntv_ctl_el0))) 563 generic_handle_domain_irq(aic_irqc->hw_domain, 564 AIC_FIQ_HWIRQ(AIC_TMR_EL0_VIRT)); 565 566 if (is_kernel_in_hyp_mode()) { 567 uint64_t enabled = read_sysreg_s(SYS_IMP_APL_VM_TMR_FIQ_ENA_EL2); 568 569 if ((enabled & VM_TMR_FIQ_ENABLE_P) && 570 TIMER_FIRING(read_sysreg_s(SYS_CNTP_CTL_EL02))) 571 generic_handle_domain_irq(aic_irqc->hw_domain, 572 AIC_FIQ_HWIRQ(AIC_TMR_EL02_PHYS)); 573 574 if ((enabled & VM_TMR_FIQ_ENABLE_V) && 575 TIMER_FIRING(read_sysreg_s(SYS_CNTV_CTL_EL02))) 576 generic_handle_domain_irq(aic_irqc->hw_domain, 577 AIC_FIQ_HWIRQ(AIC_TMR_EL02_VIRT)); 578 } 579 580 if ((read_sysreg_s(SYS_IMP_APL_PMCR0_EL1) & (PMCR0_IMODE | PMCR0_IACT)) == 581 (FIELD_PREP(PMCR0_IMODE, PMCR0_IMODE_FIQ) | PMCR0_IACT)) 582 generic_handle_domain_irq(aic_irqc->hw_domain, 583 AIC_FIQ_HWIRQ(AIC_CPU_PMU_P)); 584 585 if (static_branch_likely(&use_fast_ipi) && 586 (FIELD_GET(UPMCR0_IMODE, read_sysreg_s(SYS_IMP_APL_UPMCR0_EL1)) == UPMCR0_IMODE_FIQ) && 587 (read_sysreg_s(SYS_IMP_APL_UPMSR_EL1) & UPMSR_IACT)) { 588 /* Same story with uncore PMCs */ 589 pr_err_ratelimited("Uncore PMC FIQ fired. Masking.\n"); 590 sysreg_clear_set_s(SYS_IMP_APL_UPMCR0_EL1, UPMCR0_IMODE, 591 FIELD_PREP(UPMCR0_IMODE, UPMCR0_IMODE_OFF)); 592 } 593 } 594 595 static int aic_fiq_set_type(struct irq_data *d, unsigned int type) 596 { 597 return (type == IRQ_TYPE_LEVEL_HIGH) ? 0 : -EINVAL; 598 } 599 600 static struct irq_chip fiq_chip = { 601 .name = "AIC-FIQ", 602 .irq_mask = aic_fiq_mask, 603 .irq_unmask = aic_fiq_unmask, 604 .irq_ack = aic_fiq_set_mask, 605 .irq_eoi = aic_fiq_eoi, 606 .irq_set_type = aic_fiq_set_type, 607 }; 608 609 /* 610 * Main IRQ domain 611 */ 612 613 static int aic_irq_domain_map(struct irq_domain *id, unsigned int irq, 614 irq_hw_number_t hw) 615 { 616 struct aic_irq_chip *ic = id->host_data; 617 u32 type = FIELD_GET(AIC_EVENT_TYPE, hw); 618 struct irq_chip *chip = &aic_chip; 619 620 if (ic->info.version == 2) 621 chip = &aic2_chip; 622 623 if (type == AIC_EVENT_TYPE_IRQ) { 624 irq_domain_set_info(id, irq, hw, chip, id->host_data, 625 handle_fasteoi_irq, NULL, NULL); 626 irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(irq))); 627 } else { 628 irq_set_percpu_devid(irq); 629 irq_domain_set_info(id, irq, hw, &fiq_chip, id->host_data, 630 handle_percpu_devid_irq, NULL, NULL); 631 } 632 633 return 0; 634 } 635 636 static int aic_irq_get_fwspec_info(struct irq_fwspec *fwspec, struct irq_fwspec_info *info) 637 { 638 const struct cpumask *mask; 639 u32 intid; 640 641 info->flags = 0; 642 info->affinity = NULL; 643 644 if (fwspec->param[0] != AIC_FIQ) 645 return 0; 646 647 if (fwspec->param_count == 3) 648 intid = fwspec->param[1]; 649 else 650 intid = fwspec->param[2]; 651 652 if (aic_irqc->fiq_aff[intid]) 653 mask = &aic_irqc->fiq_aff[intid]->aff; 654 else 655 mask = cpu_possible_mask; 656 657 info->affinity = mask; 658 info->flags = IRQ_FWSPEC_INFO_AFFINITY_VALID; 659 660 return 0; 661 } 662 663 static int aic_irq_domain_translate(struct irq_domain *id, 664 struct irq_fwspec *fwspec, 665 unsigned long *hwirq, 666 unsigned int *type) 667 { 668 struct aic_irq_chip *ic = id->host_data; 669 u32 *args; 670 u32 die = 0; 671 672 if (fwspec->param_count < 3 || fwspec->param_count > 4 || 673 !is_of_node(fwspec->fwnode)) 674 return -EINVAL; 675 676 args = &fwspec->param[1]; 677 678 if (fwspec->param_count == 4) { 679 die = args[0]; 680 args++; 681 } 682 683 switch (fwspec->param[0]) { 684 case AIC_IRQ: 685 if (die >= ic->nr_die) 686 return -EINVAL; 687 if (args[0] >= ic->nr_irq) 688 return -EINVAL; 689 *hwirq = AIC_IRQ_HWIRQ(die, args[0]); 690 break; 691 case AIC_FIQ: 692 if (die != 0) 693 return -EINVAL; 694 if (args[0] >= AIC_NR_FIQ) 695 return -EINVAL; 696 *hwirq = AIC_FIQ_HWIRQ(args[0]); 697 698 /* 699 * In EL1 the non-redirected registers are the guest's, 700 * not EL2's, so remap the hwirqs to match. 701 */ 702 if (!is_kernel_in_hyp_mode()) { 703 switch (args[0]) { 704 case AIC_TMR_GUEST_PHYS: 705 *hwirq = AIC_FIQ_HWIRQ(AIC_TMR_EL0_PHYS); 706 break; 707 case AIC_TMR_GUEST_VIRT: 708 *hwirq = AIC_FIQ_HWIRQ(AIC_TMR_EL0_VIRT); 709 break; 710 case AIC_TMR_HV_PHYS: 711 case AIC_TMR_HV_VIRT: 712 return -ENOENT; 713 default: 714 break; 715 } 716 } 717 718 /* Merge the two PMUs on a single interrupt */ 719 if (*hwirq == AIC_CPU_PMU_E) 720 *hwirq = AIC_CPU_PMU_P; 721 break; 722 default: 723 return -EINVAL; 724 } 725 726 *type = args[1] & IRQ_TYPE_SENSE_MASK; 727 728 return 0; 729 } 730 731 static int aic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 732 unsigned int nr_irqs, void *arg) 733 { 734 unsigned int type = IRQ_TYPE_NONE; 735 struct irq_fwspec *fwspec = arg; 736 irq_hw_number_t hwirq; 737 int i, ret; 738 739 ret = aic_irq_domain_translate(domain, fwspec, &hwirq, &type); 740 if (ret) 741 return ret; 742 743 for (i = 0; i < nr_irqs; i++) { 744 ret = aic_irq_domain_map(domain, virq + i, hwirq + i); 745 if (ret) 746 return ret; 747 } 748 749 return 0; 750 } 751 752 static void aic_irq_domain_free(struct irq_domain *domain, unsigned int virq, 753 unsigned int nr_irqs) 754 { 755 int i; 756 757 for (i = 0; i < nr_irqs; i++) { 758 struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); 759 760 irq_set_handler(virq + i, NULL); 761 irq_domain_reset_irq_data(d); 762 } 763 } 764 765 static const struct irq_domain_ops aic_irq_domain_ops = { 766 .translate = aic_irq_domain_translate, 767 .alloc = aic_irq_domain_alloc, 768 .free = aic_irq_domain_free, 769 .get_fwspec_info = aic_irq_get_fwspec_info, 770 }; 771 772 /* 773 * IPI irqchip 774 */ 775 776 static void aic_ipi_send_fast(int cpu) 777 { 778 u64 mpidr = cpu_logical_map(cpu); 779 u64 my_mpidr = read_cpuid_mpidr(); 780 u64 cluster = MPIDR_CLUSTER(mpidr); 781 u64 idx = MPIDR_CPU(mpidr); 782 783 if (static_branch_likely(&use_local_fast_ipi) && MPIDR_CLUSTER(my_mpidr) == cluster) { 784 write_sysreg_s(FIELD_PREP(IPI_RR_CPU, idx), SYS_IMP_APL_IPI_RR_LOCAL_EL1); 785 } else { 786 write_sysreg_s(FIELD_PREP(IPI_RR_CPU, idx) | FIELD_PREP(IPI_RR_CLUSTER, cluster), 787 SYS_IMP_APL_IPI_RR_GLOBAL_EL1); 788 } 789 isb(); 790 } 791 792 static void aic_handle_ipi(struct pt_regs *regs) 793 { 794 /* 795 * Ack the IPI. We need to order this after the AIC event read, but 796 * that is enforced by normal MMIO ordering guarantees. 797 * 798 * For the Fast IPI case, this needs to be ordered before the vIPI 799 * handling below, so we need to isb(); 800 */ 801 if (static_branch_likely(&use_fast_ipi)) { 802 write_sysreg_s(IPI_SR_PENDING, SYS_IMP_APL_IPI_SR_EL1); 803 isb(); 804 } else { 805 aic_ic_write(aic_irqc, AIC_IPI_ACK, AIC_IPI_OTHER); 806 } 807 808 ipi_mux_process(); 809 810 /* 811 * No ordering needed here; at worst this just changes the timing of 812 * when the next IPI will be delivered. 813 */ 814 if (!static_branch_likely(&use_fast_ipi)) 815 aic_ic_write(aic_irqc, AIC_IPI_MASK_CLR, AIC_IPI_OTHER); 816 } 817 818 static void aic_ipi_send_single(unsigned int cpu) 819 { 820 if (static_branch_likely(&use_fast_ipi)) 821 aic_ipi_send_fast(cpu); 822 else 823 aic_ic_write(aic_irqc, AIC_IPI_SEND, AIC_IPI_SEND_CPU(cpu)); 824 } 825 826 static int __init aic_init_smp(struct aic_irq_chip *irqc, struct device_node *node) 827 { 828 int base_ipi; 829 830 base_ipi = ipi_mux_create(AIC_NR_SWIPI, aic_ipi_send_single); 831 if (WARN_ON(base_ipi <= 0)) 832 return -ENODEV; 833 834 set_smp_ipi_range(base_ipi, AIC_NR_SWIPI); 835 836 return 0; 837 } 838 839 static int aic_init_cpu(unsigned int cpu) 840 { 841 /* Mask all hard-wired per-CPU IRQ/FIQ sources */ 842 843 /* Pending Fast IPI FIQs */ 844 if (static_branch_likely(&use_fast_ipi)) 845 write_sysreg_s(IPI_SR_PENDING, SYS_IMP_APL_IPI_SR_EL1); 846 847 /* Timer FIQs */ 848 sysreg_clear_set(cntp_ctl_el0, 0, ARCH_TIMER_CTRL_IT_MASK); 849 sysreg_clear_set(cntv_ctl_el0, 0, ARCH_TIMER_CTRL_IT_MASK); 850 851 /* EL2-only (VHE mode) IRQ sources */ 852 if (is_kernel_in_hyp_mode()) { 853 /* Guest timers */ 854 sysreg_clear_set_s(SYS_IMP_APL_VM_TMR_FIQ_ENA_EL2, 855 VM_TMR_FIQ_ENABLE_V | VM_TMR_FIQ_ENABLE_P, 0); 856 857 /* vGIC maintenance IRQ */ 858 sysreg_clear_set_s(SYS_ICH_HCR_EL2, ICH_HCR_EL2_En, 0); 859 } 860 861 /* PMC FIQ */ 862 sysreg_clear_set_s(SYS_IMP_APL_PMCR0_EL1, PMCR0_IMODE | PMCR0_IACT, 863 FIELD_PREP(PMCR0_IMODE, PMCR0_IMODE_OFF)); 864 865 /* Uncore PMC FIQ */ 866 if (static_branch_likely(&use_fast_ipi)) { 867 sysreg_clear_set_s(SYS_IMP_APL_UPMCR0_EL1, UPMCR0_IMODE, 868 FIELD_PREP(UPMCR0_IMODE, UPMCR0_IMODE_OFF)); 869 } 870 871 /* Commit all of the above */ 872 isb(); 873 874 if (aic_irqc->info.version == 1) { 875 /* 876 * Make sure the kernel's idea of logical CPU order is the same as AIC's 877 * If we ever end up with a mismatch here, we will have to introduce 878 * a mapping table similar to what other irqchip drivers do. 879 */ 880 WARN_ON(aic_ic_read(aic_irqc, AIC_WHOAMI) != smp_processor_id()); 881 882 /* 883 * Always keep IPIs unmasked at the hardware level (except auto-masking 884 * by AIC during processing). We manage masks at the vIPI level. 885 * These registers only exist on AICv1, AICv2 always uses fast IPIs. 886 */ 887 aic_ic_write(aic_irqc, AIC_IPI_ACK, AIC_IPI_SELF | AIC_IPI_OTHER); 888 if (static_branch_likely(&use_fast_ipi)) { 889 aic_ic_write(aic_irqc, AIC_IPI_MASK_SET, AIC_IPI_SELF | AIC_IPI_OTHER); 890 } else { 891 aic_ic_write(aic_irqc, AIC_IPI_MASK_SET, AIC_IPI_SELF); 892 aic_ic_write(aic_irqc, AIC_IPI_MASK_CLR, AIC_IPI_OTHER); 893 } 894 } 895 896 /* Initialize the local mask state */ 897 __this_cpu_write(aic_fiq_unmasked, 0); 898 899 return 0; 900 } 901 902 static struct gic_kvm_info vgic_info __initdata = { 903 .type = GIC_V3, 904 .no_maint_irq_mask = true, 905 .no_hw_deactivation = true, 906 }; 907 908 static void build_fiq_affinity(struct aic_irq_chip *ic, struct device_node *aff) 909 { 910 int i, n; 911 u32 fiq; 912 913 if (of_property_read_u32(aff, "apple,fiq-index", &fiq) || 914 WARN_ON(fiq >= AIC_NR_FIQ) || ic->fiq_aff[fiq]) 915 return; 916 917 n = of_property_count_elems_of_size(aff, "cpus", sizeof(u32)); 918 if (WARN_ON(n < 0)) 919 return; 920 921 ic->fiq_aff[fiq] = kzalloc(sizeof(*ic->fiq_aff[fiq]), GFP_KERNEL); 922 if (!ic->fiq_aff[fiq]) 923 return; 924 925 for (i = 0; i < n; i++) { 926 struct device_node *cpu_node; 927 u32 cpu_phandle; 928 int cpu; 929 930 if (of_property_read_u32_index(aff, "cpus", i, &cpu_phandle)) 931 continue; 932 933 cpu_node = of_find_node_by_phandle(cpu_phandle); 934 if (WARN_ON(!cpu_node)) 935 continue; 936 937 cpu = of_cpu_node_to_id(cpu_node); 938 of_node_put(cpu_node); 939 if (WARN_ON(cpu < 0)) 940 continue; 941 942 cpumask_set_cpu(cpu, &ic->fiq_aff[fiq]->aff); 943 } 944 } 945 946 static int __init aic_of_ic_init(struct device_node *node, struct device_node *parent) 947 { 948 int i, die; 949 u32 off, start_off; 950 void __iomem *regs; 951 struct aic_irq_chip *irqc; 952 struct device_node *affs; 953 const struct of_device_id *match; 954 955 regs = of_iomap(node, 0); 956 if (WARN_ON(!regs)) 957 return -EIO; 958 959 irqc = kzalloc(sizeof(*irqc), GFP_KERNEL); 960 if (!irqc) { 961 iounmap(regs); 962 return -ENOMEM; 963 } 964 965 irqc->base = regs; 966 967 match = of_match_node(aic_info_match, node); 968 if (!match) 969 goto err_unmap; 970 971 irqc->info = *(struct aic_info *)match->data; 972 973 aic_irqc = irqc; 974 975 switch (irqc->info.version) { 976 case 1: { 977 u32 info; 978 979 info = aic_ic_read(irqc, AIC_INFO); 980 irqc->nr_irq = FIELD_GET(AIC_INFO_NR_IRQ, info); 981 irqc->max_irq = AIC_MAX_IRQ; 982 irqc->nr_die = irqc->max_die = 1; 983 984 off = start_off = irqc->info.target_cpu; 985 off += sizeof(u32) * irqc->max_irq; /* TARGET_CPU */ 986 987 irqc->event = irqc->base; 988 989 break; 990 } 991 case 2: { 992 u32 info1, info3; 993 994 info1 = aic_ic_read(irqc, AIC2_INFO1); 995 info3 = aic_ic_read(irqc, AIC2_INFO3); 996 997 irqc->nr_irq = FIELD_GET(AIC2_INFO1_NR_IRQ, info1); 998 irqc->max_irq = FIELD_GET(AIC2_INFO3_MAX_IRQ, info3); 999 irqc->nr_die = FIELD_GET(AIC2_INFO1_LAST_DIE, info1) + 1; 1000 irqc->max_die = FIELD_GET(AIC2_INFO3_MAX_DIE, info3); 1001 1002 off = start_off = irqc->info.irq_cfg; 1003 off += sizeof(u32) * irqc->max_irq; /* IRQ_CFG */ 1004 1005 irqc->event = of_iomap(node, 1); 1006 if (WARN_ON(!irqc->event)) 1007 goto err_unmap; 1008 1009 break; 1010 } 1011 } 1012 1013 irqc->info.sw_set = off; 1014 off += sizeof(u32) * (irqc->max_irq >> 5); /* SW_SET */ 1015 irqc->info.sw_clr = off; 1016 off += sizeof(u32) * (irqc->max_irq >> 5); /* SW_CLR */ 1017 irqc->info.mask_set = off; 1018 off += sizeof(u32) * (irqc->max_irq >> 5); /* MASK_SET */ 1019 irqc->info.mask_clr = off; 1020 off += sizeof(u32) * (irqc->max_irq >> 5); /* MASK_CLR */ 1021 off += sizeof(u32) * (irqc->max_irq >> 5); /* HW_STATE */ 1022 1023 if (!irqc->info.fast_ipi) 1024 static_branch_disable(&use_fast_ipi); 1025 1026 if (!irqc->info.local_fast_ipi) 1027 static_branch_disable(&use_local_fast_ipi); 1028 1029 irqc->info.die_stride = off - start_off; 1030 1031 irqc->hw_domain = irq_domain_create_tree(of_fwnode_handle(node), 1032 &aic_irq_domain_ops, irqc); 1033 if (WARN_ON(!irqc->hw_domain)) 1034 goto err_unmap; 1035 1036 irq_domain_update_bus_token(irqc->hw_domain, DOMAIN_BUS_WIRED); 1037 1038 if (aic_init_smp(irqc, node)) 1039 goto err_remove_domain; 1040 1041 affs = of_get_child_by_name(node, "affinities"); 1042 if (affs) { 1043 struct device_node *chld; 1044 1045 for_each_child_of_node(affs, chld) 1046 build_fiq_affinity(irqc, chld); 1047 } 1048 of_node_put(affs); 1049 1050 set_handle_irq(aic_handle_irq); 1051 set_handle_fiq(aic_handle_fiq); 1052 1053 off = 0; 1054 for (die = 0; die < irqc->nr_die; die++) { 1055 for (i = 0; i < BITS_TO_U32(irqc->nr_irq); i++) 1056 aic_ic_write(irqc, irqc->info.mask_set + off + i * 4, U32_MAX); 1057 for (i = 0; i < BITS_TO_U32(irqc->nr_irq); i++) 1058 aic_ic_write(irqc, irqc->info.sw_clr + off + i * 4, U32_MAX); 1059 if (irqc->info.target_cpu) 1060 for (i = 0; i < irqc->nr_irq; i++) 1061 aic_ic_write(irqc, irqc->info.target_cpu + off + i * 4, 1); 1062 off += irqc->info.die_stride; 1063 } 1064 1065 if (irqc->info.version == 2) { 1066 u32 config = aic_ic_read(irqc, AIC2_CONFIG); 1067 1068 config |= AIC2_CONFIG_ENABLE; 1069 aic_ic_write(irqc, AIC2_CONFIG, config); 1070 } 1071 1072 if (!is_kernel_in_hyp_mode()) 1073 pr_info("Kernel running in EL1, mapping interrupts"); 1074 1075 if (static_branch_likely(&use_fast_ipi)) 1076 pr_info("Using Fast IPIs"); 1077 1078 cpuhp_setup_state(CPUHP_AP_IRQ_APPLE_AIC_STARTING, 1079 "irqchip/apple-aic/ipi:starting", 1080 aic_init_cpu, NULL); 1081 1082 if (is_kernel_in_hyp_mode()) { 1083 struct irq_fwspec mi = { 1084 .fwnode = of_fwnode_handle(node), 1085 .param_count = 3, 1086 .param = { 1087 [0] = AIC_FIQ, /* This is a lie */ 1088 [1] = AIC_VGIC_MI, 1089 [2] = IRQ_TYPE_LEVEL_HIGH, 1090 }, 1091 }; 1092 1093 vgic_info.maint_irq = irq_create_fwspec_mapping(&mi); 1094 WARN_ON(!vgic_info.maint_irq); 1095 } 1096 1097 vgic_set_kvm_info(&vgic_info); 1098 1099 pr_info("Initialized with %d/%d IRQs * %d/%d die(s), %d FIQs, %d vIPIs", 1100 irqc->nr_irq, irqc->max_irq, irqc->nr_die, irqc->max_die, AIC_NR_FIQ, AIC_NR_SWIPI); 1101 1102 return 0; 1103 1104 err_remove_domain: 1105 irq_domain_remove(irqc->hw_domain); 1106 err_unmap: 1107 if (irqc->event && irqc->event != irqc->base) 1108 iounmap(irqc->event); 1109 iounmap(irqc->base); 1110 kfree(irqc); 1111 return -ENODEV; 1112 } 1113 1114 IRQCHIP_DECLARE(apple_aic, "apple,aic", aic_of_ic_init); 1115 IRQCHIP_DECLARE(apple_aic2, "apple,aic2", aic_of_ic_init); 1116