xref: /linux/drivers/iommu/sprd-iommu.c (revision d30c1683aaecb93d2ab95685dc4300a33d3cea7a) 
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Unisoc IOMMU driver
4  *
5  * Copyright (C) 2020 Unisoc, Inc.
6  * Author: Chunyan Zhang <chunyan.zhang@unisoc.com>
7  */
8 
9 #include <linux/clk.h>
10 #include <linux/device.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/errno.h>
13 #include <linux/iommu.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/module.h>
16 #include <linux/of_platform.h>
17 #include <linux/platform_device.h>
18 #include <linux/regmap.h>
19 #include <linux/slab.h>
20 
21 #define SPRD_IOMMU_PAGE_SHIFT	12
22 #define SPRD_IOMMU_PAGE_SIZE	SZ_4K
23 
24 #define SPRD_EX_CFG		0x0
25 #define SPRD_IOMMU_VAOR_BYPASS	BIT(4)
26 #define SPRD_IOMMU_GATE_EN	BIT(1)
27 #define SPRD_IOMMU_EN		BIT(0)
28 #define SPRD_EX_UPDATE		0x4
29 #define SPRD_EX_FIRST_VPN	0x8
30 #define SPRD_EX_VPN_RANGE	0xc
31 #define SPRD_EX_FIRST_PPN	0x10
32 #define SPRD_EX_DEFAULT_PPN	0x14
33 
34 #define SPRD_IOMMU_VERSION	0x0
35 #define SPRD_VERSION_MASK	GENMASK(15, 8)
36 #define SPRD_VERSION_SHIFT	0x8
37 #define SPRD_VAU_CFG		0x4
38 #define SPRD_VAU_UPDATE		0x8
39 #define SPRD_VAU_AUTH_CFG	0xc
40 #define SPRD_VAU_FIRST_PPN	0x10
41 #define SPRD_VAU_DEFAULT_PPN_RD	0x14
42 #define SPRD_VAU_DEFAULT_PPN_WR	0x18
43 #define SPRD_VAU_FIRST_VPN	0x1c
44 #define SPRD_VAU_VPN_RANGE	0x20
45 
46 enum sprd_iommu_version {
47 	SPRD_IOMMU_EX,
48 	SPRD_IOMMU_VAU,
49 };
50 
51 /*
52  * struct sprd_iommu_device - high-level sprd IOMMU device representation,
53  * including hardware information and configuration, also driver data, etc
54  *
55  * @ver: sprd IOMMU IP version
56  * @prot_page_va: protect page base virtual address
57  * @prot_page_pa: protect page base physical address, data would be
58  *		  written to here while translation fault
59  * @base: mapped base address for accessing registers
60  * @dev: pointer to basic device structure
61  * @iommu: IOMMU core representation
62  * @group: IOMMU group
63  * @eb: gate clock which controls IOMMU access
64  */
65 struct sprd_iommu_device {
66 	struct sprd_iommu_domain	*dom;
67 	enum sprd_iommu_version	ver;
68 	u32			*prot_page_va;
69 	dma_addr_t		prot_page_pa;
70 	void __iomem		*base;
71 	struct device		*dev;
72 	struct iommu_device	iommu;
73 	struct clk		*eb;
74 };
75 
76 struct sprd_iommu_domain {
77 	spinlock_t		pgtlock; /* lock for page table */
78 	struct iommu_domain	domain;
79 	u32			*pgt_va; /* page table virtual address base */
80 	dma_addr_t		pgt_pa; /* page table physical address base */
81 	struct sprd_iommu_device	*sdev;
82 };
83 
84 static const struct iommu_ops sprd_iommu_ops;
85 
86 static struct sprd_iommu_domain *to_sprd_domain(struct iommu_domain *dom)
87 {
88 	return container_of(dom, struct sprd_iommu_domain, domain);
89 }
90 
91 static inline void
92 sprd_iommu_write(struct sprd_iommu_device *sdev, unsigned int reg, u32 val)
93 {
94 	writel_relaxed(val, sdev->base + reg);
95 }
96 
97 static inline u32
98 sprd_iommu_read(struct sprd_iommu_device *sdev, unsigned int reg)
99 {
100 	return readl_relaxed(sdev->base + reg);
101 }
102 
103 static inline void
104 sprd_iommu_update_bits(struct sprd_iommu_device *sdev, unsigned int reg,
105 		  u32 mask, u32 shift, u32 val)
106 {
107 	u32 t = sprd_iommu_read(sdev, reg);
108 
109 	t = (t & (~(mask << shift))) | ((val & mask) << shift);
110 	sprd_iommu_write(sdev, reg, t);
111 }
112 
113 static inline int
114 sprd_iommu_get_version(struct sprd_iommu_device *sdev)
115 {
116 	int ver = (sprd_iommu_read(sdev, SPRD_IOMMU_VERSION) &
117 		   SPRD_VERSION_MASK) >> SPRD_VERSION_SHIFT;
118 
119 	switch (ver) {
120 	case SPRD_IOMMU_EX:
121 	case SPRD_IOMMU_VAU:
122 		return ver;
123 	default:
124 		return -EINVAL;
125 	}
126 }
127 
128 static size_t
129 sprd_iommu_pgt_size(struct iommu_domain *domain)
130 {
131 	return ((domain->geometry.aperture_end -
132 		 domain->geometry.aperture_start + 1) >>
133 		SPRD_IOMMU_PAGE_SHIFT) * sizeof(u32);
134 }
135 
136 static struct iommu_domain *sprd_iommu_domain_alloc_paging(struct device *dev)
137 {
138 	struct sprd_iommu_domain *dom;
139 
140 	dom = kzalloc(sizeof(*dom), GFP_KERNEL);
141 	if (!dom)
142 		return NULL;
143 
144 	spin_lock_init(&dom->pgtlock);
145 
146 	dom->domain.pgsize_bitmap = SPRD_IOMMU_PAGE_SIZE;
147 
148 	dom->domain.geometry.aperture_start = 0;
149 	dom->domain.geometry.aperture_end = SZ_256M - 1;
150 	dom->domain.geometry.force_aperture = true;
151 
152 	return &dom->domain;
153 }
154 
155 static void sprd_iommu_first_vpn(struct sprd_iommu_domain *dom)
156 {
157 	struct sprd_iommu_device *sdev = dom->sdev;
158 	u32 val;
159 	unsigned int reg;
160 
161 	if (sdev->ver == SPRD_IOMMU_EX)
162 		reg = SPRD_EX_FIRST_VPN;
163 	else
164 		reg = SPRD_VAU_FIRST_VPN;
165 
166 	val = dom->domain.geometry.aperture_start >> SPRD_IOMMU_PAGE_SHIFT;
167 	sprd_iommu_write(sdev, reg, val);
168 }
169 
170 static void sprd_iommu_vpn_range(struct sprd_iommu_domain *dom)
171 {
172 	struct sprd_iommu_device *sdev = dom->sdev;
173 	u32 val;
174 	unsigned int reg;
175 
176 	if (sdev->ver == SPRD_IOMMU_EX)
177 		reg = SPRD_EX_VPN_RANGE;
178 	else
179 		reg = SPRD_VAU_VPN_RANGE;
180 
181 	val = (dom->domain.geometry.aperture_end -
182 	       dom->domain.geometry.aperture_start) >> SPRD_IOMMU_PAGE_SHIFT;
183 	sprd_iommu_write(sdev, reg, val);
184 }
185 
186 static void sprd_iommu_first_ppn(struct sprd_iommu_domain *dom)
187 {
188 	u32 val = dom->pgt_pa >> SPRD_IOMMU_PAGE_SHIFT;
189 	struct sprd_iommu_device *sdev = dom->sdev;
190 	unsigned int reg;
191 
192 	if (sdev->ver == SPRD_IOMMU_EX)
193 		reg = SPRD_EX_FIRST_PPN;
194 	else
195 		reg = SPRD_VAU_FIRST_PPN;
196 
197 	sprd_iommu_write(sdev, reg, val);
198 }
199 
200 static void sprd_iommu_default_ppn(struct sprd_iommu_device *sdev)
201 {
202 	u32 val = sdev->prot_page_pa >> SPRD_IOMMU_PAGE_SHIFT;
203 
204 	if (sdev->ver == SPRD_IOMMU_EX) {
205 		sprd_iommu_write(sdev, SPRD_EX_DEFAULT_PPN, val);
206 	} else if (sdev->ver == SPRD_IOMMU_VAU) {
207 		sprd_iommu_write(sdev, SPRD_VAU_DEFAULT_PPN_RD, val);
208 		sprd_iommu_write(sdev, SPRD_VAU_DEFAULT_PPN_WR, val);
209 	}
210 }
211 
212 static void sprd_iommu_hw_en(struct sprd_iommu_device *sdev, bool en)
213 {
214 	unsigned int reg_cfg;
215 	u32 mask, val;
216 
217 	if (sdev->ver == SPRD_IOMMU_EX)
218 		reg_cfg = SPRD_EX_CFG;
219 	else
220 		reg_cfg = SPRD_VAU_CFG;
221 
222 	mask = SPRD_IOMMU_EN | SPRD_IOMMU_GATE_EN;
223 	val = en ? mask : 0;
224 	sprd_iommu_update_bits(sdev, reg_cfg, mask, 0, val);
225 }
226 
227 static void sprd_iommu_cleanup(struct sprd_iommu_domain *dom)
228 {
229 	size_t pgt_size;
230 
231 	/* Nothing need to do if the domain hasn't been attached */
232 	if (!dom->sdev)
233 		return;
234 
235 	pgt_size = sprd_iommu_pgt_size(&dom->domain);
236 	dma_free_coherent(dom->sdev->dev, pgt_size, dom->pgt_va, dom->pgt_pa);
237 	sprd_iommu_hw_en(dom->sdev, false);
238 	dom->sdev = NULL;
239 }
240 
241 static void sprd_iommu_domain_free(struct iommu_domain *domain)
242 {
243 	struct sprd_iommu_domain *dom = to_sprd_domain(domain);
244 
245 	sprd_iommu_cleanup(dom);
246 	kfree(dom);
247 }
248 
249 static int sprd_iommu_attach_device(struct iommu_domain *domain,
250 				    struct device *dev,
251 				    struct iommu_domain *old)
252 {
253 	struct sprd_iommu_device *sdev = dev_iommu_priv_get(dev);
254 	struct sprd_iommu_domain *dom = to_sprd_domain(domain);
255 	size_t pgt_size = sprd_iommu_pgt_size(domain);
256 
257 	/* The device is attached to this domain */
258 	if (sdev->dom == dom)
259 		return 0;
260 
261 	/* The first time that domain is attaching to a device */
262 	if (!dom->pgt_va) {
263 		dom->pgt_va = dma_alloc_coherent(sdev->dev, pgt_size, &dom->pgt_pa, GFP_KERNEL);
264 		if (!dom->pgt_va)
265 			return -ENOMEM;
266 
267 		dom->sdev = sdev;
268 	}
269 
270 	sdev->dom = dom;
271 
272 	/*
273 	 * One sprd IOMMU serves one client device only, disabled it before
274 	 * configure mapping table to avoid access conflict in case other
275 	 * mapping table is stored in.
276 	 */
277 	sprd_iommu_hw_en(sdev, false);
278 	sprd_iommu_first_ppn(dom);
279 	sprd_iommu_first_vpn(dom);
280 	sprd_iommu_vpn_range(dom);
281 	sprd_iommu_default_ppn(sdev);
282 	sprd_iommu_hw_en(sdev, true);
283 
284 	return 0;
285 }
286 
287 static int sprd_iommu_map(struct iommu_domain *domain, unsigned long iova,
288 			  phys_addr_t paddr, size_t pgsize, size_t pgcount,
289 			  int prot, gfp_t gfp, size_t *mapped)
290 {
291 	struct sprd_iommu_domain *dom = to_sprd_domain(domain);
292 	size_t size = pgcount * SPRD_IOMMU_PAGE_SIZE;
293 	unsigned long flags;
294 	unsigned int i;
295 	u32 *pgt_base_iova;
296 	u32 pabase = (u32)paddr;
297 	unsigned long start = domain->geometry.aperture_start;
298 	unsigned long end = domain->geometry.aperture_end;
299 
300 	if (!dom->sdev) {
301 		pr_err("No sprd_iommu_device attached to the domain\n");
302 		return -EINVAL;
303 	}
304 
305 	if (iova < start || (iova + size) > (end + 1)) {
306 		dev_err(dom->sdev->dev, "(iova(0x%lx) + size(%zx)) are not in the range!\n",
307 			iova, size);
308 		return -EINVAL;
309 	}
310 
311 	pgt_base_iova = dom->pgt_va + ((iova - start) >> SPRD_IOMMU_PAGE_SHIFT);
312 
313 	spin_lock_irqsave(&dom->pgtlock, flags);
314 	for (i = 0; i < pgcount; i++) {
315 		pgt_base_iova[i] = pabase >> SPRD_IOMMU_PAGE_SHIFT;
316 		pabase += SPRD_IOMMU_PAGE_SIZE;
317 	}
318 	spin_unlock_irqrestore(&dom->pgtlock, flags);
319 
320 	*mapped = size;
321 	return 0;
322 }
323 
324 static size_t sprd_iommu_unmap(struct iommu_domain *domain, unsigned long iova,
325 			       size_t pgsize, size_t pgcount,
326 			       struct iommu_iotlb_gather *iotlb_gather)
327 {
328 	struct sprd_iommu_domain *dom = to_sprd_domain(domain);
329 	unsigned long flags;
330 	u32 *pgt_base_iova;
331 	size_t size = pgcount * SPRD_IOMMU_PAGE_SIZE;
332 	unsigned long start = domain->geometry.aperture_start;
333 	unsigned long end = domain->geometry.aperture_end;
334 
335 	if (iova < start || (iova + size) > (end + 1))
336 		return 0;
337 
338 	pgt_base_iova = dom->pgt_va + ((iova - start) >> SPRD_IOMMU_PAGE_SHIFT);
339 
340 	spin_lock_irqsave(&dom->pgtlock, flags);
341 	memset(pgt_base_iova, 0, pgcount * sizeof(u32));
342 	spin_unlock_irqrestore(&dom->pgtlock, flags);
343 
344 	return size;
345 }
346 
347 static int sprd_iommu_sync_map(struct iommu_domain *domain,
348 			       unsigned long iova, size_t size)
349 {
350 	struct sprd_iommu_domain *dom = to_sprd_domain(domain);
351 	unsigned int reg;
352 
353 	if (dom->sdev->ver == SPRD_IOMMU_EX)
354 		reg = SPRD_EX_UPDATE;
355 	else
356 		reg = SPRD_VAU_UPDATE;
357 
358 	/* clear IOMMU TLB buffer after page table updated */
359 	sprd_iommu_write(dom->sdev, reg, 0xffffffff);
360 	return 0;
361 }
362 
363 static void sprd_iommu_sync(struct iommu_domain *domain,
364 			    struct iommu_iotlb_gather *iotlb_gather)
365 {
366 	sprd_iommu_sync_map(domain, 0, 0);
367 }
368 
369 static phys_addr_t sprd_iommu_iova_to_phys(struct iommu_domain *domain,
370 					   dma_addr_t iova)
371 {
372 	struct sprd_iommu_domain *dom = to_sprd_domain(domain);
373 	unsigned long flags;
374 	phys_addr_t pa;
375 	unsigned long start = domain->geometry.aperture_start;
376 	unsigned long end = domain->geometry.aperture_end;
377 
378 	if (WARN_ON(iova < start || iova > end))
379 		return 0;
380 
381 	spin_lock_irqsave(&dom->pgtlock, flags);
382 	pa = *(dom->pgt_va + ((iova - start) >> SPRD_IOMMU_PAGE_SHIFT));
383 	pa = (pa << SPRD_IOMMU_PAGE_SHIFT) + ((iova - start) & (SPRD_IOMMU_PAGE_SIZE - 1));
384 	spin_unlock_irqrestore(&dom->pgtlock, flags);
385 
386 	return pa;
387 }
388 
389 static struct iommu_device *sprd_iommu_probe_device(struct device *dev)
390 {
391 	struct sprd_iommu_device *sdev = dev_iommu_priv_get(dev);
392 
393 	return &sdev->iommu;
394 }
395 
396 static int sprd_iommu_of_xlate(struct device *dev,
397 			       const struct of_phandle_args *args)
398 {
399 	struct platform_device *pdev;
400 
401 	if (!dev_iommu_priv_get(dev)) {
402 		pdev = of_find_device_by_node(args->np);
403 		dev_iommu_priv_set(dev, platform_get_drvdata(pdev));
404 		platform_device_put(pdev);
405 	}
406 
407 	return 0;
408 }
409 
410 
411 static const struct iommu_ops sprd_iommu_ops = {
412 	.domain_alloc_paging = sprd_iommu_domain_alloc_paging,
413 	.probe_device	= sprd_iommu_probe_device,
414 	.device_group	= generic_single_device_group,
415 	.of_xlate	= sprd_iommu_of_xlate,
416 	.owner		= THIS_MODULE,
417 	.default_domain_ops = &(const struct iommu_domain_ops) {
418 		.attach_dev	= sprd_iommu_attach_device,
419 		.map_pages	= sprd_iommu_map,
420 		.unmap_pages	= sprd_iommu_unmap,
421 		.iotlb_sync_map	= sprd_iommu_sync_map,
422 		.iotlb_sync	= sprd_iommu_sync,
423 		.iova_to_phys	= sprd_iommu_iova_to_phys,
424 		.free		= sprd_iommu_domain_free,
425 	}
426 };
427 
428 static const struct of_device_id sprd_iommu_of_match[] = {
429 	{ .compatible = "sprd,iommu-v1" },
430 	{ },
431 };
432 MODULE_DEVICE_TABLE(of, sprd_iommu_of_match);
433 
434 /*
435  * Clock is not required, access to some of IOMMUs is controlled by gate
436  * clk, enabled clocks for that kind of IOMMUs before accessing.
437  * Return 0 for success or no clocks found.
438  */
439 static int sprd_iommu_clk_enable(struct sprd_iommu_device *sdev)
440 {
441 	struct clk *eb;
442 
443 	eb = devm_clk_get_optional(sdev->dev, NULL);
444 	if (!eb)
445 		return 0;
446 
447 	if (IS_ERR(eb))
448 		return PTR_ERR(eb);
449 
450 	sdev->eb = eb;
451 	return clk_prepare_enable(eb);
452 }
453 
454 static void sprd_iommu_clk_disable(struct sprd_iommu_device *sdev)
455 {
456 	if (sdev->eb)
457 		clk_disable_unprepare(sdev->eb);
458 }
459 
460 static int sprd_iommu_probe(struct platform_device *pdev)
461 {
462 	struct sprd_iommu_device *sdev;
463 	struct device *dev = &pdev->dev;
464 	void __iomem *base;
465 	int ret;
466 
467 	sdev = devm_kzalloc(dev, sizeof(*sdev), GFP_KERNEL);
468 	if (!sdev)
469 		return -ENOMEM;
470 
471 	base = devm_platform_ioremap_resource(pdev, 0);
472 	if (IS_ERR(base)) {
473 		dev_err(dev, "Failed to get ioremap resource.\n");
474 		return PTR_ERR(base);
475 	}
476 	sdev->base = base;
477 
478 	sdev->prot_page_va = dma_alloc_coherent(dev, SPRD_IOMMU_PAGE_SIZE,
479 						&sdev->prot_page_pa, GFP_KERNEL);
480 	if (!sdev->prot_page_va)
481 		return -ENOMEM;
482 
483 	platform_set_drvdata(pdev, sdev);
484 	sdev->dev = dev;
485 
486 	ret = iommu_device_sysfs_add(&sdev->iommu, dev, NULL, dev_name(dev));
487 	if (ret)
488 		goto free_page;
489 
490 	ret = iommu_device_register(&sdev->iommu, &sprd_iommu_ops, dev);
491 	if (ret)
492 		goto remove_sysfs;
493 
494 	ret = sprd_iommu_clk_enable(sdev);
495 	if (ret)
496 		goto unregister_iommu;
497 
498 	ret = sprd_iommu_get_version(sdev);
499 	if (ret < 0) {
500 		dev_err(dev, "IOMMU version(%d) is invalid.\n", ret);
501 		goto disable_clk;
502 	}
503 	sdev->ver = ret;
504 
505 	return 0;
506 
507 disable_clk:
508 	sprd_iommu_clk_disable(sdev);
509 unregister_iommu:
510 	iommu_device_unregister(&sdev->iommu);
511 remove_sysfs:
512 	iommu_device_sysfs_remove(&sdev->iommu);
513 free_page:
514 	dma_free_coherent(sdev->dev, SPRD_IOMMU_PAGE_SIZE, sdev->prot_page_va, sdev->prot_page_pa);
515 	return ret;
516 }
517 
518 static void sprd_iommu_remove(struct platform_device *pdev)
519 {
520 	struct sprd_iommu_device *sdev = platform_get_drvdata(pdev);
521 
522 	dma_free_coherent(sdev->dev, SPRD_IOMMU_PAGE_SIZE, sdev->prot_page_va, sdev->prot_page_pa);
523 
524 	platform_set_drvdata(pdev, NULL);
525 	iommu_device_sysfs_remove(&sdev->iommu);
526 	iommu_device_unregister(&sdev->iommu);
527 }
528 
529 static struct platform_driver sprd_iommu_driver = {
530 	.driver	= {
531 		.name		= "sprd-iommu",
532 		.of_match_table	= sprd_iommu_of_match,
533 		.suppress_bind_attrs = true,
534 	},
535 	.probe	= sprd_iommu_probe,
536 	.remove = sprd_iommu_remove,
537 };
538 module_platform_driver(sprd_iommu_driver);
539 
540 MODULE_DESCRIPTION("IOMMU driver for Unisoc SoCs");
541 MODULE_ALIAS("platform:sprd-iommu");
542 MODULE_LICENSE("GPL");
543