1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * IOMMU API for Rockchip 4 * 5 * Module Authors: Simon Xue <xxm@rock-chips.com> 6 * Daniel Kurtz <djkurtz@chromium.org> 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/compiler.h> 11 #include <linux/delay.h> 12 #include <linux/device.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/errno.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/iommu.h> 18 #include <linux/iopoll.h> 19 #include <linux/list.h> 20 #include <linux/mm.h> 21 #include <linux/init.h> 22 #include <linux/of.h> 23 #include <linux/of_platform.h> 24 #include <linux/platform_device.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/slab.h> 27 #include <linux/spinlock.h> 28 29 /** MMU register offsets */ 30 #define RK_MMU_DTE_ADDR 0x00 /* Directory table address */ 31 #define RK_MMU_STATUS 0x04 32 #define RK_MMU_COMMAND 0x08 33 #define RK_MMU_PAGE_FAULT_ADDR 0x0C /* IOVA of last page fault */ 34 #define RK_MMU_ZAP_ONE_LINE 0x10 /* Shootdown one IOTLB entry */ 35 #define RK_MMU_INT_RAWSTAT 0x14 /* IRQ status ignoring mask */ 36 #define RK_MMU_INT_CLEAR 0x18 /* Acknowledge and re-arm irq */ 37 #define RK_MMU_INT_MASK 0x1C /* IRQ enable */ 38 #define RK_MMU_INT_STATUS 0x20 /* IRQ status after masking */ 39 #define RK_MMU_AUTO_GATING 0x24 40 41 #define DTE_ADDR_DUMMY 0xCAFEBABE 42 43 #define RK_MMU_POLL_PERIOD_US 100 44 #define RK_MMU_FORCE_RESET_TIMEOUT_US 100000 45 #define RK_MMU_POLL_TIMEOUT_US 1000 46 47 /* RK_MMU_STATUS fields */ 48 #define RK_MMU_STATUS_PAGING_ENABLED BIT(0) 49 #define RK_MMU_STATUS_PAGE_FAULT_ACTIVE BIT(1) 50 #define RK_MMU_STATUS_STALL_ACTIVE BIT(2) 51 #define RK_MMU_STATUS_IDLE BIT(3) 52 #define RK_MMU_STATUS_REPLAY_BUFFER_EMPTY BIT(4) 53 #define RK_MMU_STATUS_PAGE_FAULT_IS_WRITE BIT(5) 54 #define RK_MMU_STATUS_STALL_NOT_ACTIVE BIT(31) 55 56 /* RK_MMU_COMMAND command values */ 57 #define RK_MMU_CMD_ENABLE_PAGING 0 /* Enable memory translation */ 58 #define RK_MMU_CMD_DISABLE_PAGING 1 /* Disable memory translation */ 59 #define RK_MMU_CMD_ENABLE_STALL 2 /* Stall paging to allow other cmds */ 60 #define RK_MMU_CMD_DISABLE_STALL 3 /* Stop stall re-enables paging */ 61 #define RK_MMU_CMD_ZAP_CACHE 4 /* Shoot down entire IOTLB */ 62 #define RK_MMU_CMD_PAGE_FAULT_DONE 5 /* Clear page fault */ 63 #define RK_MMU_CMD_FORCE_RESET 6 /* Reset all registers */ 64 65 /* RK_MMU_INT_* register fields */ 66 #define RK_MMU_IRQ_PAGE_FAULT 0x01 /* page fault */ 67 #define RK_MMU_IRQ_BUS_ERROR 0x02 /* bus read error */ 68 #define RK_MMU_IRQ_MASK (RK_MMU_IRQ_PAGE_FAULT | RK_MMU_IRQ_BUS_ERROR) 69 70 #define NUM_DT_ENTRIES 1024 71 #define NUM_PT_ENTRIES 1024 72 73 #define SPAGE_ORDER 12 74 #define SPAGE_SIZE (1 << SPAGE_ORDER) 75 76 /* 77 * Support mapping any size that fits in one page table: 78 * 4 KiB to 4 MiB 79 */ 80 #define RK_IOMMU_PGSIZE_BITMAP 0x007ff000 81 82 struct rk_iommu_domain { 83 struct list_head iommus; 84 u32 *dt; /* page directory table */ 85 dma_addr_t dt_dma; 86 spinlock_t iommus_lock; /* lock for iommus list */ 87 spinlock_t dt_lock; /* lock for modifying page directory table */ 88 89 struct iommu_domain domain; 90 }; 91 92 /* list of clocks required by IOMMU */ 93 static const char * const rk_iommu_clocks[] = { 94 "aclk", "iface", 95 }; 96 97 struct rk_iommu_ops { 98 phys_addr_t (*pt_address)(u32 dte); 99 u32 (*mk_dtentries)(dma_addr_t pt_dma); 100 u32 (*mk_ptentries)(phys_addr_t page, int prot); 101 phys_addr_t (*dte_addr_phys)(u32 addr); 102 u32 (*dma_addr_dte)(dma_addr_t dt_dma); 103 u64 dma_bit_mask; 104 }; 105 106 struct rk_iommu { 107 struct device *dev; 108 void __iomem **bases; 109 int num_mmu; 110 int num_irq; 111 struct clk_bulk_data *clocks; 112 int num_clocks; 113 bool reset_disabled; 114 struct iommu_device iommu; 115 struct list_head node; /* entry in rk_iommu_domain.iommus */ 116 struct iommu_domain *domain; /* domain to which iommu is attached */ 117 struct iommu_group *group; 118 }; 119 120 struct rk_iommudata { 121 struct device_link *link; /* runtime PM link from IOMMU to master */ 122 struct rk_iommu *iommu; 123 }; 124 125 static struct device *dma_dev; 126 static const struct rk_iommu_ops *rk_ops; 127 128 static inline void rk_table_flush(struct rk_iommu_domain *dom, dma_addr_t dma, 129 unsigned int count) 130 { 131 size_t size = count * sizeof(u32); /* count of u32 entry */ 132 133 dma_sync_single_for_device(dma_dev, dma, size, DMA_TO_DEVICE); 134 } 135 136 static struct rk_iommu_domain *to_rk_domain(struct iommu_domain *dom) 137 { 138 return container_of(dom, struct rk_iommu_domain, domain); 139 } 140 141 /* 142 * The Rockchip rk3288 iommu uses a 2-level page table. 143 * The first level is the "Directory Table" (DT). 144 * The DT consists of 1024 4-byte Directory Table Entries (DTEs), each pointing 145 * to a "Page Table". 146 * The second level is the 1024 Page Tables (PT). 147 * Each PT consists of 1024 4-byte Page Table Entries (PTEs), each pointing to 148 * a 4 KB page of physical memory. 149 * 150 * The DT and each PT fits in a single 4 KB page (4-bytes * 1024 entries). 151 * Each iommu device has a MMU_DTE_ADDR register that contains the physical 152 * address of the start of the DT page. 153 * 154 * The structure of the page table is as follows: 155 * 156 * DT 157 * MMU_DTE_ADDR -> +-----+ 158 * | | 159 * +-----+ PT 160 * | DTE | -> +-----+ 161 * +-----+ | | Memory 162 * | | +-----+ Page 163 * | | | PTE | -> +-----+ 164 * +-----+ +-----+ | | 165 * | | | | 166 * | | | | 167 * +-----+ | | 168 * | | 169 * | | 170 * +-----+ 171 */ 172 173 /* 174 * Each DTE has a PT address and a valid bit: 175 * +---------------------+-----------+-+ 176 * | PT address | Reserved |V| 177 * +---------------------+-----------+-+ 178 * 31:12 - PT address (PTs always starts on a 4 KB boundary) 179 * 11: 1 - Reserved 180 * 0 - 1 if PT @ PT address is valid 181 */ 182 #define RK_DTE_PT_ADDRESS_MASK 0xfffff000 183 #define RK_DTE_PT_VALID BIT(0) 184 185 static inline phys_addr_t rk_dte_pt_address(u32 dte) 186 { 187 return (phys_addr_t)dte & RK_DTE_PT_ADDRESS_MASK; 188 } 189 190 /* 191 * In v2: 192 * 31:12 - PT address bit 31:0 193 * 11: 8 - PT address bit 35:32 194 * 7: 4 - PT address bit 39:36 195 * 3: 1 - Reserved 196 * 0 - 1 if PT @ PT address is valid 197 */ 198 #define RK_DTE_PT_ADDRESS_MASK_V2 GENMASK_ULL(31, 4) 199 #define DTE_HI_MASK1 GENMASK(11, 8) 200 #define DTE_HI_MASK2 GENMASK(7, 4) 201 #define DTE_HI_SHIFT1 24 /* shift bit 8 to bit 32 */ 202 #define DTE_HI_SHIFT2 32 /* shift bit 4 to bit 36 */ 203 #define PAGE_DESC_HI_MASK1 GENMASK_ULL(35, 32) 204 #define PAGE_DESC_HI_MASK2 GENMASK_ULL(39, 36) 205 206 static inline phys_addr_t rk_dte_pt_address_v2(u32 dte) 207 { 208 u64 dte_v2 = dte; 209 210 dte_v2 = ((dte_v2 & DTE_HI_MASK2) << DTE_HI_SHIFT2) | 211 ((dte_v2 & DTE_HI_MASK1) << DTE_HI_SHIFT1) | 212 (dte_v2 & RK_DTE_PT_ADDRESS_MASK); 213 214 return (phys_addr_t)dte_v2; 215 } 216 217 static inline bool rk_dte_is_pt_valid(u32 dte) 218 { 219 return dte & RK_DTE_PT_VALID; 220 } 221 222 static inline u32 rk_mk_dte(dma_addr_t pt_dma) 223 { 224 return (pt_dma & RK_DTE_PT_ADDRESS_MASK) | RK_DTE_PT_VALID; 225 } 226 227 static inline u32 rk_mk_dte_v2(dma_addr_t pt_dma) 228 { 229 pt_dma = (pt_dma & RK_DTE_PT_ADDRESS_MASK) | 230 ((pt_dma & PAGE_DESC_HI_MASK1) >> DTE_HI_SHIFT1) | 231 (pt_dma & PAGE_DESC_HI_MASK2) >> DTE_HI_SHIFT2; 232 233 return (pt_dma & RK_DTE_PT_ADDRESS_MASK_V2) | RK_DTE_PT_VALID; 234 } 235 236 /* 237 * Each PTE has a Page address, some flags and a valid bit: 238 * +---------------------+---+-------+-+ 239 * | Page address |Rsv| Flags |V| 240 * +---------------------+---+-------+-+ 241 * 31:12 - Page address (Pages always start on a 4 KB boundary) 242 * 11: 9 - Reserved 243 * 8: 1 - Flags 244 * 8 - Read allocate - allocate cache space on read misses 245 * 7 - Read cache - enable cache & prefetch of data 246 * 6 - Write buffer - enable delaying writes on their way to memory 247 * 5 - Write allocate - allocate cache space on write misses 248 * 4 - Write cache - different writes can be merged together 249 * 3 - Override cache attributes 250 * if 1, bits 4-8 control cache attributes 251 * if 0, the system bus defaults are used 252 * 2 - Writable 253 * 1 - Readable 254 * 0 - 1 if Page @ Page address is valid 255 */ 256 #define RK_PTE_PAGE_ADDRESS_MASK 0xfffff000 257 #define RK_PTE_PAGE_FLAGS_MASK 0x000001fe 258 #define RK_PTE_PAGE_WRITABLE BIT(2) 259 #define RK_PTE_PAGE_READABLE BIT(1) 260 #define RK_PTE_PAGE_VALID BIT(0) 261 262 static inline bool rk_pte_is_page_valid(u32 pte) 263 { 264 return pte & RK_PTE_PAGE_VALID; 265 } 266 267 /* TODO: set cache flags per prot IOMMU_CACHE */ 268 static u32 rk_mk_pte(phys_addr_t page, int prot) 269 { 270 u32 flags = 0; 271 flags |= (prot & IOMMU_READ) ? RK_PTE_PAGE_READABLE : 0; 272 flags |= (prot & IOMMU_WRITE) ? RK_PTE_PAGE_WRITABLE : 0; 273 page &= RK_PTE_PAGE_ADDRESS_MASK; 274 return page | flags | RK_PTE_PAGE_VALID; 275 } 276 277 /* 278 * In v2: 279 * 31:12 - Page address bit 31:0 280 * 11:9 - Page address bit 34:32 281 * 8:4 - Page address bit 39:35 282 * 3 - Security 283 * 2 - Writable 284 * 1 - Readable 285 * 0 - 1 if Page @ Page address is valid 286 */ 287 288 static u32 rk_mk_pte_v2(phys_addr_t page, int prot) 289 { 290 u32 flags = 0; 291 292 flags |= (prot & IOMMU_READ) ? RK_PTE_PAGE_READABLE : 0; 293 flags |= (prot & IOMMU_WRITE) ? RK_PTE_PAGE_WRITABLE : 0; 294 295 return rk_mk_dte_v2(page) | flags; 296 } 297 298 static u32 rk_mk_pte_invalid(u32 pte) 299 { 300 return pte & ~RK_PTE_PAGE_VALID; 301 } 302 303 /* 304 * rk3288 iova (IOMMU Virtual Address) format 305 * 31 22.21 12.11 0 306 * +-----------+-----------+-------------+ 307 * | DTE index | PTE index | Page offset | 308 * +-----------+-----------+-------------+ 309 * 31:22 - DTE index - index of DTE in DT 310 * 21:12 - PTE index - index of PTE in PT @ DTE.pt_address 311 * 11: 0 - Page offset - offset into page @ PTE.page_address 312 */ 313 #define RK_IOVA_DTE_MASK 0xffc00000 314 #define RK_IOVA_DTE_SHIFT 22 315 #define RK_IOVA_PTE_MASK 0x003ff000 316 #define RK_IOVA_PTE_SHIFT 12 317 #define RK_IOVA_PAGE_MASK 0x00000fff 318 #define RK_IOVA_PAGE_SHIFT 0 319 320 static u32 rk_iova_dte_index(dma_addr_t iova) 321 { 322 return (u32)(iova & RK_IOVA_DTE_MASK) >> RK_IOVA_DTE_SHIFT; 323 } 324 325 static u32 rk_iova_pte_index(dma_addr_t iova) 326 { 327 return (u32)(iova & RK_IOVA_PTE_MASK) >> RK_IOVA_PTE_SHIFT; 328 } 329 330 static u32 rk_iova_page_offset(dma_addr_t iova) 331 { 332 return (u32)(iova & RK_IOVA_PAGE_MASK) >> RK_IOVA_PAGE_SHIFT; 333 } 334 335 static u32 rk_iommu_read(void __iomem *base, u32 offset) 336 { 337 return readl(base + offset); 338 } 339 340 static void rk_iommu_write(void __iomem *base, u32 offset, u32 value) 341 { 342 writel(value, base + offset); 343 } 344 345 static void rk_iommu_command(struct rk_iommu *iommu, u32 command) 346 { 347 int i; 348 349 for (i = 0; i < iommu->num_mmu; i++) 350 writel(command, iommu->bases[i] + RK_MMU_COMMAND); 351 } 352 353 static void rk_iommu_base_command(void __iomem *base, u32 command) 354 { 355 writel(command, base + RK_MMU_COMMAND); 356 } 357 static void rk_iommu_zap_lines(struct rk_iommu *iommu, dma_addr_t iova_start, 358 size_t size) 359 { 360 int i; 361 dma_addr_t iova_end = iova_start + size; 362 /* 363 * TODO(djkurtz): Figure out when it is more efficient to shootdown the 364 * entire iotlb rather than iterate over individual iovas. 365 */ 366 for (i = 0; i < iommu->num_mmu; i++) { 367 dma_addr_t iova; 368 369 for (iova = iova_start; iova < iova_end; iova += SPAGE_SIZE) 370 rk_iommu_write(iommu->bases[i], RK_MMU_ZAP_ONE_LINE, iova); 371 } 372 } 373 374 static bool rk_iommu_is_stall_active(struct rk_iommu *iommu) 375 { 376 bool active = true; 377 int i; 378 379 for (i = 0; i < iommu->num_mmu; i++) 380 active &= !!(rk_iommu_read(iommu->bases[i], RK_MMU_STATUS) & 381 RK_MMU_STATUS_STALL_ACTIVE); 382 383 return active; 384 } 385 386 static bool rk_iommu_is_paging_enabled(struct rk_iommu *iommu) 387 { 388 bool enable = true; 389 int i; 390 391 for (i = 0; i < iommu->num_mmu; i++) 392 enable &= !!(rk_iommu_read(iommu->bases[i], RK_MMU_STATUS) & 393 RK_MMU_STATUS_PAGING_ENABLED); 394 395 return enable; 396 } 397 398 static bool rk_iommu_is_reset_done(struct rk_iommu *iommu) 399 { 400 bool done = true; 401 int i; 402 403 for (i = 0; i < iommu->num_mmu; i++) 404 done &= rk_iommu_read(iommu->bases[i], RK_MMU_DTE_ADDR) == 0; 405 406 return done; 407 } 408 409 static int rk_iommu_enable_stall(struct rk_iommu *iommu) 410 { 411 int ret, i; 412 bool val; 413 414 if (rk_iommu_is_stall_active(iommu)) 415 return 0; 416 417 /* Stall can only be enabled if paging is enabled */ 418 if (!rk_iommu_is_paging_enabled(iommu)) 419 return 0; 420 421 rk_iommu_command(iommu, RK_MMU_CMD_ENABLE_STALL); 422 423 ret = readx_poll_timeout(rk_iommu_is_stall_active, iommu, val, 424 val, RK_MMU_POLL_PERIOD_US, 425 RK_MMU_POLL_TIMEOUT_US); 426 if (ret) 427 for (i = 0; i < iommu->num_mmu; i++) 428 dev_err(iommu->dev, "Enable stall request timed out, status: %#08x\n", 429 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); 430 431 return ret; 432 } 433 434 static int rk_iommu_disable_stall(struct rk_iommu *iommu) 435 { 436 int ret, i; 437 bool val; 438 439 if (!rk_iommu_is_stall_active(iommu)) 440 return 0; 441 442 rk_iommu_command(iommu, RK_MMU_CMD_DISABLE_STALL); 443 444 ret = readx_poll_timeout(rk_iommu_is_stall_active, iommu, val, 445 !val, RK_MMU_POLL_PERIOD_US, 446 RK_MMU_POLL_TIMEOUT_US); 447 if (ret) 448 for (i = 0; i < iommu->num_mmu; i++) 449 dev_err(iommu->dev, "Disable stall request timed out, status: %#08x\n", 450 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); 451 452 return ret; 453 } 454 455 static int rk_iommu_enable_paging(struct rk_iommu *iommu) 456 { 457 int ret, i; 458 bool val; 459 460 if (rk_iommu_is_paging_enabled(iommu)) 461 return 0; 462 463 rk_iommu_command(iommu, RK_MMU_CMD_ENABLE_PAGING); 464 465 ret = readx_poll_timeout(rk_iommu_is_paging_enabled, iommu, val, 466 val, RK_MMU_POLL_PERIOD_US, 467 RK_MMU_POLL_TIMEOUT_US); 468 if (ret) 469 for (i = 0; i < iommu->num_mmu; i++) 470 dev_err(iommu->dev, "Enable paging request timed out, status: %#08x\n", 471 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); 472 473 return ret; 474 } 475 476 static int rk_iommu_disable_paging(struct rk_iommu *iommu) 477 { 478 int ret, i; 479 bool val; 480 481 if (!rk_iommu_is_paging_enabled(iommu)) 482 return 0; 483 484 rk_iommu_command(iommu, RK_MMU_CMD_DISABLE_PAGING); 485 486 ret = readx_poll_timeout(rk_iommu_is_paging_enabled, iommu, val, 487 !val, RK_MMU_POLL_PERIOD_US, 488 RK_MMU_POLL_TIMEOUT_US); 489 if (ret) 490 for (i = 0; i < iommu->num_mmu; i++) 491 dev_err(iommu->dev, "Disable paging request timed out, status: %#08x\n", 492 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); 493 494 return ret; 495 } 496 497 static int rk_iommu_force_reset(struct rk_iommu *iommu) 498 { 499 int ret, i; 500 u32 dte_addr; 501 bool val; 502 503 if (iommu->reset_disabled) 504 return 0; 505 506 /* 507 * Check if register DTE_ADDR is working by writing DTE_ADDR_DUMMY 508 * and verifying that upper 5 nybbles are read back. 509 */ 510 for (i = 0; i < iommu->num_mmu; i++) { 511 dte_addr = rk_ops->pt_address(DTE_ADDR_DUMMY); 512 rk_iommu_write(iommu->bases[i], RK_MMU_DTE_ADDR, dte_addr); 513 514 if (dte_addr != rk_iommu_read(iommu->bases[i], RK_MMU_DTE_ADDR)) { 515 dev_err(iommu->dev, "Error during raw reset. MMU_DTE_ADDR is not functioning\n"); 516 return -EFAULT; 517 } 518 } 519 520 rk_iommu_command(iommu, RK_MMU_CMD_FORCE_RESET); 521 522 ret = readx_poll_timeout(rk_iommu_is_reset_done, iommu, val, 523 val, RK_MMU_FORCE_RESET_TIMEOUT_US, 524 RK_MMU_POLL_TIMEOUT_US); 525 if (ret) { 526 dev_err(iommu->dev, "FORCE_RESET command timed out\n"); 527 return ret; 528 } 529 530 return 0; 531 } 532 533 static inline phys_addr_t rk_dte_addr_phys(u32 addr) 534 { 535 return (phys_addr_t)addr; 536 } 537 538 static inline u32 rk_dma_addr_dte(dma_addr_t dt_dma) 539 { 540 return dt_dma; 541 } 542 543 #define DT_HI_MASK GENMASK_ULL(39, 32) 544 #define DTE_BASE_HI_MASK GENMASK(11, 4) 545 #define DT_SHIFT 28 546 547 static inline phys_addr_t rk_dte_addr_phys_v2(u32 addr) 548 { 549 u64 addr64 = addr; 550 return (phys_addr_t)(addr64 & RK_DTE_PT_ADDRESS_MASK) | 551 ((addr64 & DTE_BASE_HI_MASK) << DT_SHIFT); 552 } 553 554 static inline u32 rk_dma_addr_dte_v2(dma_addr_t dt_dma) 555 { 556 return (dt_dma & RK_DTE_PT_ADDRESS_MASK) | 557 ((dt_dma & DT_HI_MASK) >> DT_SHIFT); 558 } 559 560 static void log_iova(struct rk_iommu *iommu, int index, dma_addr_t iova) 561 { 562 void __iomem *base = iommu->bases[index]; 563 u32 dte_index, pte_index, page_offset; 564 u32 mmu_dte_addr; 565 phys_addr_t mmu_dte_addr_phys, dte_addr_phys; 566 u32 *dte_addr; 567 u32 dte; 568 phys_addr_t pte_addr_phys = 0; 569 u32 *pte_addr = NULL; 570 u32 pte = 0; 571 phys_addr_t page_addr_phys = 0; 572 u32 page_flags = 0; 573 574 dte_index = rk_iova_dte_index(iova); 575 pte_index = rk_iova_pte_index(iova); 576 page_offset = rk_iova_page_offset(iova); 577 578 mmu_dte_addr = rk_iommu_read(base, RK_MMU_DTE_ADDR); 579 mmu_dte_addr_phys = rk_ops->dte_addr_phys(mmu_dte_addr); 580 581 dte_addr_phys = mmu_dte_addr_phys + (4 * dte_index); 582 dte_addr = phys_to_virt(dte_addr_phys); 583 dte = *dte_addr; 584 585 if (!rk_dte_is_pt_valid(dte)) 586 goto print_it; 587 588 pte_addr_phys = rk_ops->pt_address(dte) + (pte_index * 4); 589 pte_addr = phys_to_virt(pte_addr_phys); 590 pte = *pte_addr; 591 592 if (!rk_pte_is_page_valid(pte)) 593 goto print_it; 594 595 page_addr_phys = rk_ops->pt_address(pte) + page_offset; 596 page_flags = pte & RK_PTE_PAGE_FLAGS_MASK; 597 598 print_it: 599 dev_err(iommu->dev, "iova = %pad: dte_index: %#03x pte_index: %#03x page_offset: %#03x\n", 600 &iova, dte_index, pte_index, page_offset); 601 dev_err(iommu->dev, "mmu_dte_addr: %pa dte@%pa: %#08x valid: %u pte@%pa: %#08x valid: %u page@%pa flags: %#03x\n", 602 &mmu_dte_addr_phys, &dte_addr_phys, dte, 603 rk_dte_is_pt_valid(dte), &pte_addr_phys, pte, 604 rk_pte_is_page_valid(pte), &page_addr_phys, page_flags); 605 } 606 607 static irqreturn_t rk_iommu_irq(int irq, void *dev_id) 608 { 609 struct rk_iommu *iommu = dev_id; 610 u32 status; 611 u32 int_status; 612 dma_addr_t iova; 613 irqreturn_t ret = IRQ_NONE; 614 int i, err; 615 616 err = pm_runtime_get_if_in_use(iommu->dev); 617 if (!err || WARN_ON_ONCE(err < 0)) 618 return ret; 619 620 if (WARN_ON(clk_bulk_enable(iommu->num_clocks, iommu->clocks))) 621 goto out; 622 623 for (i = 0; i < iommu->num_mmu; i++) { 624 int_status = rk_iommu_read(iommu->bases[i], RK_MMU_INT_STATUS); 625 if (int_status == 0) 626 continue; 627 628 ret = IRQ_HANDLED; 629 iova = rk_iommu_read(iommu->bases[i], RK_MMU_PAGE_FAULT_ADDR); 630 631 if (int_status & RK_MMU_IRQ_PAGE_FAULT) { 632 int flags; 633 634 status = rk_iommu_read(iommu->bases[i], RK_MMU_STATUS); 635 flags = (status & RK_MMU_STATUS_PAGE_FAULT_IS_WRITE) ? 636 IOMMU_FAULT_WRITE : IOMMU_FAULT_READ; 637 638 dev_err(iommu->dev, "Page fault at %pad of type %s\n", 639 &iova, 640 (flags == IOMMU_FAULT_WRITE) ? "write" : "read"); 641 642 log_iova(iommu, i, iova); 643 644 /* 645 * Report page fault to any installed handlers. 646 * Ignore the return code, though, since we always zap cache 647 * and clear the page fault anyway. 648 */ 649 if (iommu->domain) 650 report_iommu_fault(iommu->domain, iommu->dev, iova, 651 flags); 652 else 653 dev_err(iommu->dev, "Page fault while iommu not attached to domain?\n"); 654 655 rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_ZAP_CACHE); 656 rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_PAGE_FAULT_DONE); 657 } 658 659 if (int_status & RK_MMU_IRQ_BUS_ERROR) 660 dev_err(iommu->dev, "BUS_ERROR occurred at %pad\n", &iova); 661 662 if (int_status & ~RK_MMU_IRQ_MASK) 663 dev_err(iommu->dev, "unexpected int_status: %#08x\n", 664 int_status); 665 666 rk_iommu_write(iommu->bases[i], RK_MMU_INT_CLEAR, int_status); 667 } 668 669 clk_bulk_disable(iommu->num_clocks, iommu->clocks); 670 671 out: 672 pm_runtime_put(iommu->dev); 673 return ret; 674 } 675 676 static phys_addr_t rk_iommu_iova_to_phys(struct iommu_domain *domain, 677 dma_addr_t iova) 678 { 679 struct rk_iommu_domain *rk_domain = to_rk_domain(domain); 680 unsigned long flags; 681 phys_addr_t pt_phys, phys = 0; 682 u32 dte, pte; 683 u32 *page_table; 684 685 spin_lock_irqsave(&rk_domain->dt_lock, flags); 686 687 dte = rk_domain->dt[rk_iova_dte_index(iova)]; 688 if (!rk_dte_is_pt_valid(dte)) 689 goto out; 690 691 pt_phys = rk_ops->pt_address(dte); 692 page_table = (u32 *)phys_to_virt(pt_phys); 693 pte = page_table[rk_iova_pte_index(iova)]; 694 if (!rk_pte_is_page_valid(pte)) 695 goto out; 696 697 phys = rk_ops->pt_address(pte) + rk_iova_page_offset(iova); 698 out: 699 spin_unlock_irqrestore(&rk_domain->dt_lock, flags); 700 701 return phys; 702 } 703 704 static void rk_iommu_zap_iova(struct rk_iommu_domain *rk_domain, 705 dma_addr_t iova, size_t size) 706 { 707 struct list_head *pos; 708 unsigned long flags; 709 710 /* shootdown these iova from all iommus using this domain */ 711 spin_lock_irqsave(&rk_domain->iommus_lock, flags); 712 list_for_each(pos, &rk_domain->iommus) { 713 struct rk_iommu *iommu; 714 int ret; 715 716 iommu = list_entry(pos, struct rk_iommu, node); 717 718 /* Only zap TLBs of IOMMUs that are powered on. */ 719 ret = pm_runtime_get_if_in_use(iommu->dev); 720 if (WARN_ON_ONCE(ret < 0)) 721 continue; 722 if (ret) { 723 WARN_ON(clk_bulk_enable(iommu->num_clocks, 724 iommu->clocks)); 725 rk_iommu_zap_lines(iommu, iova, size); 726 clk_bulk_disable(iommu->num_clocks, iommu->clocks); 727 pm_runtime_put(iommu->dev); 728 } 729 } 730 spin_unlock_irqrestore(&rk_domain->iommus_lock, flags); 731 } 732 733 static void rk_iommu_zap_iova_first_last(struct rk_iommu_domain *rk_domain, 734 dma_addr_t iova, size_t size) 735 { 736 rk_iommu_zap_iova(rk_domain, iova, SPAGE_SIZE); 737 if (size > SPAGE_SIZE) 738 rk_iommu_zap_iova(rk_domain, iova + size - SPAGE_SIZE, 739 SPAGE_SIZE); 740 } 741 742 static u32 *rk_dte_get_page_table(struct rk_iommu_domain *rk_domain, 743 dma_addr_t iova) 744 { 745 u32 *page_table, *dte_addr; 746 u32 dte_index, dte; 747 phys_addr_t pt_phys; 748 dma_addr_t pt_dma; 749 750 assert_spin_locked(&rk_domain->dt_lock); 751 752 dte_index = rk_iova_dte_index(iova); 753 dte_addr = &rk_domain->dt[dte_index]; 754 dte = *dte_addr; 755 if (rk_dte_is_pt_valid(dte)) 756 goto done; 757 758 page_table = (u32 *)get_zeroed_page(GFP_ATOMIC | GFP_DMA32); 759 if (!page_table) 760 return ERR_PTR(-ENOMEM); 761 762 pt_dma = dma_map_single(dma_dev, page_table, SPAGE_SIZE, DMA_TO_DEVICE); 763 if (dma_mapping_error(dma_dev, pt_dma)) { 764 dev_err(dma_dev, "DMA mapping error while allocating page table\n"); 765 free_page((unsigned long)page_table); 766 return ERR_PTR(-ENOMEM); 767 } 768 769 dte = rk_ops->mk_dtentries(pt_dma); 770 *dte_addr = dte; 771 772 rk_table_flush(rk_domain, 773 rk_domain->dt_dma + dte_index * sizeof(u32), 1); 774 done: 775 pt_phys = rk_ops->pt_address(dte); 776 return (u32 *)phys_to_virt(pt_phys); 777 } 778 779 static size_t rk_iommu_unmap_iova(struct rk_iommu_domain *rk_domain, 780 u32 *pte_addr, dma_addr_t pte_dma, 781 size_t size) 782 { 783 unsigned int pte_count; 784 unsigned int pte_total = size / SPAGE_SIZE; 785 786 assert_spin_locked(&rk_domain->dt_lock); 787 788 for (pte_count = 0; pte_count < pte_total; pte_count++) { 789 u32 pte = pte_addr[pte_count]; 790 if (!rk_pte_is_page_valid(pte)) 791 break; 792 793 pte_addr[pte_count] = rk_mk_pte_invalid(pte); 794 } 795 796 rk_table_flush(rk_domain, pte_dma, pte_count); 797 798 return pte_count * SPAGE_SIZE; 799 } 800 801 static int rk_iommu_map_iova(struct rk_iommu_domain *rk_domain, u32 *pte_addr, 802 dma_addr_t pte_dma, dma_addr_t iova, 803 phys_addr_t paddr, size_t size, int prot) 804 { 805 unsigned int pte_count; 806 unsigned int pte_total = size / SPAGE_SIZE; 807 phys_addr_t page_phys; 808 809 assert_spin_locked(&rk_domain->dt_lock); 810 811 for (pte_count = 0; pte_count < pte_total; pte_count++) { 812 u32 pte = pte_addr[pte_count]; 813 814 if (rk_pte_is_page_valid(pte)) 815 goto unwind; 816 817 pte_addr[pte_count] = rk_ops->mk_ptentries(paddr, prot); 818 819 paddr += SPAGE_SIZE; 820 } 821 822 rk_table_flush(rk_domain, pte_dma, pte_total); 823 824 /* 825 * Zap the first and last iova to evict from iotlb any previously 826 * mapped cachelines holding stale values for its dte and pte. 827 * We only zap the first and last iova, since only they could have 828 * dte or pte shared with an existing mapping. 829 */ 830 rk_iommu_zap_iova_first_last(rk_domain, iova, size); 831 832 return 0; 833 unwind: 834 /* Unmap the range of iovas that we just mapped */ 835 rk_iommu_unmap_iova(rk_domain, pte_addr, pte_dma, 836 pte_count * SPAGE_SIZE); 837 838 iova += pte_count * SPAGE_SIZE; 839 page_phys = rk_ops->pt_address(pte_addr[pte_count]); 840 pr_err("iova: %pad already mapped to %pa cannot remap to phys: %pa prot: %#x\n", 841 &iova, &page_phys, &paddr, prot); 842 843 return -EADDRINUSE; 844 } 845 846 static int rk_iommu_map(struct iommu_domain *domain, unsigned long _iova, 847 phys_addr_t paddr, size_t size, int prot, gfp_t gfp) 848 { 849 struct rk_iommu_domain *rk_domain = to_rk_domain(domain); 850 unsigned long flags; 851 dma_addr_t pte_dma, iova = (dma_addr_t)_iova; 852 u32 *page_table, *pte_addr; 853 u32 dte_index, pte_index; 854 int ret; 855 856 spin_lock_irqsave(&rk_domain->dt_lock, flags); 857 858 /* 859 * pgsize_bitmap specifies iova sizes that fit in one page table 860 * (1024 4-KiB pages = 4 MiB). 861 * So, size will always be 4096 <= size <= 4194304. 862 * Since iommu_map() guarantees that both iova and size will be 863 * aligned, we will always only be mapping from a single dte here. 864 */ 865 page_table = rk_dte_get_page_table(rk_domain, iova); 866 if (IS_ERR(page_table)) { 867 spin_unlock_irqrestore(&rk_domain->dt_lock, flags); 868 return PTR_ERR(page_table); 869 } 870 871 dte_index = rk_domain->dt[rk_iova_dte_index(iova)]; 872 pte_index = rk_iova_pte_index(iova); 873 pte_addr = &page_table[pte_index]; 874 875 pte_dma = rk_ops->pt_address(dte_index) + pte_index * sizeof(u32); 876 ret = rk_iommu_map_iova(rk_domain, pte_addr, pte_dma, iova, 877 paddr, size, prot); 878 879 spin_unlock_irqrestore(&rk_domain->dt_lock, flags); 880 881 return ret; 882 } 883 884 static size_t rk_iommu_unmap(struct iommu_domain *domain, unsigned long _iova, 885 size_t size, struct iommu_iotlb_gather *gather) 886 { 887 struct rk_iommu_domain *rk_domain = to_rk_domain(domain); 888 unsigned long flags; 889 dma_addr_t pte_dma, iova = (dma_addr_t)_iova; 890 phys_addr_t pt_phys; 891 u32 dte; 892 u32 *pte_addr; 893 size_t unmap_size; 894 895 spin_lock_irqsave(&rk_domain->dt_lock, flags); 896 897 /* 898 * pgsize_bitmap specifies iova sizes that fit in one page table 899 * (1024 4-KiB pages = 4 MiB). 900 * So, size will always be 4096 <= size <= 4194304. 901 * Since iommu_unmap() guarantees that both iova and size will be 902 * aligned, we will always only be unmapping from a single dte here. 903 */ 904 dte = rk_domain->dt[rk_iova_dte_index(iova)]; 905 /* Just return 0 if iova is unmapped */ 906 if (!rk_dte_is_pt_valid(dte)) { 907 spin_unlock_irqrestore(&rk_domain->dt_lock, flags); 908 return 0; 909 } 910 911 pt_phys = rk_ops->pt_address(dte); 912 pte_addr = (u32 *)phys_to_virt(pt_phys) + rk_iova_pte_index(iova); 913 pte_dma = pt_phys + rk_iova_pte_index(iova) * sizeof(u32); 914 unmap_size = rk_iommu_unmap_iova(rk_domain, pte_addr, pte_dma, size); 915 916 spin_unlock_irqrestore(&rk_domain->dt_lock, flags); 917 918 /* Shootdown iotlb entries for iova range that was just unmapped */ 919 rk_iommu_zap_iova(rk_domain, iova, unmap_size); 920 921 return unmap_size; 922 } 923 924 static struct rk_iommu *rk_iommu_from_dev(struct device *dev) 925 { 926 struct rk_iommudata *data = dev_iommu_priv_get(dev); 927 928 return data ? data->iommu : NULL; 929 } 930 931 /* Must be called with iommu powered on and attached */ 932 static void rk_iommu_disable(struct rk_iommu *iommu) 933 { 934 int i; 935 936 /* Ignore error while disabling, just keep going */ 937 WARN_ON(clk_bulk_enable(iommu->num_clocks, iommu->clocks)); 938 rk_iommu_enable_stall(iommu); 939 rk_iommu_disable_paging(iommu); 940 for (i = 0; i < iommu->num_mmu; i++) { 941 rk_iommu_write(iommu->bases[i], RK_MMU_INT_MASK, 0); 942 rk_iommu_write(iommu->bases[i], RK_MMU_DTE_ADDR, 0); 943 } 944 rk_iommu_disable_stall(iommu); 945 clk_bulk_disable(iommu->num_clocks, iommu->clocks); 946 } 947 948 /* Must be called with iommu powered on and attached */ 949 static int rk_iommu_enable(struct rk_iommu *iommu) 950 { 951 struct iommu_domain *domain = iommu->domain; 952 struct rk_iommu_domain *rk_domain = to_rk_domain(domain); 953 int ret, i; 954 955 ret = clk_bulk_enable(iommu->num_clocks, iommu->clocks); 956 if (ret) 957 return ret; 958 959 ret = rk_iommu_enable_stall(iommu); 960 if (ret) 961 goto out_disable_clocks; 962 963 ret = rk_iommu_force_reset(iommu); 964 if (ret) 965 goto out_disable_stall; 966 967 for (i = 0; i < iommu->num_mmu; i++) { 968 rk_iommu_write(iommu->bases[i], RK_MMU_DTE_ADDR, 969 rk_ops->dma_addr_dte(rk_domain->dt_dma)); 970 rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_ZAP_CACHE); 971 rk_iommu_write(iommu->bases[i], RK_MMU_INT_MASK, RK_MMU_IRQ_MASK); 972 } 973 974 ret = rk_iommu_enable_paging(iommu); 975 976 out_disable_stall: 977 rk_iommu_disable_stall(iommu); 978 out_disable_clocks: 979 clk_bulk_disable(iommu->num_clocks, iommu->clocks); 980 return ret; 981 } 982 983 static void rk_iommu_detach_device(struct iommu_domain *domain, 984 struct device *dev) 985 { 986 struct rk_iommu *iommu; 987 struct rk_iommu_domain *rk_domain = to_rk_domain(domain); 988 unsigned long flags; 989 int ret; 990 991 /* Allow 'virtual devices' (eg drm) to detach from domain */ 992 iommu = rk_iommu_from_dev(dev); 993 if (!iommu) 994 return; 995 996 dev_dbg(dev, "Detaching from iommu domain\n"); 997 998 /* iommu already detached */ 999 if (iommu->domain != domain) 1000 return; 1001 1002 iommu->domain = NULL; 1003 1004 spin_lock_irqsave(&rk_domain->iommus_lock, flags); 1005 list_del_init(&iommu->node); 1006 spin_unlock_irqrestore(&rk_domain->iommus_lock, flags); 1007 1008 ret = pm_runtime_get_if_in_use(iommu->dev); 1009 WARN_ON_ONCE(ret < 0); 1010 if (ret > 0) { 1011 rk_iommu_disable(iommu); 1012 pm_runtime_put(iommu->dev); 1013 } 1014 } 1015 1016 static int rk_iommu_attach_device(struct iommu_domain *domain, 1017 struct device *dev) 1018 { 1019 struct rk_iommu *iommu; 1020 struct rk_iommu_domain *rk_domain = to_rk_domain(domain); 1021 unsigned long flags; 1022 int ret; 1023 1024 /* 1025 * Allow 'virtual devices' (e.g., drm) to attach to domain. 1026 * Such a device does not belong to an iommu group. 1027 */ 1028 iommu = rk_iommu_from_dev(dev); 1029 if (!iommu) 1030 return 0; 1031 1032 dev_dbg(dev, "Attaching to iommu domain\n"); 1033 1034 /* iommu already attached */ 1035 if (iommu->domain == domain) 1036 return 0; 1037 1038 if (iommu->domain) 1039 rk_iommu_detach_device(iommu->domain, dev); 1040 1041 iommu->domain = domain; 1042 1043 spin_lock_irqsave(&rk_domain->iommus_lock, flags); 1044 list_add_tail(&iommu->node, &rk_domain->iommus); 1045 spin_unlock_irqrestore(&rk_domain->iommus_lock, flags); 1046 1047 ret = pm_runtime_get_if_in_use(iommu->dev); 1048 if (!ret || WARN_ON_ONCE(ret < 0)) 1049 return 0; 1050 1051 ret = rk_iommu_enable(iommu); 1052 if (ret) 1053 rk_iommu_detach_device(iommu->domain, dev); 1054 1055 pm_runtime_put(iommu->dev); 1056 1057 return ret; 1058 } 1059 1060 static struct iommu_domain *rk_iommu_domain_alloc(unsigned type) 1061 { 1062 struct rk_iommu_domain *rk_domain; 1063 1064 if (type != IOMMU_DOMAIN_UNMANAGED && type != IOMMU_DOMAIN_DMA) 1065 return NULL; 1066 1067 if (!dma_dev) 1068 return NULL; 1069 1070 rk_domain = kzalloc(sizeof(*rk_domain), GFP_KERNEL); 1071 if (!rk_domain) 1072 return NULL; 1073 1074 /* 1075 * rk32xx iommus use a 2 level pagetable. 1076 * Each level1 (dt) and level2 (pt) table has 1024 4-byte entries. 1077 * Allocate one 4 KiB page for each table. 1078 */ 1079 rk_domain->dt = (u32 *)get_zeroed_page(GFP_KERNEL | GFP_DMA32); 1080 if (!rk_domain->dt) 1081 goto err_free_domain; 1082 1083 rk_domain->dt_dma = dma_map_single(dma_dev, rk_domain->dt, 1084 SPAGE_SIZE, DMA_TO_DEVICE); 1085 if (dma_mapping_error(dma_dev, rk_domain->dt_dma)) { 1086 dev_err(dma_dev, "DMA map error for DT\n"); 1087 goto err_free_dt; 1088 } 1089 1090 spin_lock_init(&rk_domain->iommus_lock); 1091 spin_lock_init(&rk_domain->dt_lock); 1092 INIT_LIST_HEAD(&rk_domain->iommus); 1093 1094 rk_domain->domain.geometry.aperture_start = 0; 1095 rk_domain->domain.geometry.aperture_end = DMA_BIT_MASK(32); 1096 rk_domain->domain.geometry.force_aperture = true; 1097 1098 return &rk_domain->domain; 1099 1100 err_free_dt: 1101 free_page((unsigned long)rk_domain->dt); 1102 err_free_domain: 1103 kfree(rk_domain); 1104 1105 return NULL; 1106 } 1107 1108 static void rk_iommu_domain_free(struct iommu_domain *domain) 1109 { 1110 struct rk_iommu_domain *rk_domain = to_rk_domain(domain); 1111 int i; 1112 1113 WARN_ON(!list_empty(&rk_domain->iommus)); 1114 1115 for (i = 0; i < NUM_DT_ENTRIES; i++) { 1116 u32 dte = rk_domain->dt[i]; 1117 if (rk_dte_is_pt_valid(dte)) { 1118 phys_addr_t pt_phys = rk_ops->pt_address(dte); 1119 u32 *page_table = phys_to_virt(pt_phys); 1120 dma_unmap_single(dma_dev, pt_phys, 1121 SPAGE_SIZE, DMA_TO_DEVICE); 1122 free_page((unsigned long)page_table); 1123 } 1124 } 1125 1126 dma_unmap_single(dma_dev, rk_domain->dt_dma, 1127 SPAGE_SIZE, DMA_TO_DEVICE); 1128 free_page((unsigned long)rk_domain->dt); 1129 1130 kfree(rk_domain); 1131 } 1132 1133 static struct iommu_device *rk_iommu_probe_device(struct device *dev) 1134 { 1135 struct rk_iommudata *data; 1136 struct rk_iommu *iommu; 1137 1138 data = dev_iommu_priv_get(dev); 1139 if (!data) 1140 return ERR_PTR(-ENODEV); 1141 1142 iommu = rk_iommu_from_dev(dev); 1143 1144 data->link = device_link_add(dev, iommu->dev, 1145 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME); 1146 1147 return &iommu->iommu; 1148 } 1149 1150 static void rk_iommu_release_device(struct device *dev) 1151 { 1152 struct rk_iommudata *data = dev_iommu_priv_get(dev); 1153 1154 device_link_del(data->link); 1155 } 1156 1157 static struct iommu_group *rk_iommu_device_group(struct device *dev) 1158 { 1159 struct rk_iommu *iommu; 1160 1161 iommu = rk_iommu_from_dev(dev); 1162 1163 return iommu_group_ref_get(iommu->group); 1164 } 1165 1166 static int rk_iommu_of_xlate(struct device *dev, 1167 struct of_phandle_args *args) 1168 { 1169 struct platform_device *iommu_dev; 1170 struct rk_iommudata *data; 1171 1172 data = devm_kzalloc(dma_dev, sizeof(*data), GFP_KERNEL); 1173 if (!data) 1174 return -ENOMEM; 1175 1176 iommu_dev = of_find_device_by_node(args->np); 1177 1178 data->iommu = platform_get_drvdata(iommu_dev); 1179 dev_iommu_priv_set(dev, data); 1180 1181 platform_device_put(iommu_dev); 1182 1183 return 0; 1184 } 1185 1186 static const struct iommu_ops rk_iommu_ops = { 1187 .domain_alloc = rk_iommu_domain_alloc, 1188 .probe_device = rk_iommu_probe_device, 1189 .release_device = rk_iommu_release_device, 1190 .device_group = rk_iommu_device_group, 1191 .pgsize_bitmap = RK_IOMMU_PGSIZE_BITMAP, 1192 .of_xlate = rk_iommu_of_xlate, 1193 .default_domain_ops = &(const struct iommu_domain_ops) { 1194 .attach_dev = rk_iommu_attach_device, 1195 .map = rk_iommu_map, 1196 .unmap = rk_iommu_unmap, 1197 .iova_to_phys = rk_iommu_iova_to_phys, 1198 .free = rk_iommu_domain_free, 1199 } 1200 }; 1201 1202 static int rk_iommu_probe(struct platform_device *pdev) 1203 { 1204 struct device *dev = &pdev->dev; 1205 struct rk_iommu *iommu; 1206 struct resource *res; 1207 const struct rk_iommu_ops *ops; 1208 int num_res = pdev->num_resources; 1209 int err, i; 1210 1211 iommu = devm_kzalloc(dev, sizeof(*iommu), GFP_KERNEL); 1212 if (!iommu) 1213 return -ENOMEM; 1214 1215 platform_set_drvdata(pdev, iommu); 1216 iommu->dev = dev; 1217 iommu->num_mmu = 0; 1218 1219 ops = of_device_get_match_data(dev); 1220 if (!rk_ops) 1221 rk_ops = ops; 1222 1223 /* 1224 * That should not happen unless different versions of the 1225 * hardware block are embedded the same SoC 1226 */ 1227 if (WARN_ON(rk_ops != ops)) 1228 return -EINVAL; 1229 1230 iommu->bases = devm_kcalloc(dev, num_res, sizeof(*iommu->bases), 1231 GFP_KERNEL); 1232 if (!iommu->bases) 1233 return -ENOMEM; 1234 1235 for (i = 0; i < num_res; i++) { 1236 res = platform_get_resource(pdev, IORESOURCE_MEM, i); 1237 if (!res) 1238 continue; 1239 iommu->bases[i] = devm_ioremap_resource(&pdev->dev, res); 1240 if (IS_ERR(iommu->bases[i])) 1241 continue; 1242 iommu->num_mmu++; 1243 } 1244 if (iommu->num_mmu == 0) 1245 return PTR_ERR(iommu->bases[0]); 1246 1247 iommu->num_irq = platform_irq_count(pdev); 1248 if (iommu->num_irq < 0) 1249 return iommu->num_irq; 1250 1251 iommu->reset_disabled = device_property_read_bool(dev, 1252 "rockchip,disable-mmu-reset"); 1253 1254 iommu->num_clocks = ARRAY_SIZE(rk_iommu_clocks); 1255 iommu->clocks = devm_kcalloc(iommu->dev, iommu->num_clocks, 1256 sizeof(*iommu->clocks), GFP_KERNEL); 1257 if (!iommu->clocks) 1258 return -ENOMEM; 1259 1260 for (i = 0; i < iommu->num_clocks; ++i) 1261 iommu->clocks[i].id = rk_iommu_clocks[i]; 1262 1263 /* 1264 * iommu clocks should be present for all new devices and devicetrees 1265 * but there are older devicetrees without clocks out in the wild. 1266 * So clocks as optional for the time being. 1267 */ 1268 err = devm_clk_bulk_get(iommu->dev, iommu->num_clocks, iommu->clocks); 1269 if (err == -ENOENT) 1270 iommu->num_clocks = 0; 1271 else if (err) 1272 return err; 1273 1274 err = clk_bulk_prepare(iommu->num_clocks, iommu->clocks); 1275 if (err) 1276 return err; 1277 1278 iommu->group = iommu_group_alloc(); 1279 if (IS_ERR(iommu->group)) { 1280 err = PTR_ERR(iommu->group); 1281 goto err_unprepare_clocks; 1282 } 1283 1284 err = iommu_device_sysfs_add(&iommu->iommu, dev, NULL, dev_name(dev)); 1285 if (err) 1286 goto err_put_group; 1287 1288 err = iommu_device_register(&iommu->iommu, &rk_iommu_ops, dev); 1289 if (err) 1290 goto err_remove_sysfs; 1291 1292 /* 1293 * Use the first registered IOMMU device for domain to use with DMA 1294 * API, since a domain might not physically correspond to a single 1295 * IOMMU device.. 1296 */ 1297 if (!dma_dev) 1298 dma_dev = &pdev->dev; 1299 1300 pm_runtime_enable(dev); 1301 1302 for (i = 0; i < iommu->num_irq; i++) { 1303 int irq = platform_get_irq(pdev, i); 1304 1305 if (irq < 0) 1306 return irq; 1307 1308 err = devm_request_irq(iommu->dev, irq, rk_iommu_irq, 1309 IRQF_SHARED, dev_name(dev), iommu); 1310 if (err) { 1311 pm_runtime_disable(dev); 1312 goto err_remove_sysfs; 1313 } 1314 } 1315 1316 dma_set_mask_and_coherent(dev, rk_ops->dma_bit_mask); 1317 1318 return 0; 1319 err_remove_sysfs: 1320 iommu_device_sysfs_remove(&iommu->iommu); 1321 err_put_group: 1322 iommu_group_put(iommu->group); 1323 err_unprepare_clocks: 1324 clk_bulk_unprepare(iommu->num_clocks, iommu->clocks); 1325 return err; 1326 } 1327 1328 static void rk_iommu_shutdown(struct platform_device *pdev) 1329 { 1330 struct rk_iommu *iommu = platform_get_drvdata(pdev); 1331 int i; 1332 1333 for (i = 0; i < iommu->num_irq; i++) { 1334 int irq = platform_get_irq(pdev, i); 1335 1336 devm_free_irq(iommu->dev, irq, iommu); 1337 } 1338 1339 pm_runtime_force_suspend(&pdev->dev); 1340 } 1341 1342 static int __maybe_unused rk_iommu_suspend(struct device *dev) 1343 { 1344 struct rk_iommu *iommu = dev_get_drvdata(dev); 1345 1346 if (!iommu->domain) 1347 return 0; 1348 1349 rk_iommu_disable(iommu); 1350 return 0; 1351 } 1352 1353 static int __maybe_unused rk_iommu_resume(struct device *dev) 1354 { 1355 struct rk_iommu *iommu = dev_get_drvdata(dev); 1356 1357 if (!iommu->domain) 1358 return 0; 1359 1360 return rk_iommu_enable(iommu); 1361 } 1362 1363 static const struct dev_pm_ops rk_iommu_pm_ops = { 1364 SET_RUNTIME_PM_OPS(rk_iommu_suspend, rk_iommu_resume, NULL) 1365 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1366 pm_runtime_force_resume) 1367 }; 1368 1369 static struct rk_iommu_ops iommu_data_ops_v1 = { 1370 .pt_address = &rk_dte_pt_address, 1371 .mk_dtentries = &rk_mk_dte, 1372 .mk_ptentries = &rk_mk_pte, 1373 .dte_addr_phys = &rk_dte_addr_phys, 1374 .dma_addr_dte = &rk_dma_addr_dte, 1375 .dma_bit_mask = DMA_BIT_MASK(32), 1376 }; 1377 1378 static struct rk_iommu_ops iommu_data_ops_v2 = { 1379 .pt_address = &rk_dte_pt_address_v2, 1380 .mk_dtentries = &rk_mk_dte_v2, 1381 .mk_ptentries = &rk_mk_pte_v2, 1382 .dte_addr_phys = &rk_dte_addr_phys_v2, 1383 .dma_addr_dte = &rk_dma_addr_dte_v2, 1384 .dma_bit_mask = DMA_BIT_MASK(40), 1385 }; 1386 1387 static const struct of_device_id rk_iommu_dt_ids[] = { 1388 { .compatible = "rockchip,iommu", 1389 .data = &iommu_data_ops_v1, 1390 }, 1391 { .compatible = "rockchip,rk3568-iommu", 1392 .data = &iommu_data_ops_v2, 1393 }, 1394 { /* sentinel */ } 1395 }; 1396 1397 static struct platform_driver rk_iommu_driver = { 1398 .probe = rk_iommu_probe, 1399 .shutdown = rk_iommu_shutdown, 1400 .driver = { 1401 .name = "rk_iommu", 1402 .of_match_table = rk_iommu_dt_ids, 1403 .pm = &rk_iommu_pm_ops, 1404 .suppress_bind_attrs = true, 1405 }, 1406 }; 1407 builtin_platform_driver(rk_iommu_driver); 1408