1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * RISC-V IOMMU as a platform device 4 * 5 * Copyright © 2023 FORTH-ICS/CARV 6 * Copyright © 2023-2024 Rivos Inc. 7 * 8 * Authors 9 * Nick Kossifidis <mick@ics.forth.gr> 10 * Tomasz Jeznach <tjeznach@rivosinc.com> 11 */ 12 13 #include <linux/acpi.h> 14 #include <linux/irqchip/riscv-imsic.h> 15 #include <linux/kernel.h> 16 #include <linux/msi.h> 17 #include <linux/of_irq.h> 18 #include <linux/of_platform.h> 19 #include <linux/platform_device.h> 20 21 #include "iommu-bits.h" 22 #include "iommu.h" 23 24 static void riscv_iommu_write_msi_msg(struct msi_desc *desc, struct msi_msg *msg) 25 { 26 struct device *dev = msi_desc_to_dev(desc); 27 struct riscv_iommu_device *iommu = dev_get_drvdata(dev); 28 u16 idx = desc->msi_index; 29 u64 addr; 30 31 addr = ((u64)msg->address_hi << 32) | msg->address_lo; 32 33 if (addr != (addr & RISCV_IOMMU_MSI_CFG_TBL_ADDR)) { 34 dev_err_once(dev, 35 "uh oh, the IOMMU can't send MSIs to 0x%llx, sending to 0x%llx instead\n", 36 addr, addr & RISCV_IOMMU_MSI_CFG_TBL_ADDR); 37 } 38 39 addr &= RISCV_IOMMU_MSI_CFG_TBL_ADDR; 40 41 riscv_iommu_writeq(iommu, RISCV_IOMMU_REG_MSI_CFG_TBL_ADDR(idx), addr); 42 riscv_iommu_writel(iommu, RISCV_IOMMU_REG_MSI_CFG_TBL_DATA(idx), msg->data); 43 riscv_iommu_writel(iommu, RISCV_IOMMU_REG_MSI_CFG_TBL_CTRL(idx), 0); 44 } 45 46 static int riscv_iommu_platform_probe(struct platform_device *pdev) 47 { 48 enum riscv_iommu_igs_settings igs; 49 struct device *dev = &pdev->dev; 50 struct riscv_iommu_device *iommu = NULL; 51 struct irq_domain *msi_domain; 52 struct resource *res = NULL; 53 int vec, ret; 54 55 iommu = devm_kzalloc(dev, sizeof(*iommu), GFP_KERNEL); 56 if (!iommu) 57 return -ENOMEM; 58 59 iommu->dev = dev; 60 iommu->reg = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 61 if (IS_ERR(iommu->reg)) 62 return dev_err_probe(dev, PTR_ERR(iommu->reg), 63 "could not map register region\n"); 64 65 dev_set_drvdata(dev, iommu); 66 67 /* Check device reported capabilities / features. */ 68 iommu->caps = riscv_iommu_readq(iommu, RISCV_IOMMU_REG_CAPABILITIES); 69 iommu->fctl = riscv_iommu_readl(iommu, RISCV_IOMMU_REG_FCTL); 70 71 iommu->irqs_count = platform_irq_count(pdev); 72 if (iommu->irqs_count <= 0) 73 return dev_err_probe(dev, -ENODEV, 74 "no IRQ resources provided\n"); 75 if (iommu->irqs_count > RISCV_IOMMU_INTR_COUNT) 76 iommu->irqs_count = RISCV_IOMMU_INTR_COUNT; 77 78 igs = FIELD_GET(RISCV_IOMMU_CAPABILITIES_IGS, iommu->caps); 79 switch (igs) { 80 case RISCV_IOMMU_CAPABILITIES_IGS_BOTH: 81 case RISCV_IOMMU_CAPABILITIES_IGS_MSI: 82 if (is_of_node(dev_fwnode(dev))) { 83 of_msi_configure(dev, to_of_node(dev->fwnode)); 84 } else { 85 msi_domain = irq_find_matching_fwnode(imsic_acpi_get_fwnode(dev), 86 DOMAIN_BUS_PLATFORM_MSI); 87 dev_set_msi_domain(dev, msi_domain); 88 } 89 90 if (!dev_get_msi_domain(dev)) { 91 dev_warn(dev, "failed to find an MSI domain\n"); 92 goto msi_fail; 93 } 94 95 ret = platform_device_msi_init_and_alloc_irqs(dev, iommu->irqs_count, 96 riscv_iommu_write_msi_msg); 97 if (ret) { 98 dev_warn(dev, "failed to allocate MSIs\n"); 99 goto msi_fail; 100 } 101 102 for (vec = 0; vec < iommu->irqs_count; vec++) 103 iommu->irqs[vec] = msi_get_virq(dev, vec); 104 105 /* Enable message-signaled interrupts, fctl.WSI */ 106 if (iommu->fctl & RISCV_IOMMU_FCTL_WSI) { 107 iommu->fctl ^= RISCV_IOMMU_FCTL_WSI; 108 riscv_iommu_writel(iommu, RISCV_IOMMU_REG_FCTL, iommu->fctl); 109 } 110 111 dev_info(dev, "using MSIs\n"); 112 break; 113 114 msi_fail: 115 if (igs != RISCV_IOMMU_CAPABILITIES_IGS_BOTH) { 116 return dev_err_probe(dev, -ENODEV, 117 "unable to use wire-signaled interrupts\n"); 118 } 119 120 fallthrough; 121 122 case RISCV_IOMMU_CAPABILITIES_IGS_WSI: 123 for (vec = 0; vec < iommu->irqs_count; vec++) 124 iommu->irqs[vec] = platform_get_irq(pdev, vec); 125 126 /* Enable wire-signaled interrupts, fctl.WSI */ 127 if (!(iommu->fctl & RISCV_IOMMU_FCTL_WSI)) { 128 iommu->fctl |= RISCV_IOMMU_FCTL_WSI; 129 riscv_iommu_writel(iommu, RISCV_IOMMU_REG_FCTL, iommu->fctl); 130 } 131 dev_info(dev, "using wire-signaled interrupts\n"); 132 break; 133 default: 134 return dev_err_probe(dev, -ENODEV, "invalid IGS\n"); 135 } 136 137 return riscv_iommu_init(iommu); 138 }; 139 140 static void riscv_iommu_platform_remove(struct platform_device *pdev) 141 { 142 struct riscv_iommu_device *iommu = dev_get_drvdata(&pdev->dev); 143 bool msi = !(iommu->fctl & RISCV_IOMMU_FCTL_WSI); 144 145 riscv_iommu_remove(iommu); 146 147 if (msi) 148 platform_device_msi_free_irqs_all(&pdev->dev); 149 }; 150 151 static void riscv_iommu_platform_shutdown(struct platform_device *pdev) 152 { 153 riscv_iommu_disable(dev_get_drvdata(&pdev->dev)); 154 }; 155 156 static const struct of_device_id riscv_iommu_of_match[] = { 157 {.compatible = "riscv,iommu",}, 158 {}, 159 }; 160 161 static const struct acpi_device_id riscv_iommu_acpi_match[] = { 162 { "RSCV0004", 0 }, 163 {} 164 }; 165 MODULE_DEVICE_TABLE(acpi, riscv_iommu_acpi_match); 166 167 static struct platform_driver riscv_iommu_platform_driver = { 168 .probe = riscv_iommu_platform_probe, 169 .remove = riscv_iommu_platform_remove, 170 .shutdown = riscv_iommu_platform_shutdown, 171 .driver = { 172 .name = "riscv,iommu", 173 .of_match_table = riscv_iommu_of_match, 174 .suppress_bind_attrs = true, 175 .acpi_match_table = riscv_iommu_acpi_match, 176 }, 177 }; 178 179 builtin_platform_driver(riscv_iommu_platform_driver); 180