1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright © 2022-2024 Rivos Inc. 4 * Copyright © 2023 FORTH-ICS/CARV 5 * Copyright © 2023 RISC-V IOMMU Task Group 6 * 7 * RISC-V IOMMU - Register Layout and Data Structures. 8 * 9 * Based on the 'RISC-V IOMMU Architecture Specification', Version 1.0 10 * Published at https://github.com/riscv-non-isa/riscv-iommu 11 * 12 */ 13 14 #ifndef _RISCV_IOMMU_BITS_H_ 15 #define _RISCV_IOMMU_BITS_H_ 16 17 #include <linux/types.h> 18 #include <linux/bitfield.h> 19 #include <linux/bits.h> 20 #include <asm/page.h> 21 22 /* 23 * Chapter 5: Memory Mapped register interface 24 */ 25 26 /* Common field positions */ 27 #define RISCV_IOMMU_PPN_FIELD GENMASK_ULL(53, 10) 28 #define RISCV_IOMMU_QUEUE_LOG2SZ_FIELD GENMASK_ULL(4, 0) 29 #define RISCV_IOMMU_QUEUE_INDEX_FIELD GENMASK_ULL(31, 0) 30 #define RISCV_IOMMU_QUEUE_ENABLE BIT(0) 31 #define RISCV_IOMMU_QUEUE_INTR_ENABLE BIT(1) 32 #define RISCV_IOMMU_QUEUE_MEM_FAULT BIT(8) 33 #define RISCV_IOMMU_QUEUE_OVERFLOW BIT(9) 34 #define RISCV_IOMMU_QUEUE_ACTIVE BIT(16) 35 #define RISCV_IOMMU_QUEUE_BUSY BIT(17) 36 37 #define RISCV_IOMMU_ATP_PPN_FIELD GENMASK_ULL(43, 0) 38 #define RISCV_IOMMU_ATP_MODE_FIELD GENMASK_ULL(63, 60) 39 40 /* 5.3 IOMMU Capabilities (64bits) */ 41 #define RISCV_IOMMU_REG_CAPABILITIES 0x0000 42 #define RISCV_IOMMU_CAPABILITIES_VERSION GENMASK_ULL(7, 0) 43 #define RISCV_IOMMU_CAPABILITIES_SV32 BIT_ULL(8) 44 #define RISCV_IOMMU_CAPABILITIES_SV39 BIT_ULL(9) 45 #define RISCV_IOMMU_CAPABILITIES_SV48 BIT_ULL(10) 46 #define RISCV_IOMMU_CAPABILITIES_SV57 BIT_ULL(11) 47 #define RISCV_IOMMU_CAPABILITIES_SVPBMT BIT_ULL(15) 48 #define RISCV_IOMMU_CAPABILITIES_SV32X4 BIT_ULL(16) 49 #define RISCV_IOMMU_CAPABILITIES_SV39X4 BIT_ULL(17) 50 #define RISCV_IOMMU_CAPABILITIES_SV48X4 BIT_ULL(18) 51 #define RISCV_IOMMU_CAPABILITIES_SV57X4 BIT_ULL(19) 52 #define RISCV_IOMMU_CAPABILITIES_AMO_MRIF BIT_ULL(21) 53 #define RISCV_IOMMU_CAPABILITIES_MSI_FLAT BIT_ULL(22) 54 #define RISCV_IOMMU_CAPABILITIES_MSI_MRIF BIT_ULL(23) 55 #define RISCV_IOMMU_CAPABILITIES_AMO_HWAD BIT_ULL(24) 56 #define RISCV_IOMMU_CAPABILITIES_ATS BIT_ULL(25) 57 #define RISCV_IOMMU_CAPABILITIES_T2GPA BIT_ULL(26) 58 #define RISCV_IOMMU_CAPABILITIES_END BIT_ULL(27) 59 #define RISCV_IOMMU_CAPABILITIES_IGS GENMASK_ULL(29, 28) 60 #define RISCV_IOMMU_CAPABILITIES_HPM BIT_ULL(30) 61 #define RISCV_IOMMU_CAPABILITIES_DBG BIT_ULL(31) 62 #define RISCV_IOMMU_CAPABILITIES_PAS GENMASK_ULL(37, 32) 63 #define RISCV_IOMMU_CAPABILITIES_PD8 BIT_ULL(38) 64 #define RISCV_IOMMU_CAPABILITIES_PD17 BIT_ULL(39) 65 #define RISCV_IOMMU_CAPABILITIES_PD20 BIT_ULL(40) 66 67 /** 68 * enum riscv_iommu_igs_settings - Interrupt Generation Support Settings 69 * @RISCV_IOMMU_CAPABILITIES_IGS_MSI: IOMMU supports only MSI generation 70 * @RISCV_IOMMU_CAPABILITIES_IGS_WSI: IOMMU supports only Wired-Signaled interrupt 71 * @RISCV_IOMMU_CAPABILITIES_IGS_BOTH: IOMMU supports both MSI and WSI generation 72 * @RISCV_IOMMU_CAPABILITIES_IGS_RSRV: Reserved for standard use 73 */ 74 enum riscv_iommu_igs_settings { 75 RISCV_IOMMU_CAPABILITIES_IGS_MSI = 0, 76 RISCV_IOMMU_CAPABILITIES_IGS_WSI = 1, 77 RISCV_IOMMU_CAPABILITIES_IGS_BOTH = 2, 78 RISCV_IOMMU_CAPABILITIES_IGS_RSRV = 3 79 }; 80 81 /* 5.4 Features control register (32bits) */ 82 #define RISCV_IOMMU_REG_FCTL 0x0008 83 #define RISCV_IOMMU_FCTL_BE BIT(0) 84 #define RISCV_IOMMU_FCTL_WSI BIT(1) 85 #define RISCV_IOMMU_FCTL_GXL BIT(2) 86 87 /* 5.5 Device-directory-table pointer (64bits) */ 88 #define RISCV_IOMMU_REG_DDTP 0x0010 89 #define RISCV_IOMMU_DDTP_IOMMU_MODE GENMASK_ULL(3, 0) 90 #define RISCV_IOMMU_DDTP_BUSY BIT_ULL(4) 91 #define RISCV_IOMMU_DDTP_PPN RISCV_IOMMU_PPN_FIELD 92 93 /** 94 * enum riscv_iommu_ddtp_modes - IOMMU translation modes 95 * @RISCV_IOMMU_DDTP_IOMMU_MODE_OFF: No inbound transactions allowed 96 * @RISCV_IOMMU_DDTP_IOMMU_MODE_BARE: Pass-through mode 97 * @RISCV_IOMMU_DDTP_IOMMU_MODE_1LVL: One-level DDT 98 * @RISCV_IOMMU_DDTP_IOMMU_MODE_2LVL: Two-level DDT 99 * @RISCV_IOMMU_DDTP_IOMMU_MODE_3LVL: Three-level DDT 100 * @RISCV_IOMMU_DDTP_IOMMU_MODE_MAX: Max value allowed by specification 101 */ 102 enum riscv_iommu_ddtp_modes { 103 RISCV_IOMMU_DDTP_IOMMU_MODE_OFF = 0, 104 RISCV_IOMMU_DDTP_IOMMU_MODE_BARE = 1, 105 RISCV_IOMMU_DDTP_IOMMU_MODE_1LVL = 2, 106 RISCV_IOMMU_DDTP_IOMMU_MODE_2LVL = 3, 107 RISCV_IOMMU_DDTP_IOMMU_MODE_3LVL = 4, 108 RISCV_IOMMU_DDTP_IOMMU_MODE_MAX = 4 109 }; 110 111 /* 5.6 Command Queue Base (64bits) */ 112 #define RISCV_IOMMU_REG_CQB 0x0018 113 #define RISCV_IOMMU_CQB_ENTRIES RISCV_IOMMU_QUEUE_LOG2SZ_FIELD 114 #define RISCV_IOMMU_CQB_PPN RISCV_IOMMU_PPN_FIELD 115 116 /* 5.7 Command Queue head (32bits) */ 117 #define RISCV_IOMMU_REG_CQH 0x0020 118 #define RISCV_IOMMU_CQH_INDEX RISCV_IOMMU_QUEUE_INDEX_FIELD 119 120 /* 5.8 Command Queue tail (32bits) */ 121 #define RISCV_IOMMU_REG_CQT 0x0024 122 #define RISCV_IOMMU_CQT_INDEX RISCV_IOMMU_QUEUE_INDEX_FIELD 123 124 /* 5.9 Fault Queue Base (64bits) */ 125 #define RISCV_IOMMU_REG_FQB 0x0028 126 #define RISCV_IOMMU_FQB_ENTRIES RISCV_IOMMU_QUEUE_LOG2SZ_FIELD 127 #define RISCV_IOMMU_FQB_PPN RISCV_IOMMU_PPN_FIELD 128 129 /* 5.10 Fault Queue Head (32bits) */ 130 #define RISCV_IOMMU_REG_FQH 0x0030 131 #define RISCV_IOMMU_FQH_INDEX RISCV_IOMMU_QUEUE_INDEX_FIELD 132 133 /* 5.11 Fault Queue tail (32bits) */ 134 #define RISCV_IOMMU_REG_FQT 0x0034 135 #define RISCV_IOMMU_FQT_INDEX RISCV_IOMMU_QUEUE_INDEX_FIELD 136 137 /* 5.12 Page Request Queue base (64bits) */ 138 #define RISCV_IOMMU_REG_PQB 0x0038 139 #define RISCV_IOMMU_PQB_ENTRIES RISCV_IOMMU_QUEUE_LOG2SZ_FIELD 140 #define RISCV_IOMMU_PQB_PPN RISCV_IOMMU_PPN_FIELD 141 142 /* 5.13 Page Request Queue head (32bits) */ 143 #define RISCV_IOMMU_REG_PQH 0x0040 144 #define RISCV_IOMMU_PQH_INDEX RISCV_IOMMU_QUEUE_INDEX_FIELD 145 146 /* 5.14 Page Request Queue tail (32bits) */ 147 #define RISCV_IOMMU_REG_PQT 0x0044 148 #define RISCV_IOMMU_PQT_INDEX_MASK RISCV_IOMMU_QUEUE_INDEX_FIELD 149 150 /* 5.15 Command Queue CSR (32bits) */ 151 #define RISCV_IOMMU_REG_CQCSR 0x0048 152 #define RISCV_IOMMU_CQCSR_CQEN RISCV_IOMMU_QUEUE_ENABLE 153 #define RISCV_IOMMU_CQCSR_CIE RISCV_IOMMU_QUEUE_INTR_ENABLE 154 #define RISCV_IOMMU_CQCSR_CQMF RISCV_IOMMU_QUEUE_MEM_FAULT 155 #define RISCV_IOMMU_CQCSR_CMD_TO BIT(9) 156 #define RISCV_IOMMU_CQCSR_CMD_ILL BIT(10) 157 #define RISCV_IOMMU_CQCSR_FENCE_W_IP BIT(11) 158 #define RISCV_IOMMU_CQCSR_CQON RISCV_IOMMU_QUEUE_ACTIVE 159 #define RISCV_IOMMU_CQCSR_BUSY RISCV_IOMMU_QUEUE_BUSY 160 161 /* 5.16 Fault Queue CSR (32bits) */ 162 #define RISCV_IOMMU_REG_FQCSR 0x004C 163 #define RISCV_IOMMU_FQCSR_FQEN RISCV_IOMMU_QUEUE_ENABLE 164 #define RISCV_IOMMU_FQCSR_FIE RISCV_IOMMU_QUEUE_INTR_ENABLE 165 #define RISCV_IOMMU_FQCSR_FQMF RISCV_IOMMU_QUEUE_MEM_FAULT 166 #define RISCV_IOMMU_FQCSR_FQOF RISCV_IOMMU_QUEUE_OVERFLOW 167 #define RISCV_IOMMU_FQCSR_FQON RISCV_IOMMU_QUEUE_ACTIVE 168 #define RISCV_IOMMU_FQCSR_BUSY RISCV_IOMMU_QUEUE_BUSY 169 170 /* 5.17 Page Request Queue CSR (32bits) */ 171 #define RISCV_IOMMU_REG_PQCSR 0x0050 172 #define RISCV_IOMMU_PQCSR_PQEN RISCV_IOMMU_QUEUE_ENABLE 173 #define RISCV_IOMMU_PQCSR_PIE RISCV_IOMMU_QUEUE_INTR_ENABLE 174 #define RISCV_IOMMU_PQCSR_PQMF RISCV_IOMMU_QUEUE_MEM_FAULT 175 #define RISCV_IOMMU_PQCSR_PQOF RISCV_IOMMU_QUEUE_OVERFLOW 176 #define RISCV_IOMMU_PQCSR_PQON RISCV_IOMMU_QUEUE_ACTIVE 177 #define RISCV_IOMMU_PQCSR_BUSY RISCV_IOMMU_QUEUE_BUSY 178 179 /* 5.18 Interrupt Pending Status (32bits) */ 180 #define RISCV_IOMMU_REG_IPSR 0x0054 181 182 #define RISCV_IOMMU_INTR_CQ 0 183 #define RISCV_IOMMU_INTR_FQ 1 184 #define RISCV_IOMMU_INTR_PM 2 185 #define RISCV_IOMMU_INTR_PQ 3 186 #define RISCV_IOMMU_INTR_COUNT 4 187 188 #define RISCV_IOMMU_IPSR_CIP BIT(RISCV_IOMMU_INTR_CQ) 189 #define RISCV_IOMMU_IPSR_FIP BIT(RISCV_IOMMU_INTR_FQ) 190 #define RISCV_IOMMU_IPSR_PMIP BIT(RISCV_IOMMU_INTR_PM) 191 #define RISCV_IOMMU_IPSR_PIP BIT(RISCV_IOMMU_INTR_PQ) 192 193 /* 5.19 Performance monitoring counter overflow status (32bits) */ 194 #define RISCV_IOMMU_REG_IOCOUNTOVF 0x0058 195 #define RISCV_IOMMU_IOCOUNTOVF_CY BIT(0) 196 #define RISCV_IOMMU_IOCOUNTOVF_HPM GENMASK_ULL(31, 1) 197 198 /* 5.20 Performance monitoring counter inhibits (32bits) */ 199 #define RISCV_IOMMU_REG_IOCOUNTINH 0x005C 200 #define RISCV_IOMMU_IOCOUNTINH_CY BIT(0) 201 #define RISCV_IOMMU_IOCOUNTINH_HPM GENMASK(31, 1) 202 203 /* 5.21 Performance monitoring cycles counter (64bits) */ 204 #define RISCV_IOMMU_REG_IOHPMCYCLES 0x0060 205 #define RISCV_IOMMU_IOHPMCYCLES_COUNTER GENMASK_ULL(62, 0) 206 #define RISCV_IOMMU_IOHPMCYCLES_OF BIT_ULL(63) 207 208 /* 5.22 Performance monitoring event counters (31 * 64bits) */ 209 #define RISCV_IOMMU_REG_IOHPMCTR_BASE 0x0068 210 #define RISCV_IOMMU_REG_IOHPMCTR(_n) (RISCV_IOMMU_REG_IOHPMCTR_BASE + ((_n) * 0x8)) 211 212 /* 5.23 Performance monitoring event selectors (31 * 64bits) */ 213 #define RISCV_IOMMU_REG_IOHPMEVT_BASE 0x0160 214 #define RISCV_IOMMU_REG_IOHPMEVT(_n) (RISCV_IOMMU_REG_IOHPMEVT_BASE + ((_n) * 0x8)) 215 #define RISCV_IOMMU_IOHPMEVT_EVENTID GENMASK_ULL(14, 0) 216 #define RISCV_IOMMU_IOHPMEVT_DMASK BIT_ULL(15) 217 #define RISCV_IOMMU_IOHPMEVT_PID_PSCID GENMASK_ULL(35, 16) 218 #define RISCV_IOMMU_IOHPMEVT_DID_GSCID GENMASK_ULL(59, 36) 219 #define RISCV_IOMMU_IOHPMEVT_PV_PSCV BIT_ULL(60) 220 #define RISCV_IOMMU_IOHPMEVT_DV_GSCV BIT_ULL(61) 221 #define RISCV_IOMMU_IOHPMEVT_IDT BIT_ULL(62) 222 #define RISCV_IOMMU_IOHPMEVT_OF BIT_ULL(63) 223 224 /* Number of defined performance-monitoring event selectors */ 225 #define RISCV_IOMMU_IOHPMEVT_CNT 31 226 227 /** 228 * enum riscv_iommu_hpmevent_id - Performance-monitoring event identifier 229 * 230 * @RISCV_IOMMU_HPMEVENT_INVALID: Invalid event, do not count 231 * @RISCV_IOMMU_HPMEVENT_URQ: Untranslated requests 232 * @RISCV_IOMMU_HPMEVENT_TRQ: Translated requests 233 * @RISCV_IOMMU_HPMEVENT_ATS_RQ: ATS translation requests 234 * @RISCV_IOMMU_HPMEVENT_TLB_MISS: TLB misses 235 * @RISCV_IOMMU_HPMEVENT_DD_WALK: Device directory walks 236 * @RISCV_IOMMU_HPMEVENT_PD_WALK: Process directory walks 237 * @RISCV_IOMMU_HPMEVENT_S_VS_WALKS: First-stage page table walks 238 * @RISCV_IOMMU_HPMEVENT_G_WALKS: Second-stage page table walks 239 * @RISCV_IOMMU_HPMEVENT_MAX: Value to denote maximum Event IDs 240 */ 241 enum riscv_iommu_hpmevent_id { 242 RISCV_IOMMU_HPMEVENT_INVALID = 0, 243 RISCV_IOMMU_HPMEVENT_URQ = 1, 244 RISCV_IOMMU_HPMEVENT_TRQ = 2, 245 RISCV_IOMMU_HPMEVENT_ATS_RQ = 3, 246 RISCV_IOMMU_HPMEVENT_TLB_MISS = 4, 247 RISCV_IOMMU_HPMEVENT_DD_WALK = 5, 248 RISCV_IOMMU_HPMEVENT_PD_WALK = 6, 249 RISCV_IOMMU_HPMEVENT_S_VS_WALKS = 7, 250 RISCV_IOMMU_HPMEVENT_G_WALKS = 8, 251 RISCV_IOMMU_HPMEVENT_MAX = 9 252 }; 253 254 /* 5.24 Translation request IOVA (64bits) */ 255 #define RISCV_IOMMU_REG_TR_REQ_IOVA 0x0258 256 #define RISCV_IOMMU_TR_REQ_IOVA_VPN GENMASK_ULL(63, 12) 257 258 /* 5.25 Translation request control (64bits) */ 259 #define RISCV_IOMMU_REG_TR_REQ_CTL 0x0260 260 #define RISCV_IOMMU_TR_REQ_CTL_GO_BUSY BIT_ULL(0) 261 #define RISCV_IOMMU_TR_REQ_CTL_PRIV BIT_ULL(1) 262 #define RISCV_IOMMU_TR_REQ_CTL_EXE BIT_ULL(2) 263 #define RISCV_IOMMU_TR_REQ_CTL_NW BIT_ULL(3) 264 #define RISCV_IOMMU_TR_REQ_CTL_PID GENMASK_ULL(31, 12) 265 #define RISCV_IOMMU_TR_REQ_CTL_PV BIT_ULL(32) 266 #define RISCV_IOMMU_TR_REQ_CTL_DID GENMASK_ULL(63, 40) 267 268 /* 5.26 Translation request response (64bits) */ 269 #define RISCV_IOMMU_REG_TR_RESPONSE 0x0268 270 #define RISCV_IOMMU_TR_RESPONSE_FAULT BIT_ULL(0) 271 #define RISCV_IOMMU_TR_RESPONSE_PBMT GENMASK_ULL(8, 7) 272 #define RISCV_IOMMU_TR_RESPONSE_SZ BIT_ULL(9) 273 #define RISCV_IOMMU_TR_RESPONSE_PPN RISCV_IOMMU_PPN_FIELD 274 275 /* 5.27 Interrupt cause to vector (64bits) */ 276 #define RISCV_IOMMU_REG_ICVEC 0x02F8 277 #define RISCV_IOMMU_ICVEC_CIV GENMASK_ULL(3, 0) 278 #define RISCV_IOMMU_ICVEC_FIV GENMASK_ULL(7, 4) 279 #define RISCV_IOMMU_ICVEC_PMIV GENMASK_ULL(11, 8) 280 #define RISCV_IOMMU_ICVEC_PIV GENMASK_ULL(15, 12) 281 282 /* 5.28 MSI Configuration table (32 * 64bits) */ 283 #define RISCV_IOMMU_REG_MSI_CFG_TBL 0x0300 284 #define RISCV_IOMMU_REG_MSI_CFG_TBL_ADDR(_n) \ 285 (RISCV_IOMMU_REG_MSI_CFG_TBL + ((_n) * 0x10)) 286 #define RISCV_IOMMU_MSI_CFG_TBL_ADDR GENMASK_ULL(55, 2) 287 #define RISCV_IOMMU_REG_MSI_CFG_TBL_DATA(_n) \ 288 (RISCV_IOMMU_REG_MSI_CFG_TBL + ((_n) * 0x10) + 0x08) 289 #define RISCV_IOMMU_MSI_CFG_TBL_DATA GENMASK_ULL(31, 0) 290 #define RISCV_IOMMU_REG_MSI_CFG_TBL_CTRL(_n) \ 291 (RISCV_IOMMU_REG_MSI_CFG_TBL + ((_n) * 0x10) + 0x0C) 292 #define RISCV_IOMMU_MSI_CFG_TBL_CTRL_M BIT_ULL(0) 293 294 #define RISCV_IOMMU_REG_SIZE 0x1000 295 296 /* 297 * Chapter 2: Data structures 298 */ 299 300 /* 301 * Device Directory Table macros for non-leaf nodes 302 */ 303 #define RISCV_IOMMU_DDTE_V BIT_ULL(0) 304 #define RISCV_IOMMU_DDTE_PPN RISCV_IOMMU_PPN_FIELD 305 306 /** 307 * struct riscv_iommu_dc - Device Context 308 * @tc: Translation Control 309 * @iohgatp: I/O Hypervisor guest address translation and protection 310 * (Second stage context) 311 * @ta: Translation Attributes 312 * @fsc: First stage context 313 * @msiptp: MSI page table pointer 314 * @msi_addr_mask: MSI address mask 315 * @msi_addr_pattern: MSI address pattern 316 * @_reserved: Reserved for future use, padding 317 * 318 * This structure is used for leaf nodes on the Device Directory Table, 319 * in case RISCV_IOMMU_CAPABILITIES_MSI_FLAT is not set, the bottom 4 fields 320 * are not present and are skipped with pointer arithmetic to avoid 321 * casting, check out riscv_iommu_get_dc(). 322 * See section 2.1 for more details 323 */ 324 struct riscv_iommu_dc { 325 u64 tc; 326 u64 iohgatp; 327 u64 ta; 328 u64 fsc; 329 u64 msiptp; 330 u64 msi_addr_mask; 331 u64 msi_addr_pattern; 332 u64 _reserved; 333 }; 334 335 /* Translation control fields */ 336 #define RISCV_IOMMU_DC_TC_V BIT_ULL(0) 337 #define RISCV_IOMMU_DC_TC_EN_ATS BIT_ULL(1) 338 #define RISCV_IOMMU_DC_TC_EN_PRI BIT_ULL(2) 339 #define RISCV_IOMMU_DC_TC_T2GPA BIT_ULL(3) 340 #define RISCV_IOMMU_DC_TC_DTF BIT_ULL(4) 341 #define RISCV_IOMMU_DC_TC_PDTV BIT_ULL(5) 342 #define RISCV_IOMMU_DC_TC_PRPR BIT_ULL(6) 343 #define RISCV_IOMMU_DC_TC_GADE BIT_ULL(7) 344 #define RISCV_IOMMU_DC_TC_SADE BIT_ULL(8) 345 #define RISCV_IOMMU_DC_TC_DPE BIT_ULL(9) 346 #define RISCV_IOMMU_DC_TC_SBE BIT_ULL(10) 347 #define RISCV_IOMMU_DC_TC_SXL BIT_ULL(11) 348 349 /* Second-stage (aka G-stage) context fields */ 350 #define RISCV_IOMMU_DC_IOHGATP_PPN RISCV_IOMMU_ATP_PPN_FIELD 351 #define RISCV_IOMMU_DC_IOHGATP_GSCID GENMASK_ULL(59, 44) 352 #define RISCV_IOMMU_DC_IOHGATP_MODE RISCV_IOMMU_ATP_MODE_FIELD 353 354 /** 355 * enum riscv_iommu_dc_iohgatp_modes - Guest address translation/protection modes 356 * @RISCV_IOMMU_DC_IOHGATP_MODE_BARE: No translation/protection 357 * @RISCV_IOMMU_DC_IOHGATP_MODE_SV32X4: Sv32x4 (2-bit extension of Sv32), when fctl.GXL == 1 358 * @RISCV_IOMMU_DC_IOHGATP_MODE_SV39X4: Sv39x4 (2-bit extension of Sv39), when fctl.GXL == 0 359 * @RISCV_IOMMU_DC_IOHGATP_MODE_SV48X4: Sv48x4 (2-bit extension of Sv48), when fctl.GXL == 0 360 * @RISCV_IOMMU_DC_IOHGATP_MODE_SV57X4: Sv57x4 (2-bit extension of Sv57), when fctl.GXL == 0 361 */ 362 enum riscv_iommu_dc_iohgatp_modes { 363 RISCV_IOMMU_DC_IOHGATP_MODE_BARE = 0, 364 RISCV_IOMMU_DC_IOHGATP_MODE_SV32X4 = 8, 365 RISCV_IOMMU_DC_IOHGATP_MODE_SV39X4 = 8, 366 RISCV_IOMMU_DC_IOHGATP_MODE_SV48X4 = 9, 367 RISCV_IOMMU_DC_IOHGATP_MODE_SV57X4 = 10 368 }; 369 370 /* Translation attributes fields */ 371 #define RISCV_IOMMU_DC_TA_PSCID GENMASK_ULL(31, 12) 372 373 /* First-stage context fields */ 374 #define RISCV_IOMMU_DC_FSC_PPN RISCV_IOMMU_ATP_PPN_FIELD 375 #define RISCV_IOMMU_DC_FSC_MODE RISCV_IOMMU_ATP_MODE_FIELD 376 377 /** 378 * enum riscv_iommu_dc_fsc_atp_modes - First stage address translation/protection modes 379 * @RISCV_IOMMU_DC_FSC_MODE_BARE: No translation/protection 380 * @RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV32: Sv32, when dc.tc.SXL == 1 381 * @RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV39: Sv39, when dc.tc.SXL == 0 382 * @RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV48: Sv48, when dc.tc.SXL == 0 383 * @RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV57: Sv57, when dc.tc.SXL == 0 384 * @RISCV_IOMMU_DC_FSC_PDTP_MODE_PD8: 1lvl PDT, 8bit process ids 385 * @RISCV_IOMMU_DC_FSC_PDTP_MODE_PD17: 2lvl PDT, 17bit process ids 386 * @RISCV_IOMMU_DC_FSC_PDTP_MODE_PD20: 3lvl PDT, 20bit process ids 387 * 388 * FSC holds IOSATP when RISCV_IOMMU_DC_TC_PDTV is 0 and PDTP otherwise. 389 * IOSATP controls the first stage address translation (same as the satp register on 390 * the RISC-V MMU), and PDTP holds the process directory table, used to select a 391 * first stage page table based on a process id (for devices that support multiple 392 * process ids). 393 */ 394 enum riscv_iommu_dc_fsc_atp_modes { 395 RISCV_IOMMU_DC_FSC_MODE_BARE = 0, 396 RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV32 = 8, 397 RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV39 = 8, 398 RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV48 = 9, 399 RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV57 = 10, 400 RISCV_IOMMU_DC_FSC_PDTP_MODE_PD8 = 1, 401 RISCV_IOMMU_DC_FSC_PDTP_MODE_PD17 = 2, 402 RISCV_IOMMU_DC_FSC_PDTP_MODE_PD20 = 3 403 }; 404 405 /* MSI page table pointer */ 406 #define RISCV_IOMMU_DC_MSIPTP_PPN RISCV_IOMMU_ATP_PPN_FIELD 407 #define RISCV_IOMMU_DC_MSIPTP_MODE RISCV_IOMMU_ATP_MODE_FIELD 408 #define RISCV_IOMMU_DC_MSIPTP_MODE_OFF 0 409 #define RISCV_IOMMU_DC_MSIPTP_MODE_FLAT 1 410 411 /* MSI address mask */ 412 #define RISCV_IOMMU_DC_MSI_ADDR_MASK GENMASK_ULL(51, 0) 413 414 /* MSI address pattern */ 415 #define RISCV_IOMMU_DC_MSI_PATTERN GENMASK_ULL(51, 0) 416 417 /** 418 * struct riscv_iommu_pc - Process Context 419 * @ta: Translation Attributes 420 * @fsc: First stage context 421 * 422 * This structure is used for leaf nodes on the Process Directory Table 423 * See section 2.3 for more details 424 */ 425 struct riscv_iommu_pc { 426 u64 ta; 427 u64 fsc; 428 }; 429 430 /* Translation attributes fields */ 431 #define RISCV_IOMMU_PC_TA_V BIT_ULL(0) 432 #define RISCV_IOMMU_PC_TA_ENS BIT_ULL(1) 433 #define RISCV_IOMMU_PC_TA_SUM BIT_ULL(2) 434 #define RISCV_IOMMU_PC_TA_PSCID GENMASK_ULL(31, 12) 435 436 /* First stage context fields */ 437 #define RISCV_IOMMU_PC_FSC_PPN RISCV_IOMMU_ATP_PPN_FIELD 438 #define RISCV_IOMMU_PC_FSC_MODE RISCV_IOMMU_ATP_MODE_FIELD 439 440 /* 441 * Chapter 3: In-memory queue interface 442 */ 443 444 /** 445 * struct riscv_iommu_command - Generic IOMMU command structure 446 * @dword0: Includes the opcode and the function identifier 447 * @dword1: Opcode specific data 448 * 449 * The commands are interpreted as two 64bit fields, where the first 450 * 7bits of the first field are the opcode which also defines the 451 * command's format, followed by a 3bit field that specifies the 452 * function invoked by that command, and the rest is opcode-specific. 453 * This is a generic struct which will be populated differently 454 * according to each command. For more infos on the commands and 455 * the command queue check section 3.1. 456 */ 457 struct riscv_iommu_command { 458 u64 dword0; 459 u64 dword1; 460 }; 461 462 /* Fields on dword0, common for all commands */ 463 #define RISCV_IOMMU_CMD_OPCODE GENMASK_ULL(6, 0) 464 #define RISCV_IOMMU_CMD_FUNC GENMASK_ULL(9, 7) 465 466 /* 3.1.1 IOMMU Page-table cache invalidation */ 467 /* Fields on dword0 */ 468 #define RISCV_IOMMU_CMD_IOTINVAL_OPCODE 1 469 #define RISCV_IOMMU_CMD_IOTINVAL_FUNC_VMA 0 470 #define RISCV_IOMMU_CMD_IOTINVAL_FUNC_GVMA 1 471 #define RISCV_IOMMU_CMD_IOTINVAL_AV BIT_ULL(10) 472 #define RISCV_IOMMU_CMD_IOTINVAL_PSCID GENMASK_ULL(31, 12) 473 #define RISCV_IOMMU_CMD_IOTINVAL_PSCV BIT_ULL(32) 474 #define RISCV_IOMMU_CMD_IOTINVAL_GV BIT_ULL(33) 475 #define RISCV_IOMMU_CMD_IOTINVAL_GSCID GENMASK_ULL(59, 44) 476 /* dword1[61:10] is the 4K-aligned page address */ 477 #define RISCV_IOMMU_CMD_IOTINVAL_ADDR GENMASK_ULL(61, 10) 478 479 /* 3.1.2 IOMMU Command Queue Fences */ 480 /* Fields on dword0 */ 481 #define RISCV_IOMMU_CMD_IOFENCE_OPCODE 2 482 #define RISCV_IOMMU_CMD_IOFENCE_FUNC_C 0 483 #define RISCV_IOMMU_CMD_IOFENCE_AV BIT_ULL(10) 484 #define RISCV_IOMMU_CMD_IOFENCE_WSI BIT_ULL(11) 485 #define RISCV_IOMMU_CMD_IOFENCE_PR BIT_ULL(12) 486 #define RISCV_IOMMU_CMD_IOFENCE_PW BIT_ULL(13) 487 #define RISCV_IOMMU_CMD_IOFENCE_DATA GENMASK_ULL(63, 32) 488 /* dword1 is the address, word-size aligned and shifted to the right by two bits. */ 489 490 /* 3.1.3 IOMMU Directory cache invalidation */ 491 /* Fields on dword0 */ 492 #define RISCV_IOMMU_CMD_IODIR_OPCODE 3 493 #define RISCV_IOMMU_CMD_IODIR_FUNC_INVAL_DDT 0 494 #define RISCV_IOMMU_CMD_IODIR_FUNC_INVAL_PDT 1 495 #define RISCV_IOMMU_CMD_IODIR_PID GENMASK_ULL(31, 12) 496 #define RISCV_IOMMU_CMD_IODIR_DV BIT_ULL(33) 497 #define RISCV_IOMMU_CMD_IODIR_DID GENMASK_ULL(63, 40) 498 /* dword1 is reserved for standard use */ 499 500 /* 3.1.4 IOMMU PCIe ATS */ 501 /* Fields on dword0 */ 502 #define RISCV_IOMMU_CMD_ATS_OPCODE 4 503 #define RISCV_IOMMU_CMD_ATS_FUNC_INVAL 0 504 #define RISCV_IOMMU_CMD_ATS_FUNC_PRGR 1 505 #define RISCV_IOMMU_CMD_ATS_PID GENMASK_ULL(31, 12) 506 #define RISCV_IOMMU_CMD_ATS_PV BIT_ULL(32) 507 #define RISCV_IOMMU_CMD_ATS_DSV BIT_ULL(33) 508 #define RISCV_IOMMU_CMD_ATS_RID GENMASK_ULL(55, 40) 509 #define RISCV_IOMMU_CMD_ATS_DSEG GENMASK_ULL(63, 56) 510 /* dword1 is the ATS payload, two different payload types for INVAL and PRGR */ 511 512 /* ATS.INVAL payload*/ 513 #define RISCV_IOMMU_CMD_ATS_INVAL_G BIT_ULL(0) 514 /* Bits 1 - 10 are zeroed */ 515 #define RISCV_IOMMU_CMD_ATS_INVAL_S BIT_ULL(11) 516 #define RISCV_IOMMU_CMD_ATS_INVAL_UADDR GENMASK_ULL(63, 12) 517 518 /* ATS.PRGR payload */ 519 /* Bits 0 - 31 are zeroed */ 520 #define RISCV_IOMMU_CMD_ATS_PRGR_PRG_INDEX GENMASK_ULL(40, 32) 521 /* Bits 41 - 43 are zeroed */ 522 #define RISCV_IOMMU_CMD_ATS_PRGR_RESP_CODE GENMASK_ULL(47, 44) 523 #define RISCV_IOMMU_CMD_ATS_PRGR_DST_ID GENMASK_ULL(63, 48) 524 525 /** 526 * struct riscv_iommu_fq_record - Fault/Event Queue Record 527 * @hdr: Header, includes fault/event cause, PID/DID, transaction type etc 528 * @_reserved: Low 32bits for custom use, high 32bits for standard use 529 * @iotval: Transaction-type/cause specific format 530 * @iotval2: Cause specific format 531 * 532 * The fault/event queue reports events and failures raised when 533 * processing transactions. Each record is a 32byte structure where 534 * the first dword has a fixed format for providing generic infos 535 * regarding the fault/event, and two more dwords are there for 536 * fault/event-specific information. For more details see section 537 * 3.2. 538 */ 539 struct riscv_iommu_fq_record { 540 u64 hdr; 541 u64 _reserved; 542 u64 iotval; 543 u64 iotval2; 544 }; 545 546 /* Fields on header */ 547 #define RISCV_IOMMU_FQ_HDR_CAUSE GENMASK_ULL(11, 0) 548 #define RISCV_IOMMU_FQ_HDR_PID GENMASK_ULL(31, 12) 549 #define RISCV_IOMMU_FQ_HDR_PV BIT_ULL(32) 550 #define RISCV_IOMMU_FQ_HDR_PRIV BIT_ULL(33) 551 #define RISCV_IOMMU_FQ_HDR_TTYP GENMASK_ULL(39, 34) 552 #define RISCV_IOMMU_FQ_HDR_DID GENMASK_ULL(63, 40) 553 554 /** 555 * enum riscv_iommu_fq_causes - Fault/event cause values 556 * @RISCV_IOMMU_FQ_CAUSE_INST_FAULT: Instruction access fault 557 * @RISCV_IOMMU_FQ_CAUSE_RD_ADDR_MISALIGNED: Read address misaligned 558 * @RISCV_IOMMU_FQ_CAUSE_RD_FAULT: Read load fault 559 * @RISCV_IOMMU_FQ_CAUSE_WR_ADDR_MISALIGNED: Write/AMO address misaligned 560 * @RISCV_IOMMU_FQ_CAUSE_WR_FAULT: Write/AMO access fault 561 * @RISCV_IOMMU_FQ_CAUSE_INST_FAULT_S: Instruction page fault 562 * @RISCV_IOMMU_FQ_CAUSE_RD_FAULT_S: Read page fault 563 * @RISCV_IOMMU_FQ_CAUSE_WR_FAULT_S: Write/AMO page fault 564 * @RISCV_IOMMU_FQ_CAUSE_INST_FAULT_VS: Instruction guest page fault 565 * @RISCV_IOMMU_FQ_CAUSE_RD_FAULT_VS: Read guest page fault 566 * @RISCV_IOMMU_FQ_CAUSE_WR_FAULT_VS: Write/AMO guest page fault 567 * @RISCV_IOMMU_FQ_CAUSE_DMA_DISABLED: All inbound transactions disallowed 568 * @RISCV_IOMMU_FQ_CAUSE_DDT_LOAD_FAULT: DDT entry load access fault 569 * @RISCV_IOMMU_FQ_CAUSE_DDT_INVALID: DDT entry invalid 570 * @RISCV_IOMMU_FQ_CAUSE_DDT_MISCONFIGURED: DDT entry misconfigured 571 * @RISCV_IOMMU_FQ_CAUSE_TTYP_BLOCKED: Transaction type disallowed 572 * @RISCV_IOMMU_FQ_CAUSE_MSI_LOAD_FAULT: MSI PTE load access fault 573 * @RISCV_IOMMU_FQ_CAUSE_MSI_INVALID: MSI PTE invalid 574 * @RISCV_IOMMU_FQ_CAUSE_MSI_MISCONFIGURED: MSI PTE misconfigured 575 * @RISCV_IOMMU_FQ_CAUSE_MRIF_FAULT: MRIF access fault 576 * @RISCV_IOMMU_FQ_CAUSE_PDT_LOAD_FAULT: PDT entry load access fault 577 * @RISCV_IOMMU_FQ_CAUSE_PDT_INVALID: PDT entry invalid 578 * @RISCV_IOMMU_FQ_CAUSE_PDT_MISCONFIGURED: PDT entry misconfigured 579 * @RISCV_IOMMU_FQ_CAUSE_DDT_CORRUPTED: DDT data corruption 580 * @RISCV_IOMMU_FQ_CAUSE_PDT_CORRUPTED: PDT data corruption 581 * @RISCV_IOMMU_FQ_CAUSE_MSI_PT_CORRUPTED: MSI page table data corruption 582 * @RISCV_IOMMU_FQ_CAUSE_MRIF_CORRUIPTED: MRIF data corruption 583 * @RISCV_IOMMU_FQ_CAUSE_INTERNAL_DP_ERROR: Internal data path error 584 * @RISCV_IOMMU_FQ_CAUSE_MSI_WR_FAULT: IOMMU MSI write access fault 585 * @RISCV_IOMMU_FQ_CAUSE_PT_CORRUPTED: First/second stage page table data corruption 586 * 587 * Values are on table 11 of the spec, encodings 275 - 2047 are reserved for standard 588 * use, and 2048 - 4095 for custom use. 589 */ 590 enum riscv_iommu_fq_causes { 591 RISCV_IOMMU_FQ_CAUSE_INST_FAULT = 1, 592 RISCV_IOMMU_FQ_CAUSE_RD_ADDR_MISALIGNED = 4, 593 RISCV_IOMMU_FQ_CAUSE_RD_FAULT = 5, 594 RISCV_IOMMU_FQ_CAUSE_WR_ADDR_MISALIGNED = 6, 595 RISCV_IOMMU_FQ_CAUSE_WR_FAULT = 7, 596 RISCV_IOMMU_FQ_CAUSE_INST_FAULT_S = 12, 597 RISCV_IOMMU_FQ_CAUSE_RD_FAULT_S = 13, 598 RISCV_IOMMU_FQ_CAUSE_WR_FAULT_S = 15, 599 RISCV_IOMMU_FQ_CAUSE_INST_FAULT_VS = 20, 600 RISCV_IOMMU_FQ_CAUSE_RD_FAULT_VS = 21, 601 RISCV_IOMMU_FQ_CAUSE_WR_FAULT_VS = 23, 602 RISCV_IOMMU_FQ_CAUSE_DMA_DISABLED = 256, 603 RISCV_IOMMU_FQ_CAUSE_DDT_LOAD_FAULT = 257, 604 RISCV_IOMMU_FQ_CAUSE_DDT_INVALID = 258, 605 RISCV_IOMMU_FQ_CAUSE_DDT_MISCONFIGURED = 259, 606 RISCV_IOMMU_FQ_CAUSE_TTYP_BLOCKED = 260, 607 RISCV_IOMMU_FQ_CAUSE_MSI_LOAD_FAULT = 261, 608 RISCV_IOMMU_FQ_CAUSE_MSI_INVALID = 262, 609 RISCV_IOMMU_FQ_CAUSE_MSI_MISCONFIGURED = 263, 610 RISCV_IOMMU_FQ_CAUSE_MRIF_FAULT = 264, 611 RISCV_IOMMU_FQ_CAUSE_PDT_LOAD_FAULT = 265, 612 RISCV_IOMMU_FQ_CAUSE_PDT_INVALID = 266, 613 RISCV_IOMMU_FQ_CAUSE_PDT_MISCONFIGURED = 267, 614 RISCV_IOMMU_FQ_CAUSE_DDT_CORRUPTED = 268, 615 RISCV_IOMMU_FQ_CAUSE_PDT_CORRUPTED = 269, 616 RISCV_IOMMU_FQ_CAUSE_MSI_PT_CORRUPTED = 270, 617 RISCV_IOMMU_FQ_CAUSE_MRIF_CORRUIPTED = 271, 618 RISCV_IOMMU_FQ_CAUSE_INTERNAL_DP_ERROR = 272, 619 RISCV_IOMMU_FQ_CAUSE_MSI_WR_FAULT = 273, 620 RISCV_IOMMU_FQ_CAUSE_PT_CORRUPTED = 274 621 }; 622 623 /** 624 * enum riscv_iommu_fq_ttypes: Fault/event transaction types 625 * @RISCV_IOMMU_FQ_TTYP_NONE: None. Fault not caused by an inbound transaction. 626 * @RISCV_IOMMU_FQ_TTYP_UADDR_INST_FETCH: Instruction fetch from untranslated address 627 * @RISCV_IOMMU_FQ_TTYP_UADDR_RD: Read from untranslated address 628 * @RISCV_IOMMU_FQ_TTYP_UADDR_WR: Write/AMO to untranslated address 629 * @RISCV_IOMMU_FQ_TTYP_TADDR_INST_FETCH: Instruction fetch from translated address 630 * @RISCV_IOMMU_FQ_TTYP_TADDR_RD: Read from translated address 631 * @RISCV_IOMMU_FQ_TTYP_TADDR_WR: Write/AMO to translated address 632 * @RISCV_IOMMU_FQ_TTYP_PCIE_ATS_REQ: PCIe ATS translation request 633 * @RISCV_IOMMU_FQ_TTYP_PCIE_MSG_REQ: PCIe message request 634 * 635 * Values are on table 12 of the spec, type 4 and 10 - 31 are reserved for standard use 636 * and 31 - 63 for custom use. 637 */ 638 enum riscv_iommu_fq_ttypes { 639 RISCV_IOMMU_FQ_TTYP_NONE = 0, 640 RISCV_IOMMU_FQ_TTYP_UADDR_INST_FETCH = 1, 641 RISCV_IOMMU_FQ_TTYP_UADDR_RD = 2, 642 RISCV_IOMMU_FQ_TTYP_UADDR_WR = 3, 643 RISCV_IOMMU_FQ_TTYP_TADDR_INST_FETCH = 5, 644 RISCV_IOMMU_FQ_TTYP_TADDR_RD = 6, 645 RISCV_IOMMU_FQ_TTYP_TADDR_WR = 7, 646 RISCV_IOMMU_FQ_TTYP_PCIE_ATS_REQ = 8, 647 RISCV_IOMMU_FQ_TTYP_PCIE_MSG_REQ = 9, 648 }; 649 650 /** 651 * struct riscv_iommu_pq_record - PCIe Page Request record 652 * @hdr: Header, includes PID, DID etc 653 * @payload: Holds the page address, request group and permission bits 654 * 655 * For more infos on the PCIe Page Request queue see chapter 3.3. 656 */ 657 struct riscv_iommu_pq_record { 658 u64 hdr; 659 u64 payload; 660 }; 661 662 /* Header fields */ 663 #define RISCV_IOMMU_PQ_HDR_PID GENMASK_ULL(31, 12) 664 #define RISCV_IOMMU_PQ_HDR_PV BIT_ULL(32) 665 #define RISCV_IOMMU_PQ_HDR_PRIV BIT_ULL(33) 666 #define RISCV_IOMMU_PQ_HDR_EXEC BIT_ULL(34) 667 #define RISCV_IOMMU_PQ_HDR_DID GENMASK_ULL(63, 40) 668 669 /* Payload fields */ 670 #define RISCV_IOMMU_PQ_PAYLOAD_R BIT_ULL(0) 671 #define RISCV_IOMMU_PQ_PAYLOAD_W BIT_ULL(1) 672 #define RISCV_IOMMU_PQ_PAYLOAD_L BIT_ULL(2) 673 #define RISCV_IOMMU_PQ_PAYLOAD_RWL_MASK GENMASK_ULL(2, 0) 674 #define RISCV_IOMMU_PQ_PAYLOAD_PRGI GENMASK_ULL(11, 3) /* Page Request Group Index */ 675 #define RISCV_IOMMU_PQ_PAYLOAD_ADDR GENMASK_ULL(63, 12) 676 677 /** 678 * struct riscv_iommu_msipte - MSI Page Table Entry 679 * @pte: MSI PTE 680 * @mrif_info: Memory-resident interrupt file info 681 * 682 * The MSI Page Table is used for virtualizing MSIs, so that when 683 * a device sends an MSI to a guest, the IOMMU can reroute it 684 * by translating the MSI address, either to a guest interrupt file 685 * or a memory resident interrupt file (MRIF). Note that this page table 686 * is an array of MSI PTEs, not a multi-level pt, each entry 687 * is a leaf entry. For more infos check out the AIA spec, chapter 9.5. 688 * 689 * Also in basic mode the mrif_info field is ignored by the IOMMU and can 690 * be used by software, any other reserved fields on pte must be zeroed-out 691 * by software. 692 */ 693 struct riscv_iommu_msipte { 694 u64 pte; 695 u64 mrif_info; 696 }; 697 698 /* Fields on pte */ 699 #define RISCV_IOMMU_MSIPTE_V BIT_ULL(0) 700 #define RISCV_IOMMU_MSIPTE_M GENMASK_ULL(2, 1) 701 #define RISCV_IOMMU_MSIPTE_MRIF_ADDR GENMASK_ULL(53, 7) /* When M == 1 (MRIF mode) */ 702 #define RISCV_IOMMU_MSIPTE_PPN RISCV_IOMMU_PPN_FIELD /* When M == 3 (basic mode) */ 703 #define RISCV_IOMMU_MSIPTE_C BIT_ULL(63) 704 705 /* Fields on mrif_info */ 706 #define RISCV_IOMMU_MSIPTE_MRIF_NID GENMASK_ULL(9, 0) 707 #define RISCV_IOMMU_MSIPTE_MRIF_NPPN RISCV_IOMMU_PPN_FIELD 708 #define RISCV_IOMMU_MSIPTE_MRIF_NID_MSB BIT_ULL(60) 709 710 /* Helper functions: command structure builders. */ 711 712 static inline void riscv_iommu_cmd_inval_vma(struct riscv_iommu_command *cmd) 713 { 714 cmd->dword0 = FIELD_PREP(RISCV_IOMMU_CMD_OPCODE, RISCV_IOMMU_CMD_IOTINVAL_OPCODE) | 715 FIELD_PREP(RISCV_IOMMU_CMD_FUNC, RISCV_IOMMU_CMD_IOTINVAL_FUNC_VMA); 716 cmd->dword1 = 0; 717 } 718 719 static inline void riscv_iommu_cmd_inval_set_addr(struct riscv_iommu_command *cmd, 720 u64 addr) 721 { 722 cmd->dword1 = 723 FIELD_PREP(RISCV_IOMMU_CMD_IOTINVAL_ADDR, PHYS_PFN(addr)); 724 cmd->dword0 |= RISCV_IOMMU_CMD_IOTINVAL_AV; 725 } 726 727 static inline void riscv_iommu_cmd_inval_set_pscid(struct riscv_iommu_command *cmd, 728 int pscid) 729 { 730 cmd->dword0 |= FIELD_PREP(RISCV_IOMMU_CMD_IOTINVAL_PSCID, pscid) | 731 RISCV_IOMMU_CMD_IOTINVAL_PSCV; 732 } 733 734 static inline void riscv_iommu_cmd_inval_set_gscid(struct riscv_iommu_command *cmd, 735 int gscid) 736 { 737 cmd->dword0 |= FIELD_PREP(RISCV_IOMMU_CMD_IOTINVAL_GSCID, gscid) | 738 RISCV_IOMMU_CMD_IOTINVAL_GV; 739 } 740 741 static inline void riscv_iommu_cmd_iofence(struct riscv_iommu_command *cmd) 742 { 743 cmd->dword0 = FIELD_PREP(RISCV_IOMMU_CMD_OPCODE, RISCV_IOMMU_CMD_IOFENCE_OPCODE) | 744 FIELD_PREP(RISCV_IOMMU_CMD_FUNC, RISCV_IOMMU_CMD_IOFENCE_FUNC_C) | 745 RISCV_IOMMU_CMD_IOFENCE_PR | RISCV_IOMMU_CMD_IOFENCE_PW; 746 cmd->dword1 = 0; 747 } 748 749 static inline void riscv_iommu_cmd_iofence_set_av(struct riscv_iommu_command *cmd, 750 u64 addr, u32 data) 751 { 752 cmd->dword0 = FIELD_PREP(RISCV_IOMMU_CMD_OPCODE, RISCV_IOMMU_CMD_IOFENCE_OPCODE) | 753 FIELD_PREP(RISCV_IOMMU_CMD_FUNC, RISCV_IOMMU_CMD_IOFENCE_FUNC_C) | 754 FIELD_PREP(RISCV_IOMMU_CMD_IOFENCE_DATA, data) | 755 RISCV_IOMMU_CMD_IOFENCE_AV; 756 cmd->dword1 = addr >> 2; 757 } 758 759 static inline void riscv_iommu_cmd_iodir_inval_ddt(struct riscv_iommu_command *cmd) 760 { 761 cmd->dword0 = FIELD_PREP(RISCV_IOMMU_CMD_OPCODE, RISCV_IOMMU_CMD_IODIR_OPCODE) | 762 FIELD_PREP(RISCV_IOMMU_CMD_FUNC, RISCV_IOMMU_CMD_IODIR_FUNC_INVAL_DDT); 763 cmd->dword1 = 0; 764 } 765 766 static inline void riscv_iommu_cmd_iodir_inval_pdt(struct riscv_iommu_command *cmd) 767 { 768 cmd->dword0 = FIELD_PREP(RISCV_IOMMU_CMD_OPCODE, RISCV_IOMMU_CMD_IODIR_OPCODE) | 769 FIELD_PREP(RISCV_IOMMU_CMD_FUNC, RISCV_IOMMU_CMD_IODIR_FUNC_INVAL_PDT); 770 cmd->dword1 = 0; 771 } 772 773 static inline void riscv_iommu_cmd_iodir_set_did(struct riscv_iommu_command *cmd, 774 unsigned int devid) 775 { 776 cmd->dword0 |= FIELD_PREP(RISCV_IOMMU_CMD_IODIR_DID, devid) | 777 RISCV_IOMMU_CMD_IODIR_DV; 778 } 779 780 static inline void riscv_iommu_cmd_iodir_set_pid(struct riscv_iommu_command *cmd, 781 unsigned int pasid) 782 { 783 cmd->dword0 |= FIELD_PREP(RISCV_IOMMU_CMD_IODIR_PID, pasid); 784 } 785 786 #endif /* _RISCV_IOMMU_BITS_H_ */ 787