1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright © 2022-2024 Rivos Inc. 4 * Copyright © 2023 FORTH-ICS/CARV 5 * Copyright © 2023 RISC-V IOMMU Task Group 6 * 7 * RISC-V IOMMU - Register Layout and Data Structures. 8 * 9 * Based on the 'RISC-V IOMMU Architecture Specification', Version 1.0 10 * Published at https://github.com/riscv-non-isa/riscv-iommu 11 * 12 */ 13 14 #ifndef _RISCV_IOMMU_BITS_H_ 15 #define _RISCV_IOMMU_BITS_H_ 16 17 #include <linux/types.h> 18 #include <linux/bitfield.h> 19 #include <linux/bits.h> 20 21 /* 22 * Chapter 5: Memory Mapped register interface 23 */ 24 25 /* Common field positions */ 26 #define RISCV_IOMMU_PPN_FIELD GENMASK_ULL(53, 10) 27 #define RISCV_IOMMU_QUEUE_LOG2SZ_FIELD GENMASK_ULL(4, 0) 28 #define RISCV_IOMMU_QUEUE_INDEX_FIELD GENMASK_ULL(31, 0) 29 #define RISCV_IOMMU_QUEUE_ENABLE BIT(0) 30 #define RISCV_IOMMU_QUEUE_INTR_ENABLE BIT(1) 31 #define RISCV_IOMMU_QUEUE_MEM_FAULT BIT(8) 32 #define RISCV_IOMMU_QUEUE_OVERFLOW BIT(9) 33 #define RISCV_IOMMU_QUEUE_ACTIVE BIT(16) 34 #define RISCV_IOMMU_QUEUE_BUSY BIT(17) 35 36 #define RISCV_IOMMU_ATP_PPN_FIELD GENMASK_ULL(43, 0) 37 #define RISCV_IOMMU_ATP_MODE_FIELD GENMASK_ULL(63, 60) 38 39 /* 5.3 IOMMU Capabilities (64bits) */ 40 #define RISCV_IOMMU_REG_CAPABILITIES 0x0000 41 #define RISCV_IOMMU_CAPABILITIES_VERSION GENMASK_ULL(7, 0) 42 #define RISCV_IOMMU_CAPABILITIES_SV32 BIT_ULL(8) 43 #define RISCV_IOMMU_CAPABILITIES_SV39 BIT_ULL(9) 44 #define RISCV_IOMMU_CAPABILITIES_SV48 BIT_ULL(10) 45 #define RISCV_IOMMU_CAPABILITIES_SV57 BIT_ULL(11) 46 #define RISCV_IOMMU_CAPABILITIES_SVPBMT BIT_ULL(15) 47 #define RISCV_IOMMU_CAPABILITIES_SV32X4 BIT_ULL(16) 48 #define RISCV_IOMMU_CAPABILITIES_SV39X4 BIT_ULL(17) 49 #define RISCV_IOMMU_CAPABILITIES_SV48X4 BIT_ULL(18) 50 #define RISCV_IOMMU_CAPABILITIES_SV57X4 BIT_ULL(19) 51 #define RISCV_IOMMU_CAPABILITIES_AMO_MRIF BIT_ULL(21) 52 #define RISCV_IOMMU_CAPABILITIES_MSI_FLAT BIT_ULL(22) 53 #define RISCV_IOMMU_CAPABILITIES_MSI_MRIF BIT_ULL(23) 54 #define RISCV_IOMMU_CAPABILITIES_AMO_HWAD BIT_ULL(24) 55 #define RISCV_IOMMU_CAPABILITIES_ATS BIT_ULL(25) 56 #define RISCV_IOMMU_CAPABILITIES_T2GPA BIT_ULL(26) 57 #define RISCV_IOMMU_CAPABILITIES_END BIT_ULL(27) 58 #define RISCV_IOMMU_CAPABILITIES_IGS GENMASK_ULL(29, 28) 59 #define RISCV_IOMMU_CAPABILITIES_HPM BIT_ULL(30) 60 #define RISCV_IOMMU_CAPABILITIES_DBG BIT_ULL(31) 61 #define RISCV_IOMMU_CAPABILITIES_PAS GENMASK_ULL(37, 32) 62 #define RISCV_IOMMU_CAPABILITIES_PD8 BIT_ULL(38) 63 #define RISCV_IOMMU_CAPABILITIES_PD17 BIT_ULL(39) 64 #define RISCV_IOMMU_CAPABILITIES_PD20 BIT_ULL(40) 65 66 /** 67 * enum riscv_iommu_igs_settings - Interrupt Generation Support Settings 68 * @RISCV_IOMMU_CAPABILITIES_IGS_MSI: IOMMU supports only MSI generation 69 * @RISCV_IOMMU_CAPABILITIES_IGS_WSI: IOMMU supports only Wired-Signaled interrupt 70 * @RISCV_IOMMU_CAPABILITIES_IGS_BOTH: IOMMU supports both MSI and WSI generation 71 * @RISCV_IOMMU_CAPABILITIES_IGS_RSRV: Reserved for standard use 72 */ 73 enum riscv_iommu_igs_settings { 74 RISCV_IOMMU_CAPABILITIES_IGS_MSI = 0, 75 RISCV_IOMMU_CAPABILITIES_IGS_WSI = 1, 76 RISCV_IOMMU_CAPABILITIES_IGS_BOTH = 2, 77 RISCV_IOMMU_CAPABILITIES_IGS_RSRV = 3 78 }; 79 80 /* 5.4 Features control register (32bits) */ 81 #define RISCV_IOMMU_REG_FCTL 0x0008 82 #define RISCV_IOMMU_FCTL_BE BIT(0) 83 #define RISCV_IOMMU_FCTL_WSI BIT(1) 84 #define RISCV_IOMMU_FCTL_GXL BIT(2) 85 86 /* 5.5 Device-directory-table pointer (64bits) */ 87 #define RISCV_IOMMU_REG_DDTP 0x0010 88 #define RISCV_IOMMU_DDTP_IOMMU_MODE GENMASK_ULL(3, 0) 89 #define RISCV_IOMMU_DDTP_BUSY BIT_ULL(4) 90 #define RISCV_IOMMU_DDTP_PPN RISCV_IOMMU_PPN_FIELD 91 92 /** 93 * enum riscv_iommu_ddtp_modes - IOMMU translation modes 94 * @RISCV_IOMMU_DDTP_IOMMU_MODE_OFF: No inbound transactions allowed 95 * @RISCV_IOMMU_DDTP_IOMMU_MODE_BARE: Pass-through mode 96 * @RISCV_IOMMU_DDTP_IOMMU_MODE_1LVL: One-level DDT 97 * @RISCV_IOMMU_DDTP_IOMMU_MODE_2LVL: Two-level DDT 98 * @RISCV_IOMMU_DDTP_IOMMU_MODE_3LVL: Three-level DDT 99 * @RISCV_IOMMU_DDTP_IOMMU_MODE_MAX: Max value allowed by specification 100 */ 101 enum riscv_iommu_ddtp_modes { 102 RISCV_IOMMU_DDTP_IOMMU_MODE_OFF = 0, 103 RISCV_IOMMU_DDTP_IOMMU_MODE_BARE = 1, 104 RISCV_IOMMU_DDTP_IOMMU_MODE_1LVL = 2, 105 RISCV_IOMMU_DDTP_IOMMU_MODE_2LVL = 3, 106 RISCV_IOMMU_DDTP_IOMMU_MODE_3LVL = 4, 107 RISCV_IOMMU_DDTP_IOMMU_MODE_MAX = 4 108 }; 109 110 /* 5.6 Command Queue Base (64bits) */ 111 #define RISCV_IOMMU_REG_CQB 0x0018 112 #define RISCV_IOMMU_CQB_ENTRIES RISCV_IOMMU_QUEUE_LOG2SZ_FIELD 113 #define RISCV_IOMMU_CQB_PPN RISCV_IOMMU_PPN_FIELD 114 115 /* 5.7 Command Queue head (32bits) */ 116 #define RISCV_IOMMU_REG_CQH 0x0020 117 #define RISCV_IOMMU_CQH_INDEX RISCV_IOMMU_QUEUE_INDEX_FIELD 118 119 /* 5.8 Command Queue tail (32bits) */ 120 #define RISCV_IOMMU_REG_CQT 0x0024 121 #define RISCV_IOMMU_CQT_INDEX RISCV_IOMMU_QUEUE_INDEX_FIELD 122 123 /* 5.9 Fault Queue Base (64bits) */ 124 #define RISCV_IOMMU_REG_FQB 0x0028 125 #define RISCV_IOMMU_FQB_ENTRIES RISCV_IOMMU_QUEUE_LOG2SZ_FIELD 126 #define RISCV_IOMMU_FQB_PPN RISCV_IOMMU_PPN_FIELD 127 128 /* 5.10 Fault Queue Head (32bits) */ 129 #define RISCV_IOMMU_REG_FQH 0x0030 130 #define RISCV_IOMMU_FQH_INDEX RISCV_IOMMU_QUEUE_INDEX_FIELD 131 132 /* 5.11 Fault Queue tail (32bits) */ 133 #define RISCV_IOMMU_REG_FQT 0x0034 134 #define RISCV_IOMMU_FQT_INDEX RISCV_IOMMU_QUEUE_INDEX_FIELD 135 136 /* 5.12 Page Request Queue base (64bits) */ 137 #define RISCV_IOMMU_REG_PQB 0x0038 138 #define RISCV_IOMMU_PQB_ENTRIES RISCV_IOMMU_QUEUE_LOG2SZ_FIELD 139 #define RISCV_IOMMU_PQB_PPN RISCV_IOMMU_PPN_FIELD 140 141 /* 5.13 Page Request Queue head (32bits) */ 142 #define RISCV_IOMMU_REG_PQH 0x0040 143 #define RISCV_IOMMU_PQH_INDEX RISCV_IOMMU_QUEUE_INDEX_FIELD 144 145 /* 5.14 Page Request Queue tail (32bits) */ 146 #define RISCV_IOMMU_REG_PQT 0x0044 147 #define RISCV_IOMMU_PQT_INDEX_MASK RISCV_IOMMU_QUEUE_INDEX_FIELD 148 149 /* 5.15 Command Queue CSR (32bits) */ 150 #define RISCV_IOMMU_REG_CQCSR 0x0048 151 #define RISCV_IOMMU_CQCSR_CQEN RISCV_IOMMU_QUEUE_ENABLE 152 #define RISCV_IOMMU_CQCSR_CIE RISCV_IOMMU_QUEUE_INTR_ENABLE 153 #define RISCV_IOMMU_CQCSR_CQMF RISCV_IOMMU_QUEUE_MEM_FAULT 154 #define RISCV_IOMMU_CQCSR_CMD_TO BIT(9) 155 #define RISCV_IOMMU_CQCSR_CMD_ILL BIT(10) 156 #define RISCV_IOMMU_CQCSR_FENCE_W_IP BIT(11) 157 #define RISCV_IOMMU_CQCSR_CQON RISCV_IOMMU_QUEUE_ACTIVE 158 #define RISCV_IOMMU_CQCSR_BUSY RISCV_IOMMU_QUEUE_BUSY 159 160 /* 5.16 Fault Queue CSR (32bits) */ 161 #define RISCV_IOMMU_REG_FQCSR 0x004C 162 #define RISCV_IOMMU_FQCSR_FQEN RISCV_IOMMU_QUEUE_ENABLE 163 #define RISCV_IOMMU_FQCSR_FIE RISCV_IOMMU_QUEUE_INTR_ENABLE 164 #define RISCV_IOMMU_FQCSR_FQMF RISCV_IOMMU_QUEUE_MEM_FAULT 165 #define RISCV_IOMMU_FQCSR_FQOF RISCV_IOMMU_QUEUE_OVERFLOW 166 #define RISCV_IOMMU_FQCSR_FQON RISCV_IOMMU_QUEUE_ACTIVE 167 #define RISCV_IOMMU_FQCSR_BUSY RISCV_IOMMU_QUEUE_BUSY 168 169 /* 5.17 Page Request Queue CSR (32bits) */ 170 #define RISCV_IOMMU_REG_PQCSR 0x0050 171 #define RISCV_IOMMU_PQCSR_PQEN RISCV_IOMMU_QUEUE_ENABLE 172 #define RISCV_IOMMU_PQCSR_PIE RISCV_IOMMU_QUEUE_INTR_ENABLE 173 #define RISCV_IOMMU_PQCSR_PQMF RISCV_IOMMU_QUEUE_MEM_FAULT 174 #define RISCV_IOMMU_PQCSR_PQOF RISCV_IOMMU_QUEUE_OVERFLOW 175 #define RISCV_IOMMU_PQCSR_PQON RISCV_IOMMU_QUEUE_ACTIVE 176 #define RISCV_IOMMU_PQCSR_BUSY RISCV_IOMMU_QUEUE_BUSY 177 178 /* 5.18 Interrupt Pending Status (32bits) */ 179 #define RISCV_IOMMU_REG_IPSR 0x0054 180 181 #define RISCV_IOMMU_INTR_CQ 0 182 #define RISCV_IOMMU_INTR_FQ 1 183 #define RISCV_IOMMU_INTR_PM 2 184 #define RISCV_IOMMU_INTR_PQ 3 185 #define RISCV_IOMMU_INTR_COUNT 4 186 187 #define RISCV_IOMMU_IPSR_CIP BIT(RISCV_IOMMU_INTR_CQ) 188 #define RISCV_IOMMU_IPSR_FIP BIT(RISCV_IOMMU_INTR_FQ) 189 #define RISCV_IOMMU_IPSR_PMIP BIT(RISCV_IOMMU_INTR_PM) 190 #define RISCV_IOMMU_IPSR_PIP BIT(RISCV_IOMMU_INTR_PQ) 191 192 /* 5.19 Performance monitoring counter overflow status (32bits) */ 193 #define RISCV_IOMMU_REG_IOCOUNTOVF 0x0058 194 #define RISCV_IOMMU_IOCOUNTOVF_CY BIT(0) 195 #define RISCV_IOMMU_IOCOUNTOVF_HPM GENMASK_ULL(31, 1) 196 197 /* 5.20 Performance monitoring counter inhibits (32bits) */ 198 #define RISCV_IOMMU_REG_IOCOUNTINH 0x005C 199 #define RISCV_IOMMU_IOCOUNTINH_CY BIT(0) 200 #define RISCV_IOMMU_IOCOUNTINH_HPM GENMASK(31, 1) 201 202 /* 5.21 Performance monitoring cycles counter (64bits) */ 203 #define RISCV_IOMMU_REG_IOHPMCYCLES 0x0060 204 #define RISCV_IOMMU_IOHPMCYCLES_COUNTER GENMASK_ULL(62, 0) 205 #define RISCV_IOMMU_IOHPMCYCLES_OF BIT_ULL(63) 206 207 /* 5.22 Performance monitoring event counters (31 * 64bits) */ 208 #define RISCV_IOMMU_REG_IOHPMCTR_BASE 0x0068 209 #define RISCV_IOMMU_REG_IOHPMCTR(_n) (RISCV_IOMMU_REG_IOHPMCTR_BASE + ((_n) * 0x8)) 210 211 /* 5.23 Performance monitoring event selectors (31 * 64bits) */ 212 #define RISCV_IOMMU_REG_IOHPMEVT_BASE 0x0160 213 #define RISCV_IOMMU_REG_IOHPMEVT(_n) (RISCV_IOMMU_REG_IOHPMEVT_BASE + ((_n) * 0x8)) 214 #define RISCV_IOMMU_IOHPMEVT_EVENTID GENMASK_ULL(14, 0) 215 #define RISCV_IOMMU_IOHPMEVT_DMASK BIT_ULL(15) 216 #define RISCV_IOMMU_IOHPMEVT_PID_PSCID GENMASK_ULL(35, 16) 217 #define RISCV_IOMMU_IOHPMEVT_DID_GSCID GENMASK_ULL(59, 36) 218 #define RISCV_IOMMU_IOHPMEVT_PV_PSCV BIT_ULL(60) 219 #define RISCV_IOMMU_IOHPMEVT_DV_GSCV BIT_ULL(61) 220 #define RISCV_IOMMU_IOHPMEVT_IDT BIT_ULL(62) 221 #define RISCV_IOMMU_IOHPMEVT_OF BIT_ULL(63) 222 223 /* Number of defined performance-monitoring event selectors */ 224 #define RISCV_IOMMU_IOHPMEVT_CNT 31 225 226 /** 227 * enum riscv_iommu_hpmevent_id - Performance-monitoring event identifier 228 * 229 * @RISCV_IOMMU_HPMEVENT_INVALID: Invalid event, do not count 230 * @RISCV_IOMMU_HPMEVENT_URQ: Untranslated requests 231 * @RISCV_IOMMU_HPMEVENT_TRQ: Translated requests 232 * @RISCV_IOMMU_HPMEVENT_ATS_RQ: ATS translation requests 233 * @RISCV_IOMMU_HPMEVENT_TLB_MISS: TLB misses 234 * @RISCV_IOMMU_HPMEVENT_DD_WALK: Device directory walks 235 * @RISCV_IOMMU_HPMEVENT_PD_WALK: Process directory walks 236 * @RISCV_IOMMU_HPMEVENT_S_VS_WALKS: First-stage page table walks 237 * @RISCV_IOMMU_HPMEVENT_G_WALKS: Second-stage page table walks 238 * @RISCV_IOMMU_HPMEVENT_MAX: Value to denote maximum Event IDs 239 */ 240 enum riscv_iommu_hpmevent_id { 241 RISCV_IOMMU_HPMEVENT_INVALID = 0, 242 RISCV_IOMMU_HPMEVENT_URQ = 1, 243 RISCV_IOMMU_HPMEVENT_TRQ = 2, 244 RISCV_IOMMU_HPMEVENT_ATS_RQ = 3, 245 RISCV_IOMMU_HPMEVENT_TLB_MISS = 4, 246 RISCV_IOMMU_HPMEVENT_DD_WALK = 5, 247 RISCV_IOMMU_HPMEVENT_PD_WALK = 6, 248 RISCV_IOMMU_HPMEVENT_S_VS_WALKS = 7, 249 RISCV_IOMMU_HPMEVENT_G_WALKS = 8, 250 RISCV_IOMMU_HPMEVENT_MAX = 9 251 }; 252 253 /* 5.24 Translation request IOVA (64bits) */ 254 #define RISCV_IOMMU_REG_TR_REQ_IOVA 0x0258 255 #define RISCV_IOMMU_TR_REQ_IOVA_VPN GENMASK_ULL(63, 12) 256 257 /* 5.25 Translation request control (64bits) */ 258 #define RISCV_IOMMU_REG_TR_REQ_CTL 0x0260 259 #define RISCV_IOMMU_TR_REQ_CTL_GO_BUSY BIT_ULL(0) 260 #define RISCV_IOMMU_TR_REQ_CTL_PRIV BIT_ULL(1) 261 #define RISCV_IOMMU_TR_REQ_CTL_EXE BIT_ULL(2) 262 #define RISCV_IOMMU_TR_REQ_CTL_NW BIT_ULL(3) 263 #define RISCV_IOMMU_TR_REQ_CTL_PID GENMASK_ULL(31, 12) 264 #define RISCV_IOMMU_TR_REQ_CTL_PV BIT_ULL(32) 265 #define RISCV_IOMMU_TR_REQ_CTL_DID GENMASK_ULL(63, 40) 266 267 /* 5.26 Translation request response (64bits) */ 268 #define RISCV_IOMMU_REG_TR_RESPONSE 0x0268 269 #define RISCV_IOMMU_TR_RESPONSE_FAULT BIT_ULL(0) 270 #define RISCV_IOMMU_TR_RESPONSE_PBMT GENMASK_ULL(8, 7) 271 #define RISCV_IOMMU_TR_RESPONSE_SZ BIT_ULL(9) 272 #define RISCV_IOMMU_TR_RESPONSE_PPN RISCV_IOMMU_PPN_FIELD 273 274 /* 5.27 Interrupt cause to vector (64bits) */ 275 #define RISCV_IOMMU_REG_ICVEC 0x02F8 276 #define RISCV_IOMMU_ICVEC_CIV GENMASK_ULL(3, 0) 277 #define RISCV_IOMMU_ICVEC_FIV GENMASK_ULL(7, 4) 278 #define RISCV_IOMMU_ICVEC_PMIV GENMASK_ULL(11, 8) 279 #define RISCV_IOMMU_ICVEC_PIV GENMASK_ULL(15, 12) 280 281 /* 5.28 MSI Configuration table (32 * 64bits) */ 282 #define RISCV_IOMMU_REG_MSI_CFG_TBL 0x0300 283 #define RISCV_IOMMU_REG_MSI_CFG_TBL_ADDR(_n) \ 284 (RISCV_IOMMU_REG_MSI_CFG_TBL + ((_n) * 0x10)) 285 #define RISCV_IOMMU_MSI_CFG_TBL_ADDR GENMASK_ULL(55, 2) 286 #define RISCV_IOMMU_REG_MSI_CFG_TBL_DATA(_n) \ 287 (RISCV_IOMMU_REG_MSI_CFG_TBL + ((_n) * 0x10) + 0x08) 288 #define RISCV_IOMMU_MSI_CFG_TBL_DATA GENMASK_ULL(31, 0) 289 #define RISCV_IOMMU_REG_MSI_CFG_TBL_CTRL(_n) \ 290 (RISCV_IOMMU_REG_MSI_CFG_TBL + ((_n) * 0x10) + 0x0C) 291 #define RISCV_IOMMU_MSI_CFG_TBL_CTRL_M BIT_ULL(0) 292 293 #define RISCV_IOMMU_REG_SIZE 0x1000 294 295 /* 296 * Chapter 2: Data structures 297 */ 298 299 /* 300 * Device Directory Table macros for non-leaf nodes 301 */ 302 #define RISCV_IOMMU_DDTE_V BIT_ULL(0) 303 #define RISCV_IOMMU_DDTE_PPN RISCV_IOMMU_PPN_FIELD 304 305 /** 306 * struct riscv_iommu_dc - Device Context 307 * @tc: Translation Control 308 * @iohgatp: I/O Hypervisor guest address translation and protection 309 * (Second stage context) 310 * @ta: Translation Attributes 311 * @fsc: First stage context 312 * @msiptp: MSI page table pointer 313 * @msi_addr_mask: MSI address mask 314 * @msi_addr_pattern: MSI address pattern 315 * @_reserved: Reserved for future use, padding 316 * 317 * This structure is used for leaf nodes on the Device Directory Table, 318 * in case RISCV_IOMMU_CAPABILITIES_MSI_FLAT is not set, the bottom 4 fields 319 * are not present and are skipped with pointer arithmetic to avoid 320 * casting, check out riscv_iommu_get_dc(). 321 * See section 2.1 for more details 322 */ 323 struct riscv_iommu_dc { 324 u64 tc; 325 u64 iohgatp; 326 u64 ta; 327 u64 fsc; 328 u64 msiptp; 329 u64 msi_addr_mask; 330 u64 msi_addr_pattern; 331 u64 _reserved; 332 }; 333 334 /* Translation control fields */ 335 #define RISCV_IOMMU_DC_TC_V BIT_ULL(0) 336 #define RISCV_IOMMU_DC_TC_EN_ATS BIT_ULL(1) 337 #define RISCV_IOMMU_DC_TC_EN_PRI BIT_ULL(2) 338 #define RISCV_IOMMU_DC_TC_T2GPA BIT_ULL(3) 339 #define RISCV_IOMMU_DC_TC_DTF BIT_ULL(4) 340 #define RISCV_IOMMU_DC_TC_PDTV BIT_ULL(5) 341 #define RISCV_IOMMU_DC_TC_PRPR BIT_ULL(6) 342 #define RISCV_IOMMU_DC_TC_GADE BIT_ULL(7) 343 #define RISCV_IOMMU_DC_TC_SADE BIT_ULL(8) 344 #define RISCV_IOMMU_DC_TC_DPE BIT_ULL(9) 345 #define RISCV_IOMMU_DC_TC_SBE BIT_ULL(10) 346 #define RISCV_IOMMU_DC_TC_SXL BIT_ULL(11) 347 348 /* Second-stage (aka G-stage) context fields */ 349 #define RISCV_IOMMU_DC_IOHGATP_PPN RISCV_IOMMU_ATP_PPN_FIELD 350 #define RISCV_IOMMU_DC_IOHGATP_GSCID GENMASK_ULL(59, 44) 351 #define RISCV_IOMMU_DC_IOHGATP_MODE RISCV_IOMMU_ATP_MODE_FIELD 352 353 /** 354 * enum riscv_iommu_dc_iohgatp_modes - Guest address translation/protection modes 355 * @RISCV_IOMMU_DC_IOHGATP_MODE_BARE: No translation/protection 356 * @RISCV_IOMMU_DC_IOHGATP_MODE_SV32X4: Sv32x4 (2-bit extension of Sv32), when fctl.GXL == 1 357 * @RISCV_IOMMU_DC_IOHGATP_MODE_SV39X4: Sv39x4 (2-bit extension of Sv39), when fctl.GXL == 0 358 * @RISCV_IOMMU_DC_IOHGATP_MODE_SV48X4: Sv48x4 (2-bit extension of Sv48), when fctl.GXL == 0 359 * @RISCV_IOMMU_DC_IOHGATP_MODE_SV57X4: Sv57x4 (2-bit extension of Sv57), when fctl.GXL == 0 360 */ 361 enum riscv_iommu_dc_iohgatp_modes { 362 RISCV_IOMMU_DC_IOHGATP_MODE_BARE = 0, 363 RISCV_IOMMU_DC_IOHGATP_MODE_SV32X4 = 8, 364 RISCV_IOMMU_DC_IOHGATP_MODE_SV39X4 = 8, 365 RISCV_IOMMU_DC_IOHGATP_MODE_SV48X4 = 9, 366 RISCV_IOMMU_DC_IOHGATP_MODE_SV57X4 = 10 367 }; 368 369 /* Translation attributes fields */ 370 #define RISCV_IOMMU_DC_TA_PSCID GENMASK_ULL(31, 12) 371 372 /* First-stage context fields */ 373 #define RISCV_IOMMU_DC_FSC_PPN RISCV_IOMMU_ATP_PPN_FIELD 374 #define RISCV_IOMMU_DC_FSC_MODE RISCV_IOMMU_ATP_MODE_FIELD 375 376 /** 377 * enum riscv_iommu_dc_fsc_atp_modes - First stage address translation/protection modes 378 * @RISCV_IOMMU_DC_FSC_MODE_BARE: No translation/protection 379 * @RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV32: Sv32, when dc.tc.SXL == 1 380 * @RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV39: Sv39, when dc.tc.SXL == 0 381 * @RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV48: Sv48, when dc.tc.SXL == 0 382 * @RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV57: Sv57, when dc.tc.SXL == 0 383 * @RISCV_IOMMU_DC_FSC_PDTP_MODE_PD8: 1lvl PDT, 8bit process ids 384 * @RISCV_IOMMU_DC_FSC_PDTP_MODE_PD17: 2lvl PDT, 17bit process ids 385 * @RISCV_IOMMU_DC_FSC_PDTP_MODE_PD20: 3lvl PDT, 20bit process ids 386 * 387 * FSC holds IOSATP when RISCV_IOMMU_DC_TC_PDTV is 0 and PDTP otherwise. 388 * IOSATP controls the first stage address translation (same as the satp register on 389 * the RISC-V MMU), and PDTP holds the process directory table, used to select a 390 * first stage page table based on a process id (for devices that support multiple 391 * process ids). 392 */ 393 enum riscv_iommu_dc_fsc_atp_modes { 394 RISCV_IOMMU_DC_FSC_MODE_BARE = 0, 395 RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV32 = 8, 396 RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV39 = 8, 397 RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV48 = 9, 398 RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV57 = 10, 399 RISCV_IOMMU_DC_FSC_PDTP_MODE_PD8 = 1, 400 RISCV_IOMMU_DC_FSC_PDTP_MODE_PD17 = 2, 401 RISCV_IOMMU_DC_FSC_PDTP_MODE_PD20 = 3 402 }; 403 404 /* MSI page table pointer */ 405 #define RISCV_IOMMU_DC_MSIPTP_PPN RISCV_IOMMU_ATP_PPN_FIELD 406 #define RISCV_IOMMU_DC_MSIPTP_MODE RISCV_IOMMU_ATP_MODE_FIELD 407 #define RISCV_IOMMU_DC_MSIPTP_MODE_OFF 0 408 #define RISCV_IOMMU_DC_MSIPTP_MODE_FLAT 1 409 410 /* MSI address mask */ 411 #define RISCV_IOMMU_DC_MSI_ADDR_MASK GENMASK_ULL(51, 0) 412 413 /* MSI address pattern */ 414 #define RISCV_IOMMU_DC_MSI_PATTERN GENMASK_ULL(51, 0) 415 416 /** 417 * struct riscv_iommu_pc - Process Context 418 * @ta: Translation Attributes 419 * @fsc: First stage context 420 * 421 * This structure is used for leaf nodes on the Process Directory Table 422 * See section 2.3 for more details 423 */ 424 struct riscv_iommu_pc { 425 u64 ta; 426 u64 fsc; 427 }; 428 429 /* Translation attributes fields */ 430 #define RISCV_IOMMU_PC_TA_V BIT_ULL(0) 431 #define RISCV_IOMMU_PC_TA_ENS BIT_ULL(1) 432 #define RISCV_IOMMU_PC_TA_SUM BIT_ULL(2) 433 #define RISCV_IOMMU_PC_TA_PSCID GENMASK_ULL(31, 12) 434 435 /* First stage context fields */ 436 #define RISCV_IOMMU_PC_FSC_PPN RISCV_IOMMU_ATP_PPN_FIELD 437 #define RISCV_IOMMU_PC_FSC_MODE RISCV_IOMMU_ATP_MODE_FIELD 438 439 /* 440 * Chapter 3: In-memory queue interface 441 */ 442 443 /** 444 * struct riscv_iommu_command - Generic IOMMU command structure 445 * @dword0: Includes the opcode and the function identifier 446 * @dword1: Opcode specific data 447 * 448 * The commands are interpreted as two 64bit fields, where the first 449 * 7bits of the first field are the opcode which also defines the 450 * command's format, followed by a 3bit field that specifies the 451 * function invoked by that command, and the rest is opcode-specific. 452 * This is a generic struct which will be populated differently 453 * according to each command. For more infos on the commands and 454 * the command queue check section 3.1. 455 */ 456 struct riscv_iommu_command { 457 u64 dword0; 458 u64 dword1; 459 }; 460 461 /* Fields on dword0, common for all commands */ 462 #define RISCV_IOMMU_CMD_OPCODE GENMASK_ULL(6, 0) 463 #define RISCV_IOMMU_CMD_FUNC GENMASK_ULL(9, 7) 464 465 /* 3.1.1 IOMMU Page-table cache invalidation */ 466 /* Fields on dword0 */ 467 #define RISCV_IOMMU_CMD_IOTINVAL_OPCODE 1 468 #define RISCV_IOMMU_CMD_IOTINVAL_FUNC_VMA 0 469 #define RISCV_IOMMU_CMD_IOTINVAL_FUNC_GVMA 1 470 #define RISCV_IOMMU_CMD_IOTINVAL_AV BIT_ULL(10) 471 #define RISCV_IOMMU_CMD_IOTINVAL_PSCID GENMASK_ULL(31, 12) 472 #define RISCV_IOMMU_CMD_IOTINVAL_PSCV BIT_ULL(32) 473 #define RISCV_IOMMU_CMD_IOTINVAL_GV BIT_ULL(33) 474 #define RISCV_IOMMU_CMD_IOTINVAL_GSCID GENMASK_ULL(59, 44) 475 /* dword1[61:10] is the 4K-aligned page address */ 476 #define RISCV_IOMMU_CMD_IOTINVAL_ADDR GENMASK_ULL(61, 10) 477 478 /* 3.1.2 IOMMU Command Queue Fences */ 479 /* Fields on dword0 */ 480 #define RISCV_IOMMU_CMD_IOFENCE_OPCODE 2 481 #define RISCV_IOMMU_CMD_IOFENCE_FUNC_C 0 482 #define RISCV_IOMMU_CMD_IOFENCE_AV BIT_ULL(10) 483 #define RISCV_IOMMU_CMD_IOFENCE_WSI BIT_ULL(11) 484 #define RISCV_IOMMU_CMD_IOFENCE_PR BIT_ULL(12) 485 #define RISCV_IOMMU_CMD_IOFENCE_PW BIT_ULL(13) 486 #define RISCV_IOMMU_CMD_IOFENCE_DATA GENMASK_ULL(63, 32) 487 /* dword1 is the address, word-size aligned and shifted to the right by two bits. */ 488 489 /* 3.1.3 IOMMU Directory cache invalidation */ 490 /* Fields on dword0 */ 491 #define RISCV_IOMMU_CMD_IODIR_OPCODE 3 492 #define RISCV_IOMMU_CMD_IODIR_FUNC_INVAL_DDT 0 493 #define RISCV_IOMMU_CMD_IODIR_FUNC_INVAL_PDT 1 494 #define RISCV_IOMMU_CMD_IODIR_PID GENMASK_ULL(31, 12) 495 #define RISCV_IOMMU_CMD_IODIR_DV BIT_ULL(33) 496 #define RISCV_IOMMU_CMD_IODIR_DID GENMASK_ULL(63, 40) 497 /* dword1 is reserved for standard use */ 498 499 /* 3.1.4 IOMMU PCIe ATS */ 500 /* Fields on dword0 */ 501 #define RISCV_IOMMU_CMD_ATS_OPCODE 4 502 #define RISCV_IOMMU_CMD_ATS_FUNC_INVAL 0 503 #define RISCV_IOMMU_CMD_ATS_FUNC_PRGR 1 504 #define RISCV_IOMMU_CMD_ATS_PID GENMASK_ULL(31, 12) 505 #define RISCV_IOMMU_CMD_ATS_PV BIT_ULL(32) 506 #define RISCV_IOMMU_CMD_ATS_DSV BIT_ULL(33) 507 #define RISCV_IOMMU_CMD_ATS_RID GENMASK_ULL(55, 40) 508 #define RISCV_IOMMU_CMD_ATS_DSEG GENMASK_ULL(63, 56) 509 /* dword1 is the ATS payload, two different payload types for INVAL and PRGR */ 510 511 /* ATS.INVAL payload*/ 512 #define RISCV_IOMMU_CMD_ATS_INVAL_G BIT_ULL(0) 513 /* Bits 1 - 10 are zeroed */ 514 #define RISCV_IOMMU_CMD_ATS_INVAL_S BIT_ULL(11) 515 #define RISCV_IOMMU_CMD_ATS_INVAL_UADDR GENMASK_ULL(63, 12) 516 517 /* ATS.PRGR payload */ 518 /* Bits 0 - 31 are zeroed */ 519 #define RISCV_IOMMU_CMD_ATS_PRGR_PRG_INDEX GENMASK_ULL(40, 32) 520 /* Bits 41 - 43 are zeroed */ 521 #define RISCV_IOMMU_CMD_ATS_PRGR_RESP_CODE GENMASK_ULL(47, 44) 522 #define RISCV_IOMMU_CMD_ATS_PRGR_DST_ID GENMASK_ULL(63, 48) 523 524 /** 525 * struct riscv_iommu_fq_record - Fault/Event Queue Record 526 * @hdr: Header, includes fault/event cause, PID/DID, transaction type etc 527 * @_reserved: Low 32bits for custom use, high 32bits for standard use 528 * @iotval: Transaction-type/cause specific format 529 * @iotval2: Cause specific format 530 * 531 * The fault/event queue reports events and failures raised when 532 * processing transactions. Each record is a 32byte structure where 533 * the first dword has a fixed format for providing generic infos 534 * regarding the fault/event, and two more dwords are there for 535 * fault/event-specific information. For more details see section 536 * 3.2. 537 */ 538 struct riscv_iommu_fq_record { 539 u64 hdr; 540 u64 _reserved; 541 u64 iotval; 542 u64 iotval2; 543 }; 544 545 /* Fields on header */ 546 #define RISCV_IOMMU_FQ_HDR_CAUSE GENMASK_ULL(11, 0) 547 #define RISCV_IOMMU_FQ_HDR_PID GENMASK_ULL(31, 12) 548 #define RISCV_IOMMU_FQ_HDR_PV BIT_ULL(32) 549 #define RISCV_IOMMU_FQ_HDR_PRIV BIT_ULL(33) 550 #define RISCV_IOMMU_FQ_HDR_TTYP GENMASK_ULL(39, 34) 551 #define RISCV_IOMMU_FQ_HDR_DID GENMASK_ULL(63, 40) 552 553 /** 554 * enum riscv_iommu_fq_causes - Fault/event cause values 555 * @RISCV_IOMMU_FQ_CAUSE_INST_FAULT: Instruction access fault 556 * @RISCV_IOMMU_FQ_CAUSE_RD_ADDR_MISALIGNED: Read address misaligned 557 * @RISCV_IOMMU_FQ_CAUSE_RD_FAULT: Read load fault 558 * @RISCV_IOMMU_FQ_CAUSE_WR_ADDR_MISALIGNED: Write/AMO address misaligned 559 * @RISCV_IOMMU_FQ_CAUSE_WR_FAULT: Write/AMO access fault 560 * @RISCV_IOMMU_FQ_CAUSE_INST_FAULT_S: Instruction page fault 561 * @RISCV_IOMMU_FQ_CAUSE_RD_FAULT_S: Read page fault 562 * @RISCV_IOMMU_FQ_CAUSE_WR_FAULT_S: Write/AMO page fault 563 * @RISCV_IOMMU_FQ_CAUSE_INST_FAULT_VS: Instruction guest page fault 564 * @RISCV_IOMMU_FQ_CAUSE_RD_FAULT_VS: Read guest page fault 565 * @RISCV_IOMMU_FQ_CAUSE_WR_FAULT_VS: Write/AMO guest page fault 566 * @RISCV_IOMMU_FQ_CAUSE_DMA_DISABLED: All inbound transactions disallowed 567 * @RISCV_IOMMU_FQ_CAUSE_DDT_LOAD_FAULT: DDT entry load access fault 568 * @RISCV_IOMMU_FQ_CAUSE_DDT_INVALID: DDT entry invalid 569 * @RISCV_IOMMU_FQ_CAUSE_DDT_MISCONFIGURED: DDT entry misconfigured 570 * @RISCV_IOMMU_FQ_CAUSE_TTYP_BLOCKED: Transaction type disallowed 571 * @RISCV_IOMMU_FQ_CAUSE_MSI_LOAD_FAULT: MSI PTE load access fault 572 * @RISCV_IOMMU_FQ_CAUSE_MSI_INVALID: MSI PTE invalid 573 * @RISCV_IOMMU_FQ_CAUSE_MSI_MISCONFIGURED: MSI PTE misconfigured 574 * @RISCV_IOMMU_FQ_CAUSE_MRIF_FAULT: MRIF access fault 575 * @RISCV_IOMMU_FQ_CAUSE_PDT_LOAD_FAULT: PDT entry load access fault 576 * @RISCV_IOMMU_FQ_CAUSE_PDT_INVALID: PDT entry invalid 577 * @RISCV_IOMMU_FQ_CAUSE_PDT_MISCONFIGURED: PDT entry misconfigured 578 * @RISCV_IOMMU_FQ_CAUSE_DDT_CORRUPTED: DDT data corruption 579 * @RISCV_IOMMU_FQ_CAUSE_PDT_CORRUPTED: PDT data corruption 580 * @RISCV_IOMMU_FQ_CAUSE_MSI_PT_CORRUPTED: MSI page table data corruption 581 * @RISCV_IOMMU_FQ_CAUSE_MRIF_CORRUIPTED: MRIF data corruption 582 * @RISCV_IOMMU_FQ_CAUSE_INTERNAL_DP_ERROR: Internal data path error 583 * @RISCV_IOMMU_FQ_CAUSE_MSI_WR_FAULT: IOMMU MSI write access fault 584 * @RISCV_IOMMU_FQ_CAUSE_PT_CORRUPTED: First/second stage page table data corruption 585 * 586 * Values are on table 11 of the spec, encodings 275 - 2047 are reserved for standard 587 * use, and 2048 - 4095 for custom use. 588 */ 589 enum riscv_iommu_fq_causes { 590 RISCV_IOMMU_FQ_CAUSE_INST_FAULT = 1, 591 RISCV_IOMMU_FQ_CAUSE_RD_ADDR_MISALIGNED = 4, 592 RISCV_IOMMU_FQ_CAUSE_RD_FAULT = 5, 593 RISCV_IOMMU_FQ_CAUSE_WR_ADDR_MISALIGNED = 6, 594 RISCV_IOMMU_FQ_CAUSE_WR_FAULT = 7, 595 RISCV_IOMMU_FQ_CAUSE_INST_FAULT_S = 12, 596 RISCV_IOMMU_FQ_CAUSE_RD_FAULT_S = 13, 597 RISCV_IOMMU_FQ_CAUSE_WR_FAULT_S = 15, 598 RISCV_IOMMU_FQ_CAUSE_INST_FAULT_VS = 20, 599 RISCV_IOMMU_FQ_CAUSE_RD_FAULT_VS = 21, 600 RISCV_IOMMU_FQ_CAUSE_WR_FAULT_VS = 23, 601 RISCV_IOMMU_FQ_CAUSE_DMA_DISABLED = 256, 602 RISCV_IOMMU_FQ_CAUSE_DDT_LOAD_FAULT = 257, 603 RISCV_IOMMU_FQ_CAUSE_DDT_INVALID = 258, 604 RISCV_IOMMU_FQ_CAUSE_DDT_MISCONFIGURED = 259, 605 RISCV_IOMMU_FQ_CAUSE_TTYP_BLOCKED = 260, 606 RISCV_IOMMU_FQ_CAUSE_MSI_LOAD_FAULT = 261, 607 RISCV_IOMMU_FQ_CAUSE_MSI_INVALID = 262, 608 RISCV_IOMMU_FQ_CAUSE_MSI_MISCONFIGURED = 263, 609 RISCV_IOMMU_FQ_CAUSE_MRIF_FAULT = 264, 610 RISCV_IOMMU_FQ_CAUSE_PDT_LOAD_FAULT = 265, 611 RISCV_IOMMU_FQ_CAUSE_PDT_INVALID = 266, 612 RISCV_IOMMU_FQ_CAUSE_PDT_MISCONFIGURED = 267, 613 RISCV_IOMMU_FQ_CAUSE_DDT_CORRUPTED = 268, 614 RISCV_IOMMU_FQ_CAUSE_PDT_CORRUPTED = 269, 615 RISCV_IOMMU_FQ_CAUSE_MSI_PT_CORRUPTED = 270, 616 RISCV_IOMMU_FQ_CAUSE_MRIF_CORRUIPTED = 271, 617 RISCV_IOMMU_FQ_CAUSE_INTERNAL_DP_ERROR = 272, 618 RISCV_IOMMU_FQ_CAUSE_MSI_WR_FAULT = 273, 619 RISCV_IOMMU_FQ_CAUSE_PT_CORRUPTED = 274 620 }; 621 622 /** 623 * enum riscv_iommu_fq_ttypes: Fault/event transaction types 624 * @RISCV_IOMMU_FQ_TTYP_NONE: None. Fault not caused by an inbound transaction. 625 * @RISCV_IOMMU_FQ_TTYP_UADDR_INST_FETCH: Instruction fetch from untranslated address 626 * @RISCV_IOMMU_FQ_TTYP_UADDR_RD: Read from untranslated address 627 * @RISCV_IOMMU_FQ_TTYP_UADDR_WR: Write/AMO to untranslated address 628 * @RISCV_IOMMU_FQ_TTYP_TADDR_INST_FETCH: Instruction fetch from translated address 629 * @RISCV_IOMMU_FQ_TTYP_TADDR_RD: Read from translated address 630 * @RISCV_IOMMU_FQ_TTYP_TADDR_WR: Write/AMO to translated address 631 * @RISCV_IOMMU_FQ_TTYP_PCIE_ATS_REQ: PCIe ATS translation request 632 * @RISCV_IOMMU_FQ_TTYP_PCIE_MSG_REQ: PCIe message request 633 * 634 * Values are on table 12 of the spec, type 4 and 10 - 31 are reserved for standard use 635 * and 31 - 63 for custom use. 636 */ 637 enum riscv_iommu_fq_ttypes { 638 RISCV_IOMMU_FQ_TTYP_NONE = 0, 639 RISCV_IOMMU_FQ_TTYP_UADDR_INST_FETCH = 1, 640 RISCV_IOMMU_FQ_TTYP_UADDR_RD = 2, 641 RISCV_IOMMU_FQ_TTYP_UADDR_WR = 3, 642 RISCV_IOMMU_FQ_TTYP_TADDR_INST_FETCH = 5, 643 RISCV_IOMMU_FQ_TTYP_TADDR_RD = 6, 644 RISCV_IOMMU_FQ_TTYP_TADDR_WR = 7, 645 RISCV_IOMMU_FQ_TTYP_PCIE_ATS_REQ = 8, 646 RISCV_IOMMU_FQ_TTYP_PCIE_MSG_REQ = 9, 647 }; 648 649 /** 650 * struct riscv_iommu_pq_record - PCIe Page Request record 651 * @hdr: Header, includes PID, DID etc 652 * @payload: Holds the page address, request group and permission bits 653 * 654 * For more infos on the PCIe Page Request queue see chapter 3.3. 655 */ 656 struct riscv_iommu_pq_record { 657 u64 hdr; 658 u64 payload; 659 }; 660 661 /* Header fields */ 662 #define RISCV_IOMMU_PQ_HDR_PID GENMASK_ULL(31, 12) 663 #define RISCV_IOMMU_PQ_HDR_PV BIT_ULL(32) 664 #define RISCV_IOMMU_PQ_HDR_PRIV BIT_ULL(33) 665 #define RISCV_IOMMU_PQ_HDR_EXEC BIT_ULL(34) 666 #define RISCV_IOMMU_PQ_HDR_DID GENMASK_ULL(63, 40) 667 668 /* Payload fields */ 669 #define RISCV_IOMMU_PQ_PAYLOAD_R BIT_ULL(0) 670 #define RISCV_IOMMU_PQ_PAYLOAD_W BIT_ULL(1) 671 #define RISCV_IOMMU_PQ_PAYLOAD_L BIT_ULL(2) 672 #define RISCV_IOMMU_PQ_PAYLOAD_RWL_MASK GENMASK_ULL(2, 0) 673 #define RISCV_IOMMU_PQ_PAYLOAD_PRGI GENMASK_ULL(11, 3) /* Page Request Group Index */ 674 #define RISCV_IOMMU_PQ_PAYLOAD_ADDR GENMASK_ULL(63, 12) 675 676 /** 677 * struct riscv_iommu_msipte - MSI Page Table Entry 678 * @pte: MSI PTE 679 * @mrif_info: Memory-resident interrupt file info 680 * 681 * The MSI Page Table is used for virtualizing MSIs, so that when 682 * a device sends an MSI to a guest, the IOMMU can reroute it 683 * by translating the MSI address, either to a guest interrupt file 684 * or a memory resident interrupt file (MRIF). Note that this page table 685 * is an array of MSI PTEs, not a multi-level pt, each entry 686 * is a leaf entry. For more infos check out the AIA spec, chapter 9.5. 687 * 688 * Also in basic mode the mrif_info field is ignored by the IOMMU and can 689 * be used by software, any other reserved fields on pte must be zeroed-out 690 * by software. 691 */ 692 struct riscv_iommu_msipte { 693 u64 pte; 694 u64 mrif_info; 695 }; 696 697 /* Fields on pte */ 698 #define RISCV_IOMMU_MSIPTE_V BIT_ULL(0) 699 #define RISCV_IOMMU_MSIPTE_M GENMASK_ULL(2, 1) 700 #define RISCV_IOMMU_MSIPTE_MRIF_ADDR GENMASK_ULL(53, 7) /* When M == 1 (MRIF mode) */ 701 #define RISCV_IOMMU_MSIPTE_PPN RISCV_IOMMU_PPN_FIELD /* When M == 3 (basic mode) */ 702 #define RISCV_IOMMU_MSIPTE_C BIT_ULL(63) 703 704 /* Fields on mrif_info */ 705 #define RISCV_IOMMU_MSIPTE_MRIF_NID GENMASK_ULL(9, 0) 706 #define RISCV_IOMMU_MSIPTE_MRIF_NPPN RISCV_IOMMU_PPN_FIELD 707 #define RISCV_IOMMU_MSIPTE_MRIF_NID_MSB BIT_ULL(60) 708 709 /* Helper functions: command structure builders. */ 710 711 static inline void riscv_iommu_cmd_inval_vma(struct riscv_iommu_command *cmd) 712 { 713 cmd->dword0 = FIELD_PREP(RISCV_IOMMU_CMD_OPCODE, RISCV_IOMMU_CMD_IOTINVAL_OPCODE) | 714 FIELD_PREP(RISCV_IOMMU_CMD_FUNC, RISCV_IOMMU_CMD_IOTINVAL_FUNC_VMA); 715 cmd->dword1 = 0; 716 } 717 718 static inline void riscv_iommu_cmd_inval_set_addr(struct riscv_iommu_command *cmd, 719 u64 addr) 720 { 721 cmd->dword1 = FIELD_PREP(RISCV_IOMMU_CMD_IOTINVAL_ADDR, phys_to_pfn(addr)); 722 cmd->dword0 |= RISCV_IOMMU_CMD_IOTINVAL_AV; 723 } 724 725 static inline void riscv_iommu_cmd_inval_set_pscid(struct riscv_iommu_command *cmd, 726 int pscid) 727 { 728 cmd->dword0 |= FIELD_PREP(RISCV_IOMMU_CMD_IOTINVAL_PSCID, pscid) | 729 RISCV_IOMMU_CMD_IOTINVAL_PSCV; 730 } 731 732 static inline void riscv_iommu_cmd_inval_set_gscid(struct riscv_iommu_command *cmd, 733 int gscid) 734 { 735 cmd->dword0 |= FIELD_PREP(RISCV_IOMMU_CMD_IOTINVAL_GSCID, gscid) | 736 RISCV_IOMMU_CMD_IOTINVAL_GV; 737 } 738 739 static inline void riscv_iommu_cmd_iofence(struct riscv_iommu_command *cmd) 740 { 741 cmd->dword0 = FIELD_PREP(RISCV_IOMMU_CMD_OPCODE, RISCV_IOMMU_CMD_IOFENCE_OPCODE) | 742 FIELD_PREP(RISCV_IOMMU_CMD_FUNC, RISCV_IOMMU_CMD_IOFENCE_FUNC_C) | 743 RISCV_IOMMU_CMD_IOFENCE_PR | RISCV_IOMMU_CMD_IOFENCE_PW; 744 cmd->dword1 = 0; 745 } 746 747 static inline void riscv_iommu_cmd_iofence_set_av(struct riscv_iommu_command *cmd, 748 u64 addr, u32 data) 749 { 750 cmd->dword0 = FIELD_PREP(RISCV_IOMMU_CMD_OPCODE, RISCV_IOMMU_CMD_IOFENCE_OPCODE) | 751 FIELD_PREP(RISCV_IOMMU_CMD_FUNC, RISCV_IOMMU_CMD_IOFENCE_FUNC_C) | 752 FIELD_PREP(RISCV_IOMMU_CMD_IOFENCE_DATA, data) | 753 RISCV_IOMMU_CMD_IOFENCE_AV; 754 cmd->dword1 = addr >> 2; 755 } 756 757 static inline void riscv_iommu_cmd_iodir_inval_ddt(struct riscv_iommu_command *cmd) 758 { 759 cmd->dword0 = FIELD_PREP(RISCV_IOMMU_CMD_OPCODE, RISCV_IOMMU_CMD_IODIR_OPCODE) | 760 FIELD_PREP(RISCV_IOMMU_CMD_FUNC, RISCV_IOMMU_CMD_IODIR_FUNC_INVAL_DDT); 761 cmd->dword1 = 0; 762 } 763 764 static inline void riscv_iommu_cmd_iodir_inval_pdt(struct riscv_iommu_command *cmd) 765 { 766 cmd->dword0 = FIELD_PREP(RISCV_IOMMU_CMD_OPCODE, RISCV_IOMMU_CMD_IODIR_OPCODE) | 767 FIELD_PREP(RISCV_IOMMU_CMD_FUNC, RISCV_IOMMU_CMD_IODIR_FUNC_INVAL_PDT); 768 cmd->dword1 = 0; 769 } 770 771 static inline void riscv_iommu_cmd_iodir_set_did(struct riscv_iommu_command *cmd, 772 unsigned int devid) 773 { 774 cmd->dword0 |= FIELD_PREP(RISCV_IOMMU_CMD_IODIR_DID, devid) | 775 RISCV_IOMMU_CMD_IODIR_DV; 776 } 777 778 static inline void riscv_iommu_cmd_iodir_set_pid(struct riscv_iommu_command *cmd, 779 unsigned int pasid) 780 { 781 cmd->dword0 |= FIELD_PREP(RISCV_IOMMU_CMD_IODIR_PID, pasid); 782 } 783 784 #endif /* _RISCV_IOMMU_BITS_H_ */ 785