1 /* 2 * omap iommu: tlb and pagetable primitives 3 * 4 * Copyright (C) 2008-2010 Nokia Corporation 5 * 6 * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>, 7 * Paul Mundt and Toshihiro Kobayashi 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 14 #include <linux/err.h> 15 #include <linux/module.h> 16 #include <linux/slab.h> 17 #include <linux/interrupt.h> 18 #include <linux/ioport.h> 19 #include <linux/platform_device.h> 20 #include <linux/iommu.h> 21 #include <linux/omap-iommu.h> 22 #include <linux/mutex.h> 23 #include <linux/spinlock.h> 24 #include <linux/io.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/of.h> 27 #include <linux/of_iommu.h> 28 #include <linux/of_irq.h> 29 #include <linux/of_platform.h> 30 31 #include <asm/cacheflush.h> 32 33 #include <linux/platform_data/iommu-omap.h> 34 35 #include "omap-iopgtable.h" 36 #include "omap-iommu.h" 37 38 #define to_iommu(dev) \ 39 ((struct omap_iommu *)platform_get_drvdata(to_platform_device(dev))) 40 41 #define for_each_iotlb_cr(obj, n, __i, cr) \ 42 for (__i = 0; \ 43 (__i < (n)) && (cr = __iotlb_read_cr((obj), __i), true); \ 44 __i++) 45 46 /* bitmap of the page sizes currently supported */ 47 #define OMAP_IOMMU_PGSIZES (SZ_4K | SZ_64K | SZ_1M | SZ_16M) 48 49 /** 50 * struct omap_iommu_domain - omap iommu domain 51 * @pgtable: the page table 52 * @iommu_dev: an omap iommu device attached to this domain. only a single 53 * iommu device can be attached for now. 54 * @dev: Device using this domain. 55 * @lock: domain lock, should be taken when attaching/detaching 56 */ 57 struct omap_iommu_domain { 58 u32 *pgtable; 59 struct omap_iommu *iommu_dev; 60 struct device *dev; 61 spinlock_t lock; 62 struct iommu_domain domain; 63 }; 64 65 #define MMU_LOCK_BASE_SHIFT 10 66 #define MMU_LOCK_BASE_MASK (0x1f << MMU_LOCK_BASE_SHIFT) 67 #define MMU_LOCK_BASE(x) \ 68 ((x & MMU_LOCK_BASE_MASK) >> MMU_LOCK_BASE_SHIFT) 69 70 #define MMU_LOCK_VICT_SHIFT 4 71 #define MMU_LOCK_VICT_MASK (0x1f << MMU_LOCK_VICT_SHIFT) 72 #define MMU_LOCK_VICT(x) \ 73 ((x & MMU_LOCK_VICT_MASK) >> MMU_LOCK_VICT_SHIFT) 74 75 struct iotlb_lock { 76 short base; 77 short vict; 78 }; 79 80 static struct platform_driver omap_iommu_driver; 81 static struct kmem_cache *iopte_cachep; 82 83 /** 84 * to_omap_domain - Get struct omap_iommu_domain from generic iommu_domain 85 * @dom: generic iommu domain handle 86 **/ 87 static struct omap_iommu_domain *to_omap_domain(struct iommu_domain *dom) 88 { 89 return container_of(dom, struct omap_iommu_domain, domain); 90 } 91 92 /** 93 * omap_iommu_save_ctx - Save registers for pm off-mode support 94 * @dev: client device 95 **/ 96 void omap_iommu_save_ctx(struct device *dev) 97 { 98 struct omap_iommu *obj = dev_to_omap_iommu(dev); 99 u32 *p = obj->ctx; 100 int i; 101 102 for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) { 103 p[i] = iommu_read_reg(obj, i * sizeof(u32)); 104 dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]); 105 } 106 } 107 EXPORT_SYMBOL_GPL(omap_iommu_save_ctx); 108 109 /** 110 * omap_iommu_restore_ctx - Restore registers for pm off-mode support 111 * @dev: client device 112 **/ 113 void omap_iommu_restore_ctx(struct device *dev) 114 { 115 struct omap_iommu *obj = dev_to_omap_iommu(dev); 116 u32 *p = obj->ctx; 117 int i; 118 119 for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) { 120 iommu_write_reg(obj, p[i], i * sizeof(u32)); 121 dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]); 122 } 123 } 124 EXPORT_SYMBOL_GPL(omap_iommu_restore_ctx); 125 126 static void __iommu_set_twl(struct omap_iommu *obj, bool on) 127 { 128 u32 l = iommu_read_reg(obj, MMU_CNTL); 129 130 if (on) 131 iommu_write_reg(obj, MMU_IRQ_TWL_MASK, MMU_IRQENABLE); 132 else 133 iommu_write_reg(obj, MMU_IRQ_TLB_MISS_MASK, MMU_IRQENABLE); 134 135 l &= ~MMU_CNTL_MASK; 136 if (on) 137 l |= (MMU_CNTL_MMU_EN | MMU_CNTL_TWL_EN); 138 else 139 l |= (MMU_CNTL_MMU_EN); 140 141 iommu_write_reg(obj, l, MMU_CNTL); 142 } 143 144 static int omap2_iommu_enable(struct omap_iommu *obj) 145 { 146 u32 l, pa; 147 148 if (!obj->iopgd || !IS_ALIGNED((u32)obj->iopgd, SZ_16K)) 149 return -EINVAL; 150 151 pa = virt_to_phys(obj->iopgd); 152 if (!IS_ALIGNED(pa, SZ_16K)) 153 return -EINVAL; 154 155 l = iommu_read_reg(obj, MMU_REVISION); 156 dev_info(obj->dev, "%s: version %d.%d\n", obj->name, 157 (l >> 4) & 0xf, l & 0xf); 158 159 iommu_write_reg(obj, pa, MMU_TTB); 160 161 if (obj->has_bus_err_back) 162 iommu_write_reg(obj, MMU_GP_REG_BUS_ERR_BACK_EN, MMU_GP_REG); 163 164 __iommu_set_twl(obj, true); 165 166 return 0; 167 } 168 169 static void omap2_iommu_disable(struct omap_iommu *obj) 170 { 171 u32 l = iommu_read_reg(obj, MMU_CNTL); 172 173 l &= ~MMU_CNTL_MASK; 174 iommu_write_reg(obj, l, MMU_CNTL); 175 176 dev_dbg(obj->dev, "%s is shutting down\n", obj->name); 177 } 178 179 static int iommu_enable(struct omap_iommu *obj) 180 { 181 int err; 182 struct platform_device *pdev = to_platform_device(obj->dev); 183 struct iommu_platform_data *pdata = dev_get_platdata(&pdev->dev); 184 185 if (pdata && pdata->deassert_reset) { 186 err = pdata->deassert_reset(pdev, pdata->reset_name); 187 if (err) { 188 dev_err(obj->dev, "deassert_reset failed: %d\n", err); 189 return err; 190 } 191 } 192 193 pm_runtime_get_sync(obj->dev); 194 195 err = omap2_iommu_enable(obj); 196 197 return err; 198 } 199 200 static void iommu_disable(struct omap_iommu *obj) 201 { 202 struct platform_device *pdev = to_platform_device(obj->dev); 203 struct iommu_platform_data *pdata = dev_get_platdata(&pdev->dev); 204 205 omap2_iommu_disable(obj); 206 207 pm_runtime_put_sync(obj->dev); 208 209 if (pdata && pdata->assert_reset) 210 pdata->assert_reset(pdev, pdata->reset_name); 211 } 212 213 /* 214 * TLB operations 215 */ 216 static inline int iotlb_cr_valid(struct cr_regs *cr) 217 { 218 if (!cr) 219 return -EINVAL; 220 221 return cr->cam & MMU_CAM_V; 222 } 223 224 static u32 iotlb_cr_to_virt(struct cr_regs *cr) 225 { 226 u32 page_size = cr->cam & MMU_CAM_PGSZ_MASK; 227 u32 mask = get_cam_va_mask(cr->cam & page_size); 228 229 return cr->cam & mask; 230 } 231 232 static u32 get_iopte_attr(struct iotlb_entry *e) 233 { 234 u32 attr; 235 236 attr = e->mixed << 5; 237 attr |= e->endian; 238 attr |= e->elsz >> 3; 239 attr <<= (((e->pgsz == MMU_CAM_PGSZ_4K) || 240 (e->pgsz == MMU_CAM_PGSZ_64K)) ? 0 : 6); 241 return attr; 242 } 243 244 static u32 iommu_report_fault(struct omap_iommu *obj, u32 *da) 245 { 246 u32 status, fault_addr; 247 248 status = iommu_read_reg(obj, MMU_IRQSTATUS); 249 status &= MMU_IRQ_MASK; 250 if (!status) { 251 *da = 0; 252 return 0; 253 } 254 255 fault_addr = iommu_read_reg(obj, MMU_FAULT_AD); 256 *da = fault_addr; 257 258 iommu_write_reg(obj, status, MMU_IRQSTATUS); 259 260 return status; 261 } 262 263 static void iotlb_lock_get(struct omap_iommu *obj, struct iotlb_lock *l) 264 { 265 u32 val; 266 267 val = iommu_read_reg(obj, MMU_LOCK); 268 269 l->base = MMU_LOCK_BASE(val); 270 l->vict = MMU_LOCK_VICT(val); 271 272 } 273 274 static void iotlb_lock_set(struct omap_iommu *obj, struct iotlb_lock *l) 275 { 276 u32 val; 277 278 val = (l->base << MMU_LOCK_BASE_SHIFT); 279 val |= (l->vict << MMU_LOCK_VICT_SHIFT); 280 281 iommu_write_reg(obj, val, MMU_LOCK); 282 } 283 284 static void iotlb_read_cr(struct omap_iommu *obj, struct cr_regs *cr) 285 { 286 cr->cam = iommu_read_reg(obj, MMU_READ_CAM); 287 cr->ram = iommu_read_reg(obj, MMU_READ_RAM); 288 } 289 290 static void iotlb_load_cr(struct omap_iommu *obj, struct cr_regs *cr) 291 { 292 iommu_write_reg(obj, cr->cam | MMU_CAM_V, MMU_CAM); 293 iommu_write_reg(obj, cr->ram, MMU_RAM); 294 295 iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY); 296 iommu_write_reg(obj, 1, MMU_LD_TLB); 297 } 298 299 /* only used in iotlb iteration for-loop */ 300 static struct cr_regs __iotlb_read_cr(struct omap_iommu *obj, int n) 301 { 302 struct cr_regs cr; 303 struct iotlb_lock l; 304 305 iotlb_lock_get(obj, &l); 306 l.vict = n; 307 iotlb_lock_set(obj, &l); 308 iotlb_read_cr(obj, &cr); 309 310 return cr; 311 } 312 313 #ifdef PREFETCH_IOTLB 314 static struct cr_regs *iotlb_alloc_cr(struct omap_iommu *obj, 315 struct iotlb_entry *e) 316 { 317 struct cr_regs *cr; 318 319 if (!e) 320 return NULL; 321 322 if (e->da & ~(get_cam_va_mask(e->pgsz))) { 323 dev_err(obj->dev, "%s:\twrong alignment: %08x\n", __func__, 324 e->da); 325 return ERR_PTR(-EINVAL); 326 } 327 328 cr = kmalloc(sizeof(*cr), GFP_KERNEL); 329 if (!cr) 330 return ERR_PTR(-ENOMEM); 331 332 cr->cam = (e->da & MMU_CAM_VATAG_MASK) | e->prsvd | e->pgsz | e->valid; 333 cr->ram = e->pa | e->endian | e->elsz | e->mixed; 334 335 return cr; 336 } 337 338 /** 339 * load_iotlb_entry - Set an iommu tlb entry 340 * @obj: target iommu 341 * @e: an iommu tlb entry info 342 **/ 343 static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e) 344 { 345 int err = 0; 346 struct iotlb_lock l; 347 struct cr_regs *cr; 348 349 if (!obj || !obj->nr_tlb_entries || !e) 350 return -EINVAL; 351 352 pm_runtime_get_sync(obj->dev); 353 354 iotlb_lock_get(obj, &l); 355 if (l.base == obj->nr_tlb_entries) { 356 dev_warn(obj->dev, "%s: preserve entries full\n", __func__); 357 err = -EBUSY; 358 goto out; 359 } 360 if (!e->prsvd) { 361 int i; 362 struct cr_regs tmp; 363 364 for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, tmp) 365 if (!iotlb_cr_valid(&tmp)) 366 break; 367 368 if (i == obj->nr_tlb_entries) { 369 dev_dbg(obj->dev, "%s: full: no entry\n", __func__); 370 err = -EBUSY; 371 goto out; 372 } 373 374 iotlb_lock_get(obj, &l); 375 } else { 376 l.vict = l.base; 377 iotlb_lock_set(obj, &l); 378 } 379 380 cr = iotlb_alloc_cr(obj, e); 381 if (IS_ERR(cr)) { 382 pm_runtime_put_sync(obj->dev); 383 return PTR_ERR(cr); 384 } 385 386 iotlb_load_cr(obj, cr); 387 kfree(cr); 388 389 if (e->prsvd) 390 l.base++; 391 /* increment victim for next tlb load */ 392 if (++l.vict == obj->nr_tlb_entries) 393 l.vict = l.base; 394 iotlb_lock_set(obj, &l); 395 out: 396 pm_runtime_put_sync(obj->dev); 397 return err; 398 } 399 400 #else /* !PREFETCH_IOTLB */ 401 402 static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e) 403 { 404 return 0; 405 } 406 407 #endif /* !PREFETCH_IOTLB */ 408 409 static int prefetch_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e) 410 { 411 return load_iotlb_entry(obj, e); 412 } 413 414 /** 415 * flush_iotlb_page - Clear an iommu tlb entry 416 * @obj: target iommu 417 * @da: iommu device virtual address 418 * 419 * Clear an iommu tlb entry which includes 'da' address. 420 **/ 421 static void flush_iotlb_page(struct omap_iommu *obj, u32 da) 422 { 423 int i; 424 struct cr_regs cr; 425 426 pm_runtime_get_sync(obj->dev); 427 428 for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, cr) { 429 u32 start; 430 size_t bytes; 431 432 if (!iotlb_cr_valid(&cr)) 433 continue; 434 435 start = iotlb_cr_to_virt(&cr); 436 bytes = iopgsz_to_bytes(cr.cam & 3); 437 438 if ((start <= da) && (da < start + bytes)) { 439 dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n", 440 __func__, start, da, bytes); 441 iotlb_load_cr(obj, &cr); 442 iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY); 443 break; 444 } 445 } 446 pm_runtime_put_sync(obj->dev); 447 448 if (i == obj->nr_tlb_entries) 449 dev_dbg(obj->dev, "%s: no page for %08x\n", __func__, da); 450 } 451 452 /** 453 * flush_iotlb_all - Clear all iommu tlb entries 454 * @obj: target iommu 455 **/ 456 static void flush_iotlb_all(struct omap_iommu *obj) 457 { 458 struct iotlb_lock l; 459 460 pm_runtime_get_sync(obj->dev); 461 462 l.base = 0; 463 l.vict = 0; 464 iotlb_lock_set(obj, &l); 465 466 iommu_write_reg(obj, 1, MMU_GFLUSH); 467 468 pm_runtime_put_sync(obj->dev); 469 } 470 471 #ifdef CONFIG_OMAP_IOMMU_DEBUG 472 473 #define pr_reg(name) \ 474 do { \ 475 ssize_t bytes; \ 476 const char *str = "%20s: %08x\n"; \ 477 const int maxcol = 32; \ 478 bytes = snprintf(p, maxcol, str, __stringify(name), \ 479 iommu_read_reg(obj, MMU_##name)); \ 480 p += bytes; \ 481 len -= bytes; \ 482 if (len < maxcol) \ 483 goto out; \ 484 } while (0) 485 486 static ssize_t 487 omap2_iommu_dump_ctx(struct omap_iommu *obj, char *buf, ssize_t len) 488 { 489 char *p = buf; 490 491 pr_reg(REVISION); 492 pr_reg(IRQSTATUS); 493 pr_reg(IRQENABLE); 494 pr_reg(WALKING_ST); 495 pr_reg(CNTL); 496 pr_reg(FAULT_AD); 497 pr_reg(TTB); 498 pr_reg(LOCK); 499 pr_reg(LD_TLB); 500 pr_reg(CAM); 501 pr_reg(RAM); 502 pr_reg(GFLUSH); 503 pr_reg(FLUSH_ENTRY); 504 pr_reg(READ_CAM); 505 pr_reg(READ_RAM); 506 pr_reg(EMU_FAULT_AD); 507 out: 508 return p - buf; 509 } 510 511 ssize_t omap_iommu_dump_ctx(struct omap_iommu *obj, char *buf, ssize_t bytes) 512 { 513 if (!obj || !buf) 514 return -EINVAL; 515 516 pm_runtime_get_sync(obj->dev); 517 518 bytes = omap2_iommu_dump_ctx(obj, buf, bytes); 519 520 pm_runtime_put_sync(obj->dev); 521 522 return bytes; 523 } 524 525 static int 526 __dump_tlb_entries(struct omap_iommu *obj, struct cr_regs *crs, int num) 527 { 528 int i; 529 struct iotlb_lock saved; 530 struct cr_regs tmp; 531 struct cr_regs *p = crs; 532 533 pm_runtime_get_sync(obj->dev); 534 iotlb_lock_get(obj, &saved); 535 536 for_each_iotlb_cr(obj, num, i, tmp) { 537 if (!iotlb_cr_valid(&tmp)) 538 continue; 539 *p++ = tmp; 540 } 541 542 iotlb_lock_set(obj, &saved); 543 pm_runtime_put_sync(obj->dev); 544 545 return p - crs; 546 } 547 548 /** 549 * iotlb_dump_cr - Dump an iommu tlb entry into buf 550 * @obj: target iommu 551 * @cr: contents of cam and ram register 552 * @buf: output buffer 553 **/ 554 static ssize_t iotlb_dump_cr(struct omap_iommu *obj, struct cr_regs *cr, 555 char *buf) 556 { 557 char *p = buf; 558 559 /* FIXME: Need more detail analysis of cam/ram */ 560 p += sprintf(p, "%08x %08x %01x\n", cr->cam, cr->ram, 561 (cr->cam & MMU_CAM_P) ? 1 : 0); 562 563 return p - buf; 564 } 565 566 /** 567 * omap_dump_tlb_entries - dump cr arrays to given buffer 568 * @obj: target iommu 569 * @buf: output buffer 570 **/ 571 size_t omap_dump_tlb_entries(struct omap_iommu *obj, char *buf, ssize_t bytes) 572 { 573 int i, num; 574 struct cr_regs *cr; 575 char *p = buf; 576 577 num = bytes / sizeof(*cr); 578 num = min(obj->nr_tlb_entries, num); 579 580 cr = kcalloc(num, sizeof(*cr), GFP_KERNEL); 581 if (!cr) 582 return 0; 583 584 num = __dump_tlb_entries(obj, cr, num); 585 for (i = 0; i < num; i++) 586 p += iotlb_dump_cr(obj, cr + i, p); 587 kfree(cr); 588 589 return p - buf; 590 } 591 592 #endif /* CONFIG_OMAP_IOMMU_DEBUG */ 593 594 /* 595 * H/W pagetable operations 596 */ 597 static void flush_iopgd_range(u32 *first, u32 *last) 598 { 599 /* FIXME: L2 cache should be taken care of if it exists */ 600 do { 601 asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pgd" 602 : : "r" (first)); 603 first += L1_CACHE_BYTES / sizeof(*first); 604 } while (first <= last); 605 } 606 607 static void flush_iopte_range(u32 *first, u32 *last) 608 { 609 /* FIXME: L2 cache should be taken care of if it exists */ 610 do { 611 asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pte" 612 : : "r" (first)); 613 first += L1_CACHE_BYTES / sizeof(*first); 614 } while (first <= last); 615 } 616 617 static void iopte_free(u32 *iopte) 618 { 619 /* Note: freed iopte's must be clean ready for re-use */ 620 if (iopte) 621 kmem_cache_free(iopte_cachep, iopte); 622 } 623 624 static u32 *iopte_alloc(struct omap_iommu *obj, u32 *iopgd, u32 da) 625 { 626 u32 *iopte; 627 628 /* a table has already existed */ 629 if (*iopgd) 630 goto pte_ready; 631 632 /* 633 * do the allocation outside the page table lock 634 */ 635 spin_unlock(&obj->page_table_lock); 636 iopte = kmem_cache_zalloc(iopte_cachep, GFP_KERNEL); 637 spin_lock(&obj->page_table_lock); 638 639 if (!*iopgd) { 640 if (!iopte) 641 return ERR_PTR(-ENOMEM); 642 643 *iopgd = virt_to_phys(iopte) | IOPGD_TABLE; 644 flush_iopgd_range(iopgd, iopgd); 645 646 dev_vdbg(obj->dev, "%s: a new pte:%p\n", __func__, iopte); 647 } else { 648 /* We raced, free the reduniovant table */ 649 iopte_free(iopte); 650 } 651 652 pte_ready: 653 iopte = iopte_offset(iopgd, da); 654 655 dev_vdbg(obj->dev, 656 "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n", 657 __func__, da, iopgd, *iopgd, iopte, *iopte); 658 659 return iopte; 660 } 661 662 static int iopgd_alloc_section(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) 663 { 664 u32 *iopgd = iopgd_offset(obj, da); 665 666 if ((da | pa) & ~IOSECTION_MASK) { 667 dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n", 668 __func__, da, pa, IOSECTION_SIZE); 669 return -EINVAL; 670 } 671 672 *iopgd = (pa & IOSECTION_MASK) | prot | IOPGD_SECTION; 673 flush_iopgd_range(iopgd, iopgd); 674 return 0; 675 } 676 677 static int iopgd_alloc_super(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) 678 { 679 u32 *iopgd = iopgd_offset(obj, da); 680 int i; 681 682 if ((da | pa) & ~IOSUPER_MASK) { 683 dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n", 684 __func__, da, pa, IOSUPER_SIZE); 685 return -EINVAL; 686 } 687 688 for (i = 0; i < 16; i++) 689 *(iopgd + i) = (pa & IOSUPER_MASK) | prot | IOPGD_SUPER; 690 flush_iopgd_range(iopgd, iopgd + 15); 691 return 0; 692 } 693 694 static int iopte_alloc_page(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) 695 { 696 u32 *iopgd = iopgd_offset(obj, da); 697 u32 *iopte = iopte_alloc(obj, iopgd, da); 698 699 if (IS_ERR(iopte)) 700 return PTR_ERR(iopte); 701 702 *iopte = (pa & IOPAGE_MASK) | prot | IOPTE_SMALL; 703 flush_iopte_range(iopte, iopte); 704 705 dev_vdbg(obj->dev, "%s: da:%08x pa:%08x pte:%p *pte:%08x\n", 706 __func__, da, pa, iopte, *iopte); 707 708 return 0; 709 } 710 711 static int iopte_alloc_large(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) 712 { 713 u32 *iopgd = iopgd_offset(obj, da); 714 u32 *iopte = iopte_alloc(obj, iopgd, da); 715 int i; 716 717 if ((da | pa) & ~IOLARGE_MASK) { 718 dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n", 719 __func__, da, pa, IOLARGE_SIZE); 720 return -EINVAL; 721 } 722 723 if (IS_ERR(iopte)) 724 return PTR_ERR(iopte); 725 726 for (i = 0; i < 16; i++) 727 *(iopte + i) = (pa & IOLARGE_MASK) | prot | IOPTE_LARGE; 728 flush_iopte_range(iopte, iopte + 15); 729 return 0; 730 } 731 732 static int 733 iopgtable_store_entry_core(struct omap_iommu *obj, struct iotlb_entry *e) 734 { 735 int (*fn)(struct omap_iommu *, u32, u32, u32); 736 u32 prot; 737 int err; 738 739 if (!obj || !e) 740 return -EINVAL; 741 742 switch (e->pgsz) { 743 case MMU_CAM_PGSZ_16M: 744 fn = iopgd_alloc_super; 745 break; 746 case MMU_CAM_PGSZ_1M: 747 fn = iopgd_alloc_section; 748 break; 749 case MMU_CAM_PGSZ_64K: 750 fn = iopte_alloc_large; 751 break; 752 case MMU_CAM_PGSZ_4K: 753 fn = iopte_alloc_page; 754 break; 755 default: 756 fn = NULL; 757 BUG(); 758 break; 759 } 760 761 prot = get_iopte_attr(e); 762 763 spin_lock(&obj->page_table_lock); 764 err = fn(obj, e->da, e->pa, prot); 765 spin_unlock(&obj->page_table_lock); 766 767 return err; 768 } 769 770 /** 771 * omap_iopgtable_store_entry - Make an iommu pte entry 772 * @obj: target iommu 773 * @e: an iommu tlb entry info 774 **/ 775 static int 776 omap_iopgtable_store_entry(struct omap_iommu *obj, struct iotlb_entry *e) 777 { 778 int err; 779 780 flush_iotlb_page(obj, e->da); 781 err = iopgtable_store_entry_core(obj, e); 782 if (!err) 783 prefetch_iotlb_entry(obj, e); 784 return err; 785 } 786 787 /** 788 * iopgtable_lookup_entry - Lookup an iommu pte entry 789 * @obj: target iommu 790 * @da: iommu device virtual address 791 * @ppgd: iommu pgd entry pointer to be returned 792 * @ppte: iommu pte entry pointer to be returned 793 **/ 794 static void 795 iopgtable_lookup_entry(struct omap_iommu *obj, u32 da, u32 **ppgd, u32 **ppte) 796 { 797 u32 *iopgd, *iopte = NULL; 798 799 iopgd = iopgd_offset(obj, da); 800 if (!*iopgd) 801 goto out; 802 803 if (iopgd_is_table(*iopgd)) 804 iopte = iopte_offset(iopgd, da); 805 out: 806 *ppgd = iopgd; 807 *ppte = iopte; 808 } 809 810 static size_t iopgtable_clear_entry_core(struct omap_iommu *obj, u32 da) 811 { 812 size_t bytes; 813 u32 *iopgd = iopgd_offset(obj, da); 814 int nent = 1; 815 816 if (!*iopgd) 817 return 0; 818 819 if (iopgd_is_table(*iopgd)) { 820 int i; 821 u32 *iopte = iopte_offset(iopgd, da); 822 823 bytes = IOPTE_SIZE; 824 if (*iopte & IOPTE_LARGE) { 825 nent *= 16; 826 /* rewind to the 1st entry */ 827 iopte = iopte_offset(iopgd, (da & IOLARGE_MASK)); 828 } 829 bytes *= nent; 830 memset(iopte, 0, nent * sizeof(*iopte)); 831 flush_iopte_range(iopte, iopte + (nent - 1) * sizeof(*iopte)); 832 833 /* 834 * do table walk to check if this table is necessary or not 835 */ 836 iopte = iopte_offset(iopgd, 0); 837 for (i = 0; i < PTRS_PER_IOPTE; i++) 838 if (iopte[i]) 839 goto out; 840 841 iopte_free(iopte); 842 nent = 1; /* for the next L1 entry */ 843 } else { 844 bytes = IOPGD_SIZE; 845 if ((*iopgd & IOPGD_SUPER) == IOPGD_SUPER) { 846 nent *= 16; 847 /* rewind to the 1st entry */ 848 iopgd = iopgd_offset(obj, (da & IOSUPER_MASK)); 849 } 850 bytes *= nent; 851 } 852 memset(iopgd, 0, nent * sizeof(*iopgd)); 853 flush_iopgd_range(iopgd, iopgd + (nent - 1) * sizeof(*iopgd)); 854 out: 855 return bytes; 856 } 857 858 /** 859 * iopgtable_clear_entry - Remove an iommu pte entry 860 * @obj: target iommu 861 * @da: iommu device virtual address 862 **/ 863 static size_t iopgtable_clear_entry(struct omap_iommu *obj, u32 da) 864 { 865 size_t bytes; 866 867 spin_lock(&obj->page_table_lock); 868 869 bytes = iopgtable_clear_entry_core(obj, da); 870 flush_iotlb_page(obj, da); 871 872 spin_unlock(&obj->page_table_lock); 873 874 return bytes; 875 } 876 877 static void iopgtable_clear_entry_all(struct omap_iommu *obj) 878 { 879 int i; 880 881 spin_lock(&obj->page_table_lock); 882 883 for (i = 0; i < PTRS_PER_IOPGD; i++) { 884 u32 da; 885 u32 *iopgd; 886 887 da = i << IOPGD_SHIFT; 888 iopgd = iopgd_offset(obj, da); 889 890 if (!*iopgd) 891 continue; 892 893 if (iopgd_is_table(*iopgd)) 894 iopte_free(iopte_offset(iopgd, 0)); 895 896 *iopgd = 0; 897 flush_iopgd_range(iopgd, iopgd); 898 } 899 900 flush_iotlb_all(obj); 901 902 spin_unlock(&obj->page_table_lock); 903 } 904 905 /* 906 * Device IOMMU generic operations 907 */ 908 static irqreturn_t iommu_fault_handler(int irq, void *data) 909 { 910 u32 da, errs; 911 u32 *iopgd, *iopte; 912 struct omap_iommu *obj = data; 913 struct iommu_domain *domain = obj->domain; 914 struct omap_iommu_domain *omap_domain = to_omap_domain(domain); 915 916 if (!omap_domain->iommu_dev) 917 return IRQ_NONE; 918 919 errs = iommu_report_fault(obj, &da); 920 if (errs == 0) 921 return IRQ_HANDLED; 922 923 /* Fault callback or TLB/PTE Dynamic loading */ 924 if (!report_iommu_fault(domain, obj->dev, da, 0)) 925 return IRQ_HANDLED; 926 927 iommu_disable(obj); 928 929 iopgd = iopgd_offset(obj, da); 930 931 if (!iopgd_is_table(*iopgd)) { 932 dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:px%08x\n", 933 obj->name, errs, da, iopgd, *iopgd); 934 return IRQ_NONE; 935 } 936 937 iopte = iopte_offset(iopgd, da); 938 939 dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:0x%08x pte:0x%p *pte:0x%08x\n", 940 obj->name, errs, da, iopgd, *iopgd, iopte, *iopte); 941 942 return IRQ_NONE; 943 } 944 945 static int device_match_by_alias(struct device *dev, void *data) 946 { 947 struct omap_iommu *obj = to_iommu(dev); 948 const char *name = data; 949 950 pr_debug("%s: %s %s\n", __func__, obj->name, name); 951 952 return strcmp(obj->name, name) == 0; 953 } 954 955 /** 956 * omap_iommu_attach() - attach iommu device to an iommu domain 957 * @name: name of target omap iommu device 958 * @iopgd: page table 959 **/ 960 static struct omap_iommu *omap_iommu_attach(const char *name, u32 *iopgd) 961 { 962 int err; 963 struct device *dev; 964 struct omap_iommu *obj; 965 966 dev = driver_find_device(&omap_iommu_driver.driver, NULL, 967 (void *)name, 968 device_match_by_alias); 969 if (!dev) 970 return ERR_PTR(-ENODEV); 971 972 obj = to_iommu(dev); 973 974 spin_lock(&obj->iommu_lock); 975 976 obj->iopgd = iopgd; 977 err = iommu_enable(obj); 978 if (err) 979 goto err_enable; 980 flush_iotlb_all(obj); 981 982 spin_unlock(&obj->iommu_lock); 983 984 dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name); 985 return obj; 986 987 err_enable: 988 spin_unlock(&obj->iommu_lock); 989 return ERR_PTR(err); 990 } 991 992 /** 993 * omap_iommu_detach - release iommu device 994 * @obj: target iommu 995 **/ 996 static void omap_iommu_detach(struct omap_iommu *obj) 997 { 998 if (!obj || IS_ERR(obj)) 999 return; 1000 1001 spin_lock(&obj->iommu_lock); 1002 1003 iommu_disable(obj); 1004 obj->iopgd = NULL; 1005 1006 spin_unlock(&obj->iommu_lock); 1007 1008 dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name); 1009 } 1010 1011 /* 1012 * OMAP Device MMU(IOMMU) detection 1013 */ 1014 static int omap_iommu_probe(struct platform_device *pdev) 1015 { 1016 int err = -ENODEV; 1017 int irq; 1018 struct omap_iommu *obj; 1019 struct resource *res; 1020 struct iommu_platform_data *pdata = dev_get_platdata(&pdev->dev); 1021 struct device_node *of = pdev->dev.of_node; 1022 1023 obj = devm_kzalloc(&pdev->dev, sizeof(*obj) + MMU_REG_SIZE, GFP_KERNEL); 1024 if (!obj) 1025 return -ENOMEM; 1026 1027 if (of) { 1028 obj->name = dev_name(&pdev->dev); 1029 obj->nr_tlb_entries = 32; 1030 err = of_property_read_u32(of, "ti,#tlb-entries", 1031 &obj->nr_tlb_entries); 1032 if (err && err != -EINVAL) 1033 return err; 1034 if (obj->nr_tlb_entries != 32 && obj->nr_tlb_entries != 8) 1035 return -EINVAL; 1036 if (of_find_property(of, "ti,iommu-bus-err-back", NULL)) 1037 obj->has_bus_err_back = MMU_GP_REG_BUS_ERR_BACK_EN; 1038 } else { 1039 obj->nr_tlb_entries = pdata->nr_tlb_entries; 1040 obj->name = pdata->name; 1041 } 1042 1043 obj->dev = &pdev->dev; 1044 obj->ctx = (void *)obj + sizeof(*obj); 1045 1046 spin_lock_init(&obj->iommu_lock); 1047 spin_lock_init(&obj->page_table_lock); 1048 1049 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1050 obj->regbase = devm_ioremap_resource(obj->dev, res); 1051 if (IS_ERR(obj->regbase)) 1052 return PTR_ERR(obj->regbase); 1053 1054 irq = platform_get_irq(pdev, 0); 1055 if (irq < 0) 1056 return -ENODEV; 1057 1058 err = devm_request_irq(obj->dev, irq, iommu_fault_handler, IRQF_SHARED, 1059 dev_name(obj->dev), obj); 1060 if (err < 0) 1061 return err; 1062 platform_set_drvdata(pdev, obj); 1063 1064 pm_runtime_irq_safe(obj->dev); 1065 pm_runtime_enable(obj->dev); 1066 1067 omap_iommu_debugfs_add(obj); 1068 1069 dev_info(&pdev->dev, "%s registered\n", obj->name); 1070 return 0; 1071 } 1072 1073 static int omap_iommu_remove(struct platform_device *pdev) 1074 { 1075 struct omap_iommu *obj = platform_get_drvdata(pdev); 1076 1077 iopgtable_clear_entry_all(obj); 1078 omap_iommu_debugfs_remove(obj); 1079 1080 pm_runtime_disable(obj->dev); 1081 1082 dev_info(&pdev->dev, "%s removed\n", obj->name); 1083 return 0; 1084 } 1085 1086 static const struct of_device_id omap_iommu_of_match[] = { 1087 { .compatible = "ti,omap2-iommu" }, 1088 { .compatible = "ti,omap4-iommu" }, 1089 { .compatible = "ti,dra7-iommu" }, 1090 {}, 1091 }; 1092 MODULE_DEVICE_TABLE(of, omap_iommu_of_match); 1093 1094 static struct platform_driver omap_iommu_driver = { 1095 .probe = omap_iommu_probe, 1096 .remove = omap_iommu_remove, 1097 .driver = { 1098 .name = "omap-iommu", 1099 .of_match_table = of_match_ptr(omap_iommu_of_match), 1100 }, 1101 }; 1102 1103 static void iopte_cachep_ctor(void *iopte) 1104 { 1105 clean_dcache_area(iopte, IOPTE_TABLE_SIZE); 1106 } 1107 1108 static u32 iotlb_init_entry(struct iotlb_entry *e, u32 da, u32 pa, int pgsz) 1109 { 1110 memset(e, 0, sizeof(*e)); 1111 1112 e->da = da; 1113 e->pa = pa; 1114 e->valid = MMU_CAM_V; 1115 e->pgsz = pgsz; 1116 e->endian = MMU_RAM_ENDIAN_LITTLE; 1117 e->elsz = MMU_RAM_ELSZ_8; 1118 e->mixed = 0; 1119 1120 return iopgsz_to_bytes(e->pgsz); 1121 } 1122 1123 static int omap_iommu_map(struct iommu_domain *domain, unsigned long da, 1124 phys_addr_t pa, size_t bytes, int prot) 1125 { 1126 struct omap_iommu_domain *omap_domain = to_omap_domain(domain); 1127 struct omap_iommu *oiommu = omap_domain->iommu_dev; 1128 struct device *dev = oiommu->dev; 1129 struct iotlb_entry e; 1130 int omap_pgsz; 1131 u32 ret; 1132 1133 omap_pgsz = bytes_to_iopgsz(bytes); 1134 if (omap_pgsz < 0) { 1135 dev_err(dev, "invalid size to map: %d\n", bytes); 1136 return -EINVAL; 1137 } 1138 1139 dev_dbg(dev, "mapping da 0x%lx to pa %pa size 0x%x\n", da, &pa, bytes); 1140 1141 iotlb_init_entry(&e, da, pa, omap_pgsz); 1142 1143 ret = omap_iopgtable_store_entry(oiommu, &e); 1144 if (ret) 1145 dev_err(dev, "omap_iopgtable_store_entry failed: %d\n", ret); 1146 1147 return ret; 1148 } 1149 1150 static size_t omap_iommu_unmap(struct iommu_domain *domain, unsigned long da, 1151 size_t size) 1152 { 1153 struct omap_iommu_domain *omap_domain = to_omap_domain(domain); 1154 struct omap_iommu *oiommu = omap_domain->iommu_dev; 1155 struct device *dev = oiommu->dev; 1156 1157 dev_dbg(dev, "unmapping da 0x%lx size %u\n", da, size); 1158 1159 return iopgtable_clear_entry(oiommu, da); 1160 } 1161 1162 static int 1163 omap_iommu_attach_dev(struct iommu_domain *domain, struct device *dev) 1164 { 1165 struct omap_iommu_domain *omap_domain = to_omap_domain(domain); 1166 struct omap_iommu *oiommu; 1167 struct omap_iommu_arch_data *arch_data = dev->archdata.iommu; 1168 int ret = 0; 1169 1170 if (!arch_data || !arch_data->name) { 1171 dev_err(dev, "device doesn't have an associated iommu\n"); 1172 return -EINVAL; 1173 } 1174 1175 spin_lock(&omap_domain->lock); 1176 1177 /* only a single device is supported per domain for now */ 1178 if (omap_domain->iommu_dev) { 1179 dev_err(dev, "iommu domain is already attached\n"); 1180 ret = -EBUSY; 1181 goto out; 1182 } 1183 1184 /* get a handle to and enable the omap iommu */ 1185 oiommu = omap_iommu_attach(arch_data->name, omap_domain->pgtable); 1186 if (IS_ERR(oiommu)) { 1187 ret = PTR_ERR(oiommu); 1188 dev_err(dev, "can't get omap iommu: %d\n", ret); 1189 goto out; 1190 } 1191 1192 omap_domain->iommu_dev = arch_data->iommu_dev = oiommu; 1193 omap_domain->dev = dev; 1194 oiommu->domain = domain; 1195 1196 out: 1197 spin_unlock(&omap_domain->lock); 1198 return ret; 1199 } 1200 1201 static void _omap_iommu_detach_dev(struct omap_iommu_domain *omap_domain, 1202 struct device *dev) 1203 { 1204 struct omap_iommu *oiommu = dev_to_omap_iommu(dev); 1205 struct omap_iommu_arch_data *arch_data = dev->archdata.iommu; 1206 1207 /* only a single device is supported per domain for now */ 1208 if (omap_domain->iommu_dev != oiommu) { 1209 dev_err(dev, "invalid iommu device\n"); 1210 return; 1211 } 1212 1213 iopgtable_clear_entry_all(oiommu); 1214 1215 omap_iommu_detach(oiommu); 1216 1217 omap_domain->iommu_dev = arch_data->iommu_dev = NULL; 1218 omap_domain->dev = NULL; 1219 oiommu->domain = NULL; 1220 } 1221 1222 static void omap_iommu_detach_dev(struct iommu_domain *domain, 1223 struct device *dev) 1224 { 1225 struct omap_iommu_domain *omap_domain = to_omap_domain(domain); 1226 1227 spin_lock(&omap_domain->lock); 1228 _omap_iommu_detach_dev(omap_domain, dev); 1229 spin_unlock(&omap_domain->lock); 1230 } 1231 1232 static struct iommu_domain *omap_iommu_domain_alloc(unsigned type) 1233 { 1234 struct omap_iommu_domain *omap_domain; 1235 1236 if (type != IOMMU_DOMAIN_UNMANAGED) 1237 return NULL; 1238 1239 omap_domain = kzalloc(sizeof(*omap_domain), GFP_KERNEL); 1240 if (!omap_domain) { 1241 pr_err("kzalloc failed\n"); 1242 goto out; 1243 } 1244 1245 omap_domain->pgtable = kzalloc(IOPGD_TABLE_SIZE, GFP_KERNEL); 1246 if (!omap_domain->pgtable) { 1247 pr_err("kzalloc failed\n"); 1248 goto fail_nomem; 1249 } 1250 1251 /* 1252 * should never fail, but please keep this around to ensure 1253 * we keep the hardware happy 1254 */ 1255 BUG_ON(!IS_ALIGNED((long)omap_domain->pgtable, IOPGD_TABLE_SIZE)); 1256 1257 clean_dcache_area(omap_domain->pgtable, IOPGD_TABLE_SIZE); 1258 spin_lock_init(&omap_domain->lock); 1259 1260 omap_domain->domain.geometry.aperture_start = 0; 1261 omap_domain->domain.geometry.aperture_end = (1ULL << 32) - 1; 1262 omap_domain->domain.geometry.force_aperture = true; 1263 1264 return &omap_domain->domain; 1265 1266 fail_nomem: 1267 kfree(omap_domain); 1268 out: 1269 return NULL; 1270 } 1271 1272 static void omap_iommu_domain_free(struct iommu_domain *domain) 1273 { 1274 struct omap_iommu_domain *omap_domain = to_omap_domain(domain); 1275 1276 /* 1277 * An iommu device is still attached 1278 * (currently, only one device can be attached) ? 1279 */ 1280 if (omap_domain->iommu_dev) 1281 _omap_iommu_detach_dev(omap_domain, omap_domain->dev); 1282 1283 kfree(omap_domain->pgtable); 1284 kfree(omap_domain); 1285 } 1286 1287 static phys_addr_t omap_iommu_iova_to_phys(struct iommu_domain *domain, 1288 dma_addr_t da) 1289 { 1290 struct omap_iommu_domain *omap_domain = to_omap_domain(domain); 1291 struct omap_iommu *oiommu = omap_domain->iommu_dev; 1292 struct device *dev = oiommu->dev; 1293 u32 *pgd, *pte; 1294 phys_addr_t ret = 0; 1295 1296 iopgtable_lookup_entry(oiommu, da, &pgd, &pte); 1297 1298 if (pte) { 1299 if (iopte_is_small(*pte)) 1300 ret = omap_iommu_translate(*pte, da, IOPTE_MASK); 1301 else if (iopte_is_large(*pte)) 1302 ret = omap_iommu_translate(*pte, da, IOLARGE_MASK); 1303 else 1304 dev_err(dev, "bogus pte 0x%x, da 0x%llx", *pte, 1305 (unsigned long long)da); 1306 } else { 1307 if (iopgd_is_section(*pgd)) 1308 ret = omap_iommu_translate(*pgd, da, IOSECTION_MASK); 1309 else if (iopgd_is_super(*pgd)) 1310 ret = omap_iommu_translate(*pgd, da, IOSUPER_MASK); 1311 else 1312 dev_err(dev, "bogus pgd 0x%x, da 0x%llx", *pgd, 1313 (unsigned long long)da); 1314 } 1315 1316 return ret; 1317 } 1318 1319 static int omap_iommu_add_device(struct device *dev) 1320 { 1321 struct omap_iommu_arch_data *arch_data; 1322 struct device_node *np; 1323 struct platform_device *pdev; 1324 1325 /* 1326 * Allocate the archdata iommu structure for DT-based devices. 1327 * 1328 * TODO: Simplify this when removing non-DT support completely from the 1329 * IOMMU users. 1330 */ 1331 if (!dev->of_node) 1332 return 0; 1333 1334 np = of_parse_phandle(dev->of_node, "iommus", 0); 1335 if (!np) 1336 return 0; 1337 1338 pdev = of_find_device_by_node(np); 1339 if (WARN_ON(!pdev)) { 1340 of_node_put(np); 1341 return -EINVAL; 1342 } 1343 1344 arch_data = kzalloc(sizeof(*arch_data), GFP_KERNEL); 1345 if (!arch_data) { 1346 of_node_put(np); 1347 return -ENOMEM; 1348 } 1349 1350 arch_data->name = kstrdup(dev_name(&pdev->dev), GFP_KERNEL); 1351 dev->archdata.iommu = arch_data; 1352 1353 of_node_put(np); 1354 1355 return 0; 1356 } 1357 1358 static void omap_iommu_remove_device(struct device *dev) 1359 { 1360 struct omap_iommu_arch_data *arch_data = dev->archdata.iommu; 1361 1362 if (!dev->of_node || !arch_data) 1363 return; 1364 1365 kfree(arch_data->name); 1366 kfree(arch_data); 1367 } 1368 1369 static const struct iommu_ops omap_iommu_ops = { 1370 .domain_alloc = omap_iommu_domain_alloc, 1371 .domain_free = omap_iommu_domain_free, 1372 .attach_dev = omap_iommu_attach_dev, 1373 .detach_dev = omap_iommu_detach_dev, 1374 .map = omap_iommu_map, 1375 .unmap = omap_iommu_unmap, 1376 .map_sg = default_iommu_map_sg, 1377 .iova_to_phys = omap_iommu_iova_to_phys, 1378 .add_device = omap_iommu_add_device, 1379 .remove_device = omap_iommu_remove_device, 1380 .pgsize_bitmap = OMAP_IOMMU_PGSIZES, 1381 }; 1382 1383 static int __init omap_iommu_init(void) 1384 { 1385 struct kmem_cache *p; 1386 const unsigned long flags = SLAB_HWCACHE_ALIGN; 1387 size_t align = 1 << 10; /* L2 pagetable alignement */ 1388 struct device_node *np; 1389 1390 np = of_find_matching_node(NULL, omap_iommu_of_match); 1391 if (!np) 1392 return 0; 1393 1394 of_node_put(np); 1395 1396 p = kmem_cache_create("iopte_cache", IOPTE_TABLE_SIZE, align, flags, 1397 iopte_cachep_ctor); 1398 if (!p) 1399 return -ENOMEM; 1400 iopte_cachep = p; 1401 1402 bus_set_iommu(&platform_bus_type, &omap_iommu_ops); 1403 1404 omap_iommu_debugfs_init(); 1405 1406 return platform_driver_register(&omap_iommu_driver); 1407 } 1408 /* must be ready before omap3isp is probed */ 1409 subsys_initcall(omap_iommu_init); 1410 1411 static void __exit omap_iommu_exit(void) 1412 { 1413 kmem_cache_destroy(iopte_cachep); 1414 1415 platform_driver_unregister(&omap_iommu_driver); 1416 1417 omap_iommu_debugfs_exit(); 1418 } 1419 module_exit(omap_iommu_exit); 1420 1421 MODULE_DESCRIPTION("omap iommu: tlb and pagetable primitives"); 1422 MODULE_ALIAS("platform:omap-iommu"); 1423 MODULE_AUTHOR("Hiroshi DOYU, Paul Mundt and Toshihiro Kobayashi"); 1424 MODULE_LICENSE("GPL v2"); 1425