1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * OF helpers for IOMMU 4 * 5 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 6 */ 7 8 #include <linux/export.h> 9 #include <linux/iommu.h> 10 #include <linux/limits.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/of_address.h> 14 #include <linux/of_iommu.h> 15 #include <linux/of_pci.h> 16 #include <linux/pci.h> 17 #include <linux/slab.h> 18 #include <linux/fsl/mc.h> 19 20 #include "iommu-priv.h" 21 22 static int of_iommu_xlate(struct device *dev, 23 struct of_phandle_args *iommu_spec) 24 { 25 const struct iommu_ops *ops; 26 int ret; 27 28 if (!of_device_is_available(iommu_spec->np)) 29 return -ENODEV; 30 31 ret = iommu_fwspec_init(dev, of_fwnode_handle(iommu_spec->np)); 32 if (ret) 33 return ret; 34 35 ops = iommu_ops_from_fwnode(&iommu_spec->np->fwnode); 36 if (!ops->of_xlate || !try_module_get(ops->owner)) 37 return -ENODEV; 38 39 ret = ops->of_xlate(dev, iommu_spec); 40 module_put(ops->owner); 41 return ret; 42 } 43 44 static int of_iommu_configure_dev_id(struct device_node *master_np, 45 struct device *dev, 46 const u32 *id) 47 { 48 struct of_phandle_args iommu_spec = { .args_count = 1 }; 49 int err; 50 51 err = of_map_id(master_np, *id, "iommu-map", 52 "iommu-map-mask", &iommu_spec.np, 53 iommu_spec.args); 54 if (err) 55 return err; 56 57 err = of_iommu_xlate(dev, &iommu_spec); 58 of_node_put(iommu_spec.np); 59 return err; 60 } 61 62 static int of_iommu_configure_dev(struct device_node *master_np, 63 struct device *dev) 64 { 65 struct of_phandle_args iommu_spec; 66 int err = -ENODEV, idx = 0; 67 68 while (!of_parse_phandle_with_args(master_np, "iommus", 69 "#iommu-cells", 70 idx, &iommu_spec)) { 71 err = of_iommu_xlate(dev, &iommu_spec); 72 of_node_put(iommu_spec.np); 73 idx++; 74 if (err) 75 break; 76 } 77 78 return err; 79 } 80 81 struct of_pci_iommu_alias_info { 82 struct device *dev; 83 struct device_node *np; 84 }; 85 86 static int of_pci_iommu_init(struct pci_dev *pdev, u16 alias, void *data) 87 { 88 struct of_pci_iommu_alias_info *info = data; 89 u32 input_id = alias; 90 91 return of_iommu_configure_dev_id(info->np, info->dev, &input_id); 92 } 93 94 static int of_iommu_configure_device(struct device_node *master_np, 95 struct device *dev, const u32 *id) 96 { 97 return (id) ? of_iommu_configure_dev_id(master_np, dev, id) : 98 of_iommu_configure_dev(master_np, dev); 99 } 100 101 static void of_pci_check_device_ats(struct device *dev, struct device_node *np) 102 { 103 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 104 105 if (fwspec && of_property_read_bool(np, "ats-supported")) 106 fwspec->flags |= IOMMU_FWSPEC_PCI_RC_ATS; 107 } 108 109 /* 110 * Returns: 111 * 0 on success, an iommu was configured 112 * -ENODEV if the device does not have any IOMMU 113 * -EPROBEDEFER if probing should be tried again 114 * -errno fatal errors 115 */ 116 int of_iommu_configure(struct device *dev, struct device_node *master_np, 117 const u32 *id) 118 { 119 bool dev_iommu_present; 120 int err; 121 122 if (!master_np) 123 return -ENODEV; 124 125 /* Serialise to make dev->iommu stable under our potential fwspec */ 126 mutex_lock(&iommu_probe_device_lock); 127 if (dev_iommu_fwspec_get(dev)) { 128 mutex_unlock(&iommu_probe_device_lock); 129 return 0; 130 } 131 dev_iommu_present = dev->iommu; 132 133 /* 134 * We don't currently walk up the tree looking for a parent IOMMU. 135 * See the `Notes:' section of 136 * Documentation/devicetree/bindings/iommu/iommu.txt 137 */ 138 if (dev_is_pci(dev)) { 139 struct of_pci_iommu_alias_info info = { 140 .dev = dev, 141 .np = master_np, 142 }; 143 144 pci_request_acs(); 145 err = pci_for_each_dma_alias(to_pci_dev(dev), 146 of_pci_iommu_init, &info); 147 of_pci_check_device_ats(dev, master_np); 148 } else { 149 err = of_iommu_configure_device(master_np, dev, id); 150 } 151 152 if (err && dev_iommu_present) 153 iommu_fwspec_free(dev); 154 else if (err && dev->iommu) 155 dev_iommu_free(dev); 156 mutex_unlock(&iommu_probe_device_lock); 157 158 /* 159 * If we're not on the iommu_probe_device() path (as indicated by the 160 * initial dev->iommu) then try to simulate it. This should no longer 161 * happen unless of_dma_configure() is being misused outside bus code. 162 */ 163 if (!err && dev->bus && !dev_iommu_present) 164 err = iommu_probe_device(dev); 165 166 if (err && err != -EPROBE_DEFER) 167 dev_dbg(dev, "Adding to IOMMU failed: %d\n", err); 168 169 return err; 170 } 171 172 static enum iommu_resv_type __maybe_unused 173 iommu_resv_region_get_type(struct device *dev, 174 struct resource *phys, 175 phys_addr_t start, size_t length) 176 { 177 phys_addr_t end = start + length - 1; 178 179 /* 180 * IOMMU regions without an associated physical region cannot be 181 * mapped and are simply reservations. 182 */ 183 if (phys->start >= phys->end) 184 return IOMMU_RESV_RESERVED; 185 186 /* may be IOMMU_RESV_DIRECT_RELAXABLE for certain cases */ 187 if (start == phys->start && end == phys->end) 188 return IOMMU_RESV_DIRECT; 189 190 dev_warn(dev, "treating non-direct mapping [%pr] -> [%pap-%pap] as reservation\n", phys, 191 &start, &end); 192 return IOMMU_RESV_RESERVED; 193 } 194 195 /** 196 * of_iommu_get_resv_regions - reserved region driver helper for device tree 197 * @dev: device for which to get reserved regions 198 * @list: reserved region list 199 * 200 * IOMMU drivers can use this to implement their .get_resv_regions() callback 201 * for memory regions attached to a device tree node. See the reserved-memory 202 * device tree bindings on how to use these: 203 * 204 * Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt 205 */ 206 void of_iommu_get_resv_regions(struct device *dev, struct list_head *list) 207 { 208 #if IS_ENABLED(CONFIG_OF_ADDRESS) 209 struct of_phandle_iterator it; 210 int err; 211 212 of_for_each_phandle(&it, err, dev->of_node, "memory-region", NULL, 0) { 213 const __be32 *maps, *end; 214 struct resource phys; 215 int size; 216 217 memset(&phys, 0, sizeof(phys)); 218 219 /* 220 * The "reg" property is optional and can be omitted by reserved-memory regions 221 * that represent reservations in the IOVA space, which are regions that should 222 * not be mapped. 223 */ 224 if (of_property_present(it.node, "reg")) { 225 err = of_address_to_resource(it.node, 0, &phys); 226 if (err < 0) { 227 dev_err(dev, "failed to parse memory region %pOF: %d\n", 228 it.node, err); 229 continue; 230 } 231 } 232 233 maps = of_get_property(it.node, "iommu-addresses", &size); 234 if (!maps) 235 continue; 236 237 end = maps + size / sizeof(__be32); 238 239 while (maps < end) { 240 struct device_node *np; 241 u32 phandle; 242 243 phandle = be32_to_cpup(maps++); 244 np = of_find_node_by_phandle(phandle); 245 246 if (np == dev->of_node) { 247 int prot = IOMMU_READ | IOMMU_WRITE; 248 struct iommu_resv_region *region; 249 enum iommu_resv_type type; 250 phys_addr_t iova; 251 size_t length; 252 253 if (of_dma_is_coherent(dev->of_node)) 254 prot |= IOMMU_CACHE; 255 256 maps = of_translate_dma_region(np, maps, &iova, &length); 257 if (length == 0) { 258 dev_warn(dev, "Cannot reserve IOVA region of 0 size\n"); 259 continue; 260 } 261 type = iommu_resv_region_get_type(dev, &phys, iova, length); 262 263 region = iommu_alloc_resv_region(iova, length, prot, type, 264 GFP_KERNEL); 265 if (region) 266 list_add_tail(®ion->list, list); 267 } 268 } 269 } 270 #endif 271 } 272 EXPORT_SYMBOL(of_iommu_get_resv_regions); 273