1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * OF helpers for IOMMU 4 * 5 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 6 */ 7 8 #include <linux/export.h> 9 #include <linux/iommu.h> 10 #include <linux/limits.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/of_address.h> 14 #include <linux/of_iommu.h> 15 #include <linux/of_pci.h> 16 #include <linux/pci.h> 17 #include <linux/slab.h> 18 #include <linux/fsl/mc.h> 19 20 #include "iommu-priv.h" 21 22 static int of_iommu_xlate(struct device *dev, 23 struct of_phandle_args *iommu_spec) 24 { 25 const struct iommu_ops *ops; 26 int ret; 27 28 if (!of_device_is_available(iommu_spec->np)) 29 return -ENODEV; 30 31 ret = iommu_fwspec_init(dev, of_fwnode_handle(iommu_spec->np)); 32 if (ret) 33 return ret; 34 35 ops = iommu_ops_from_fwnode(&iommu_spec->np->fwnode); 36 if (!ops->of_xlate || !try_module_get(ops->owner)) 37 return -ENODEV; 38 39 ret = ops->of_xlate(dev, iommu_spec); 40 module_put(ops->owner); 41 return ret; 42 } 43 44 static int of_iommu_configure_dev_id(struct device_node *master_np, 45 struct device *dev, 46 const u32 *id) 47 { 48 struct of_phandle_args iommu_spec = { .args_count = 1 }; 49 int err; 50 51 err = of_map_id(master_np, *id, "iommu-map", 52 "iommu-map-mask", &iommu_spec.np, 53 iommu_spec.args); 54 if (err) 55 return err; 56 57 err = of_iommu_xlate(dev, &iommu_spec); 58 of_node_put(iommu_spec.np); 59 return err; 60 } 61 62 static int of_iommu_configure_dev(struct device_node *master_np, 63 struct device *dev) 64 { 65 struct of_phandle_args iommu_spec; 66 int err = -ENODEV, idx = 0; 67 68 while (!of_parse_phandle_with_args(master_np, "iommus", 69 "#iommu-cells", 70 idx, &iommu_spec)) { 71 err = of_iommu_xlate(dev, &iommu_spec); 72 of_node_put(iommu_spec.np); 73 idx++; 74 if (err) 75 break; 76 } 77 78 return err; 79 } 80 81 struct of_pci_iommu_alias_info { 82 struct device *dev; 83 struct device_node *np; 84 }; 85 86 static int of_pci_iommu_init(struct pci_dev *pdev, u16 alias, void *data) 87 { 88 struct of_pci_iommu_alias_info *info = data; 89 u32 input_id = alias; 90 91 return of_iommu_configure_dev_id(info->np, info->dev, &input_id); 92 } 93 94 static int of_iommu_configure_device(struct device_node *master_np, 95 struct device *dev, const u32 *id) 96 { 97 return (id) ? of_iommu_configure_dev_id(master_np, dev, id) : 98 of_iommu_configure_dev(master_np, dev); 99 } 100 101 static void of_pci_check_device_ats(struct device *dev, struct device_node *np) 102 { 103 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 104 105 if (fwspec && of_property_read_bool(np, "ats-supported")) 106 fwspec->flags |= IOMMU_FWSPEC_PCI_RC_ATS; 107 } 108 109 /* 110 * Returns: 111 * 0 on success, an iommu was configured 112 * -ENODEV if the device does not have any IOMMU 113 * -EPROBEDEFER if probing should be tried again 114 * -errno fatal errors 115 */ 116 int of_iommu_configure(struct device *dev, struct device_node *master_np, 117 const u32 *id) 118 { 119 int err; 120 121 if (!master_np) 122 return -ENODEV; 123 124 /* Serialise to make dev->iommu stable under our potential fwspec */ 125 mutex_lock(&iommu_probe_device_lock); 126 if (dev_iommu_fwspec_get(dev)) { 127 mutex_unlock(&iommu_probe_device_lock); 128 return 0; 129 } 130 131 /* 132 * We don't currently walk up the tree looking for a parent IOMMU. 133 * See the `Notes:' section of 134 * Documentation/devicetree/bindings/iommu/iommu.txt 135 */ 136 if (dev_is_pci(dev)) { 137 struct of_pci_iommu_alias_info info = { 138 .dev = dev, 139 .np = master_np, 140 }; 141 142 pci_request_acs(); 143 err = pci_for_each_dma_alias(to_pci_dev(dev), 144 of_pci_iommu_init, &info); 145 of_pci_check_device_ats(dev, master_np); 146 } else { 147 err = of_iommu_configure_device(master_np, dev, id); 148 } 149 150 if (err) 151 iommu_fwspec_free(dev); 152 mutex_unlock(&iommu_probe_device_lock); 153 154 if (!err && dev->bus) 155 err = iommu_probe_device(dev); 156 157 if (err && err != -EPROBE_DEFER) 158 dev_dbg(dev, "Adding to IOMMU failed: %d\n", err); 159 160 return err; 161 } 162 163 static enum iommu_resv_type __maybe_unused 164 iommu_resv_region_get_type(struct device *dev, 165 struct resource *phys, 166 phys_addr_t start, size_t length) 167 { 168 phys_addr_t end = start + length - 1; 169 170 /* 171 * IOMMU regions without an associated physical region cannot be 172 * mapped and are simply reservations. 173 */ 174 if (phys->start >= phys->end) 175 return IOMMU_RESV_RESERVED; 176 177 /* may be IOMMU_RESV_DIRECT_RELAXABLE for certain cases */ 178 if (start == phys->start && end == phys->end) 179 return IOMMU_RESV_DIRECT; 180 181 dev_warn(dev, "treating non-direct mapping [%pr] -> [%pap-%pap] as reservation\n", phys, 182 &start, &end); 183 return IOMMU_RESV_RESERVED; 184 } 185 186 /** 187 * of_iommu_get_resv_regions - reserved region driver helper for device tree 188 * @dev: device for which to get reserved regions 189 * @list: reserved region list 190 * 191 * IOMMU drivers can use this to implement their .get_resv_regions() callback 192 * for memory regions attached to a device tree node. See the reserved-memory 193 * device tree bindings on how to use these: 194 * 195 * Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt 196 */ 197 void of_iommu_get_resv_regions(struct device *dev, struct list_head *list) 198 { 199 #if IS_ENABLED(CONFIG_OF_ADDRESS) 200 struct of_phandle_iterator it; 201 int err; 202 203 of_for_each_phandle(&it, err, dev->of_node, "memory-region", NULL, 0) { 204 const __be32 *maps, *end; 205 struct resource phys; 206 int size; 207 208 memset(&phys, 0, sizeof(phys)); 209 210 /* 211 * The "reg" property is optional and can be omitted by reserved-memory regions 212 * that represent reservations in the IOVA space, which are regions that should 213 * not be mapped. 214 */ 215 if (of_property_present(it.node, "reg")) { 216 err = of_address_to_resource(it.node, 0, &phys); 217 if (err < 0) { 218 dev_err(dev, "failed to parse memory region %pOF: %d\n", 219 it.node, err); 220 continue; 221 } 222 } 223 224 maps = of_get_property(it.node, "iommu-addresses", &size); 225 if (!maps) 226 continue; 227 228 end = maps + size / sizeof(__be32); 229 230 while (maps < end) { 231 struct device_node *np; 232 u32 phandle; 233 234 phandle = be32_to_cpup(maps++); 235 np = of_find_node_by_phandle(phandle); 236 237 if (np == dev->of_node) { 238 int prot = IOMMU_READ | IOMMU_WRITE; 239 struct iommu_resv_region *region; 240 enum iommu_resv_type type; 241 phys_addr_t iova; 242 size_t length; 243 244 if (of_dma_is_coherent(dev->of_node)) 245 prot |= IOMMU_CACHE; 246 247 maps = of_translate_dma_region(np, maps, &iova, &length); 248 if (length == 0) { 249 dev_warn(dev, "Cannot reserve IOVA region of 0 size\n"); 250 continue; 251 } 252 type = iommu_resv_region_get_type(dev, &phys, iova, length); 253 254 region = iommu_alloc_resv_region(iova, length, prot, type, 255 GFP_KERNEL); 256 if (region) 257 list_add_tail(®ion->list, list); 258 } 259 } 260 } 261 #endif 262 } 263 EXPORT_SYMBOL(of_iommu_get_resv_regions); 264