1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * IOMMU API for MTK architected m4u v1 implementations 4 * 5 * Copyright (c) 2015-2016 MediaTek Inc. 6 * Author: Honghui Zhang <honghui.zhang@mediatek.com> 7 * 8 * Based on driver/iommu/mtk_iommu.c 9 */ 10 #include <linux/bug.h> 11 #include <linux/clk.h> 12 #include <linux/component.h> 13 #include <linux/device.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/err.h> 16 #include <linux/interrupt.h> 17 #include <linux/io.h> 18 #include <linux/iommu.h> 19 #include <linux/iopoll.h> 20 #include <linux/list.h> 21 #include <linux/module.h> 22 #include <linux/of_address.h> 23 #include <linux/of_irq.h> 24 #include <linux/of_platform.h> 25 #include <linux/platform_device.h> 26 #include <linux/slab.h> 27 #include <linux/spinlock.h> 28 #include <asm/barrier.h> 29 #include <asm/dma-iommu.h> 30 #include <dt-bindings/memory/mtk-memory-port.h> 31 #include <dt-bindings/memory/mt2701-larb-port.h> 32 #include <soc/mediatek/smi.h> 33 34 #define REG_MMU_PT_BASE_ADDR 0x000 35 36 #define F_ALL_INVLD 0x2 37 #define F_MMU_INV_RANGE 0x1 38 #define F_INVLD_EN0 BIT(0) 39 #define F_INVLD_EN1 BIT(1) 40 41 #define F_MMU_FAULT_VA_MSK 0xfffff000 42 #define MTK_PROTECT_PA_ALIGN 128 43 44 #define REG_MMU_CTRL_REG 0x210 45 #define F_MMU_CTRL_COHERENT_EN BIT(8) 46 #define REG_MMU_IVRP_PADDR 0x214 47 #define REG_MMU_INT_CONTROL 0x220 48 #define F_INT_TRANSLATION_FAULT BIT(0) 49 #define F_INT_MAIN_MULTI_HIT_FAULT BIT(1) 50 #define F_INT_INVALID_PA_FAULT BIT(2) 51 #define F_INT_ENTRY_REPLACEMENT_FAULT BIT(3) 52 #define F_INT_TABLE_WALK_FAULT BIT(4) 53 #define F_INT_TLB_MISS_FAULT BIT(5) 54 #define F_INT_PFH_DMA_FIFO_OVERFLOW BIT(6) 55 #define F_INT_MISS_DMA_FIFO_OVERFLOW BIT(7) 56 57 #define F_MMU_TF_PROTECT_SEL(prot) (((prot) & 0x3) << 5) 58 #define F_INT_CLR_BIT BIT(12) 59 60 #define REG_MMU_FAULT_ST 0x224 61 #define REG_MMU_FAULT_VA 0x228 62 #define REG_MMU_INVLD_PA 0x22C 63 #define REG_MMU_INT_ID 0x388 64 #define REG_MMU_INVALIDATE 0x5c0 65 #define REG_MMU_INVLD_START_A 0x5c4 66 #define REG_MMU_INVLD_END_A 0x5c8 67 68 #define REG_MMU_INV_SEL 0x5d8 69 #define REG_MMU_STANDARD_AXI_MODE 0x5e8 70 71 #define REG_MMU_DCM 0x5f0 72 #define F_MMU_DCM_ON BIT(1) 73 #define REG_MMU_CPE_DONE 0x60c 74 #define F_DESC_VALID 0x2 75 #define F_DESC_NONSEC BIT(3) 76 #define MT2701_M4U_TF_LARB(TF) (6 - (((TF) >> 13) & 0x7)) 77 #define MT2701_M4U_TF_PORT(TF) (((TF) >> 8) & 0xF) 78 /* MTK generation one iommu HW only support 4K size mapping */ 79 #define MT2701_IOMMU_PAGE_SHIFT 12 80 #define MT2701_IOMMU_PAGE_SIZE (1UL << MT2701_IOMMU_PAGE_SHIFT) 81 #define MT2701_LARB_NR_MAX 3 82 83 /* 84 * MTK m4u support 4GB iova address space, and only support 4K page 85 * mapping. So the pagetable size should be exactly as 4M. 86 */ 87 #define M2701_IOMMU_PGT_SIZE SZ_4M 88 89 struct mtk_iommu_v1_suspend_reg { 90 u32 standard_axi_mode; 91 u32 dcm_dis; 92 u32 ctrl_reg; 93 u32 int_control0; 94 }; 95 96 struct mtk_iommu_v1_data { 97 void __iomem *base; 98 int irq; 99 struct device *dev; 100 struct clk *bclk; 101 phys_addr_t protect_base; /* protect memory base */ 102 struct mtk_iommu_v1_domain *m4u_dom; 103 104 struct iommu_device iommu; 105 struct dma_iommu_mapping *mapping; 106 struct mtk_smi_larb_iommu larb_imu[MTK_LARB_NR_MAX]; 107 108 struct mtk_iommu_v1_suspend_reg reg; 109 }; 110 111 struct mtk_iommu_v1_domain { 112 spinlock_t pgtlock; /* lock for page table */ 113 struct iommu_domain domain; 114 u32 *pgt_va; 115 dma_addr_t pgt_pa; 116 struct mtk_iommu_v1_data *data; 117 }; 118 119 static int mtk_iommu_v1_bind(struct device *dev) 120 { 121 struct mtk_iommu_v1_data *data = dev_get_drvdata(dev); 122 123 return component_bind_all(dev, &data->larb_imu); 124 } 125 126 static void mtk_iommu_v1_unbind(struct device *dev) 127 { 128 struct mtk_iommu_v1_data *data = dev_get_drvdata(dev); 129 130 component_unbind_all(dev, &data->larb_imu); 131 } 132 133 static struct mtk_iommu_v1_domain *to_mtk_domain(struct iommu_domain *dom) 134 { 135 return container_of(dom, struct mtk_iommu_v1_domain, domain); 136 } 137 138 static const int mt2701_m4u_in_larb[] = { 139 LARB0_PORT_OFFSET, LARB1_PORT_OFFSET, 140 LARB2_PORT_OFFSET, LARB3_PORT_OFFSET 141 }; 142 143 static inline int mt2701_m4u_to_larb(int id) 144 { 145 int i; 146 147 for (i = ARRAY_SIZE(mt2701_m4u_in_larb) - 1; i >= 0; i--) 148 if ((id) >= mt2701_m4u_in_larb[i]) 149 return i; 150 151 return 0; 152 } 153 154 static inline int mt2701_m4u_to_port(int id) 155 { 156 int larb = mt2701_m4u_to_larb(id); 157 158 return id - mt2701_m4u_in_larb[larb]; 159 } 160 161 static void mtk_iommu_v1_tlb_flush_all(struct mtk_iommu_v1_data *data) 162 { 163 writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, 164 data->base + REG_MMU_INV_SEL); 165 writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE); 166 wmb(); /* Make sure the tlb flush all done */ 167 } 168 169 static void mtk_iommu_v1_tlb_flush_range(struct mtk_iommu_v1_data *data, 170 unsigned long iova, size_t size) 171 { 172 int ret; 173 u32 tmp; 174 175 writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, 176 data->base + REG_MMU_INV_SEL); 177 writel_relaxed(iova & F_MMU_FAULT_VA_MSK, 178 data->base + REG_MMU_INVLD_START_A); 179 writel_relaxed((iova + size - 1) & F_MMU_FAULT_VA_MSK, 180 data->base + REG_MMU_INVLD_END_A); 181 writel_relaxed(F_MMU_INV_RANGE, data->base + REG_MMU_INVALIDATE); 182 183 ret = readl_poll_timeout_atomic(data->base + REG_MMU_CPE_DONE, 184 tmp, tmp != 0, 10, 100000); 185 if (ret) { 186 dev_warn(data->dev, 187 "Partial TLB flush timed out, falling back to full flush\n"); 188 mtk_iommu_v1_tlb_flush_all(data); 189 } 190 /* Clear the CPE status */ 191 writel_relaxed(0, data->base + REG_MMU_CPE_DONE); 192 } 193 194 static irqreturn_t mtk_iommu_v1_isr(int irq, void *dev_id) 195 { 196 struct mtk_iommu_v1_data *data = dev_id; 197 struct mtk_iommu_v1_domain *dom = data->m4u_dom; 198 u32 int_state, regval, fault_iova, fault_pa; 199 unsigned int fault_larb, fault_port; 200 201 /* Read error information from registers */ 202 int_state = readl_relaxed(data->base + REG_MMU_FAULT_ST); 203 fault_iova = readl_relaxed(data->base + REG_MMU_FAULT_VA); 204 205 fault_iova &= F_MMU_FAULT_VA_MSK; 206 fault_pa = readl_relaxed(data->base + REG_MMU_INVLD_PA); 207 regval = readl_relaxed(data->base + REG_MMU_INT_ID); 208 fault_larb = MT2701_M4U_TF_LARB(regval); 209 fault_port = MT2701_M4U_TF_PORT(regval); 210 211 /* 212 * MTK v1 iommu HW could not determine whether the fault is read or 213 * write fault, report as read fault. 214 */ 215 if (report_iommu_fault(&dom->domain, data->dev, fault_iova, 216 IOMMU_FAULT_READ)) 217 dev_err_ratelimited(data->dev, 218 "fault type=0x%x iova=0x%x pa=0x%x larb=%d port=%d\n", 219 int_state, fault_iova, fault_pa, 220 fault_larb, fault_port); 221 222 /* Interrupt clear */ 223 regval = readl_relaxed(data->base + REG_MMU_INT_CONTROL); 224 regval |= F_INT_CLR_BIT; 225 writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL); 226 227 mtk_iommu_v1_tlb_flush_all(data); 228 229 return IRQ_HANDLED; 230 } 231 232 static void mtk_iommu_v1_config(struct mtk_iommu_v1_data *data, 233 struct device *dev, bool enable) 234 { 235 struct mtk_smi_larb_iommu *larb_mmu; 236 unsigned int larbid, portid; 237 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 238 int i; 239 240 for (i = 0; i < fwspec->num_ids; ++i) { 241 larbid = mt2701_m4u_to_larb(fwspec->ids[i]); 242 portid = mt2701_m4u_to_port(fwspec->ids[i]); 243 larb_mmu = &data->larb_imu[larbid]; 244 245 dev_dbg(dev, "%s iommu port: %d\n", 246 enable ? "enable" : "disable", portid); 247 248 if (enable) 249 larb_mmu->mmu |= MTK_SMI_MMU_EN(portid); 250 else 251 larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid); 252 } 253 } 254 255 static int mtk_iommu_v1_domain_finalise(struct mtk_iommu_v1_data *data) 256 { 257 struct mtk_iommu_v1_domain *dom = data->m4u_dom; 258 259 spin_lock_init(&dom->pgtlock); 260 261 dom->pgt_va = dma_alloc_coherent(data->dev, M2701_IOMMU_PGT_SIZE, 262 &dom->pgt_pa, GFP_KERNEL); 263 if (!dom->pgt_va) 264 return -ENOMEM; 265 266 writel(dom->pgt_pa, data->base + REG_MMU_PT_BASE_ADDR); 267 268 dom->data = data; 269 270 return 0; 271 } 272 273 static struct iommu_domain *mtk_iommu_v1_domain_alloc_paging(struct device *dev) 274 { 275 struct mtk_iommu_v1_domain *dom; 276 277 dom = kzalloc(sizeof(*dom), GFP_KERNEL); 278 if (!dom) 279 return NULL; 280 281 return &dom->domain; 282 } 283 284 static void mtk_iommu_v1_domain_free(struct iommu_domain *domain) 285 { 286 struct mtk_iommu_v1_domain *dom = to_mtk_domain(domain); 287 struct mtk_iommu_v1_data *data = dom->data; 288 289 dma_free_coherent(data->dev, M2701_IOMMU_PGT_SIZE, 290 dom->pgt_va, dom->pgt_pa); 291 kfree(to_mtk_domain(domain)); 292 } 293 294 static int mtk_iommu_v1_attach_device(struct iommu_domain *domain, struct device *dev) 295 { 296 struct mtk_iommu_v1_data *data = dev_iommu_priv_get(dev); 297 struct mtk_iommu_v1_domain *dom = to_mtk_domain(domain); 298 struct dma_iommu_mapping *mtk_mapping; 299 int ret; 300 301 /* Only allow the domain created internally. */ 302 mtk_mapping = data->mapping; 303 if (mtk_mapping->domain != domain) 304 return 0; 305 306 if (!data->m4u_dom) { 307 data->m4u_dom = dom; 308 ret = mtk_iommu_v1_domain_finalise(data); 309 if (ret) { 310 data->m4u_dom = NULL; 311 return ret; 312 } 313 } 314 315 mtk_iommu_v1_config(data, dev, true); 316 return 0; 317 } 318 319 static int mtk_iommu_v1_identity_attach(struct iommu_domain *identity_domain, 320 struct device *dev) 321 { 322 struct mtk_iommu_v1_data *data = dev_iommu_priv_get(dev); 323 324 mtk_iommu_v1_config(data, dev, false); 325 return 0; 326 } 327 328 static struct iommu_domain_ops mtk_iommu_v1_identity_ops = { 329 .attach_dev = mtk_iommu_v1_identity_attach, 330 }; 331 332 static struct iommu_domain mtk_iommu_v1_identity_domain = { 333 .type = IOMMU_DOMAIN_IDENTITY, 334 .ops = &mtk_iommu_v1_identity_ops, 335 }; 336 337 static int mtk_iommu_v1_map(struct iommu_domain *domain, unsigned long iova, 338 phys_addr_t paddr, size_t pgsize, size_t pgcount, 339 int prot, gfp_t gfp, size_t *mapped) 340 { 341 struct mtk_iommu_v1_domain *dom = to_mtk_domain(domain); 342 unsigned long flags; 343 unsigned int i; 344 u32 *pgt_base_iova = dom->pgt_va + (iova >> MT2701_IOMMU_PAGE_SHIFT); 345 u32 pabase = (u32)paddr; 346 347 spin_lock_irqsave(&dom->pgtlock, flags); 348 for (i = 0; i < pgcount; i++) { 349 if (pgt_base_iova[i]) 350 break; 351 pgt_base_iova[i] = pabase | F_DESC_VALID | F_DESC_NONSEC; 352 pabase += MT2701_IOMMU_PAGE_SIZE; 353 } 354 355 spin_unlock_irqrestore(&dom->pgtlock, flags); 356 357 *mapped = i * MT2701_IOMMU_PAGE_SIZE; 358 mtk_iommu_v1_tlb_flush_range(dom->data, iova, *mapped); 359 360 return i == pgcount ? 0 : -EEXIST; 361 } 362 363 static size_t mtk_iommu_v1_unmap(struct iommu_domain *domain, unsigned long iova, 364 size_t pgsize, size_t pgcount, 365 struct iommu_iotlb_gather *gather) 366 { 367 struct mtk_iommu_v1_domain *dom = to_mtk_domain(domain); 368 unsigned long flags; 369 u32 *pgt_base_iova = dom->pgt_va + (iova >> MT2701_IOMMU_PAGE_SHIFT); 370 size_t size = pgcount * MT2701_IOMMU_PAGE_SIZE; 371 372 spin_lock_irqsave(&dom->pgtlock, flags); 373 memset(pgt_base_iova, 0, pgcount * sizeof(u32)); 374 spin_unlock_irqrestore(&dom->pgtlock, flags); 375 376 mtk_iommu_v1_tlb_flush_range(dom->data, iova, size); 377 378 return size; 379 } 380 381 static phys_addr_t mtk_iommu_v1_iova_to_phys(struct iommu_domain *domain, dma_addr_t iova) 382 { 383 struct mtk_iommu_v1_domain *dom = to_mtk_domain(domain); 384 unsigned long flags; 385 phys_addr_t pa; 386 387 spin_lock_irqsave(&dom->pgtlock, flags); 388 pa = *(dom->pgt_va + (iova >> MT2701_IOMMU_PAGE_SHIFT)); 389 pa = pa & (~(MT2701_IOMMU_PAGE_SIZE - 1)); 390 spin_unlock_irqrestore(&dom->pgtlock, flags); 391 392 return pa; 393 } 394 395 static const struct iommu_ops mtk_iommu_v1_ops; 396 397 /* 398 * MTK generation one iommu HW only support one iommu domain, and all the client 399 * sharing the same iova address space. 400 */ 401 static int mtk_iommu_v1_create_mapping(struct device *dev, 402 const struct of_phandle_args *args) 403 { 404 struct mtk_iommu_v1_data *data; 405 struct platform_device *m4updev; 406 struct dma_iommu_mapping *mtk_mapping; 407 int ret; 408 409 if (args->args_count != 1) { 410 dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n", 411 args->args_count); 412 return -EINVAL; 413 } 414 415 ret = iommu_fwspec_init(dev, of_fwnode_handle(args->np)); 416 if (ret) 417 return ret; 418 419 if (!dev_iommu_priv_get(dev)) { 420 /* Get the m4u device */ 421 m4updev = of_find_device_by_node(args->np); 422 if (WARN_ON(!m4updev)) 423 return -EINVAL; 424 425 dev_iommu_priv_set(dev, platform_get_drvdata(m4updev)); 426 } 427 428 ret = iommu_fwspec_add_ids(dev, args->args, 1); 429 if (ret) 430 return ret; 431 432 data = dev_iommu_priv_get(dev); 433 mtk_mapping = data->mapping; 434 if (!mtk_mapping) { 435 /* MTK iommu support 4GB iova address space. */ 436 mtk_mapping = arm_iommu_create_mapping(dev, 0, 1ULL << 32); 437 if (IS_ERR(mtk_mapping)) 438 return PTR_ERR(mtk_mapping); 439 440 data->mapping = mtk_mapping; 441 } 442 443 return 0; 444 } 445 446 static struct iommu_device *mtk_iommu_v1_probe_device(struct device *dev) 447 { 448 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 449 struct of_phandle_args iommu_spec; 450 struct mtk_iommu_v1_data *data; 451 int err, idx = 0, larbid, larbidx; 452 struct device_link *link; 453 struct device *larbdev; 454 455 /* 456 * In the deferred case, free the existed fwspec. 457 * Always initialize the fwspec internally. 458 */ 459 if (fwspec) { 460 iommu_fwspec_free(dev); 461 fwspec = dev_iommu_fwspec_get(dev); 462 } 463 464 while (!of_parse_phandle_with_args(dev->of_node, "iommus", 465 "#iommu-cells", 466 idx, &iommu_spec)) { 467 468 err = mtk_iommu_v1_create_mapping(dev, &iommu_spec); 469 of_node_put(iommu_spec.np); 470 if (err) 471 return ERR_PTR(err); 472 473 /* dev->iommu_fwspec might have changed */ 474 fwspec = dev_iommu_fwspec_get(dev); 475 idx++; 476 } 477 478 data = dev_iommu_priv_get(dev); 479 480 /* Link the consumer device with the smi-larb device(supplier) */ 481 larbid = mt2701_m4u_to_larb(fwspec->ids[0]); 482 if (larbid >= MT2701_LARB_NR_MAX) 483 return ERR_PTR(-EINVAL); 484 485 for (idx = 1; idx < fwspec->num_ids; idx++) { 486 larbidx = mt2701_m4u_to_larb(fwspec->ids[idx]); 487 if (larbid != larbidx) { 488 dev_err(dev, "Can only use one larb. Fail@larb%d-%d.\n", 489 larbid, larbidx); 490 return ERR_PTR(-EINVAL); 491 } 492 } 493 494 larbdev = data->larb_imu[larbid].dev; 495 if (!larbdev) 496 return ERR_PTR(-EINVAL); 497 498 link = device_link_add(dev, larbdev, 499 DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS); 500 if (!link) 501 dev_err(dev, "Unable to link %s\n", dev_name(larbdev)); 502 503 return &data->iommu; 504 } 505 506 static void mtk_iommu_v1_probe_finalize(struct device *dev) 507 { 508 struct dma_iommu_mapping *mtk_mapping; 509 struct mtk_iommu_v1_data *data; 510 int err; 511 512 data = dev_iommu_priv_get(dev); 513 mtk_mapping = data->mapping; 514 515 err = arm_iommu_attach_device(dev, mtk_mapping); 516 if (err) 517 dev_err(dev, "Can't create IOMMU mapping - DMA-OPS will not work\n"); 518 } 519 520 static void mtk_iommu_v1_release_device(struct device *dev) 521 { 522 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 523 struct mtk_iommu_v1_data *data; 524 struct device *larbdev; 525 unsigned int larbid; 526 527 data = dev_iommu_priv_get(dev); 528 larbid = mt2701_m4u_to_larb(fwspec->ids[0]); 529 larbdev = data->larb_imu[larbid].dev; 530 device_link_remove(dev, larbdev); 531 } 532 533 static int mtk_iommu_v1_hw_init(const struct mtk_iommu_v1_data *data) 534 { 535 u32 regval; 536 int ret; 537 538 ret = clk_prepare_enable(data->bclk); 539 if (ret) { 540 dev_err(data->dev, "Failed to enable iommu bclk(%d)\n", ret); 541 return ret; 542 } 543 544 regval = F_MMU_CTRL_COHERENT_EN | F_MMU_TF_PROTECT_SEL(2); 545 writel_relaxed(regval, data->base + REG_MMU_CTRL_REG); 546 547 regval = F_INT_TRANSLATION_FAULT | 548 F_INT_MAIN_MULTI_HIT_FAULT | 549 F_INT_INVALID_PA_FAULT | 550 F_INT_ENTRY_REPLACEMENT_FAULT | 551 F_INT_TABLE_WALK_FAULT | 552 F_INT_TLB_MISS_FAULT | 553 F_INT_PFH_DMA_FIFO_OVERFLOW | 554 F_INT_MISS_DMA_FIFO_OVERFLOW; 555 writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL); 556 557 /* protect memory,hw will write here while translation fault */ 558 writel_relaxed(data->protect_base, 559 data->base + REG_MMU_IVRP_PADDR); 560 561 writel_relaxed(F_MMU_DCM_ON, data->base + REG_MMU_DCM); 562 563 if (devm_request_irq(data->dev, data->irq, mtk_iommu_v1_isr, 0, 564 dev_name(data->dev), (void *)data)) { 565 writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR); 566 clk_disable_unprepare(data->bclk); 567 dev_err(data->dev, "Failed @ IRQ-%d Request\n", data->irq); 568 return -ENODEV; 569 } 570 571 return 0; 572 } 573 574 static const struct iommu_ops mtk_iommu_v1_ops = { 575 .identity_domain = &mtk_iommu_v1_identity_domain, 576 .domain_alloc_paging = mtk_iommu_v1_domain_alloc_paging, 577 .probe_device = mtk_iommu_v1_probe_device, 578 .probe_finalize = mtk_iommu_v1_probe_finalize, 579 .release_device = mtk_iommu_v1_release_device, 580 .device_group = generic_device_group, 581 .pgsize_bitmap = MT2701_IOMMU_PAGE_SIZE, 582 .owner = THIS_MODULE, 583 .default_domain_ops = &(const struct iommu_domain_ops) { 584 .attach_dev = mtk_iommu_v1_attach_device, 585 .map_pages = mtk_iommu_v1_map, 586 .unmap_pages = mtk_iommu_v1_unmap, 587 .iova_to_phys = mtk_iommu_v1_iova_to_phys, 588 .free = mtk_iommu_v1_domain_free, 589 } 590 }; 591 592 static const struct of_device_id mtk_iommu_v1_of_ids[] = { 593 { .compatible = "mediatek,mt2701-m4u", }, 594 {} 595 }; 596 MODULE_DEVICE_TABLE(of, mtk_iommu_v1_of_ids); 597 598 static const struct component_master_ops mtk_iommu_v1_com_ops = { 599 .bind = mtk_iommu_v1_bind, 600 .unbind = mtk_iommu_v1_unbind, 601 }; 602 603 static int mtk_iommu_v1_probe(struct platform_device *pdev) 604 { 605 struct device *dev = &pdev->dev; 606 struct mtk_iommu_v1_data *data; 607 struct resource *res; 608 struct component_match *match = NULL; 609 void *protect; 610 int larb_nr, ret, i; 611 612 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 613 if (!data) 614 return -ENOMEM; 615 616 data->dev = dev; 617 618 /* Protect memory. HW will access here while translation fault.*/ 619 protect = devm_kcalloc(dev, 2, MTK_PROTECT_PA_ALIGN, 620 GFP_KERNEL | GFP_DMA); 621 if (!protect) 622 return -ENOMEM; 623 data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN); 624 625 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 626 data->base = devm_ioremap_resource(dev, res); 627 if (IS_ERR(data->base)) 628 return PTR_ERR(data->base); 629 630 data->irq = platform_get_irq(pdev, 0); 631 if (data->irq < 0) 632 return data->irq; 633 634 data->bclk = devm_clk_get(dev, "bclk"); 635 if (IS_ERR(data->bclk)) 636 return PTR_ERR(data->bclk); 637 638 larb_nr = of_count_phandle_with_args(dev->of_node, 639 "mediatek,larbs", NULL); 640 if (larb_nr < 0) 641 return larb_nr; 642 643 for (i = 0; i < larb_nr; i++) { 644 struct device_node *larbnode; 645 struct platform_device *plarbdev; 646 647 larbnode = of_parse_phandle(dev->of_node, "mediatek,larbs", i); 648 if (!larbnode) 649 return -EINVAL; 650 651 if (!of_device_is_available(larbnode)) { 652 of_node_put(larbnode); 653 continue; 654 } 655 656 plarbdev = of_find_device_by_node(larbnode); 657 if (!plarbdev) { 658 of_node_put(larbnode); 659 return -ENODEV; 660 } 661 if (!plarbdev->dev.driver) { 662 of_node_put(larbnode); 663 return -EPROBE_DEFER; 664 } 665 data->larb_imu[i].dev = &plarbdev->dev; 666 667 component_match_add_release(dev, &match, component_release_of, 668 component_compare_of, larbnode); 669 } 670 671 platform_set_drvdata(pdev, data); 672 673 ret = mtk_iommu_v1_hw_init(data); 674 if (ret) 675 return ret; 676 677 ret = iommu_device_sysfs_add(&data->iommu, &pdev->dev, NULL, 678 dev_name(&pdev->dev)); 679 if (ret) 680 goto out_clk_unprepare; 681 682 ret = iommu_device_register(&data->iommu, &mtk_iommu_v1_ops, dev); 683 if (ret) 684 goto out_sysfs_remove; 685 686 ret = component_master_add_with_match(dev, &mtk_iommu_v1_com_ops, match); 687 if (ret) 688 goto out_dev_unreg; 689 return ret; 690 691 out_dev_unreg: 692 iommu_device_unregister(&data->iommu); 693 out_sysfs_remove: 694 iommu_device_sysfs_remove(&data->iommu); 695 out_clk_unprepare: 696 clk_disable_unprepare(data->bclk); 697 return ret; 698 } 699 700 static void mtk_iommu_v1_remove(struct platform_device *pdev) 701 { 702 struct mtk_iommu_v1_data *data = platform_get_drvdata(pdev); 703 704 iommu_device_sysfs_remove(&data->iommu); 705 iommu_device_unregister(&data->iommu); 706 707 clk_disable_unprepare(data->bclk); 708 devm_free_irq(&pdev->dev, data->irq, data); 709 component_master_del(&pdev->dev, &mtk_iommu_v1_com_ops); 710 } 711 712 static int __maybe_unused mtk_iommu_v1_suspend(struct device *dev) 713 { 714 struct mtk_iommu_v1_data *data = dev_get_drvdata(dev); 715 struct mtk_iommu_v1_suspend_reg *reg = &data->reg; 716 void __iomem *base = data->base; 717 718 reg->standard_axi_mode = readl_relaxed(base + 719 REG_MMU_STANDARD_AXI_MODE); 720 reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM); 721 reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG); 722 reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL); 723 return 0; 724 } 725 726 static int __maybe_unused mtk_iommu_v1_resume(struct device *dev) 727 { 728 struct mtk_iommu_v1_data *data = dev_get_drvdata(dev); 729 struct mtk_iommu_v1_suspend_reg *reg = &data->reg; 730 void __iomem *base = data->base; 731 732 writel_relaxed(data->m4u_dom->pgt_pa, base + REG_MMU_PT_BASE_ADDR); 733 writel_relaxed(reg->standard_axi_mode, 734 base + REG_MMU_STANDARD_AXI_MODE); 735 writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM); 736 writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG); 737 writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL); 738 writel_relaxed(data->protect_base, base + REG_MMU_IVRP_PADDR); 739 return 0; 740 } 741 742 static const struct dev_pm_ops mtk_iommu_v1_pm_ops = { 743 SET_SYSTEM_SLEEP_PM_OPS(mtk_iommu_v1_suspend, mtk_iommu_v1_resume) 744 }; 745 746 static struct platform_driver mtk_iommu_v1_driver = { 747 .probe = mtk_iommu_v1_probe, 748 .remove_new = mtk_iommu_v1_remove, 749 .driver = { 750 .name = "mtk-iommu-v1", 751 .of_match_table = mtk_iommu_v1_of_ids, 752 .pm = &mtk_iommu_v1_pm_ops, 753 } 754 }; 755 module_platform_driver(mtk_iommu_v1_driver); 756 757 MODULE_DESCRIPTION("IOMMU API for MediaTek M4U v1 implementations"); 758 MODULE_LICENSE("GPL v2"); 759