1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * IOMMU API for MTK architected m4u v1 implementations 4 * 5 * Copyright (c) 2015-2016 MediaTek Inc. 6 * Author: Honghui Zhang <honghui.zhang@mediatek.com> 7 * 8 * Based on driver/iommu/mtk_iommu.c 9 */ 10 #include <linux/bug.h> 11 #include <linux/clk.h> 12 #include <linux/component.h> 13 #include <linux/device.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/err.h> 16 #include <linux/interrupt.h> 17 #include <linux/io.h> 18 #include <linux/iommu.h> 19 #include <linux/iopoll.h> 20 #include <linux/list.h> 21 #include <linux/module.h> 22 #include <linux/of_address.h> 23 #include <linux/of_irq.h> 24 #include <linux/of_platform.h> 25 #include <linux/platform_device.h> 26 #include <linux/slab.h> 27 #include <linux/spinlock.h> 28 #include <linux/string_choices.h> 29 #include <asm/barrier.h> 30 #include <dt-bindings/memory/mtk-memory-port.h> 31 #include <dt-bindings/memory/mt2701-larb-port.h> 32 #include <soc/mediatek/smi.h> 33 34 #if defined(CONFIG_ARM) 35 #include <asm/dma-iommu.h> 36 #else 37 #define arm_iommu_create_mapping(...) NULL 38 #define arm_iommu_attach_device(...) -ENODEV 39 struct dma_iommu_mapping { 40 struct iommu_domain *domain; 41 }; 42 #endif 43 44 #define REG_MMU_PT_BASE_ADDR 0x000 45 46 #define F_ALL_INVLD 0x2 47 #define F_MMU_INV_RANGE 0x1 48 #define F_INVLD_EN0 BIT(0) 49 #define F_INVLD_EN1 BIT(1) 50 51 #define F_MMU_FAULT_VA_MSK 0xfffff000 52 #define MTK_PROTECT_PA_ALIGN 128 53 54 #define REG_MMU_CTRL_REG 0x210 55 #define F_MMU_CTRL_COHERENT_EN BIT(8) 56 #define REG_MMU_IVRP_PADDR 0x214 57 #define REG_MMU_INT_CONTROL 0x220 58 #define F_INT_TRANSLATION_FAULT BIT(0) 59 #define F_INT_MAIN_MULTI_HIT_FAULT BIT(1) 60 #define F_INT_INVALID_PA_FAULT BIT(2) 61 #define F_INT_ENTRY_REPLACEMENT_FAULT BIT(3) 62 #define F_INT_TABLE_WALK_FAULT BIT(4) 63 #define F_INT_TLB_MISS_FAULT BIT(5) 64 #define F_INT_PFH_DMA_FIFO_OVERFLOW BIT(6) 65 #define F_INT_MISS_DMA_FIFO_OVERFLOW BIT(7) 66 67 #define F_MMU_TF_PROTECT_SEL(prot) (((prot) & 0x3) << 5) 68 #define F_INT_CLR_BIT BIT(12) 69 70 #define REG_MMU_FAULT_ST 0x224 71 #define REG_MMU_FAULT_VA 0x228 72 #define REG_MMU_INVLD_PA 0x22C 73 #define REG_MMU_INT_ID 0x388 74 #define REG_MMU_INVALIDATE 0x5c0 75 #define REG_MMU_INVLD_START_A 0x5c4 76 #define REG_MMU_INVLD_END_A 0x5c8 77 78 #define REG_MMU_INV_SEL 0x5d8 79 #define REG_MMU_STANDARD_AXI_MODE 0x5e8 80 81 #define REG_MMU_DCM 0x5f0 82 #define F_MMU_DCM_ON BIT(1) 83 #define REG_MMU_CPE_DONE 0x60c 84 #define F_DESC_VALID 0x2 85 #define F_DESC_NONSEC BIT(3) 86 #define MT2701_M4U_TF_LARB(TF) (6 - (((TF) >> 13) & 0x7)) 87 #define MT2701_M4U_TF_PORT(TF) (((TF) >> 8) & 0xF) 88 /* MTK generation one iommu HW only support 4K size mapping */ 89 #define MT2701_IOMMU_PAGE_SHIFT 12 90 #define MT2701_IOMMU_PAGE_SIZE (1UL << MT2701_IOMMU_PAGE_SHIFT) 91 #define MT2701_LARB_NR_MAX 3 92 93 /* 94 * MTK m4u support 4GB iova address space, and only support 4K page 95 * mapping. So the pagetable size should be exactly as 4M. 96 */ 97 #define M2701_IOMMU_PGT_SIZE SZ_4M 98 99 struct mtk_iommu_v1_suspend_reg { 100 u32 standard_axi_mode; 101 u32 dcm_dis; 102 u32 ctrl_reg; 103 u32 int_control0; 104 }; 105 106 struct mtk_iommu_v1_data { 107 void __iomem *base; 108 int irq; 109 struct device *dev; 110 struct clk *bclk; 111 phys_addr_t protect_base; /* protect memory base */ 112 struct mtk_iommu_v1_domain *m4u_dom; 113 114 struct iommu_device iommu; 115 struct dma_iommu_mapping *mapping; 116 struct mtk_smi_larb_iommu larb_imu[MTK_LARB_NR_MAX]; 117 118 struct mtk_iommu_v1_suspend_reg reg; 119 }; 120 121 struct mtk_iommu_v1_domain { 122 spinlock_t pgtlock; /* lock for page table */ 123 struct iommu_domain domain; 124 u32 *pgt_va; 125 dma_addr_t pgt_pa; 126 struct mtk_iommu_v1_data *data; 127 }; 128 129 static int mtk_iommu_v1_bind(struct device *dev) 130 { 131 struct mtk_iommu_v1_data *data = dev_get_drvdata(dev); 132 133 return component_bind_all(dev, &data->larb_imu); 134 } 135 136 static void mtk_iommu_v1_unbind(struct device *dev) 137 { 138 struct mtk_iommu_v1_data *data = dev_get_drvdata(dev); 139 140 component_unbind_all(dev, &data->larb_imu); 141 } 142 143 static struct mtk_iommu_v1_domain *to_mtk_domain(struct iommu_domain *dom) 144 { 145 return container_of(dom, struct mtk_iommu_v1_domain, domain); 146 } 147 148 static const int mt2701_m4u_in_larb[] = { 149 LARB0_PORT_OFFSET, LARB1_PORT_OFFSET, 150 LARB2_PORT_OFFSET, LARB3_PORT_OFFSET 151 }; 152 153 static inline int mt2701_m4u_to_larb(int id) 154 { 155 int i; 156 157 for (i = ARRAY_SIZE(mt2701_m4u_in_larb) - 1; i >= 0; i--) 158 if ((id) >= mt2701_m4u_in_larb[i]) 159 return i; 160 161 return 0; 162 } 163 164 static inline int mt2701_m4u_to_port(int id) 165 { 166 int larb = mt2701_m4u_to_larb(id); 167 168 return id - mt2701_m4u_in_larb[larb]; 169 } 170 171 static void mtk_iommu_v1_tlb_flush_all(struct mtk_iommu_v1_data *data) 172 { 173 writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, 174 data->base + REG_MMU_INV_SEL); 175 writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE); 176 wmb(); /* Make sure the tlb flush all done */ 177 } 178 179 static void mtk_iommu_v1_tlb_flush_range(struct mtk_iommu_v1_data *data, 180 unsigned long iova, size_t size) 181 { 182 int ret; 183 u32 tmp; 184 185 writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, 186 data->base + REG_MMU_INV_SEL); 187 writel_relaxed(iova & F_MMU_FAULT_VA_MSK, 188 data->base + REG_MMU_INVLD_START_A); 189 writel_relaxed((iova + size - 1) & F_MMU_FAULT_VA_MSK, 190 data->base + REG_MMU_INVLD_END_A); 191 writel_relaxed(F_MMU_INV_RANGE, data->base + REG_MMU_INVALIDATE); 192 193 ret = readl_poll_timeout_atomic(data->base + REG_MMU_CPE_DONE, 194 tmp, tmp != 0, 10, 100000); 195 if (ret) { 196 dev_warn(data->dev, 197 "Partial TLB flush timed out, falling back to full flush\n"); 198 mtk_iommu_v1_tlb_flush_all(data); 199 } 200 /* Clear the CPE status */ 201 writel_relaxed(0, data->base + REG_MMU_CPE_DONE); 202 } 203 204 static irqreturn_t mtk_iommu_v1_isr(int irq, void *dev_id) 205 { 206 struct mtk_iommu_v1_data *data = dev_id; 207 struct mtk_iommu_v1_domain *dom = data->m4u_dom; 208 u32 int_state, regval, fault_iova, fault_pa; 209 unsigned int fault_larb, fault_port; 210 211 /* Read error information from registers */ 212 int_state = readl_relaxed(data->base + REG_MMU_FAULT_ST); 213 fault_iova = readl_relaxed(data->base + REG_MMU_FAULT_VA); 214 215 fault_iova &= F_MMU_FAULT_VA_MSK; 216 fault_pa = readl_relaxed(data->base + REG_MMU_INVLD_PA); 217 regval = readl_relaxed(data->base + REG_MMU_INT_ID); 218 fault_larb = MT2701_M4U_TF_LARB(regval); 219 fault_port = MT2701_M4U_TF_PORT(regval); 220 221 /* 222 * MTK v1 iommu HW could not determine whether the fault is read or 223 * write fault, report as read fault. 224 */ 225 if (report_iommu_fault(&dom->domain, data->dev, fault_iova, 226 IOMMU_FAULT_READ)) 227 dev_err_ratelimited(data->dev, 228 "fault type=0x%x iova=0x%x pa=0x%x larb=%d port=%d\n", 229 int_state, fault_iova, fault_pa, 230 fault_larb, fault_port); 231 232 /* Interrupt clear */ 233 regval = readl_relaxed(data->base + REG_MMU_INT_CONTROL); 234 regval |= F_INT_CLR_BIT; 235 writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL); 236 237 mtk_iommu_v1_tlb_flush_all(data); 238 239 return IRQ_HANDLED; 240 } 241 242 static void mtk_iommu_v1_config(struct mtk_iommu_v1_data *data, 243 struct device *dev, bool enable) 244 { 245 struct mtk_smi_larb_iommu *larb_mmu; 246 unsigned int larbid, portid; 247 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 248 int i; 249 250 for (i = 0; i < fwspec->num_ids; ++i) { 251 larbid = mt2701_m4u_to_larb(fwspec->ids[i]); 252 portid = mt2701_m4u_to_port(fwspec->ids[i]); 253 larb_mmu = &data->larb_imu[larbid]; 254 255 dev_dbg(dev, "%s iommu port: %d\n", 256 str_enable_disable(enable), portid); 257 258 if (enable) 259 larb_mmu->mmu |= MTK_SMI_MMU_EN(portid); 260 else 261 larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid); 262 } 263 } 264 265 static int mtk_iommu_v1_domain_finalise(struct mtk_iommu_v1_data *data) 266 { 267 struct mtk_iommu_v1_domain *dom = data->m4u_dom; 268 269 spin_lock_init(&dom->pgtlock); 270 271 dom->pgt_va = dma_alloc_coherent(data->dev, M2701_IOMMU_PGT_SIZE, 272 &dom->pgt_pa, GFP_KERNEL); 273 if (!dom->pgt_va) 274 return -ENOMEM; 275 276 writel(dom->pgt_pa, data->base + REG_MMU_PT_BASE_ADDR); 277 278 dom->data = data; 279 280 return 0; 281 } 282 283 static struct iommu_domain *mtk_iommu_v1_domain_alloc_paging(struct device *dev) 284 { 285 struct mtk_iommu_v1_domain *dom; 286 287 dom = kzalloc(sizeof(*dom), GFP_KERNEL); 288 if (!dom) 289 return NULL; 290 291 dom->domain.pgsize_bitmap = MT2701_IOMMU_PAGE_SIZE; 292 293 return &dom->domain; 294 } 295 296 static void mtk_iommu_v1_domain_free(struct iommu_domain *domain) 297 { 298 struct mtk_iommu_v1_domain *dom = to_mtk_domain(domain); 299 struct mtk_iommu_v1_data *data = dom->data; 300 301 dma_free_coherent(data->dev, M2701_IOMMU_PGT_SIZE, 302 dom->pgt_va, dom->pgt_pa); 303 kfree(to_mtk_domain(domain)); 304 } 305 306 static int mtk_iommu_v1_attach_device(struct iommu_domain *domain, struct device *dev) 307 { 308 struct mtk_iommu_v1_data *data = dev_iommu_priv_get(dev); 309 struct mtk_iommu_v1_domain *dom = to_mtk_domain(domain); 310 struct dma_iommu_mapping *mtk_mapping; 311 int ret; 312 313 /* Only allow the domain created internally. */ 314 mtk_mapping = data->mapping; 315 if (mtk_mapping->domain != domain) 316 return 0; 317 318 if (!data->m4u_dom) { 319 data->m4u_dom = dom; 320 ret = mtk_iommu_v1_domain_finalise(data); 321 if (ret) { 322 data->m4u_dom = NULL; 323 return ret; 324 } 325 } 326 327 mtk_iommu_v1_config(data, dev, true); 328 return 0; 329 } 330 331 static int mtk_iommu_v1_identity_attach(struct iommu_domain *identity_domain, 332 struct device *dev) 333 { 334 struct mtk_iommu_v1_data *data = dev_iommu_priv_get(dev); 335 336 mtk_iommu_v1_config(data, dev, false); 337 return 0; 338 } 339 340 static struct iommu_domain_ops mtk_iommu_v1_identity_ops = { 341 .attach_dev = mtk_iommu_v1_identity_attach, 342 }; 343 344 static struct iommu_domain mtk_iommu_v1_identity_domain = { 345 .type = IOMMU_DOMAIN_IDENTITY, 346 .ops = &mtk_iommu_v1_identity_ops, 347 }; 348 349 static int mtk_iommu_v1_map(struct iommu_domain *domain, unsigned long iova, 350 phys_addr_t paddr, size_t pgsize, size_t pgcount, 351 int prot, gfp_t gfp, size_t *mapped) 352 { 353 struct mtk_iommu_v1_domain *dom = to_mtk_domain(domain); 354 unsigned long flags; 355 unsigned int i; 356 u32 *pgt_base_iova = dom->pgt_va + (iova >> MT2701_IOMMU_PAGE_SHIFT); 357 u32 pabase = (u32)paddr; 358 359 spin_lock_irqsave(&dom->pgtlock, flags); 360 for (i = 0; i < pgcount; i++) { 361 if (pgt_base_iova[i]) 362 break; 363 pgt_base_iova[i] = pabase | F_DESC_VALID | F_DESC_NONSEC; 364 pabase += MT2701_IOMMU_PAGE_SIZE; 365 } 366 367 spin_unlock_irqrestore(&dom->pgtlock, flags); 368 369 *mapped = i * MT2701_IOMMU_PAGE_SIZE; 370 mtk_iommu_v1_tlb_flush_range(dom->data, iova, *mapped); 371 372 return i == pgcount ? 0 : -EEXIST; 373 } 374 375 static size_t mtk_iommu_v1_unmap(struct iommu_domain *domain, unsigned long iova, 376 size_t pgsize, size_t pgcount, 377 struct iommu_iotlb_gather *gather) 378 { 379 struct mtk_iommu_v1_domain *dom = to_mtk_domain(domain); 380 unsigned long flags; 381 u32 *pgt_base_iova = dom->pgt_va + (iova >> MT2701_IOMMU_PAGE_SHIFT); 382 size_t size = pgcount * MT2701_IOMMU_PAGE_SIZE; 383 384 spin_lock_irqsave(&dom->pgtlock, flags); 385 memset(pgt_base_iova, 0, pgcount * sizeof(u32)); 386 spin_unlock_irqrestore(&dom->pgtlock, flags); 387 388 mtk_iommu_v1_tlb_flush_range(dom->data, iova, size); 389 390 return size; 391 } 392 393 static phys_addr_t mtk_iommu_v1_iova_to_phys(struct iommu_domain *domain, dma_addr_t iova) 394 { 395 struct mtk_iommu_v1_domain *dom = to_mtk_domain(domain); 396 unsigned long flags; 397 phys_addr_t pa; 398 399 spin_lock_irqsave(&dom->pgtlock, flags); 400 pa = *(dom->pgt_va + (iova >> MT2701_IOMMU_PAGE_SHIFT)); 401 pa = pa & (~(MT2701_IOMMU_PAGE_SIZE - 1)); 402 spin_unlock_irqrestore(&dom->pgtlock, flags); 403 404 return pa; 405 } 406 407 static const struct iommu_ops mtk_iommu_v1_ops; 408 409 /* 410 * MTK generation one iommu HW only support one iommu domain, and all the client 411 * sharing the same iova address space. 412 */ 413 static int mtk_iommu_v1_create_mapping(struct device *dev, 414 const struct of_phandle_args *args) 415 { 416 struct mtk_iommu_v1_data *data; 417 struct platform_device *m4updev; 418 struct dma_iommu_mapping *mtk_mapping; 419 int ret; 420 421 if (args->args_count != 1) { 422 dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n", 423 args->args_count); 424 return -EINVAL; 425 } 426 427 ret = iommu_fwspec_init(dev, of_fwnode_handle(args->np)); 428 if (ret) 429 return ret; 430 431 if (!dev_iommu_priv_get(dev)) { 432 /* Get the m4u device */ 433 m4updev = of_find_device_by_node(args->np); 434 if (WARN_ON(!m4updev)) 435 return -EINVAL; 436 437 dev_iommu_priv_set(dev, platform_get_drvdata(m4updev)); 438 } 439 440 ret = iommu_fwspec_add_ids(dev, args->args, 1); 441 if (ret) 442 return ret; 443 444 data = dev_iommu_priv_get(dev); 445 mtk_mapping = data->mapping; 446 if (!mtk_mapping) { 447 /* MTK iommu support 4GB iova address space. */ 448 mtk_mapping = arm_iommu_create_mapping(dev, 0, 1ULL << 32); 449 if (IS_ERR(mtk_mapping)) 450 return PTR_ERR(mtk_mapping); 451 452 data->mapping = mtk_mapping; 453 } 454 455 return 0; 456 } 457 458 static struct iommu_device *mtk_iommu_v1_probe_device(struct device *dev) 459 { 460 struct iommu_fwspec *fwspec = NULL; 461 struct of_phandle_args iommu_spec; 462 struct mtk_iommu_v1_data *data; 463 int err, idx = 0, larbid, larbidx; 464 struct device_link *link; 465 struct device *larbdev; 466 467 while (!of_parse_phandle_with_args(dev->of_node, "iommus", 468 "#iommu-cells", 469 idx, &iommu_spec)) { 470 471 err = mtk_iommu_v1_create_mapping(dev, &iommu_spec); 472 of_node_put(iommu_spec.np); 473 if (err) 474 return ERR_PTR(err); 475 476 /* dev->iommu_fwspec might have changed */ 477 fwspec = dev_iommu_fwspec_get(dev); 478 idx++; 479 } 480 481 if (!fwspec) 482 return ERR_PTR(-ENODEV); 483 484 data = dev_iommu_priv_get(dev); 485 486 /* Link the consumer device with the smi-larb device(supplier) */ 487 larbid = mt2701_m4u_to_larb(fwspec->ids[0]); 488 if (larbid >= MT2701_LARB_NR_MAX) 489 return ERR_PTR(-EINVAL); 490 491 for (idx = 1; idx < fwspec->num_ids; idx++) { 492 larbidx = mt2701_m4u_to_larb(fwspec->ids[idx]); 493 if (larbid != larbidx) { 494 dev_err(dev, "Can only use one larb. Fail@larb%d-%d.\n", 495 larbid, larbidx); 496 return ERR_PTR(-EINVAL); 497 } 498 } 499 500 larbdev = data->larb_imu[larbid].dev; 501 if (!larbdev) 502 return ERR_PTR(-EINVAL); 503 504 link = device_link_add(dev, larbdev, 505 DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS); 506 if (!link) 507 dev_err(dev, "Unable to link %s\n", dev_name(larbdev)); 508 509 return &data->iommu; 510 } 511 512 static void mtk_iommu_v1_probe_finalize(struct device *dev) 513 { 514 __maybe_unused struct mtk_iommu_v1_data *data = dev_iommu_priv_get(dev); 515 int err; 516 517 err = arm_iommu_attach_device(dev, data->mapping); 518 if (err) 519 dev_err(dev, "Can't create IOMMU mapping - DMA-OPS will not work\n"); 520 } 521 522 static void mtk_iommu_v1_release_device(struct device *dev) 523 { 524 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 525 struct mtk_iommu_v1_data *data; 526 struct device *larbdev; 527 unsigned int larbid; 528 529 data = dev_iommu_priv_get(dev); 530 larbid = mt2701_m4u_to_larb(fwspec->ids[0]); 531 larbdev = data->larb_imu[larbid].dev; 532 device_link_remove(dev, larbdev); 533 } 534 535 static int mtk_iommu_v1_hw_init(const struct mtk_iommu_v1_data *data) 536 { 537 u32 regval; 538 int ret; 539 540 ret = clk_prepare_enable(data->bclk); 541 if (ret) { 542 dev_err(data->dev, "Failed to enable iommu bclk(%d)\n", ret); 543 return ret; 544 } 545 546 regval = F_MMU_CTRL_COHERENT_EN | F_MMU_TF_PROTECT_SEL(2); 547 writel_relaxed(regval, data->base + REG_MMU_CTRL_REG); 548 549 regval = F_INT_TRANSLATION_FAULT | 550 F_INT_MAIN_MULTI_HIT_FAULT | 551 F_INT_INVALID_PA_FAULT | 552 F_INT_ENTRY_REPLACEMENT_FAULT | 553 F_INT_TABLE_WALK_FAULT | 554 F_INT_TLB_MISS_FAULT | 555 F_INT_PFH_DMA_FIFO_OVERFLOW | 556 F_INT_MISS_DMA_FIFO_OVERFLOW; 557 writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL); 558 559 /* protect memory,hw will write here while translation fault */ 560 writel_relaxed(data->protect_base, 561 data->base + REG_MMU_IVRP_PADDR); 562 563 writel_relaxed(F_MMU_DCM_ON, data->base + REG_MMU_DCM); 564 565 if (devm_request_irq(data->dev, data->irq, mtk_iommu_v1_isr, 0, 566 dev_name(data->dev), (void *)data)) { 567 writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR); 568 clk_disable_unprepare(data->bclk); 569 dev_err(data->dev, "Failed @ IRQ-%d Request\n", data->irq); 570 return -ENODEV; 571 } 572 573 return 0; 574 } 575 576 static const struct iommu_ops mtk_iommu_v1_ops = { 577 .identity_domain = &mtk_iommu_v1_identity_domain, 578 .domain_alloc_paging = mtk_iommu_v1_domain_alloc_paging, 579 .probe_device = mtk_iommu_v1_probe_device, 580 .probe_finalize = mtk_iommu_v1_probe_finalize, 581 .release_device = mtk_iommu_v1_release_device, 582 .device_group = generic_device_group, 583 .owner = THIS_MODULE, 584 .default_domain_ops = &(const struct iommu_domain_ops) { 585 .attach_dev = mtk_iommu_v1_attach_device, 586 .map_pages = mtk_iommu_v1_map, 587 .unmap_pages = mtk_iommu_v1_unmap, 588 .iova_to_phys = mtk_iommu_v1_iova_to_phys, 589 .free = mtk_iommu_v1_domain_free, 590 } 591 }; 592 593 static const struct of_device_id mtk_iommu_v1_of_ids[] = { 594 { .compatible = "mediatek,mt2701-m4u", }, 595 {} 596 }; 597 MODULE_DEVICE_TABLE(of, mtk_iommu_v1_of_ids); 598 599 static const struct component_master_ops mtk_iommu_v1_com_ops = { 600 .bind = mtk_iommu_v1_bind, 601 .unbind = mtk_iommu_v1_unbind, 602 }; 603 604 static int mtk_iommu_v1_probe(struct platform_device *pdev) 605 { 606 struct device *dev = &pdev->dev; 607 struct mtk_iommu_v1_data *data; 608 struct resource *res; 609 struct component_match *match = NULL; 610 void *protect; 611 int larb_nr, ret, i; 612 613 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 614 if (!data) 615 return -ENOMEM; 616 617 data->dev = dev; 618 619 /* Protect memory. HW will access here while translation fault.*/ 620 protect = devm_kcalloc(dev, 2, MTK_PROTECT_PA_ALIGN, 621 GFP_KERNEL | GFP_DMA); 622 if (!protect) 623 return -ENOMEM; 624 data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN); 625 626 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 627 data->base = devm_ioremap_resource(dev, res); 628 if (IS_ERR(data->base)) 629 return PTR_ERR(data->base); 630 631 data->irq = platform_get_irq(pdev, 0); 632 if (data->irq < 0) 633 return data->irq; 634 635 data->bclk = devm_clk_get(dev, "bclk"); 636 if (IS_ERR(data->bclk)) 637 return PTR_ERR(data->bclk); 638 639 larb_nr = of_count_phandle_with_args(dev->of_node, 640 "mediatek,larbs", NULL); 641 if (larb_nr < 0) 642 return larb_nr; 643 644 for (i = 0; i < larb_nr; i++) { 645 struct device_node *larbnode; 646 struct platform_device *plarbdev; 647 648 larbnode = of_parse_phandle(dev->of_node, "mediatek,larbs", i); 649 if (!larbnode) 650 return -EINVAL; 651 652 if (!of_device_is_available(larbnode)) { 653 of_node_put(larbnode); 654 continue; 655 } 656 657 plarbdev = of_find_device_by_node(larbnode); 658 if (!plarbdev) { 659 of_node_put(larbnode); 660 return -ENODEV; 661 } 662 if (!plarbdev->dev.driver) { 663 of_node_put(larbnode); 664 return -EPROBE_DEFER; 665 } 666 data->larb_imu[i].dev = &plarbdev->dev; 667 668 component_match_add_release(dev, &match, component_release_of, 669 component_compare_of, larbnode); 670 } 671 672 platform_set_drvdata(pdev, data); 673 674 ret = mtk_iommu_v1_hw_init(data); 675 if (ret) 676 return ret; 677 678 ret = iommu_device_sysfs_add(&data->iommu, &pdev->dev, NULL, 679 dev_name(&pdev->dev)); 680 if (ret) 681 goto out_clk_unprepare; 682 683 ret = iommu_device_register(&data->iommu, &mtk_iommu_v1_ops, dev); 684 if (ret) 685 goto out_sysfs_remove; 686 687 ret = component_master_add_with_match(dev, &mtk_iommu_v1_com_ops, match); 688 if (ret) 689 goto out_dev_unreg; 690 return ret; 691 692 out_dev_unreg: 693 iommu_device_unregister(&data->iommu); 694 out_sysfs_remove: 695 iommu_device_sysfs_remove(&data->iommu); 696 out_clk_unprepare: 697 clk_disable_unprepare(data->bclk); 698 return ret; 699 } 700 701 static void mtk_iommu_v1_remove(struct platform_device *pdev) 702 { 703 struct mtk_iommu_v1_data *data = platform_get_drvdata(pdev); 704 705 iommu_device_sysfs_remove(&data->iommu); 706 iommu_device_unregister(&data->iommu); 707 708 clk_disable_unprepare(data->bclk); 709 devm_free_irq(&pdev->dev, data->irq, data); 710 component_master_del(&pdev->dev, &mtk_iommu_v1_com_ops); 711 } 712 713 static int __maybe_unused mtk_iommu_v1_suspend(struct device *dev) 714 { 715 struct mtk_iommu_v1_data *data = dev_get_drvdata(dev); 716 struct mtk_iommu_v1_suspend_reg *reg = &data->reg; 717 void __iomem *base = data->base; 718 719 reg->standard_axi_mode = readl_relaxed(base + 720 REG_MMU_STANDARD_AXI_MODE); 721 reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM); 722 reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG); 723 reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL); 724 return 0; 725 } 726 727 static int __maybe_unused mtk_iommu_v1_resume(struct device *dev) 728 { 729 struct mtk_iommu_v1_data *data = dev_get_drvdata(dev); 730 struct mtk_iommu_v1_suspend_reg *reg = &data->reg; 731 void __iomem *base = data->base; 732 733 writel_relaxed(data->m4u_dom->pgt_pa, base + REG_MMU_PT_BASE_ADDR); 734 writel_relaxed(reg->standard_axi_mode, 735 base + REG_MMU_STANDARD_AXI_MODE); 736 writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM); 737 writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG); 738 writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL); 739 writel_relaxed(data->protect_base, base + REG_MMU_IVRP_PADDR); 740 return 0; 741 } 742 743 static const struct dev_pm_ops mtk_iommu_v1_pm_ops = { 744 SET_SYSTEM_SLEEP_PM_OPS(mtk_iommu_v1_suspend, mtk_iommu_v1_resume) 745 }; 746 747 static struct platform_driver mtk_iommu_v1_driver = { 748 .probe = mtk_iommu_v1_probe, 749 .remove = mtk_iommu_v1_remove, 750 .driver = { 751 .name = "mtk-iommu-v1", 752 .of_match_table = mtk_iommu_v1_of_ids, 753 .pm = &mtk_iommu_v1_pm_ops, 754 } 755 }; 756 module_platform_driver(mtk_iommu_v1_driver); 757 758 MODULE_DESCRIPTION("IOMMU API for MediaTek M4U v1 implementations"); 759 MODULE_LICENSE("GPL v2"); 760