1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015-2016 MediaTek Inc. 4 * Author: Yong Wu <yong.wu@mediatek.com> 5 */ 6 #include <linux/arm-smccc.h> 7 #include <linux/bitfield.h> 8 #include <linux/bug.h> 9 #include <linux/clk.h> 10 #include <linux/component.h> 11 #include <linux/device.h> 12 #include <linux/err.h> 13 #include <linux/interrupt.h> 14 #include <linux/io.h> 15 #include <linux/iommu.h> 16 #include <linux/iopoll.h> 17 #include <linux/io-pgtable.h> 18 #include <linux/list.h> 19 #include <linux/mfd/syscon.h> 20 #include <linux/module.h> 21 #include <linux/of_address.h> 22 #include <linux/of_irq.h> 23 #include <linux/of_platform.h> 24 #include <linux/pci.h> 25 #include <linux/platform_device.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/regmap.h> 28 #include <linux/slab.h> 29 #include <linux/spinlock.h> 30 #include <linux/soc/mediatek/infracfg.h> 31 #include <linux/soc/mediatek/mtk_sip_svc.h> 32 #include <linux/string_choices.h> 33 #include <asm/barrier.h> 34 #include <soc/mediatek/smi.h> 35 36 #include <dt-bindings/memory/mtk-memory-port.h> 37 38 #define REG_MMU_PT_BASE_ADDR 0x000 39 40 #define REG_MMU_INVALIDATE 0x020 41 #define F_ALL_INVLD 0x2 42 #define F_MMU_INV_RANGE 0x1 43 44 #define REG_MMU_INVLD_START_A 0x024 45 #define REG_MMU_INVLD_END_A 0x028 46 47 #define REG_MMU_INV_SEL_GEN2 0x02c 48 #define REG_MMU_INV_SEL_GEN1 0x038 49 #define F_INVLD_EN0 BIT(0) 50 #define F_INVLD_EN1 BIT(1) 51 52 #define REG_MMU_MISC_CTRL 0x048 53 #define F_MMU_IN_ORDER_WR_EN_MASK (BIT(1) | BIT(17)) 54 #define F_MMU_STANDARD_AXI_MODE_MASK (BIT(3) | BIT(19)) 55 56 #define REG_MMU_DCM_DIS 0x050 57 #define F_MMU_DCM BIT(8) 58 59 #define REG_MMU_WR_LEN_CTRL 0x054 60 #define F_MMU_WR_THROT_DIS_MASK (BIT(5) | BIT(21)) 61 62 #define REG_MMU_CTRL_REG 0x110 63 #define F_MMU_TF_PROT_TO_PROGRAM_ADDR (2 << 4) 64 #define F_MMU_PREFETCH_RT_REPLACE_MOD BIT(4) 65 #define F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173 (2 << 5) 66 67 #define REG_MMU_IVRP_PADDR 0x114 68 69 #define REG_MMU_VLD_PA_RNG 0x118 70 #define F_MMU_VLD_PA_RNG(EA, SA) (((EA) << 8) | (SA)) 71 72 #define REG_MMU_INT_CONTROL0 0x120 73 #define F_L2_MULIT_HIT_EN BIT(0) 74 #define F_TABLE_WALK_FAULT_INT_EN BIT(1) 75 #define F_PREETCH_FIFO_OVERFLOW_INT_EN BIT(2) 76 #define F_MISS_FIFO_OVERFLOW_INT_EN BIT(3) 77 #define F_PREFETCH_FIFO_ERR_INT_EN BIT(5) 78 #define F_MISS_FIFO_ERR_INT_EN BIT(6) 79 #define F_INT_CLR_BIT BIT(12) 80 81 #define REG_MMU_INT_MAIN_CONTROL 0x124 82 /* mmu0 | mmu1 */ 83 #define F_INT_TRANSLATION_FAULT (BIT(0) | BIT(7)) 84 #define F_INT_MAIN_MULTI_HIT_FAULT (BIT(1) | BIT(8)) 85 #define F_INT_INVALID_PA_FAULT (BIT(2) | BIT(9)) 86 #define F_INT_ENTRY_REPLACEMENT_FAULT (BIT(3) | BIT(10)) 87 #define F_INT_TLB_MISS_FAULT (BIT(4) | BIT(11)) 88 #define F_INT_MISS_TRANSACTION_FIFO_FAULT (BIT(5) | BIT(12)) 89 #define F_INT_PRETETCH_TRANSATION_FIFO_FAULT (BIT(6) | BIT(13)) 90 91 #define REG_MMU_CPE_DONE 0x12C 92 93 #define REG_MMU_FAULT_ST1 0x134 94 #define F_REG_MMU0_FAULT_MASK GENMASK(6, 0) 95 #define F_REG_MMU1_FAULT_MASK GENMASK(13, 7) 96 97 #define REG_MMU0_FAULT_VA 0x13c 98 #define F_MMU_INVAL_VA_31_12_MASK GENMASK(31, 12) 99 #define F_MMU_INVAL_VA_34_32_MASK GENMASK(11, 9) 100 #define F_MMU_INVAL_PA_34_32_MASK GENMASK(8, 6) 101 #define F_MMU_FAULT_VA_WRITE_BIT BIT(1) 102 #define F_MMU_FAULT_VA_LAYER_BIT BIT(0) 103 104 #define REG_MMU0_INVLD_PA 0x140 105 #define REG_MMU1_FAULT_VA 0x144 106 #define REG_MMU1_INVLD_PA 0x148 107 #define REG_MMU0_INT_ID 0x150 108 #define REG_MMU1_INT_ID 0x154 109 #define F_MMU_INT_ID_COMM_ID(a) (((a) >> 9) & 0x7) 110 #define F_MMU_INT_ID_SUB_COMM_ID(a) (((a) >> 7) & 0x3) 111 #define F_MMU_INT_ID_COMM_ID_EXT(a) (((a) >> 10) & 0x7) 112 #define F_MMU_INT_ID_SUB_COMM_ID_EXT(a) (((a) >> 7) & 0x7) 113 /* Macro for 5 bits length port ID field (default) */ 114 #define F_MMU_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7) 115 #define F_MMU_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f) 116 /* Macro for 6 bits length port ID field */ 117 #define F_MMU_INT_ID_LARB_ID_WID_6(a) (((a) >> 8) & 0x7) 118 #define F_MMU_INT_ID_PORT_ID_WID_6(a) (((a) >> 2) & 0x3f) 119 120 #define MTK_PROTECT_PA_ALIGN 256 121 #define MTK_IOMMU_BANK_SZ 0x1000 122 123 #define PERICFG_IOMMU_1 0x714 124 125 #define HAS_4GB_MODE BIT(0) 126 /* HW will use the EMI clock if there isn't the "bclk". */ 127 #define HAS_BCLK BIT(1) 128 #define HAS_VLD_PA_RNG BIT(2) 129 #define RESET_AXI BIT(3) 130 #define OUT_ORDER_WR_EN BIT(4) 131 #define HAS_SUB_COMM_2BITS BIT(5) 132 #define HAS_SUB_COMM_3BITS BIT(6) 133 #define WR_THROT_EN BIT(7) 134 #define HAS_LEGACY_IVRP_PADDR BIT(8) 135 #define IOVA_34_EN BIT(9) 136 #define SHARE_PGTABLE BIT(10) /* 2 HW share pgtable */ 137 #define DCM_DISABLE BIT(11) 138 #define STD_AXI_MODE BIT(12) /* For non MM iommu */ 139 /* 2 bits: iommu type */ 140 #define MTK_IOMMU_TYPE_MM (0x0 << 13) 141 #define MTK_IOMMU_TYPE_INFRA (0x1 << 13) 142 #define MTK_IOMMU_TYPE_MASK (0x3 << 13) 143 /* PM and clock always on. e.g. infra iommu */ 144 #define PM_CLK_AO BIT(15) 145 #define IFA_IOMMU_PCIE_SUPPORT BIT(16) 146 #define PGTABLE_PA_35_EN BIT(17) 147 #define TF_PORT_TO_ADDR_MT8173 BIT(18) 148 #define INT_ID_PORT_WIDTH_6 BIT(19) 149 #define CFG_IFA_MASTER_IN_ATF BIT(20) 150 151 #define MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, mask) \ 152 ((((pdata)->flags) & (mask)) == (_x)) 153 154 #define MTK_IOMMU_HAS_FLAG(pdata, _x) MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, _x) 155 #define MTK_IOMMU_IS_TYPE(pdata, _x) MTK_IOMMU_HAS_FLAG_MASK(pdata, _x,\ 156 MTK_IOMMU_TYPE_MASK) 157 158 #define MTK_INVALID_LARBID MTK_LARB_NR_MAX 159 160 #define MTK_LARB_COM_MAX 8 161 #define MTK_LARB_SUBCOM_MAX 8 162 163 #define MTK_IOMMU_GROUP_MAX 8 164 #define MTK_IOMMU_BANK_MAX 5 165 166 enum mtk_iommu_plat { 167 M4U_MT2712, 168 M4U_MT6779, 169 M4U_MT6795, 170 M4U_MT8167, 171 M4U_MT8173, 172 M4U_MT8183, 173 M4U_MT8186, 174 M4U_MT8188, 175 M4U_MT8192, 176 M4U_MT8195, 177 M4U_MT8365, 178 }; 179 180 struct mtk_iommu_iova_region { 181 dma_addr_t iova_base; 182 unsigned long long size; 183 }; 184 185 struct mtk_iommu_suspend_reg { 186 u32 misc_ctrl; 187 u32 dcm_dis; 188 u32 ctrl_reg; 189 u32 vld_pa_rng; 190 u32 wr_len_ctrl; 191 192 u32 int_control[MTK_IOMMU_BANK_MAX]; 193 u32 int_main_control[MTK_IOMMU_BANK_MAX]; 194 u32 ivrp_paddr[MTK_IOMMU_BANK_MAX]; 195 }; 196 197 struct mtk_iommu_plat_data { 198 enum mtk_iommu_plat m4u_plat; 199 u32 flags; 200 u32 inv_sel_reg; 201 202 char *pericfg_comp_str; 203 struct list_head *hw_list; 204 205 /* 206 * The IOMMU HW may support 16GB iova. In order to balance the IOVA ranges, 207 * different masters will be put in different iova ranges, for example vcodec 208 * is in 4G-8G and cam is in 8G-12G. Meanwhile, some masters may have the 209 * special IOVA range requirement, like CCU can only support the address 210 * 0x40000000-0x44000000. 211 * Here list the iova ranges this SoC supports and which larbs/ports are in 212 * which region. 213 * 214 * 16GB iova all use one pgtable, but each a region is a iommu group. 215 */ 216 struct { 217 unsigned int iova_region_nr; 218 const struct mtk_iommu_iova_region *iova_region; 219 /* 220 * Indicate the correspondance between larbs, ports and regions. 221 * 222 * The index is the same as iova_region and larb port numbers are 223 * described as bit positions. 224 * For example, storing BIT(0) at index 2,1 means "larb 1, port0 is in region 2". 225 * [2] = { [1] = BIT(0) } 226 */ 227 const u32 (*iova_region_larb_msk)[MTK_LARB_NR_MAX]; 228 }; 229 230 /* 231 * The IOMMU HW may have 5 banks. Each bank has a independent pgtable. 232 * Here list how many banks this SoC supports/enables and which ports are in which bank. 233 */ 234 struct { 235 u8 banks_num; 236 bool banks_enable[MTK_IOMMU_BANK_MAX]; 237 unsigned int banks_portmsk[MTK_IOMMU_BANK_MAX]; 238 }; 239 240 unsigned char larbid_remap[MTK_LARB_COM_MAX][MTK_LARB_SUBCOM_MAX]; 241 }; 242 243 struct mtk_iommu_bank_data { 244 void __iomem *base; 245 int irq; 246 u8 id; 247 struct device *parent_dev; 248 struct mtk_iommu_data *parent_data; 249 spinlock_t tlb_lock; /* lock for tlb range flush */ 250 struct mtk_iommu_domain *m4u_dom; /* Each bank has a domain */ 251 }; 252 253 struct mtk_iommu_data { 254 struct device *dev; 255 struct clk *bclk; 256 phys_addr_t protect_base; /* protect memory base */ 257 struct mtk_iommu_suspend_reg reg; 258 struct iommu_group *m4u_group[MTK_IOMMU_GROUP_MAX]; 259 bool enable_4GB; 260 261 struct iommu_device iommu; 262 const struct mtk_iommu_plat_data *plat_data; 263 struct device *smicomm_dev; 264 265 struct mtk_iommu_bank_data *bank; 266 struct mtk_iommu_domain *share_dom; 267 268 struct regmap *pericfg; 269 struct mutex mutex; /* Protect m4u_group/m4u_dom above */ 270 271 /* 272 * In the sharing pgtable case, list data->list to the global list like m4ulist. 273 * In the non-sharing pgtable case, list data->list to the itself hw_list_head. 274 */ 275 struct list_head *hw_list; 276 struct list_head hw_list_head; 277 struct list_head list; 278 struct mtk_smi_larb_iommu larb_imu[MTK_LARB_NR_MAX]; 279 }; 280 281 struct mtk_iommu_domain { 282 struct io_pgtable_cfg cfg; 283 struct io_pgtable_ops *iop; 284 285 struct mtk_iommu_bank_data *bank; 286 struct iommu_domain domain; 287 288 struct mutex mutex; /* Protect "data" in this structure */ 289 }; 290 291 static int mtk_iommu_bind(struct device *dev) 292 { 293 struct mtk_iommu_data *data = dev_get_drvdata(dev); 294 295 return component_bind_all(dev, &data->larb_imu); 296 } 297 298 static void mtk_iommu_unbind(struct device *dev) 299 { 300 struct mtk_iommu_data *data = dev_get_drvdata(dev); 301 302 component_unbind_all(dev, &data->larb_imu); 303 } 304 305 static const struct iommu_ops mtk_iommu_ops; 306 307 static int mtk_iommu_hw_init(const struct mtk_iommu_data *data, unsigned int bankid); 308 309 #define MTK_IOMMU_TLB_ADDR(iova) ({ \ 310 dma_addr_t _addr = iova; \ 311 ((lower_32_bits(_addr) & GENMASK(31, 12)) | upper_32_bits(_addr));\ 312 }) 313 314 /* 315 * In M4U 4GB mode, the physical address is remapped as below: 316 * 317 * CPU Physical address: 318 * ==================== 319 * 320 * 0 1G 2G 3G 4G 5G 321 * |---A---|---B---|---C---|---D---|---E---| 322 * +--I/O--+------------Memory-------------+ 323 * 324 * IOMMU output physical address: 325 * ============================= 326 * 327 * 4G 5G 6G 7G 8G 328 * |---E---|---B---|---C---|---D---| 329 * +------------Memory-------------+ 330 * 331 * The Region 'A'(I/O) can NOT be mapped by M4U; For Region 'B'/'C'/'D', the 332 * bit32 of the CPU physical address always is needed to set, and for Region 333 * 'E', the CPU physical address keep as is. 334 * Additionally, The iommu consumers always use the CPU phyiscal address. 335 */ 336 #define MTK_IOMMU_4GB_MODE_REMAP_BASE 0x140000000UL 337 338 static LIST_HEAD(m4ulist); /* List all the M4U HWs */ 339 340 #define for_each_m4u(data, head) list_for_each_entry(data, head, list) 341 342 #define MTK_IOMMU_IOVA_SZ_4G (SZ_4G - SZ_8M) /* 8M as gap */ 343 344 static const struct mtk_iommu_iova_region single_domain[] = { 345 {.iova_base = 0, .size = MTK_IOMMU_IOVA_SZ_4G}, 346 }; 347 348 #define MT8192_MULTI_REGION_NR_MAX 6 349 350 #define MT8192_MULTI_REGION_NR (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) ? \ 351 MT8192_MULTI_REGION_NR_MAX : 1) 352 353 static const struct mtk_iommu_iova_region mt8192_multi_dom[MT8192_MULTI_REGION_NR] = { 354 { .iova_base = 0x0, .size = MTK_IOMMU_IOVA_SZ_4G}, /* 0 ~ 4G, */ 355 #if IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) 356 { .iova_base = SZ_4G, .size = MTK_IOMMU_IOVA_SZ_4G}, /* 4G ~ 8G */ 357 { .iova_base = SZ_4G * 2, .size = MTK_IOMMU_IOVA_SZ_4G}, /* 8G ~ 12G */ 358 { .iova_base = SZ_4G * 3, .size = MTK_IOMMU_IOVA_SZ_4G}, /* 12G ~ 16G */ 359 360 { .iova_base = 0x240000000ULL, .size = 0x4000000}, /* CCU0 */ 361 { .iova_base = 0x244000000ULL, .size = 0x4000000}, /* CCU1 */ 362 #endif 363 }; 364 365 /* If 2 M4U share a domain(use the same hwlist), Put the corresponding info in first data.*/ 366 static struct mtk_iommu_data *mtk_iommu_get_frst_data(struct list_head *hwlist) 367 { 368 return list_first_entry(hwlist, struct mtk_iommu_data, list); 369 } 370 371 static struct mtk_iommu_domain *to_mtk_domain(struct iommu_domain *dom) 372 { 373 return container_of(dom, struct mtk_iommu_domain, domain); 374 } 375 376 static void mtk_iommu_tlb_flush_all(struct mtk_iommu_data *data) 377 { 378 /* Tlb flush all always is in bank0. */ 379 struct mtk_iommu_bank_data *bank = &data->bank[0]; 380 void __iomem *base = bank->base; 381 unsigned long flags; 382 383 spin_lock_irqsave(&bank->tlb_lock, flags); 384 writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, base + data->plat_data->inv_sel_reg); 385 writel_relaxed(F_ALL_INVLD, base + REG_MMU_INVALIDATE); 386 wmb(); /* Make sure the tlb flush all done */ 387 spin_unlock_irqrestore(&bank->tlb_lock, flags); 388 } 389 390 static void mtk_iommu_tlb_flush_range_sync(unsigned long iova, size_t size, 391 struct mtk_iommu_bank_data *bank) 392 { 393 struct list_head *head = bank->parent_data->hw_list; 394 struct mtk_iommu_bank_data *curbank; 395 struct mtk_iommu_data *data; 396 bool check_pm_status; 397 unsigned long flags; 398 void __iomem *base; 399 int ret; 400 u32 tmp; 401 402 for_each_m4u(data, head) { 403 /* 404 * To avoid resume the iommu device frequently when the iommu device 405 * is not active, it doesn't always call pm_runtime_get here, then tlb 406 * flush depends on the tlb flush all in the runtime resume. 407 * 408 * There are 2 special cases: 409 * 410 * Case1: The iommu dev doesn't have power domain but has bclk. This case 411 * should also avoid the tlb flush while the dev is not active to mute 412 * the tlb timeout log. like mt8173. 413 * 414 * Case2: The power/clock of infra iommu is always on, and it doesn't 415 * have the device link with the master devices. This case should avoid 416 * the PM status check. 417 */ 418 check_pm_status = !MTK_IOMMU_HAS_FLAG(data->plat_data, PM_CLK_AO); 419 420 if (check_pm_status) { 421 if (pm_runtime_get_if_in_use(data->dev) <= 0) 422 continue; 423 } 424 425 curbank = &data->bank[bank->id]; 426 base = curbank->base; 427 428 spin_lock_irqsave(&curbank->tlb_lock, flags); 429 writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, 430 base + data->plat_data->inv_sel_reg); 431 432 writel_relaxed(MTK_IOMMU_TLB_ADDR(iova), base + REG_MMU_INVLD_START_A); 433 writel_relaxed(MTK_IOMMU_TLB_ADDR(iova + size - 1), 434 base + REG_MMU_INVLD_END_A); 435 writel_relaxed(F_MMU_INV_RANGE, base + REG_MMU_INVALIDATE); 436 437 /* tlb sync */ 438 ret = readl_poll_timeout_atomic(base + REG_MMU_CPE_DONE, 439 tmp, tmp != 0, 10, 1000); 440 441 /* Clear the CPE status */ 442 writel_relaxed(0, base + REG_MMU_CPE_DONE); 443 spin_unlock_irqrestore(&curbank->tlb_lock, flags); 444 445 if (ret) { 446 dev_warn(data->dev, 447 "Partial TLB flush timed out, falling back to full flush\n"); 448 mtk_iommu_tlb_flush_all(data); 449 } 450 451 if (check_pm_status) 452 pm_runtime_put(data->dev); 453 } 454 } 455 456 static irqreturn_t mtk_iommu_isr(int irq, void *dev_id) 457 { 458 struct mtk_iommu_bank_data *bank = dev_id; 459 struct mtk_iommu_data *data = bank->parent_data; 460 struct mtk_iommu_domain *dom = bank->m4u_dom; 461 unsigned int fault_larb = MTK_INVALID_LARBID, fault_port = 0, sub_comm = 0; 462 u32 int_state, regval, va34_32, pa34_32; 463 const struct mtk_iommu_plat_data *plat_data = data->plat_data; 464 void __iomem *base = bank->base; 465 u64 fault_iova, fault_pa; 466 bool layer, write; 467 468 /* Read error info from registers */ 469 int_state = readl_relaxed(base + REG_MMU_FAULT_ST1); 470 if (int_state & F_REG_MMU0_FAULT_MASK) { 471 regval = readl_relaxed(base + REG_MMU0_INT_ID); 472 fault_iova = readl_relaxed(base + REG_MMU0_FAULT_VA); 473 fault_pa = readl_relaxed(base + REG_MMU0_INVLD_PA); 474 } else { 475 regval = readl_relaxed(base + REG_MMU1_INT_ID); 476 fault_iova = readl_relaxed(base + REG_MMU1_FAULT_VA); 477 fault_pa = readl_relaxed(base + REG_MMU1_INVLD_PA); 478 } 479 layer = fault_iova & F_MMU_FAULT_VA_LAYER_BIT; 480 write = fault_iova & F_MMU_FAULT_VA_WRITE_BIT; 481 if (MTK_IOMMU_HAS_FLAG(plat_data, IOVA_34_EN)) { 482 va34_32 = FIELD_GET(F_MMU_INVAL_VA_34_32_MASK, fault_iova); 483 fault_iova = fault_iova & F_MMU_INVAL_VA_31_12_MASK; 484 fault_iova |= (u64)va34_32 << 32; 485 } 486 pa34_32 = FIELD_GET(F_MMU_INVAL_PA_34_32_MASK, fault_iova); 487 fault_pa |= (u64)pa34_32 << 32; 488 489 if (MTK_IOMMU_IS_TYPE(plat_data, MTK_IOMMU_TYPE_MM)) { 490 if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_SUB_COMM_2BITS)) { 491 fault_larb = F_MMU_INT_ID_COMM_ID(regval); 492 sub_comm = F_MMU_INT_ID_SUB_COMM_ID(regval); 493 fault_port = F_MMU_INT_ID_PORT_ID(regval); 494 } else if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_SUB_COMM_3BITS)) { 495 fault_larb = F_MMU_INT_ID_COMM_ID_EXT(regval); 496 sub_comm = F_MMU_INT_ID_SUB_COMM_ID_EXT(regval); 497 fault_port = F_MMU_INT_ID_PORT_ID(regval); 498 } else if (MTK_IOMMU_HAS_FLAG(plat_data, INT_ID_PORT_WIDTH_6)) { 499 fault_port = F_MMU_INT_ID_PORT_ID_WID_6(regval); 500 fault_larb = F_MMU_INT_ID_LARB_ID_WID_6(regval); 501 } else { 502 fault_port = F_MMU_INT_ID_PORT_ID(regval); 503 fault_larb = F_MMU_INT_ID_LARB_ID(regval); 504 } 505 fault_larb = data->plat_data->larbid_remap[fault_larb][sub_comm]; 506 } 507 508 if (!dom || report_iommu_fault(&dom->domain, bank->parent_dev, fault_iova, 509 write ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ)) { 510 dev_err_ratelimited( 511 bank->parent_dev, 512 "fault type=0x%x iova=0x%llx pa=0x%llx master=0x%x(larb=%d port=%d) layer=%d %s\n", 513 int_state, fault_iova, fault_pa, regval, fault_larb, fault_port, 514 layer, str_write_read(write)); 515 } 516 517 /* Interrupt clear */ 518 regval = readl_relaxed(base + REG_MMU_INT_CONTROL0); 519 regval |= F_INT_CLR_BIT; 520 writel_relaxed(regval, base + REG_MMU_INT_CONTROL0); 521 522 mtk_iommu_tlb_flush_all(data); 523 524 return IRQ_HANDLED; 525 } 526 527 static unsigned int mtk_iommu_get_bank_id(struct device *dev, 528 const struct mtk_iommu_plat_data *plat_data) 529 { 530 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 531 unsigned int i, portmsk = 0, bankid = 0; 532 533 if (plat_data->banks_num == 1) 534 return bankid; 535 536 for (i = 0; i < fwspec->num_ids; i++) 537 portmsk |= BIT(MTK_M4U_TO_PORT(fwspec->ids[i])); 538 539 for (i = 0; i < plat_data->banks_num && i < MTK_IOMMU_BANK_MAX; i++) { 540 if (!plat_data->banks_enable[i]) 541 continue; 542 543 if (portmsk & plat_data->banks_portmsk[i]) { 544 bankid = i; 545 break; 546 } 547 } 548 return bankid; /* default is 0 */ 549 } 550 551 static int mtk_iommu_get_iova_region_id(struct device *dev, 552 const struct mtk_iommu_plat_data *plat_data) 553 { 554 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 555 unsigned int portidmsk = 0, larbid; 556 const u32 *rgn_larb_msk; 557 int i; 558 559 if (plat_data->iova_region_nr == 1) 560 return 0; 561 562 larbid = MTK_M4U_TO_LARB(fwspec->ids[0]); 563 for (i = 0; i < fwspec->num_ids; i++) 564 portidmsk |= BIT(MTK_M4U_TO_PORT(fwspec->ids[i])); 565 566 for (i = 0; i < plat_data->iova_region_nr; i++) { 567 rgn_larb_msk = plat_data->iova_region_larb_msk[i]; 568 if (!rgn_larb_msk) 569 continue; 570 571 if ((rgn_larb_msk[larbid] & portidmsk) == portidmsk) 572 return i; 573 } 574 575 dev_err(dev, "Can NOT find the region for larb(%d-%x).\n", 576 larbid, portidmsk); 577 return -EINVAL; 578 } 579 580 static int mtk_iommu_config(struct mtk_iommu_data *data, struct device *dev, 581 bool enable, unsigned int regionid) 582 { 583 struct mtk_smi_larb_iommu *larb_mmu; 584 unsigned int larbid, portid; 585 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 586 const struct mtk_iommu_iova_region *region; 587 unsigned long portid_msk = 0; 588 struct arm_smccc_res res; 589 int i, ret = 0; 590 591 for (i = 0; i < fwspec->num_ids; ++i) { 592 portid = MTK_M4U_TO_PORT(fwspec->ids[i]); 593 portid_msk |= BIT(portid); 594 } 595 596 if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) { 597 /* All ports should be in the same larb. just use 0 here */ 598 larbid = MTK_M4U_TO_LARB(fwspec->ids[0]); 599 larb_mmu = &data->larb_imu[larbid]; 600 region = data->plat_data->iova_region + regionid; 601 602 for_each_set_bit(portid, &portid_msk, 32) 603 larb_mmu->bank[portid] = upper_32_bits(region->iova_base); 604 605 dev_dbg(dev, "%s iommu for larb(%s) port 0x%lx region %d rgn-bank %d.\n", 606 str_enable_disable(enable), dev_name(larb_mmu->dev), 607 portid_msk, regionid, upper_32_bits(region->iova_base)); 608 609 if (enable) 610 larb_mmu->mmu |= portid_msk; 611 else 612 larb_mmu->mmu &= ~portid_msk; 613 } else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA)) { 614 if (MTK_IOMMU_HAS_FLAG(data->plat_data, CFG_IFA_MASTER_IN_ATF)) { 615 arm_smccc_smc(MTK_SIP_KERNEL_IOMMU_CONTROL, 616 IOMMU_ATF_CMD_CONFIG_INFRA_IOMMU, 617 portid_msk, enable, 0, 0, 0, 0, &res); 618 ret = res.a0; 619 } else { 620 /* PCI dev has only one output id, enable the next writing bit for PCIe */ 621 if (dev_is_pci(dev)) { 622 if (fwspec->num_ids != 1) { 623 dev_err(dev, "PCI dev can only have one port.\n"); 624 return -ENODEV; 625 } 626 portid_msk |= BIT(portid + 1); 627 } 628 629 ret = regmap_update_bits(data->pericfg, PERICFG_IOMMU_1, 630 (u32)portid_msk, enable ? (u32)portid_msk : 0); 631 } 632 if (ret) 633 dev_err(dev, "%s iommu(%s) inframaster 0x%lx fail(%d).\n", 634 str_enable_disable(enable), dev_name(data->dev), 635 portid_msk, ret); 636 } 637 return ret; 638 } 639 640 static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom, 641 struct mtk_iommu_data *data, 642 unsigned int region_id) 643 { 644 struct mtk_iommu_domain *share_dom = data->share_dom; 645 const struct mtk_iommu_iova_region *region; 646 647 /* Share pgtable when 2 MM IOMMU share the pgtable or one IOMMU use multiple iova ranges */ 648 if (share_dom) { 649 dom->iop = share_dom->iop; 650 dom->cfg = share_dom->cfg; 651 dom->domain.pgsize_bitmap = share_dom->cfg.pgsize_bitmap; 652 goto update_iova_region; 653 } 654 655 dom->cfg = (struct io_pgtable_cfg) { 656 .quirks = IO_PGTABLE_QUIRK_ARM_NS | 657 IO_PGTABLE_QUIRK_NO_PERMS | 658 IO_PGTABLE_QUIRK_ARM_MTK_EXT, 659 .pgsize_bitmap = mtk_iommu_ops.pgsize_bitmap, 660 .ias = MTK_IOMMU_HAS_FLAG(data->plat_data, IOVA_34_EN) ? 34 : 32, 661 .iommu_dev = data->dev, 662 }; 663 664 if (MTK_IOMMU_HAS_FLAG(data->plat_data, PGTABLE_PA_35_EN)) 665 dom->cfg.quirks |= IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT; 666 667 if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE)) 668 dom->cfg.oas = data->enable_4GB ? 33 : 32; 669 else 670 dom->cfg.oas = 35; 671 672 dom->iop = alloc_io_pgtable_ops(ARM_V7S, &dom->cfg, data); 673 if (!dom->iop) { 674 dev_err(data->dev, "Failed to alloc io pgtable\n"); 675 return -ENOMEM; 676 } 677 678 /* Update our support page sizes bitmap */ 679 dom->domain.pgsize_bitmap = dom->cfg.pgsize_bitmap; 680 681 data->share_dom = dom; 682 683 update_iova_region: 684 /* Update the iova region for this domain */ 685 region = data->plat_data->iova_region + region_id; 686 dom->domain.geometry.aperture_start = region->iova_base; 687 dom->domain.geometry.aperture_end = region->iova_base + region->size - 1; 688 dom->domain.geometry.force_aperture = true; 689 return 0; 690 } 691 692 static struct iommu_domain *mtk_iommu_domain_alloc_paging(struct device *dev) 693 { 694 struct mtk_iommu_domain *dom; 695 696 dom = kzalloc(sizeof(*dom), GFP_KERNEL); 697 if (!dom) 698 return NULL; 699 mutex_init(&dom->mutex); 700 701 return &dom->domain; 702 } 703 704 static void mtk_iommu_domain_free(struct iommu_domain *domain) 705 { 706 kfree(to_mtk_domain(domain)); 707 } 708 709 static int mtk_iommu_attach_device(struct iommu_domain *domain, 710 struct device *dev) 711 { 712 struct mtk_iommu_data *data = dev_iommu_priv_get(dev), *frstdata; 713 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 714 struct list_head *hw_list = data->hw_list; 715 struct device *m4udev = data->dev; 716 struct mtk_iommu_bank_data *bank; 717 unsigned int bankid; 718 int ret, region_id; 719 720 region_id = mtk_iommu_get_iova_region_id(dev, data->plat_data); 721 if (region_id < 0) 722 return region_id; 723 724 bankid = mtk_iommu_get_bank_id(dev, data->plat_data); 725 mutex_lock(&dom->mutex); 726 if (!dom->bank) { 727 /* Data is in the frstdata in sharing pgtable case. */ 728 frstdata = mtk_iommu_get_frst_data(hw_list); 729 730 mutex_lock(&frstdata->mutex); 731 ret = mtk_iommu_domain_finalise(dom, frstdata, region_id); 732 mutex_unlock(&frstdata->mutex); 733 if (ret) { 734 mutex_unlock(&dom->mutex); 735 return ret; 736 } 737 dom->bank = &data->bank[bankid]; 738 } 739 mutex_unlock(&dom->mutex); 740 741 mutex_lock(&data->mutex); 742 bank = &data->bank[bankid]; 743 if (!bank->m4u_dom) { /* Initialize the M4U HW for each a BANK */ 744 ret = pm_runtime_resume_and_get(m4udev); 745 if (ret < 0) { 746 dev_err(m4udev, "pm get fail(%d) in attach.\n", ret); 747 goto err_unlock; 748 } 749 750 ret = mtk_iommu_hw_init(data, bankid); 751 if (ret) { 752 pm_runtime_put(m4udev); 753 goto err_unlock; 754 } 755 bank->m4u_dom = dom; 756 writel(dom->cfg.arm_v7s_cfg.ttbr, bank->base + REG_MMU_PT_BASE_ADDR); 757 758 pm_runtime_put(m4udev); 759 } 760 mutex_unlock(&data->mutex); 761 762 if (region_id > 0) { 763 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(34)); 764 if (ret) { 765 dev_err(m4udev, "Failed to set dma_mask for %s(%d).\n", dev_name(dev), ret); 766 return ret; 767 } 768 } 769 770 return mtk_iommu_config(data, dev, true, region_id); 771 772 err_unlock: 773 mutex_unlock(&data->mutex); 774 return ret; 775 } 776 777 static int mtk_iommu_identity_attach(struct iommu_domain *identity_domain, 778 struct device *dev) 779 { 780 struct iommu_domain *domain = iommu_get_domain_for_dev(dev); 781 struct mtk_iommu_data *data = dev_iommu_priv_get(dev); 782 783 if (domain == identity_domain || !domain) 784 return 0; 785 786 mtk_iommu_config(data, dev, false, 0); 787 return 0; 788 } 789 790 static struct iommu_domain_ops mtk_iommu_identity_ops = { 791 .attach_dev = mtk_iommu_identity_attach, 792 }; 793 794 static struct iommu_domain mtk_iommu_identity_domain = { 795 .type = IOMMU_DOMAIN_IDENTITY, 796 .ops = &mtk_iommu_identity_ops, 797 }; 798 799 static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova, 800 phys_addr_t paddr, size_t pgsize, size_t pgcount, 801 int prot, gfp_t gfp, size_t *mapped) 802 { 803 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 804 805 /* The "4GB mode" M4U physically can not use the lower remap of Dram. */ 806 if (dom->bank->parent_data->enable_4GB) 807 paddr |= BIT_ULL(32); 808 809 /* Synchronize with the tlb_lock */ 810 return dom->iop->map_pages(dom->iop, iova, paddr, pgsize, pgcount, prot, gfp, mapped); 811 } 812 813 static size_t mtk_iommu_unmap(struct iommu_domain *domain, 814 unsigned long iova, size_t pgsize, size_t pgcount, 815 struct iommu_iotlb_gather *gather) 816 { 817 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 818 819 iommu_iotlb_gather_add_range(gather, iova, pgsize * pgcount); 820 return dom->iop->unmap_pages(dom->iop, iova, pgsize, pgcount, gather); 821 } 822 823 static void mtk_iommu_flush_iotlb_all(struct iommu_domain *domain) 824 { 825 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 826 827 if (dom->bank) 828 mtk_iommu_tlb_flush_all(dom->bank->parent_data); 829 } 830 831 static void mtk_iommu_iotlb_sync(struct iommu_domain *domain, 832 struct iommu_iotlb_gather *gather) 833 { 834 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 835 size_t length = gather->end - gather->start + 1; 836 837 mtk_iommu_tlb_flush_range_sync(gather->start, length, dom->bank); 838 } 839 840 static int mtk_iommu_sync_map(struct iommu_domain *domain, unsigned long iova, 841 size_t size) 842 { 843 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 844 845 mtk_iommu_tlb_flush_range_sync(iova, size, dom->bank); 846 return 0; 847 } 848 849 static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain, 850 dma_addr_t iova) 851 { 852 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 853 phys_addr_t pa; 854 855 pa = dom->iop->iova_to_phys(dom->iop, iova); 856 if (IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) && 857 dom->bank->parent_data->enable_4GB && 858 pa >= MTK_IOMMU_4GB_MODE_REMAP_BASE) 859 pa &= ~BIT_ULL(32); 860 861 return pa; 862 } 863 864 static struct iommu_device *mtk_iommu_probe_device(struct device *dev) 865 { 866 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 867 struct mtk_iommu_data *data = dev_iommu_priv_get(dev); 868 struct device_link *link; 869 struct device *larbdev; 870 unsigned int larbid, larbidx, i; 871 872 if (!MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) 873 return &data->iommu; 874 875 /* 876 * Link the consumer device with the smi-larb device(supplier). 877 * The device that connects with each a larb is a independent HW. 878 * All the ports in each a device should be in the same larbs. 879 */ 880 larbid = MTK_M4U_TO_LARB(fwspec->ids[0]); 881 if (larbid >= MTK_LARB_NR_MAX) 882 return ERR_PTR(-EINVAL); 883 884 for (i = 1; i < fwspec->num_ids; i++) { 885 larbidx = MTK_M4U_TO_LARB(fwspec->ids[i]); 886 if (larbid != larbidx) { 887 dev_err(dev, "Can only use one larb. Fail@larb%d-%d.\n", 888 larbid, larbidx); 889 return ERR_PTR(-EINVAL); 890 } 891 } 892 larbdev = data->larb_imu[larbid].dev; 893 if (!larbdev) 894 return ERR_PTR(-EINVAL); 895 896 link = device_link_add(dev, larbdev, 897 DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS); 898 if (!link) 899 dev_err(dev, "Unable to link %s\n", dev_name(larbdev)); 900 return &data->iommu; 901 } 902 903 static void mtk_iommu_release_device(struct device *dev) 904 { 905 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 906 struct mtk_iommu_data *data; 907 struct device *larbdev; 908 unsigned int larbid; 909 910 data = dev_iommu_priv_get(dev); 911 if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) { 912 larbid = MTK_M4U_TO_LARB(fwspec->ids[0]); 913 larbdev = data->larb_imu[larbid].dev; 914 device_link_remove(dev, larbdev); 915 } 916 } 917 918 static int mtk_iommu_get_group_id(struct device *dev, const struct mtk_iommu_plat_data *plat_data) 919 { 920 unsigned int bankid; 921 922 /* 923 * If the bank function is enabled, each bank is a iommu group/domain. 924 * Otherwise, each iova region is a iommu group/domain. 925 */ 926 bankid = mtk_iommu_get_bank_id(dev, plat_data); 927 if (bankid) 928 return bankid; 929 930 return mtk_iommu_get_iova_region_id(dev, plat_data); 931 } 932 933 static struct iommu_group *mtk_iommu_device_group(struct device *dev) 934 { 935 struct mtk_iommu_data *c_data = dev_iommu_priv_get(dev), *data; 936 struct list_head *hw_list = c_data->hw_list; 937 struct iommu_group *group; 938 int groupid; 939 940 data = mtk_iommu_get_frst_data(hw_list); 941 if (!data) 942 return ERR_PTR(-ENODEV); 943 944 groupid = mtk_iommu_get_group_id(dev, data->plat_data); 945 if (groupid < 0) 946 return ERR_PTR(groupid); 947 948 mutex_lock(&data->mutex); 949 group = data->m4u_group[groupid]; 950 if (!group) { 951 group = iommu_group_alloc(); 952 if (!IS_ERR(group)) 953 data->m4u_group[groupid] = group; 954 } else { 955 iommu_group_ref_get(group); 956 } 957 mutex_unlock(&data->mutex); 958 return group; 959 } 960 961 static int mtk_iommu_of_xlate(struct device *dev, 962 const struct of_phandle_args *args) 963 { 964 struct platform_device *m4updev; 965 966 if (args->args_count != 1) { 967 dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n", 968 args->args_count); 969 return -EINVAL; 970 } 971 972 if (!dev_iommu_priv_get(dev)) { 973 /* Get the m4u device */ 974 m4updev = of_find_device_by_node(args->np); 975 if (WARN_ON(!m4updev)) 976 return -EINVAL; 977 978 dev_iommu_priv_set(dev, platform_get_drvdata(m4updev)); 979 } 980 981 return iommu_fwspec_add_ids(dev, args->args, 1); 982 } 983 984 static void mtk_iommu_get_resv_regions(struct device *dev, 985 struct list_head *head) 986 { 987 struct mtk_iommu_data *data = dev_iommu_priv_get(dev); 988 unsigned int regionid = mtk_iommu_get_iova_region_id(dev, data->plat_data), i; 989 const struct mtk_iommu_iova_region *resv, *curdom; 990 struct iommu_resv_region *region; 991 int prot = IOMMU_WRITE | IOMMU_READ; 992 993 if ((int)regionid < 0) 994 return; 995 curdom = data->plat_data->iova_region + regionid; 996 for (i = 0; i < data->plat_data->iova_region_nr; i++) { 997 resv = data->plat_data->iova_region + i; 998 999 /* Only reserve when the region is inside the current domain */ 1000 if (resv->iova_base <= curdom->iova_base || 1001 resv->iova_base + resv->size >= curdom->iova_base + curdom->size) 1002 continue; 1003 1004 region = iommu_alloc_resv_region(resv->iova_base, resv->size, 1005 prot, IOMMU_RESV_RESERVED, 1006 GFP_KERNEL); 1007 if (!region) 1008 return; 1009 1010 list_add_tail(®ion->list, head); 1011 } 1012 } 1013 1014 static const struct iommu_ops mtk_iommu_ops = { 1015 .identity_domain = &mtk_iommu_identity_domain, 1016 .domain_alloc_paging = mtk_iommu_domain_alloc_paging, 1017 .probe_device = mtk_iommu_probe_device, 1018 .release_device = mtk_iommu_release_device, 1019 .device_group = mtk_iommu_device_group, 1020 .of_xlate = mtk_iommu_of_xlate, 1021 .get_resv_regions = mtk_iommu_get_resv_regions, 1022 .pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M, 1023 .owner = THIS_MODULE, 1024 .default_domain_ops = &(const struct iommu_domain_ops) { 1025 .attach_dev = mtk_iommu_attach_device, 1026 .map_pages = mtk_iommu_map, 1027 .unmap_pages = mtk_iommu_unmap, 1028 .flush_iotlb_all = mtk_iommu_flush_iotlb_all, 1029 .iotlb_sync = mtk_iommu_iotlb_sync, 1030 .iotlb_sync_map = mtk_iommu_sync_map, 1031 .iova_to_phys = mtk_iommu_iova_to_phys, 1032 .free = mtk_iommu_domain_free, 1033 } 1034 }; 1035 1036 static int mtk_iommu_hw_init(const struct mtk_iommu_data *data, unsigned int bankid) 1037 { 1038 const struct mtk_iommu_bank_data *bankx = &data->bank[bankid]; 1039 const struct mtk_iommu_bank_data *bank0 = &data->bank[0]; 1040 u32 regval; 1041 1042 /* 1043 * Global control settings are in bank0. May re-init these global registers 1044 * since no sure if there is bank0 consumers. 1045 */ 1046 if (MTK_IOMMU_HAS_FLAG(data->plat_data, TF_PORT_TO_ADDR_MT8173)) { 1047 regval = F_MMU_PREFETCH_RT_REPLACE_MOD | 1048 F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173; 1049 } else { 1050 regval = readl_relaxed(bank0->base + REG_MMU_CTRL_REG); 1051 regval |= F_MMU_TF_PROT_TO_PROGRAM_ADDR; 1052 } 1053 writel_relaxed(regval, bank0->base + REG_MMU_CTRL_REG); 1054 1055 if (data->enable_4GB && 1056 MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_VLD_PA_RNG)) { 1057 /* 1058 * If 4GB mode is enabled, the validate PA range is from 1059 * 0x1_0000_0000 to 0x1_ffff_ffff. here record bit[32:30]. 1060 */ 1061 regval = F_MMU_VLD_PA_RNG(7, 4); 1062 writel_relaxed(regval, bank0->base + REG_MMU_VLD_PA_RNG); 1063 } 1064 if (MTK_IOMMU_HAS_FLAG(data->plat_data, DCM_DISABLE)) 1065 writel_relaxed(F_MMU_DCM, bank0->base + REG_MMU_DCM_DIS); 1066 else 1067 writel_relaxed(0, bank0->base + REG_MMU_DCM_DIS); 1068 1069 if (MTK_IOMMU_HAS_FLAG(data->plat_data, WR_THROT_EN)) { 1070 /* write command throttling mode */ 1071 regval = readl_relaxed(bank0->base + REG_MMU_WR_LEN_CTRL); 1072 regval &= ~F_MMU_WR_THROT_DIS_MASK; 1073 writel_relaxed(regval, bank0->base + REG_MMU_WR_LEN_CTRL); 1074 } 1075 1076 if (MTK_IOMMU_HAS_FLAG(data->plat_data, RESET_AXI)) { 1077 /* The register is called STANDARD_AXI_MODE in this case */ 1078 regval = 0; 1079 } else { 1080 regval = readl_relaxed(bank0->base + REG_MMU_MISC_CTRL); 1081 if (!MTK_IOMMU_HAS_FLAG(data->plat_data, STD_AXI_MODE)) 1082 regval &= ~F_MMU_STANDARD_AXI_MODE_MASK; 1083 if (MTK_IOMMU_HAS_FLAG(data->plat_data, OUT_ORDER_WR_EN)) 1084 regval &= ~F_MMU_IN_ORDER_WR_EN_MASK; 1085 } 1086 writel_relaxed(regval, bank0->base + REG_MMU_MISC_CTRL); 1087 1088 /* Independent settings for each bank */ 1089 regval = F_L2_MULIT_HIT_EN | 1090 F_TABLE_WALK_FAULT_INT_EN | 1091 F_PREETCH_FIFO_OVERFLOW_INT_EN | 1092 F_MISS_FIFO_OVERFLOW_INT_EN | 1093 F_PREFETCH_FIFO_ERR_INT_EN | 1094 F_MISS_FIFO_ERR_INT_EN; 1095 writel_relaxed(regval, bankx->base + REG_MMU_INT_CONTROL0); 1096 1097 regval = F_INT_TRANSLATION_FAULT | 1098 F_INT_MAIN_MULTI_HIT_FAULT | 1099 F_INT_INVALID_PA_FAULT | 1100 F_INT_ENTRY_REPLACEMENT_FAULT | 1101 F_INT_TLB_MISS_FAULT | 1102 F_INT_MISS_TRANSACTION_FIFO_FAULT | 1103 F_INT_PRETETCH_TRANSATION_FIFO_FAULT; 1104 writel_relaxed(regval, bankx->base + REG_MMU_INT_MAIN_CONTROL); 1105 1106 if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_LEGACY_IVRP_PADDR)) 1107 regval = (data->protect_base >> 1) | (data->enable_4GB << 31); 1108 else 1109 regval = lower_32_bits(data->protect_base) | 1110 upper_32_bits(data->protect_base); 1111 writel_relaxed(regval, bankx->base + REG_MMU_IVRP_PADDR); 1112 1113 if (devm_request_irq(bankx->parent_dev, bankx->irq, mtk_iommu_isr, 0, 1114 dev_name(bankx->parent_dev), (void *)bankx)) { 1115 writel_relaxed(0, bankx->base + REG_MMU_PT_BASE_ADDR); 1116 dev_err(bankx->parent_dev, "Failed @ IRQ-%d Request\n", bankx->irq); 1117 return -ENODEV; 1118 } 1119 1120 return 0; 1121 } 1122 1123 static const struct component_master_ops mtk_iommu_com_ops = { 1124 .bind = mtk_iommu_bind, 1125 .unbind = mtk_iommu_unbind, 1126 }; 1127 1128 static int mtk_iommu_mm_dts_parse(struct device *dev, struct component_match **match, 1129 struct mtk_iommu_data *data) 1130 { 1131 struct device_node *larbnode, *frst_avail_smicomm_node = NULL; 1132 struct platform_device *plarbdev, *pcommdev; 1133 struct device_link *link; 1134 int i, larb_nr, ret; 1135 1136 larb_nr = of_count_phandle_with_args(dev->of_node, "mediatek,larbs", NULL); 1137 if (larb_nr < 0) 1138 return larb_nr; 1139 if (larb_nr == 0 || larb_nr > MTK_LARB_NR_MAX) 1140 return -EINVAL; 1141 1142 for (i = 0; i < larb_nr; i++) { 1143 struct device_node *smicomm_node, *smi_subcomm_node; 1144 u32 id; 1145 1146 larbnode = of_parse_phandle(dev->of_node, "mediatek,larbs", i); 1147 if (!larbnode) { 1148 ret = -EINVAL; 1149 goto err_larbdev_put; 1150 } 1151 1152 if (!of_device_is_available(larbnode)) { 1153 of_node_put(larbnode); 1154 continue; 1155 } 1156 1157 ret = of_property_read_u32(larbnode, "mediatek,larb-id", &id); 1158 if (ret)/* The id is consecutive if there is no this property */ 1159 id = i; 1160 if (id >= MTK_LARB_NR_MAX) { 1161 of_node_put(larbnode); 1162 ret = -EINVAL; 1163 goto err_larbdev_put; 1164 } 1165 1166 plarbdev = of_find_device_by_node(larbnode); 1167 of_node_put(larbnode); 1168 if (!plarbdev) { 1169 ret = -ENODEV; 1170 goto err_larbdev_put; 1171 } 1172 if (data->larb_imu[id].dev) { 1173 platform_device_put(plarbdev); 1174 ret = -EEXIST; 1175 goto err_larbdev_put; 1176 } 1177 data->larb_imu[id].dev = &plarbdev->dev; 1178 1179 if (!plarbdev->dev.driver) { 1180 ret = -EPROBE_DEFER; 1181 goto err_larbdev_put; 1182 } 1183 1184 /* Get smi-(sub)-common dev from the last larb. */ 1185 smi_subcomm_node = of_parse_phandle(larbnode, "mediatek,smi", 0); 1186 if (!smi_subcomm_node) { 1187 ret = -EINVAL; 1188 goto err_larbdev_put; 1189 } 1190 1191 /* 1192 * It may have two level smi-common. the node is smi-sub-common if it 1193 * has a new mediatek,smi property. otherwise it is smi-commmon. 1194 */ 1195 smicomm_node = of_parse_phandle(smi_subcomm_node, "mediatek,smi", 0); 1196 if (smicomm_node) 1197 of_node_put(smi_subcomm_node); 1198 else 1199 smicomm_node = smi_subcomm_node; 1200 1201 /* 1202 * All the larbs that connect to one IOMMU must connect with the same 1203 * smi-common. 1204 */ 1205 if (!frst_avail_smicomm_node) { 1206 frst_avail_smicomm_node = smicomm_node; 1207 } else if (frst_avail_smicomm_node != smicomm_node) { 1208 dev_err(dev, "mediatek,smi property is not right @larb%d.", id); 1209 of_node_put(smicomm_node); 1210 ret = -EINVAL; 1211 goto err_larbdev_put; 1212 } else { 1213 of_node_put(smicomm_node); 1214 } 1215 1216 component_match_add(dev, match, component_compare_dev, &plarbdev->dev); 1217 platform_device_put(plarbdev); 1218 } 1219 1220 if (!frst_avail_smicomm_node) 1221 return -EINVAL; 1222 1223 pcommdev = of_find_device_by_node(frst_avail_smicomm_node); 1224 of_node_put(frst_avail_smicomm_node); 1225 if (!pcommdev) 1226 return -ENODEV; 1227 data->smicomm_dev = &pcommdev->dev; 1228 1229 link = device_link_add(data->smicomm_dev, dev, 1230 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME); 1231 platform_device_put(pcommdev); 1232 if (!link) { 1233 dev_err(dev, "Unable to link %s.\n", dev_name(data->smicomm_dev)); 1234 return -EINVAL; 1235 } 1236 return 0; 1237 1238 err_larbdev_put: 1239 for (i = MTK_LARB_NR_MAX - 1; i >= 0; i--) { 1240 if (!data->larb_imu[i].dev) 1241 continue; 1242 put_device(data->larb_imu[i].dev); 1243 } 1244 return ret; 1245 } 1246 1247 static int mtk_iommu_probe(struct platform_device *pdev) 1248 { 1249 struct mtk_iommu_data *data; 1250 struct device *dev = &pdev->dev; 1251 struct resource *res; 1252 resource_size_t ioaddr; 1253 struct component_match *match = NULL; 1254 struct regmap *infracfg; 1255 void *protect; 1256 int ret, banks_num, i = 0; 1257 u32 val; 1258 char *p; 1259 struct mtk_iommu_bank_data *bank; 1260 void __iomem *base; 1261 1262 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 1263 if (!data) 1264 return -ENOMEM; 1265 data->dev = dev; 1266 data->plat_data = of_device_get_match_data(dev); 1267 1268 /* Protect memory. HW will access here while translation fault.*/ 1269 protect = devm_kcalloc(dev, 2, MTK_PROTECT_PA_ALIGN, GFP_KERNEL); 1270 if (!protect) 1271 return -ENOMEM; 1272 data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN); 1273 1274 if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE)) { 1275 infracfg = syscon_regmap_lookup_by_phandle(dev->of_node, "mediatek,infracfg"); 1276 if (IS_ERR(infracfg)) { 1277 /* 1278 * Legacy devicetrees will not specify a phandle to 1279 * mediatek,infracfg: in that case, we use the older 1280 * way to retrieve a syscon to infra. 1281 * 1282 * This is for retrocompatibility purposes only, hence 1283 * no more compatibles shall be added to this. 1284 */ 1285 switch (data->plat_data->m4u_plat) { 1286 case M4U_MT2712: 1287 p = "mediatek,mt2712-infracfg"; 1288 break; 1289 case M4U_MT8173: 1290 p = "mediatek,mt8173-infracfg"; 1291 break; 1292 default: 1293 p = NULL; 1294 } 1295 1296 infracfg = syscon_regmap_lookup_by_compatible(p); 1297 if (IS_ERR(infracfg)) 1298 return PTR_ERR(infracfg); 1299 } 1300 1301 ret = regmap_read(infracfg, REG_INFRA_MISC, &val); 1302 if (ret) 1303 return ret; 1304 data->enable_4GB = !!(val & F_DDR_4GB_SUPPORT_EN); 1305 } 1306 1307 banks_num = data->plat_data->banks_num; 1308 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1309 if (!res) 1310 return -EINVAL; 1311 if (resource_size(res) < banks_num * MTK_IOMMU_BANK_SZ) { 1312 dev_err(dev, "banknr %d. res %pR is not enough.\n", banks_num, res); 1313 return -EINVAL; 1314 } 1315 base = devm_ioremap_resource(dev, res); 1316 if (IS_ERR(base)) 1317 return PTR_ERR(base); 1318 ioaddr = res->start; 1319 1320 data->bank = devm_kmalloc(dev, banks_num * sizeof(*data->bank), GFP_KERNEL); 1321 if (!data->bank) 1322 return -ENOMEM; 1323 1324 do { 1325 if (!data->plat_data->banks_enable[i]) 1326 continue; 1327 bank = &data->bank[i]; 1328 bank->id = i; 1329 bank->base = base + i * MTK_IOMMU_BANK_SZ; 1330 bank->m4u_dom = NULL; 1331 1332 bank->irq = platform_get_irq(pdev, i); 1333 if (bank->irq < 0) 1334 return bank->irq; 1335 bank->parent_dev = dev; 1336 bank->parent_data = data; 1337 spin_lock_init(&bank->tlb_lock); 1338 } while (++i < banks_num); 1339 1340 if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_BCLK)) { 1341 data->bclk = devm_clk_get(dev, "bclk"); 1342 if (IS_ERR(data->bclk)) 1343 return PTR_ERR(data->bclk); 1344 } 1345 1346 if (MTK_IOMMU_HAS_FLAG(data->plat_data, PGTABLE_PA_35_EN)) { 1347 ret = dma_set_mask(dev, DMA_BIT_MASK(35)); 1348 if (ret) { 1349 dev_err(dev, "Failed to set dma_mask 35.\n"); 1350 return ret; 1351 } 1352 } 1353 1354 pm_runtime_enable(dev); 1355 1356 if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) { 1357 ret = mtk_iommu_mm_dts_parse(dev, &match, data); 1358 if (ret) { 1359 dev_err_probe(dev, ret, "mm dts parse fail\n"); 1360 goto out_runtime_disable; 1361 } 1362 } else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA) && 1363 !MTK_IOMMU_HAS_FLAG(data->plat_data, CFG_IFA_MASTER_IN_ATF)) { 1364 p = data->plat_data->pericfg_comp_str; 1365 data->pericfg = syscon_regmap_lookup_by_compatible(p); 1366 if (IS_ERR(data->pericfg)) { 1367 ret = PTR_ERR(data->pericfg); 1368 goto out_runtime_disable; 1369 } 1370 } 1371 1372 platform_set_drvdata(pdev, data); 1373 mutex_init(&data->mutex); 1374 1375 if (MTK_IOMMU_HAS_FLAG(data->plat_data, SHARE_PGTABLE)) { 1376 list_add_tail(&data->list, data->plat_data->hw_list); 1377 data->hw_list = data->plat_data->hw_list; 1378 } else { 1379 INIT_LIST_HEAD(&data->hw_list_head); 1380 list_add_tail(&data->list, &data->hw_list_head); 1381 data->hw_list = &data->hw_list_head; 1382 } 1383 1384 ret = iommu_device_sysfs_add(&data->iommu, dev, NULL, 1385 "mtk-iommu.%pa", &ioaddr); 1386 if (ret) 1387 goto out_list_del; 1388 1389 ret = iommu_device_register(&data->iommu, &mtk_iommu_ops, dev); 1390 if (ret) 1391 goto out_sysfs_remove; 1392 1393 if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) { 1394 ret = component_master_add_with_match(dev, &mtk_iommu_com_ops, match); 1395 if (ret) 1396 goto out_device_unregister; 1397 } 1398 return ret; 1399 1400 out_device_unregister: 1401 iommu_device_unregister(&data->iommu); 1402 out_sysfs_remove: 1403 iommu_device_sysfs_remove(&data->iommu); 1404 out_list_del: 1405 list_del(&data->list); 1406 if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) 1407 device_link_remove(data->smicomm_dev, dev); 1408 out_runtime_disable: 1409 pm_runtime_disable(dev); 1410 return ret; 1411 } 1412 1413 static void mtk_iommu_remove(struct platform_device *pdev) 1414 { 1415 struct mtk_iommu_data *data = platform_get_drvdata(pdev); 1416 struct mtk_iommu_bank_data *bank; 1417 int i; 1418 1419 iommu_device_sysfs_remove(&data->iommu); 1420 iommu_device_unregister(&data->iommu); 1421 1422 list_del(&data->list); 1423 1424 if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) { 1425 device_link_remove(data->smicomm_dev, &pdev->dev); 1426 component_master_del(&pdev->dev, &mtk_iommu_com_ops); 1427 } 1428 pm_runtime_disable(&pdev->dev); 1429 for (i = 0; i < data->plat_data->banks_num; i++) { 1430 bank = &data->bank[i]; 1431 if (!bank->m4u_dom) 1432 continue; 1433 devm_free_irq(&pdev->dev, bank->irq, bank); 1434 } 1435 } 1436 1437 static int __maybe_unused mtk_iommu_runtime_suspend(struct device *dev) 1438 { 1439 struct mtk_iommu_data *data = dev_get_drvdata(dev); 1440 struct mtk_iommu_suspend_reg *reg = &data->reg; 1441 void __iomem *base; 1442 int i = 0; 1443 1444 base = data->bank[i].base; 1445 reg->wr_len_ctrl = readl_relaxed(base + REG_MMU_WR_LEN_CTRL); 1446 reg->misc_ctrl = readl_relaxed(base + REG_MMU_MISC_CTRL); 1447 reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS); 1448 reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG); 1449 reg->vld_pa_rng = readl_relaxed(base + REG_MMU_VLD_PA_RNG); 1450 do { 1451 if (!data->plat_data->banks_enable[i]) 1452 continue; 1453 base = data->bank[i].base; 1454 reg->int_control[i] = readl_relaxed(base + REG_MMU_INT_CONTROL0); 1455 reg->int_main_control[i] = readl_relaxed(base + REG_MMU_INT_MAIN_CONTROL); 1456 reg->ivrp_paddr[i] = readl_relaxed(base + REG_MMU_IVRP_PADDR); 1457 } while (++i < data->plat_data->banks_num); 1458 clk_disable_unprepare(data->bclk); 1459 return 0; 1460 } 1461 1462 static int __maybe_unused mtk_iommu_runtime_resume(struct device *dev) 1463 { 1464 struct mtk_iommu_data *data = dev_get_drvdata(dev); 1465 struct mtk_iommu_suspend_reg *reg = &data->reg; 1466 struct mtk_iommu_domain *m4u_dom; 1467 void __iomem *base; 1468 int ret, i = 0; 1469 1470 ret = clk_prepare_enable(data->bclk); 1471 if (ret) { 1472 dev_err(data->dev, "Failed to enable clk(%d) in resume\n", ret); 1473 return ret; 1474 } 1475 1476 /* 1477 * Uppon first resume, only enable the clk and return, since the values of the 1478 * registers are not yet set. 1479 */ 1480 if (!reg->wr_len_ctrl) 1481 return 0; 1482 1483 base = data->bank[i].base; 1484 writel_relaxed(reg->wr_len_ctrl, base + REG_MMU_WR_LEN_CTRL); 1485 writel_relaxed(reg->misc_ctrl, base + REG_MMU_MISC_CTRL); 1486 writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS); 1487 writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG); 1488 writel_relaxed(reg->vld_pa_rng, base + REG_MMU_VLD_PA_RNG); 1489 do { 1490 m4u_dom = data->bank[i].m4u_dom; 1491 if (!data->plat_data->banks_enable[i] || !m4u_dom) 1492 continue; 1493 base = data->bank[i].base; 1494 writel_relaxed(reg->int_control[i], base + REG_MMU_INT_CONTROL0); 1495 writel_relaxed(reg->int_main_control[i], base + REG_MMU_INT_MAIN_CONTROL); 1496 writel_relaxed(reg->ivrp_paddr[i], base + REG_MMU_IVRP_PADDR); 1497 writel(m4u_dom->cfg.arm_v7s_cfg.ttbr, base + REG_MMU_PT_BASE_ADDR); 1498 } while (++i < data->plat_data->banks_num); 1499 1500 /* 1501 * Users may allocate dma buffer before they call pm_runtime_get, 1502 * in which case it will lack the necessary tlb flush. 1503 * Thus, make sure to update the tlb after each PM resume. 1504 */ 1505 mtk_iommu_tlb_flush_all(data); 1506 return 0; 1507 } 1508 1509 static const struct dev_pm_ops mtk_iommu_pm_ops = { 1510 SET_RUNTIME_PM_OPS(mtk_iommu_runtime_suspend, mtk_iommu_runtime_resume, NULL) 1511 SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1512 pm_runtime_force_resume) 1513 }; 1514 1515 static const struct mtk_iommu_plat_data mt2712_data = { 1516 .m4u_plat = M4U_MT2712, 1517 .flags = HAS_4GB_MODE | HAS_BCLK | HAS_VLD_PA_RNG | SHARE_PGTABLE | 1518 MTK_IOMMU_TYPE_MM, 1519 .hw_list = &m4ulist, 1520 .inv_sel_reg = REG_MMU_INV_SEL_GEN1, 1521 .iova_region = single_domain, 1522 .banks_num = 1, 1523 .banks_enable = {true}, 1524 .iova_region_nr = ARRAY_SIZE(single_domain), 1525 .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}, {6}, {7}}, 1526 }; 1527 1528 static const struct mtk_iommu_plat_data mt6779_data = { 1529 .m4u_plat = M4U_MT6779, 1530 .flags = HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN | WR_THROT_EN | 1531 MTK_IOMMU_TYPE_MM | PGTABLE_PA_35_EN, 1532 .inv_sel_reg = REG_MMU_INV_SEL_GEN2, 1533 .banks_num = 1, 1534 .banks_enable = {true}, 1535 .iova_region = single_domain, 1536 .iova_region_nr = ARRAY_SIZE(single_domain), 1537 .larbid_remap = {{0}, {1}, {2}, {3}, {5}, {7, 8}, {10}, {9}}, 1538 }; 1539 1540 static const struct mtk_iommu_plat_data mt6795_data = { 1541 .m4u_plat = M4U_MT6795, 1542 .flags = HAS_4GB_MODE | HAS_BCLK | RESET_AXI | 1543 HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM | 1544 TF_PORT_TO_ADDR_MT8173, 1545 .inv_sel_reg = REG_MMU_INV_SEL_GEN1, 1546 .banks_num = 1, 1547 .banks_enable = {true}, 1548 .iova_region = single_domain, 1549 .iova_region_nr = ARRAY_SIZE(single_domain), 1550 .larbid_remap = {{0}, {1}, {2}, {3}, {4}}, /* Linear mapping. */ 1551 }; 1552 1553 static const struct mtk_iommu_plat_data mt8167_data = { 1554 .m4u_plat = M4U_MT8167, 1555 .flags = RESET_AXI | HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM, 1556 .inv_sel_reg = REG_MMU_INV_SEL_GEN1, 1557 .banks_num = 1, 1558 .banks_enable = {true}, 1559 .iova_region = single_domain, 1560 .iova_region_nr = ARRAY_SIZE(single_domain), 1561 .larbid_remap = {{0}, {1}, {2}}, /* Linear mapping. */ 1562 }; 1563 1564 static const struct mtk_iommu_plat_data mt8173_data = { 1565 .m4u_plat = M4U_MT8173, 1566 .flags = HAS_4GB_MODE | HAS_BCLK | RESET_AXI | 1567 HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM | 1568 TF_PORT_TO_ADDR_MT8173, 1569 .inv_sel_reg = REG_MMU_INV_SEL_GEN1, 1570 .banks_num = 1, 1571 .banks_enable = {true}, 1572 .iova_region = single_domain, 1573 .iova_region_nr = ARRAY_SIZE(single_domain), 1574 .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */ 1575 }; 1576 1577 static const struct mtk_iommu_plat_data mt8183_data = { 1578 .m4u_plat = M4U_MT8183, 1579 .flags = RESET_AXI | MTK_IOMMU_TYPE_MM, 1580 .inv_sel_reg = REG_MMU_INV_SEL_GEN1, 1581 .banks_num = 1, 1582 .banks_enable = {true}, 1583 .iova_region = single_domain, 1584 .iova_region_nr = ARRAY_SIZE(single_domain), 1585 .larbid_remap = {{0}, {4}, {5}, {6}, {7}, {2}, {3}, {1}}, 1586 }; 1587 1588 static const unsigned int mt8186_larb_region_msk[MT8192_MULTI_REGION_NR_MAX][MTK_LARB_NR_MAX] = { 1589 [0] = {~0, ~0, ~0}, /* Region0: all ports for larb0/1/2 */ 1590 [1] = {0, 0, 0, 0, ~0, 0, 0, ~0}, /* Region1: larb4/7 */ 1591 [2] = {0, 0, 0, 0, 0, 0, 0, 0, /* Region2: larb8/9/11/13/16/17/19/20 */ 1592 ~0, ~0, 0, ~0, 0, ~(u32)(BIT(9) | BIT(10)), 0, 0, 1593 /* larb13: the other ports except port9/10 */ 1594 ~0, ~0, 0, ~0, ~0}, 1595 [3] = {0}, 1596 [4] = {[13] = BIT(9) | BIT(10)}, /* larb13 port9/10 */ 1597 [5] = {[14] = ~0}, /* larb14 */ 1598 }; 1599 1600 static const struct mtk_iommu_plat_data mt8186_data_mm = { 1601 .m4u_plat = M4U_MT8186, 1602 .flags = HAS_BCLK | HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN | 1603 WR_THROT_EN | IOVA_34_EN | MTK_IOMMU_TYPE_MM | PGTABLE_PA_35_EN, 1604 .larbid_remap = {{0}, {1, MTK_INVALID_LARBID, 8}, {4}, {7}, {2}, {9, 11, 19, 20}, 1605 {MTK_INVALID_LARBID, 14, 16}, 1606 {MTK_INVALID_LARBID, 13, MTK_INVALID_LARBID, 17}}, 1607 .inv_sel_reg = REG_MMU_INV_SEL_GEN2, 1608 .banks_num = 1, 1609 .banks_enable = {true}, 1610 .iova_region = mt8192_multi_dom, 1611 .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom), 1612 .iova_region_larb_msk = mt8186_larb_region_msk, 1613 }; 1614 1615 static const struct mtk_iommu_plat_data mt8188_data_infra = { 1616 .m4u_plat = M4U_MT8188, 1617 .flags = WR_THROT_EN | DCM_DISABLE | STD_AXI_MODE | PM_CLK_AO | 1618 MTK_IOMMU_TYPE_INFRA | IFA_IOMMU_PCIE_SUPPORT | 1619 PGTABLE_PA_35_EN | CFG_IFA_MASTER_IN_ATF, 1620 .inv_sel_reg = REG_MMU_INV_SEL_GEN2, 1621 .banks_num = 1, 1622 .banks_enable = {true}, 1623 .iova_region = single_domain, 1624 .iova_region_nr = ARRAY_SIZE(single_domain), 1625 }; 1626 1627 static const u32 mt8188_larb_region_msk[MT8192_MULTI_REGION_NR_MAX][MTK_LARB_NR_MAX] = { 1628 [0] = {~0, ~0, ~0, ~0}, /* Region0: all ports for larb0/1/2/3 */ 1629 [1] = {0, 0, 0, 0, 0, 0, 0, 0, 1630 0, 0, 0, 0, 0, 0, 0, 0, 1631 0, 0, 0, 0, 0, ~0, ~0, ~0}, /* Region1: larb19(21)/21(22)/23 */ 1632 [2] = {0, 0, 0, 0, ~0, ~0, ~0, ~0, /* Region2: the other larbs. */ 1633 ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0, 1634 ~0, ~0, ~0, ~0, ~0, 0, 0, 0, 1635 0, ~0}, 1636 [3] = {0}, 1637 [4] = {[24] = BIT(0) | BIT(1)}, /* Only larb27(24) port0/1 */ 1638 [5] = {[24] = BIT(2) | BIT(3)}, /* Only larb27(24) port2/3 */ 1639 }; 1640 1641 static const struct mtk_iommu_plat_data mt8188_data_vdo = { 1642 .m4u_plat = M4U_MT8188, 1643 .flags = HAS_BCLK | HAS_SUB_COMM_3BITS | OUT_ORDER_WR_EN | 1644 WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE | 1645 PGTABLE_PA_35_EN | MTK_IOMMU_TYPE_MM, 1646 .hw_list = &m4ulist, 1647 .inv_sel_reg = REG_MMU_INV_SEL_GEN2, 1648 .banks_num = 1, 1649 .banks_enable = {true}, 1650 .iova_region = mt8192_multi_dom, 1651 .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom), 1652 .iova_region_larb_msk = mt8188_larb_region_msk, 1653 .larbid_remap = {{2}, {0}, {21}, {0}, {19}, {9, 10, 1654 11 /* 11a */, 25 /* 11c */}, 1655 {13, 0, 29 /* 16b */, 30 /* 17b */, 0}, {5}}, 1656 }; 1657 1658 static const struct mtk_iommu_plat_data mt8188_data_vpp = { 1659 .m4u_plat = M4U_MT8188, 1660 .flags = HAS_BCLK | HAS_SUB_COMM_3BITS | OUT_ORDER_WR_EN | 1661 WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE | 1662 PGTABLE_PA_35_EN | MTK_IOMMU_TYPE_MM, 1663 .hw_list = &m4ulist, 1664 .inv_sel_reg = REG_MMU_INV_SEL_GEN2, 1665 .banks_num = 1, 1666 .banks_enable = {true}, 1667 .iova_region = mt8192_multi_dom, 1668 .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom), 1669 .iova_region_larb_msk = mt8188_larb_region_msk, 1670 .larbid_remap = {{1}, {3}, {23}, {7}, {MTK_INVALID_LARBID}, 1671 {12, 15, 24 /* 11b */}, {14, MTK_INVALID_LARBID, 1672 16 /* 16a */, 17 /* 17a */, MTK_INVALID_LARBID, 1673 27, 28 /* ccu0 */, MTK_INVALID_LARBID}, {4, 6}}, 1674 }; 1675 1676 static const unsigned int mt8192_larb_region_msk[MT8192_MULTI_REGION_NR_MAX][MTK_LARB_NR_MAX] = { 1677 [0] = {~0, ~0}, /* Region0: larb0/1 */ 1678 [1] = {0, 0, 0, 0, ~0, ~0, 0, ~0}, /* Region1: larb4/5/7 */ 1679 [2] = {0, 0, ~0, 0, 0, 0, 0, 0, /* Region2: larb2/9/11/13/14/16/17/18/19/20 */ 1680 0, ~0, 0, ~0, 0, ~(u32)(BIT(9) | BIT(10)), ~(u32)(BIT(4) | BIT(5)), 0, 1681 ~0, ~0, ~0, ~0, ~0}, 1682 [3] = {0}, 1683 [4] = {[13] = BIT(9) | BIT(10)}, /* larb13 port9/10 */ 1684 [5] = {[14] = BIT(4) | BIT(5)}, /* larb14 port4/5 */ 1685 }; 1686 1687 static const struct mtk_iommu_plat_data mt8192_data = { 1688 .m4u_plat = M4U_MT8192, 1689 .flags = HAS_BCLK | HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN | 1690 WR_THROT_EN | IOVA_34_EN | MTK_IOMMU_TYPE_MM, 1691 .inv_sel_reg = REG_MMU_INV_SEL_GEN2, 1692 .banks_num = 1, 1693 .banks_enable = {true}, 1694 .iova_region = mt8192_multi_dom, 1695 .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom), 1696 .iova_region_larb_msk = mt8192_larb_region_msk, 1697 .larbid_remap = {{0}, {1}, {4, 5}, {7}, {2}, {9, 11, 19, 20}, 1698 {0, 14, 16}, {0, 13, 18, 17}}, 1699 }; 1700 1701 static const struct mtk_iommu_plat_data mt8195_data_infra = { 1702 .m4u_plat = M4U_MT8195, 1703 .flags = WR_THROT_EN | DCM_DISABLE | STD_AXI_MODE | PM_CLK_AO | 1704 MTK_IOMMU_TYPE_INFRA | IFA_IOMMU_PCIE_SUPPORT, 1705 .pericfg_comp_str = "mediatek,mt8195-pericfg_ao", 1706 .inv_sel_reg = REG_MMU_INV_SEL_GEN2, 1707 .banks_num = 5, 1708 .banks_enable = {true, false, false, false, true}, 1709 .banks_portmsk = {[0] = GENMASK(19, 16), /* PCIe */ 1710 [4] = GENMASK(31, 20), /* USB */ 1711 }, 1712 .iova_region = single_domain, 1713 .iova_region_nr = ARRAY_SIZE(single_domain), 1714 }; 1715 1716 static const unsigned int mt8195_larb_region_msk[MT8192_MULTI_REGION_NR_MAX][MTK_LARB_NR_MAX] = { 1717 [0] = {~0, ~0, ~0, ~0}, /* Region0: all ports for larb0/1/2/3 */ 1718 [1] = {0, 0, 0, 0, 0, 0, 0, 0, 1719 0, 0, 0, 0, 0, 0, 0, 0, 1720 0, 0, 0, ~0, ~0, ~0, ~0, ~0, /* Region1: larb19/20/21/22/23/24 */ 1721 ~0}, 1722 [2] = {0, 0, 0, 0, ~0, ~0, ~0, ~0, /* Region2: the other larbs. */ 1723 ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0, 1724 ~0, ~0, 0, 0, 0, 0, 0, 0, 1725 0, ~0, ~0, ~0, ~0}, 1726 [3] = {0}, 1727 [4] = {[18] = BIT(0) | BIT(1)}, /* Only larb18 port0/1 */ 1728 [5] = {[18] = BIT(2) | BIT(3)}, /* Only larb18 port2/3 */ 1729 }; 1730 1731 static const struct mtk_iommu_plat_data mt8195_data_vdo = { 1732 .m4u_plat = M4U_MT8195, 1733 .flags = HAS_BCLK | HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN | 1734 WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE | MTK_IOMMU_TYPE_MM, 1735 .hw_list = &m4ulist, 1736 .inv_sel_reg = REG_MMU_INV_SEL_GEN2, 1737 .banks_num = 1, 1738 .banks_enable = {true}, 1739 .iova_region = mt8192_multi_dom, 1740 .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom), 1741 .iova_region_larb_msk = mt8195_larb_region_msk, 1742 .larbid_remap = {{2, 0}, {21}, {24}, {7}, {19}, {9, 10, 11}, 1743 {13, 17, 15/* 17b */, 25}, {5}}, 1744 }; 1745 1746 static const struct mtk_iommu_plat_data mt8195_data_vpp = { 1747 .m4u_plat = M4U_MT8195, 1748 .flags = HAS_BCLK | HAS_SUB_COMM_3BITS | OUT_ORDER_WR_EN | 1749 WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE | MTK_IOMMU_TYPE_MM, 1750 .hw_list = &m4ulist, 1751 .inv_sel_reg = REG_MMU_INV_SEL_GEN2, 1752 .banks_num = 1, 1753 .banks_enable = {true}, 1754 .iova_region = mt8192_multi_dom, 1755 .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom), 1756 .iova_region_larb_msk = mt8195_larb_region_msk, 1757 .larbid_remap = {{1}, {3}, 1758 {22, MTK_INVALID_LARBID, MTK_INVALID_LARBID, MTK_INVALID_LARBID, 23}, 1759 {8}, {20}, {12}, 1760 /* 16: 16a; 29: 16b; 30: CCUtop0; 31: CCUtop1 */ 1761 {14, 16, 29, 26, 30, 31, 18}, 1762 {4, MTK_INVALID_LARBID, MTK_INVALID_LARBID, MTK_INVALID_LARBID, 6}}, 1763 }; 1764 1765 static const struct mtk_iommu_plat_data mt8365_data = { 1766 .m4u_plat = M4U_MT8365, 1767 .flags = RESET_AXI | INT_ID_PORT_WIDTH_6, 1768 .inv_sel_reg = REG_MMU_INV_SEL_GEN1, 1769 .banks_num = 1, 1770 .banks_enable = {true}, 1771 .iova_region = single_domain, 1772 .iova_region_nr = ARRAY_SIZE(single_domain), 1773 .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */ 1774 }; 1775 1776 static const struct of_device_id mtk_iommu_of_ids[] = { 1777 { .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data}, 1778 { .compatible = "mediatek,mt6779-m4u", .data = &mt6779_data}, 1779 { .compatible = "mediatek,mt6795-m4u", .data = &mt6795_data}, 1780 { .compatible = "mediatek,mt8167-m4u", .data = &mt8167_data}, 1781 { .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data}, 1782 { .compatible = "mediatek,mt8183-m4u", .data = &mt8183_data}, 1783 { .compatible = "mediatek,mt8186-iommu-mm", .data = &mt8186_data_mm}, /* mm: m4u */ 1784 { .compatible = "mediatek,mt8188-iommu-infra", .data = &mt8188_data_infra}, 1785 { .compatible = "mediatek,mt8188-iommu-vdo", .data = &mt8188_data_vdo}, 1786 { .compatible = "mediatek,mt8188-iommu-vpp", .data = &mt8188_data_vpp}, 1787 { .compatible = "mediatek,mt8192-m4u", .data = &mt8192_data}, 1788 { .compatible = "mediatek,mt8195-iommu-infra", .data = &mt8195_data_infra}, 1789 { .compatible = "mediatek,mt8195-iommu-vdo", .data = &mt8195_data_vdo}, 1790 { .compatible = "mediatek,mt8195-iommu-vpp", .data = &mt8195_data_vpp}, 1791 { .compatible = "mediatek,mt8365-m4u", .data = &mt8365_data}, 1792 {} 1793 }; 1794 MODULE_DEVICE_TABLE(of, mtk_iommu_of_ids); 1795 1796 static struct platform_driver mtk_iommu_driver = { 1797 .probe = mtk_iommu_probe, 1798 .remove = mtk_iommu_remove, 1799 .driver = { 1800 .name = "mtk-iommu", 1801 .of_match_table = mtk_iommu_of_ids, 1802 .pm = &mtk_iommu_pm_ops, 1803 } 1804 }; 1805 module_platform_driver(mtk_iommu_driver); 1806 1807 MODULE_DESCRIPTION("IOMMU API for MediaTek M4U implementations"); 1808 MODULE_LICENSE("GPL v2"); 1809