1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015-2016 MediaTek Inc. 4 * Author: Yong Wu <yong.wu@mediatek.com> 5 */ 6 #include <linux/bitfield.h> 7 #include <linux/bug.h> 8 #include <linux/clk.h> 9 #include <linux/component.h> 10 #include <linux/device.h> 11 #include <linux/dma-direct.h> 12 #include <linux/err.h> 13 #include <linux/interrupt.h> 14 #include <linux/io.h> 15 #include <linux/iommu.h> 16 #include <linux/iopoll.h> 17 #include <linux/io-pgtable.h> 18 #include <linux/list.h> 19 #include <linux/mfd/syscon.h> 20 #include <linux/module.h> 21 #include <linux/of_address.h> 22 #include <linux/of_irq.h> 23 #include <linux/of_platform.h> 24 #include <linux/pci.h> 25 #include <linux/platform_device.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/regmap.h> 28 #include <linux/slab.h> 29 #include <linux/spinlock.h> 30 #include <linux/soc/mediatek/infracfg.h> 31 #include <asm/barrier.h> 32 #include <soc/mediatek/smi.h> 33 34 #include <dt-bindings/memory/mtk-memory-port.h> 35 36 #define REG_MMU_PT_BASE_ADDR 0x000 37 #define MMU_PT_ADDR_MASK GENMASK(31, 7) 38 39 #define REG_MMU_INVALIDATE 0x020 40 #define F_ALL_INVLD 0x2 41 #define F_MMU_INV_RANGE 0x1 42 43 #define REG_MMU_INVLD_START_A 0x024 44 #define REG_MMU_INVLD_END_A 0x028 45 46 #define REG_MMU_INV_SEL_GEN2 0x02c 47 #define REG_MMU_INV_SEL_GEN1 0x038 48 #define F_INVLD_EN0 BIT(0) 49 #define F_INVLD_EN1 BIT(1) 50 51 #define REG_MMU_MISC_CTRL 0x048 52 #define F_MMU_IN_ORDER_WR_EN_MASK (BIT(1) | BIT(17)) 53 #define F_MMU_STANDARD_AXI_MODE_MASK (BIT(3) | BIT(19)) 54 55 #define REG_MMU_DCM_DIS 0x050 56 #define F_MMU_DCM BIT(8) 57 58 #define REG_MMU_WR_LEN_CTRL 0x054 59 #define F_MMU_WR_THROT_DIS_MASK (BIT(5) | BIT(21)) 60 61 #define REG_MMU_CTRL_REG 0x110 62 #define F_MMU_TF_PROT_TO_PROGRAM_ADDR (2 << 4) 63 #define F_MMU_PREFETCH_RT_REPLACE_MOD BIT(4) 64 #define F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173 (2 << 5) 65 66 #define REG_MMU_IVRP_PADDR 0x114 67 68 #define REG_MMU_VLD_PA_RNG 0x118 69 #define F_MMU_VLD_PA_RNG(EA, SA) (((EA) << 8) | (SA)) 70 71 #define REG_MMU_INT_CONTROL0 0x120 72 #define F_L2_MULIT_HIT_EN BIT(0) 73 #define F_TABLE_WALK_FAULT_INT_EN BIT(1) 74 #define F_PREETCH_FIFO_OVERFLOW_INT_EN BIT(2) 75 #define F_MISS_FIFO_OVERFLOW_INT_EN BIT(3) 76 #define F_PREFETCH_FIFO_ERR_INT_EN BIT(5) 77 #define F_MISS_FIFO_ERR_INT_EN BIT(6) 78 #define F_INT_CLR_BIT BIT(12) 79 80 #define REG_MMU_INT_MAIN_CONTROL 0x124 81 /* mmu0 | mmu1 */ 82 #define F_INT_TRANSLATION_FAULT (BIT(0) | BIT(7)) 83 #define F_INT_MAIN_MULTI_HIT_FAULT (BIT(1) | BIT(8)) 84 #define F_INT_INVALID_PA_FAULT (BIT(2) | BIT(9)) 85 #define F_INT_ENTRY_REPLACEMENT_FAULT (BIT(3) | BIT(10)) 86 #define F_INT_TLB_MISS_FAULT (BIT(4) | BIT(11)) 87 #define F_INT_MISS_TRANSACTION_FIFO_FAULT (BIT(5) | BIT(12)) 88 #define F_INT_PRETETCH_TRANSATION_FIFO_FAULT (BIT(6) | BIT(13)) 89 90 #define REG_MMU_CPE_DONE 0x12C 91 92 #define REG_MMU_FAULT_ST1 0x134 93 #define F_REG_MMU0_FAULT_MASK GENMASK(6, 0) 94 #define F_REG_MMU1_FAULT_MASK GENMASK(13, 7) 95 96 #define REG_MMU0_FAULT_VA 0x13c 97 #define F_MMU_INVAL_VA_31_12_MASK GENMASK(31, 12) 98 #define F_MMU_INVAL_VA_34_32_MASK GENMASK(11, 9) 99 #define F_MMU_INVAL_PA_34_32_MASK GENMASK(8, 6) 100 #define F_MMU_FAULT_VA_WRITE_BIT BIT(1) 101 #define F_MMU_FAULT_VA_LAYER_BIT BIT(0) 102 103 #define REG_MMU0_INVLD_PA 0x140 104 #define REG_MMU1_FAULT_VA 0x144 105 #define REG_MMU1_INVLD_PA 0x148 106 #define REG_MMU0_INT_ID 0x150 107 #define REG_MMU1_INT_ID 0x154 108 #define F_MMU_INT_ID_COMM_ID(a) (((a) >> 9) & 0x7) 109 #define F_MMU_INT_ID_SUB_COMM_ID(a) (((a) >> 7) & 0x3) 110 #define F_MMU_INT_ID_COMM_ID_EXT(a) (((a) >> 10) & 0x7) 111 #define F_MMU_INT_ID_SUB_COMM_ID_EXT(a) (((a) >> 7) & 0x7) 112 #define F_MMU_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7) 113 #define F_MMU_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f) 114 115 #define MTK_PROTECT_PA_ALIGN 256 116 #define MTK_IOMMU_BANK_SZ 0x1000 117 118 #define PERICFG_IOMMU_1 0x714 119 120 #define HAS_4GB_MODE BIT(0) 121 /* HW will use the EMI clock if there isn't the "bclk". */ 122 #define HAS_BCLK BIT(1) 123 #define HAS_VLD_PA_RNG BIT(2) 124 #define RESET_AXI BIT(3) 125 #define OUT_ORDER_WR_EN BIT(4) 126 #define HAS_SUB_COMM_2BITS BIT(5) 127 #define HAS_SUB_COMM_3BITS BIT(6) 128 #define WR_THROT_EN BIT(7) 129 #define HAS_LEGACY_IVRP_PADDR BIT(8) 130 #define IOVA_34_EN BIT(9) 131 #define SHARE_PGTABLE BIT(10) /* 2 HW share pgtable */ 132 #define DCM_DISABLE BIT(11) 133 #define STD_AXI_MODE BIT(12) /* For non MM iommu */ 134 /* 2 bits: iommu type */ 135 #define MTK_IOMMU_TYPE_MM (0x0 << 13) 136 #define MTK_IOMMU_TYPE_INFRA (0x1 << 13) 137 #define MTK_IOMMU_TYPE_MASK (0x3 << 13) 138 /* PM and clock always on. e.g. infra iommu */ 139 #define PM_CLK_AO BIT(15) 140 #define IFA_IOMMU_PCIE_SUPPORT BIT(16) 141 142 #define MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, mask) \ 143 ((((pdata)->flags) & (mask)) == (_x)) 144 145 #define MTK_IOMMU_HAS_FLAG(pdata, _x) MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, _x) 146 #define MTK_IOMMU_IS_TYPE(pdata, _x) MTK_IOMMU_HAS_FLAG_MASK(pdata, _x,\ 147 MTK_IOMMU_TYPE_MASK) 148 149 #define MTK_INVALID_LARBID MTK_LARB_NR_MAX 150 151 #define MTK_LARB_COM_MAX 8 152 #define MTK_LARB_SUBCOM_MAX 8 153 154 #define MTK_IOMMU_GROUP_MAX 8 155 #define MTK_IOMMU_BANK_MAX 5 156 157 enum mtk_iommu_plat { 158 M4U_MT2712, 159 M4U_MT6779, 160 M4U_MT8167, 161 M4U_MT8173, 162 M4U_MT8183, 163 M4U_MT8186, 164 M4U_MT8192, 165 M4U_MT8195, 166 }; 167 168 struct mtk_iommu_iova_region { 169 dma_addr_t iova_base; 170 unsigned long long size; 171 }; 172 173 struct mtk_iommu_suspend_reg { 174 u32 misc_ctrl; 175 u32 dcm_dis; 176 u32 ctrl_reg; 177 u32 vld_pa_rng; 178 u32 wr_len_ctrl; 179 180 u32 int_control[MTK_IOMMU_BANK_MAX]; 181 u32 int_main_control[MTK_IOMMU_BANK_MAX]; 182 u32 ivrp_paddr[MTK_IOMMU_BANK_MAX]; 183 }; 184 185 struct mtk_iommu_plat_data { 186 enum mtk_iommu_plat m4u_plat; 187 u32 flags; 188 u32 inv_sel_reg; 189 190 char *pericfg_comp_str; 191 struct list_head *hw_list; 192 unsigned int iova_region_nr; 193 const struct mtk_iommu_iova_region *iova_region; 194 195 u8 banks_num; 196 bool banks_enable[MTK_IOMMU_BANK_MAX]; 197 unsigned int banks_portmsk[MTK_IOMMU_BANK_MAX]; 198 unsigned char larbid_remap[MTK_LARB_COM_MAX][MTK_LARB_SUBCOM_MAX]; 199 }; 200 201 struct mtk_iommu_bank_data { 202 void __iomem *base; 203 int irq; 204 u8 id; 205 struct device *parent_dev; 206 struct mtk_iommu_data *parent_data; 207 spinlock_t tlb_lock; /* lock for tlb range flush */ 208 struct mtk_iommu_domain *m4u_dom; /* Each bank has a domain */ 209 }; 210 211 struct mtk_iommu_data { 212 struct device *dev; 213 struct clk *bclk; 214 phys_addr_t protect_base; /* protect memory base */ 215 struct mtk_iommu_suspend_reg reg; 216 struct iommu_group *m4u_group[MTK_IOMMU_GROUP_MAX]; 217 bool enable_4GB; 218 219 struct iommu_device iommu; 220 const struct mtk_iommu_plat_data *plat_data; 221 struct device *smicomm_dev; 222 223 struct mtk_iommu_bank_data *bank; 224 225 struct dma_iommu_mapping *mapping; /* For mtk_iommu_v1.c */ 226 struct regmap *pericfg; 227 228 struct mutex mutex; /* Protect m4u_group/m4u_dom above */ 229 230 /* 231 * In the sharing pgtable case, list data->list to the global list like m4ulist. 232 * In the non-sharing pgtable case, list data->list to the itself hw_list_head. 233 */ 234 struct list_head *hw_list; 235 struct list_head hw_list_head; 236 struct list_head list; 237 struct mtk_smi_larb_iommu larb_imu[MTK_LARB_NR_MAX]; 238 }; 239 240 struct mtk_iommu_domain { 241 struct io_pgtable_cfg cfg; 242 struct io_pgtable_ops *iop; 243 244 struct mtk_iommu_bank_data *bank; 245 struct iommu_domain domain; 246 247 struct mutex mutex; /* Protect "data" in this structure */ 248 }; 249 250 static int mtk_iommu_bind(struct device *dev) 251 { 252 struct mtk_iommu_data *data = dev_get_drvdata(dev); 253 254 return component_bind_all(dev, &data->larb_imu); 255 } 256 257 static void mtk_iommu_unbind(struct device *dev) 258 { 259 struct mtk_iommu_data *data = dev_get_drvdata(dev); 260 261 component_unbind_all(dev, &data->larb_imu); 262 } 263 264 static const struct iommu_ops mtk_iommu_ops; 265 266 static int mtk_iommu_hw_init(const struct mtk_iommu_data *data, unsigned int bankid); 267 268 #define MTK_IOMMU_TLB_ADDR(iova) ({ \ 269 dma_addr_t _addr = iova; \ 270 ((lower_32_bits(_addr) & GENMASK(31, 12)) | upper_32_bits(_addr));\ 271 }) 272 273 /* 274 * In M4U 4GB mode, the physical address is remapped as below: 275 * 276 * CPU Physical address: 277 * ==================== 278 * 279 * 0 1G 2G 3G 4G 5G 280 * |---A---|---B---|---C---|---D---|---E---| 281 * +--I/O--+------------Memory-------------+ 282 * 283 * IOMMU output physical address: 284 * ============================= 285 * 286 * 4G 5G 6G 7G 8G 287 * |---E---|---B---|---C---|---D---| 288 * +------------Memory-------------+ 289 * 290 * The Region 'A'(I/O) can NOT be mapped by M4U; For Region 'B'/'C'/'D', the 291 * bit32 of the CPU physical address always is needed to set, and for Region 292 * 'E', the CPU physical address keep as is. 293 * Additionally, The iommu consumers always use the CPU phyiscal address. 294 */ 295 #define MTK_IOMMU_4GB_MODE_REMAP_BASE 0x140000000UL 296 297 static LIST_HEAD(m4ulist); /* List all the M4U HWs */ 298 299 #define for_each_m4u(data, head) list_for_each_entry(data, head, list) 300 301 static const struct mtk_iommu_iova_region single_domain[] = { 302 {.iova_base = 0, .size = SZ_4G}, 303 }; 304 305 static const struct mtk_iommu_iova_region mt8192_multi_dom[] = { 306 { .iova_base = 0x0, .size = SZ_4G}, /* 0 ~ 4G */ 307 #if IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) 308 { .iova_base = SZ_4G, .size = SZ_4G}, /* 4G ~ 8G */ 309 { .iova_base = SZ_4G * 2, .size = SZ_4G}, /* 8G ~ 12G */ 310 { .iova_base = SZ_4G * 3, .size = SZ_4G}, /* 12G ~ 16G */ 311 312 { .iova_base = 0x240000000ULL, .size = 0x4000000}, /* CCU0 */ 313 { .iova_base = 0x244000000ULL, .size = 0x4000000}, /* CCU1 */ 314 #endif 315 }; 316 317 /* If 2 M4U share a domain(use the same hwlist), Put the corresponding info in first data.*/ 318 static struct mtk_iommu_data *mtk_iommu_get_frst_data(struct list_head *hwlist) 319 { 320 return list_first_entry(hwlist, struct mtk_iommu_data, list); 321 } 322 323 static struct mtk_iommu_domain *to_mtk_domain(struct iommu_domain *dom) 324 { 325 return container_of(dom, struct mtk_iommu_domain, domain); 326 } 327 328 static void mtk_iommu_tlb_flush_all(struct mtk_iommu_data *data) 329 { 330 /* Tlb flush all always is in bank0. */ 331 struct mtk_iommu_bank_data *bank = &data->bank[0]; 332 void __iomem *base = bank->base; 333 unsigned long flags; 334 335 spin_lock_irqsave(&bank->tlb_lock, flags); 336 writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, base + data->plat_data->inv_sel_reg); 337 writel_relaxed(F_ALL_INVLD, base + REG_MMU_INVALIDATE); 338 wmb(); /* Make sure the tlb flush all done */ 339 spin_unlock_irqrestore(&bank->tlb_lock, flags); 340 } 341 342 static void mtk_iommu_tlb_flush_range_sync(unsigned long iova, size_t size, 343 struct mtk_iommu_bank_data *bank) 344 { 345 struct list_head *head = bank->parent_data->hw_list; 346 struct mtk_iommu_bank_data *curbank; 347 struct mtk_iommu_data *data; 348 bool check_pm_status; 349 unsigned long flags; 350 void __iomem *base; 351 int ret; 352 u32 tmp; 353 354 for_each_m4u(data, head) { 355 /* 356 * To avoid resume the iommu device frequently when the iommu device 357 * is not active, it doesn't always call pm_runtime_get here, then tlb 358 * flush depends on the tlb flush all in the runtime resume. 359 * 360 * There are 2 special cases: 361 * 362 * Case1: The iommu dev doesn't have power domain but has bclk. This case 363 * should also avoid the tlb flush while the dev is not active to mute 364 * the tlb timeout log. like mt8173. 365 * 366 * Case2: The power/clock of infra iommu is always on, and it doesn't 367 * have the device link with the master devices. This case should avoid 368 * the PM status check. 369 */ 370 check_pm_status = !MTK_IOMMU_HAS_FLAG(data->plat_data, PM_CLK_AO); 371 372 if (check_pm_status) { 373 if (pm_runtime_get_if_in_use(data->dev) <= 0) 374 continue; 375 } 376 377 curbank = &data->bank[bank->id]; 378 base = curbank->base; 379 380 spin_lock_irqsave(&curbank->tlb_lock, flags); 381 writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, 382 base + data->plat_data->inv_sel_reg); 383 384 writel_relaxed(MTK_IOMMU_TLB_ADDR(iova), base + REG_MMU_INVLD_START_A); 385 writel_relaxed(MTK_IOMMU_TLB_ADDR(iova + size - 1), 386 base + REG_MMU_INVLD_END_A); 387 writel_relaxed(F_MMU_INV_RANGE, base + REG_MMU_INVALIDATE); 388 389 /* tlb sync */ 390 ret = readl_poll_timeout_atomic(base + REG_MMU_CPE_DONE, 391 tmp, tmp != 0, 10, 1000); 392 393 /* Clear the CPE status */ 394 writel_relaxed(0, base + REG_MMU_CPE_DONE); 395 spin_unlock_irqrestore(&curbank->tlb_lock, flags); 396 397 if (ret) { 398 dev_warn(data->dev, 399 "Partial TLB flush timed out, falling back to full flush\n"); 400 mtk_iommu_tlb_flush_all(data); 401 } 402 403 if (check_pm_status) 404 pm_runtime_put(data->dev); 405 } 406 } 407 408 static irqreturn_t mtk_iommu_isr(int irq, void *dev_id) 409 { 410 struct mtk_iommu_bank_data *bank = dev_id; 411 struct mtk_iommu_data *data = bank->parent_data; 412 struct mtk_iommu_domain *dom = bank->m4u_dom; 413 unsigned int fault_larb = MTK_INVALID_LARBID, fault_port = 0, sub_comm = 0; 414 u32 int_state, regval, va34_32, pa34_32; 415 const struct mtk_iommu_plat_data *plat_data = data->plat_data; 416 void __iomem *base = bank->base; 417 u64 fault_iova, fault_pa; 418 bool layer, write; 419 420 /* Read error info from registers */ 421 int_state = readl_relaxed(base + REG_MMU_FAULT_ST1); 422 if (int_state & F_REG_MMU0_FAULT_MASK) { 423 regval = readl_relaxed(base + REG_MMU0_INT_ID); 424 fault_iova = readl_relaxed(base + REG_MMU0_FAULT_VA); 425 fault_pa = readl_relaxed(base + REG_MMU0_INVLD_PA); 426 } else { 427 regval = readl_relaxed(base + REG_MMU1_INT_ID); 428 fault_iova = readl_relaxed(base + REG_MMU1_FAULT_VA); 429 fault_pa = readl_relaxed(base + REG_MMU1_INVLD_PA); 430 } 431 layer = fault_iova & F_MMU_FAULT_VA_LAYER_BIT; 432 write = fault_iova & F_MMU_FAULT_VA_WRITE_BIT; 433 if (MTK_IOMMU_HAS_FLAG(plat_data, IOVA_34_EN)) { 434 va34_32 = FIELD_GET(F_MMU_INVAL_VA_34_32_MASK, fault_iova); 435 fault_iova = fault_iova & F_MMU_INVAL_VA_31_12_MASK; 436 fault_iova |= (u64)va34_32 << 32; 437 } 438 pa34_32 = FIELD_GET(F_MMU_INVAL_PA_34_32_MASK, fault_iova); 439 fault_pa |= (u64)pa34_32 << 32; 440 441 if (MTK_IOMMU_IS_TYPE(plat_data, MTK_IOMMU_TYPE_MM)) { 442 fault_port = F_MMU_INT_ID_PORT_ID(regval); 443 if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_SUB_COMM_2BITS)) { 444 fault_larb = F_MMU_INT_ID_COMM_ID(regval); 445 sub_comm = F_MMU_INT_ID_SUB_COMM_ID(regval); 446 } else if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_SUB_COMM_3BITS)) { 447 fault_larb = F_MMU_INT_ID_COMM_ID_EXT(regval); 448 sub_comm = F_MMU_INT_ID_SUB_COMM_ID_EXT(regval); 449 } else { 450 fault_larb = F_MMU_INT_ID_LARB_ID(regval); 451 } 452 fault_larb = data->plat_data->larbid_remap[fault_larb][sub_comm]; 453 } 454 455 if (report_iommu_fault(&dom->domain, bank->parent_dev, fault_iova, 456 write ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ)) { 457 dev_err_ratelimited( 458 bank->parent_dev, 459 "fault type=0x%x iova=0x%llx pa=0x%llx master=0x%x(larb=%d port=%d) layer=%d %s\n", 460 int_state, fault_iova, fault_pa, regval, fault_larb, fault_port, 461 layer, write ? "write" : "read"); 462 } 463 464 /* Interrupt clear */ 465 regval = readl_relaxed(base + REG_MMU_INT_CONTROL0); 466 regval |= F_INT_CLR_BIT; 467 writel_relaxed(regval, base + REG_MMU_INT_CONTROL0); 468 469 mtk_iommu_tlb_flush_all(data); 470 471 return IRQ_HANDLED; 472 } 473 474 static unsigned int mtk_iommu_get_bank_id(struct device *dev, 475 const struct mtk_iommu_plat_data *plat_data) 476 { 477 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 478 unsigned int i, portmsk = 0, bankid = 0; 479 480 if (plat_data->banks_num == 1) 481 return bankid; 482 483 for (i = 0; i < fwspec->num_ids; i++) 484 portmsk |= BIT(MTK_M4U_TO_PORT(fwspec->ids[i])); 485 486 for (i = 0; i < plat_data->banks_num && i < MTK_IOMMU_BANK_MAX; i++) { 487 if (!plat_data->banks_enable[i]) 488 continue; 489 490 if (portmsk & plat_data->banks_portmsk[i]) { 491 bankid = i; 492 break; 493 } 494 } 495 return bankid; /* default is 0 */ 496 } 497 498 static int mtk_iommu_get_iova_region_id(struct device *dev, 499 const struct mtk_iommu_plat_data *plat_data) 500 { 501 const struct mtk_iommu_iova_region *rgn = plat_data->iova_region; 502 const struct bus_dma_region *dma_rgn = dev->dma_range_map; 503 int i, candidate = -1; 504 dma_addr_t dma_end; 505 506 if (!dma_rgn || plat_data->iova_region_nr == 1) 507 return 0; 508 509 dma_end = dma_rgn->dma_start + dma_rgn->size - 1; 510 for (i = 0; i < plat_data->iova_region_nr; i++, rgn++) { 511 /* Best fit. */ 512 if (dma_rgn->dma_start == rgn->iova_base && 513 dma_end == rgn->iova_base + rgn->size - 1) 514 return i; 515 /* ok if it is inside this region. */ 516 if (dma_rgn->dma_start >= rgn->iova_base && 517 dma_end < rgn->iova_base + rgn->size) 518 candidate = i; 519 } 520 521 if (candidate >= 0) 522 return candidate; 523 dev_err(dev, "Can NOT find the iommu domain id(%pad 0x%llx).\n", 524 &dma_rgn->dma_start, dma_rgn->size); 525 return -EINVAL; 526 } 527 528 static int mtk_iommu_config(struct mtk_iommu_data *data, struct device *dev, 529 bool enable, unsigned int regionid) 530 { 531 struct mtk_smi_larb_iommu *larb_mmu; 532 unsigned int larbid, portid; 533 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 534 const struct mtk_iommu_iova_region *region; 535 u32 peri_mmuen, peri_mmuen_msk; 536 int i, ret = 0; 537 538 for (i = 0; i < fwspec->num_ids; ++i) { 539 larbid = MTK_M4U_TO_LARB(fwspec->ids[i]); 540 portid = MTK_M4U_TO_PORT(fwspec->ids[i]); 541 542 if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) { 543 larb_mmu = &data->larb_imu[larbid]; 544 545 region = data->plat_data->iova_region + regionid; 546 larb_mmu->bank[portid] = upper_32_bits(region->iova_base); 547 548 dev_dbg(dev, "%s iommu for larb(%s) port %d region %d rgn-bank %d.\n", 549 enable ? "enable" : "disable", dev_name(larb_mmu->dev), 550 portid, regionid, larb_mmu->bank[portid]); 551 552 if (enable) 553 larb_mmu->mmu |= MTK_SMI_MMU_EN(portid); 554 else 555 larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid); 556 } else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA)) { 557 peri_mmuen_msk = BIT(portid); 558 /* PCI dev has only one output id, enable the next writing bit for PCIe */ 559 if (dev_is_pci(dev)) 560 peri_mmuen_msk |= BIT(portid + 1); 561 562 peri_mmuen = enable ? peri_mmuen_msk : 0; 563 ret = regmap_update_bits(data->pericfg, PERICFG_IOMMU_1, 564 peri_mmuen_msk, peri_mmuen); 565 if (ret) 566 dev_err(dev, "%s iommu(%s) inframaster 0x%x fail(%d).\n", 567 enable ? "enable" : "disable", 568 dev_name(data->dev), peri_mmuen_msk, ret); 569 } 570 } 571 return ret; 572 } 573 574 static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom, 575 struct mtk_iommu_data *data, 576 unsigned int region_id) 577 { 578 const struct mtk_iommu_iova_region *region; 579 struct mtk_iommu_domain *m4u_dom; 580 581 /* Always use bank0 in sharing pgtable case */ 582 m4u_dom = data->bank[0].m4u_dom; 583 if (m4u_dom) { 584 dom->iop = m4u_dom->iop; 585 dom->cfg = m4u_dom->cfg; 586 dom->domain.pgsize_bitmap = m4u_dom->cfg.pgsize_bitmap; 587 goto update_iova_region; 588 } 589 590 dom->cfg = (struct io_pgtable_cfg) { 591 .quirks = IO_PGTABLE_QUIRK_ARM_NS | 592 IO_PGTABLE_QUIRK_NO_PERMS | 593 IO_PGTABLE_QUIRK_ARM_MTK_EXT, 594 .pgsize_bitmap = mtk_iommu_ops.pgsize_bitmap, 595 .ias = MTK_IOMMU_HAS_FLAG(data->plat_data, IOVA_34_EN) ? 34 : 32, 596 .iommu_dev = data->dev, 597 }; 598 599 if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE)) 600 dom->cfg.oas = data->enable_4GB ? 33 : 32; 601 else 602 dom->cfg.oas = 35; 603 604 dom->iop = alloc_io_pgtable_ops(ARM_V7S, &dom->cfg, data); 605 if (!dom->iop) { 606 dev_err(data->dev, "Failed to alloc io pgtable\n"); 607 return -EINVAL; 608 } 609 610 /* Update our support page sizes bitmap */ 611 dom->domain.pgsize_bitmap = dom->cfg.pgsize_bitmap; 612 613 update_iova_region: 614 /* Update the iova region for this domain */ 615 region = data->plat_data->iova_region + region_id; 616 dom->domain.geometry.aperture_start = region->iova_base; 617 dom->domain.geometry.aperture_end = region->iova_base + region->size - 1; 618 dom->domain.geometry.force_aperture = true; 619 return 0; 620 } 621 622 static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type) 623 { 624 struct mtk_iommu_domain *dom; 625 626 if (type != IOMMU_DOMAIN_DMA && type != IOMMU_DOMAIN_UNMANAGED) 627 return NULL; 628 629 dom = kzalloc(sizeof(*dom), GFP_KERNEL); 630 if (!dom) 631 return NULL; 632 mutex_init(&dom->mutex); 633 634 return &dom->domain; 635 } 636 637 static void mtk_iommu_domain_free(struct iommu_domain *domain) 638 { 639 kfree(to_mtk_domain(domain)); 640 } 641 642 static int mtk_iommu_attach_device(struct iommu_domain *domain, 643 struct device *dev) 644 { 645 struct mtk_iommu_data *data = dev_iommu_priv_get(dev), *frstdata; 646 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 647 struct list_head *hw_list = data->hw_list; 648 struct device *m4udev = data->dev; 649 struct mtk_iommu_bank_data *bank; 650 unsigned int bankid; 651 int ret, region_id; 652 653 region_id = mtk_iommu_get_iova_region_id(dev, data->plat_data); 654 if (region_id < 0) 655 return region_id; 656 657 bankid = mtk_iommu_get_bank_id(dev, data->plat_data); 658 mutex_lock(&dom->mutex); 659 if (!dom->bank) { 660 /* Data is in the frstdata in sharing pgtable case. */ 661 frstdata = mtk_iommu_get_frst_data(hw_list); 662 663 ret = mtk_iommu_domain_finalise(dom, frstdata, region_id); 664 if (ret) { 665 mutex_unlock(&dom->mutex); 666 return -ENODEV; 667 } 668 dom->bank = &data->bank[bankid]; 669 } 670 mutex_unlock(&dom->mutex); 671 672 mutex_lock(&data->mutex); 673 bank = &data->bank[bankid]; 674 if (!bank->m4u_dom) { /* Initialize the M4U HW for each a BANK */ 675 ret = pm_runtime_resume_and_get(m4udev); 676 if (ret < 0) { 677 dev_err(m4udev, "pm get fail(%d) in attach.\n", ret); 678 goto err_unlock; 679 } 680 681 ret = mtk_iommu_hw_init(data, bankid); 682 if (ret) { 683 pm_runtime_put(m4udev); 684 goto err_unlock; 685 } 686 bank->m4u_dom = dom; 687 writel(dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK, 688 bank->base + REG_MMU_PT_BASE_ADDR); 689 690 pm_runtime_put(m4udev); 691 } 692 mutex_unlock(&data->mutex); 693 694 return mtk_iommu_config(data, dev, true, region_id); 695 696 err_unlock: 697 mutex_unlock(&data->mutex); 698 return ret; 699 } 700 701 static void mtk_iommu_detach_device(struct iommu_domain *domain, 702 struct device *dev) 703 { 704 struct mtk_iommu_data *data = dev_iommu_priv_get(dev); 705 706 mtk_iommu_config(data, dev, false, 0); 707 } 708 709 static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova, 710 phys_addr_t paddr, size_t size, int prot, gfp_t gfp) 711 { 712 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 713 714 /* The "4GB mode" M4U physically can not use the lower remap of Dram. */ 715 if (dom->bank->parent_data->enable_4GB) 716 paddr |= BIT_ULL(32); 717 718 /* Synchronize with the tlb_lock */ 719 return dom->iop->map(dom->iop, iova, paddr, size, prot, gfp); 720 } 721 722 static size_t mtk_iommu_unmap(struct iommu_domain *domain, 723 unsigned long iova, size_t size, 724 struct iommu_iotlb_gather *gather) 725 { 726 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 727 728 iommu_iotlb_gather_add_range(gather, iova, size); 729 return dom->iop->unmap(dom->iop, iova, size, gather); 730 } 731 732 static void mtk_iommu_flush_iotlb_all(struct iommu_domain *domain) 733 { 734 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 735 736 mtk_iommu_tlb_flush_all(dom->bank->parent_data); 737 } 738 739 static void mtk_iommu_iotlb_sync(struct iommu_domain *domain, 740 struct iommu_iotlb_gather *gather) 741 { 742 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 743 size_t length = gather->end - gather->start + 1; 744 745 mtk_iommu_tlb_flush_range_sync(gather->start, length, dom->bank); 746 } 747 748 static void mtk_iommu_sync_map(struct iommu_domain *domain, unsigned long iova, 749 size_t size) 750 { 751 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 752 753 mtk_iommu_tlb_flush_range_sync(iova, size, dom->bank); 754 } 755 756 static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain, 757 dma_addr_t iova) 758 { 759 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 760 phys_addr_t pa; 761 762 pa = dom->iop->iova_to_phys(dom->iop, iova); 763 if (IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) && 764 dom->bank->parent_data->enable_4GB && 765 pa >= MTK_IOMMU_4GB_MODE_REMAP_BASE) 766 pa &= ~BIT_ULL(32); 767 768 return pa; 769 } 770 771 static struct iommu_device *mtk_iommu_probe_device(struct device *dev) 772 { 773 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 774 struct mtk_iommu_data *data; 775 struct device_link *link; 776 struct device *larbdev; 777 unsigned int larbid, larbidx, i; 778 779 if (!fwspec || fwspec->ops != &mtk_iommu_ops) 780 return ERR_PTR(-ENODEV); /* Not a iommu client device */ 781 782 data = dev_iommu_priv_get(dev); 783 784 if (!MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) 785 return &data->iommu; 786 787 /* 788 * Link the consumer device with the smi-larb device(supplier). 789 * The device that connects with each a larb is a independent HW. 790 * All the ports in each a device should be in the same larbs. 791 */ 792 larbid = MTK_M4U_TO_LARB(fwspec->ids[0]); 793 if (larbid >= MTK_LARB_NR_MAX) 794 return ERR_PTR(-EINVAL); 795 796 for (i = 1; i < fwspec->num_ids; i++) { 797 larbidx = MTK_M4U_TO_LARB(fwspec->ids[i]); 798 if (larbid != larbidx) { 799 dev_err(dev, "Can only use one larb. Fail@larb%d-%d.\n", 800 larbid, larbidx); 801 return ERR_PTR(-EINVAL); 802 } 803 } 804 larbdev = data->larb_imu[larbid].dev; 805 if (!larbdev) 806 return ERR_PTR(-EINVAL); 807 808 link = device_link_add(dev, larbdev, 809 DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS); 810 if (!link) 811 dev_err(dev, "Unable to link %s\n", dev_name(larbdev)); 812 return &data->iommu; 813 } 814 815 static void mtk_iommu_release_device(struct device *dev) 816 { 817 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 818 struct mtk_iommu_data *data; 819 struct device *larbdev; 820 unsigned int larbid; 821 822 if (!fwspec || fwspec->ops != &mtk_iommu_ops) 823 return; 824 825 data = dev_iommu_priv_get(dev); 826 if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) { 827 larbid = MTK_M4U_TO_LARB(fwspec->ids[0]); 828 larbdev = data->larb_imu[larbid].dev; 829 device_link_remove(dev, larbdev); 830 } 831 832 iommu_fwspec_free(dev); 833 } 834 835 static int mtk_iommu_get_group_id(struct device *dev, const struct mtk_iommu_plat_data *plat_data) 836 { 837 unsigned int bankid; 838 839 /* 840 * If the bank function is enabled, each bank is a iommu group/domain. 841 * Otherwise, each iova region is a iommu group/domain. 842 */ 843 bankid = mtk_iommu_get_bank_id(dev, plat_data); 844 if (bankid) 845 return bankid; 846 847 return mtk_iommu_get_iova_region_id(dev, plat_data); 848 } 849 850 static struct iommu_group *mtk_iommu_device_group(struct device *dev) 851 { 852 struct mtk_iommu_data *c_data = dev_iommu_priv_get(dev), *data; 853 struct list_head *hw_list = c_data->hw_list; 854 struct iommu_group *group; 855 int groupid; 856 857 data = mtk_iommu_get_frst_data(hw_list); 858 if (!data) 859 return ERR_PTR(-ENODEV); 860 861 groupid = mtk_iommu_get_group_id(dev, data->plat_data); 862 if (groupid < 0) 863 return ERR_PTR(groupid); 864 865 mutex_lock(&data->mutex); 866 group = data->m4u_group[groupid]; 867 if (!group) { 868 group = iommu_group_alloc(); 869 if (!IS_ERR(group)) 870 data->m4u_group[groupid] = group; 871 } else { 872 iommu_group_ref_get(group); 873 } 874 mutex_unlock(&data->mutex); 875 return group; 876 } 877 878 static int mtk_iommu_of_xlate(struct device *dev, struct of_phandle_args *args) 879 { 880 struct platform_device *m4updev; 881 882 if (args->args_count != 1) { 883 dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n", 884 args->args_count); 885 return -EINVAL; 886 } 887 888 if (!dev_iommu_priv_get(dev)) { 889 /* Get the m4u device */ 890 m4updev = of_find_device_by_node(args->np); 891 if (WARN_ON(!m4updev)) 892 return -EINVAL; 893 894 dev_iommu_priv_set(dev, platform_get_drvdata(m4updev)); 895 } 896 897 return iommu_fwspec_add_ids(dev, args->args, 1); 898 } 899 900 static void mtk_iommu_get_resv_regions(struct device *dev, 901 struct list_head *head) 902 { 903 struct mtk_iommu_data *data = dev_iommu_priv_get(dev); 904 unsigned int regionid = mtk_iommu_get_iova_region_id(dev, data->plat_data), i; 905 const struct mtk_iommu_iova_region *resv, *curdom; 906 struct iommu_resv_region *region; 907 int prot = IOMMU_WRITE | IOMMU_READ; 908 909 if ((int)regionid < 0) 910 return; 911 curdom = data->plat_data->iova_region + regionid; 912 for (i = 0; i < data->plat_data->iova_region_nr; i++) { 913 resv = data->plat_data->iova_region + i; 914 915 /* Only reserve when the region is inside the current domain */ 916 if (resv->iova_base <= curdom->iova_base || 917 resv->iova_base + resv->size >= curdom->iova_base + curdom->size) 918 continue; 919 920 region = iommu_alloc_resv_region(resv->iova_base, resv->size, 921 prot, IOMMU_RESV_RESERVED); 922 if (!region) 923 return; 924 925 list_add_tail(®ion->list, head); 926 } 927 } 928 929 static const struct iommu_ops mtk_iommu_ops = { 930 .domain_alloc = mtk_iommu_domain_alloc, 931 .probe_device = mtk_iommu_probe_device, 932 .release_device = mtk_iommu_release_device, 933 .device_group = mtk_iommu_device_group, 934 .of_xlate = mtk_iommu_of_xlate, 935 .get_resv_regions = mtk_iommu_get_resv_regions, 936 .put_resv_regions = generic_iommu_put_resv_regions, 937 .pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M, 938 .owner = THIS_MODULE, 939 .default_domain_ops = &(const struct iommu_domain_ops) { 940 .attach_dev = mtk_iommu_attach_device, 941 .detach_dev = mtk_iommu_detach_device, 942 .map = mtk_iommu_map, 943 .unmap = mtk_iommu_unmap, 944 .flush_iotlb_all = mtk_iommu_flush_iotlb_all, 945 .iotlb_sync = mtk_iommu_iotlb_sync, 946 .iotlb_sync_map = mtk_iommu_sync_map, 947 .iova_to_phys = mtk_iommu_iova_to_phys, 948 .free = mtk_iommu_domain_free, 949 } 950 }; 951 952 static int mtk_iommu_hw_init(const struct mtk_iommu_data *data, unsigned int bankid) 953 { 954 const struct mtk_iommu_bank_data *bankx = &data->bank[bankid]; 955 const struct mtk_iommu_bank_data *bank0 = &data->bank[0]; 956 u32 regval; 957 958 /* 959 * Global control settings are in bank0. May re-init these global registers 960 * since no sure if there is bank0 consumers. 961 */ 962 if (data->plat_data->m4u_plat == M4U_MT8173) { 963 regval = F_MMU_PREFETCH_RT_REPLACE_MOD | 964 F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173; 965 } else { 966 regval = readl_relaxed(bank0->base + REG_MMU_CTRL_REG); 967 regval |= F_MMU_TF_PROT_TO_PROGRAM_ADDR; 968 } 969 writel_relaxed(regval, bank0->base + REG_MMU_CTRL_REG); 970 971 if (data->enable_4GB && 972 MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_VLD_PA_RNG)) { 973 /* 974 * If 4GB mode is enabled, the validate PA range is from 975 * 0x1_0000_0000 to 0x1_ffff_ffff. here record bit[32:30]. 976 */ 977 regval = F_MMU_VLD_PA_RNG(7, 4); 978 writel_relaxed(regval, bank0->base + REG_MMU_VLD_PA_RNG); 979 } 980 if (MTK_IOMMU_HAS_FLAG(data->plat_data, DCM_DISABLE)) 981 writel_relaxed(F_MMU_DCM, bank0->base + REG_MMU_DCM_DIS); 982 else 983 writel_relaxed(0, bank0->base + REG_MMU_DCM_DIS); 984 985 if (MTK_IOMMU_HAS_FLAG(data->plat_data, WR_THROT_EN)) { 986 /* write command throttling mode */ 987 regval = readl_relaxed(bank0->base + REG_MMU_WR_LEN_CTRL); 988 regval &= ~F_MMU_WR_THROT_DIS_MASK; 989 writel_relaxed(regval, bank0->base + REG_MMU_WR_LEN_CTRL); 990 } 991 992 if (MTK_IOMMU_HAS_FLAG(data->plat_data, RESET_AXI)) { 993 /* The register is called STANDARD_AXI_MODE in this case */ 994 regval = 0; 995 } else { 996 regval = readl_relaxed(bank0->base + REG_MMU_MISC_CTRL); 997 if (!MTK_IOMMU_HAS_FLAG(data->plat_data, STD_AXI_MODE)) 998 regval &= ~F_MMU_STANDARD_AXI_MODE_MASK; 999 if (MTK_IOMMU_HAS_FLAG(data->plat_data, OUT_ORDER_WR_EN)) 1000 regval &= ~F_MMU_IN_ORDER_WR_EN_MASK; 1001 } 1002 writel_relaxed(regval, bank0->base + REG_MMU_MISC_CTRL); 1003 1004 /* Independent settings for each bank */ 1005 regval = F_L2_MULIT_HIT_EN | 1006 F_TABLE_WALK_FAULT_INT_EN | 1007 F_PREETCH_FIFO_OVERFLOW_INT_EN | 1008 F_MISS_FIFO_OVERFLOW_INT_EN | 1009 F_PREFETCH_FIFO_ERR_INT_EN | 1010 F_MISS_FIFO_ERR_INT_EN; 1011 writel_relaxed(regval, bankx->base + REG_MMU_INT_CONTROL0); 1012 1013 regval = F_INT_TRANSLATION_FAULT | 1014 F_INT_MAIN_MULTI_HIT_FAULT | 1015 F_INT_INVALID_PA_FAULT | 1016 F_INT_ENTRY_REPLACEMENT_FAULT | 1017 F_INT_TLB_MISS_FAULT | 1018 F_INT_MISS_TRANSACTION_FIFO_FAULT | 1019 F_INT_PRETETCH_TRANSATION_FIFO_FAULT; 1020 writel_relaxed(regval, bankx->base + REG_MMU_INT_MAIN_CONTROL); 1021 1022 if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_LEGACY_IVRP_PADDR)) 1023 regval = (data->protect_base >> 1) | (data->enable_4GB << 31); 1024 else 1025 regval = lower_32_bits(data->protect_base) | 1026 upper_32_bits(data->protect_base); 1027 writel_relaxed(regval, bankx->base + REG_MMU_IVRP_PADDR); 1028 1029 if (devm_request_irq(bankx->parent_dev, bankx->irq, mtk_iommu_isr, 0, 1030 dev_name(bankx->parent_dev), (void *)bankx)) { 1031 writel_relaxed(0, bankx->base + REG_MMU_PT_BASE_ADDR); 1032 dev_err(bankx->parent_dev, "Failed @ IRQ-%d Request\n", bankx->irq); 1033 return -ENODEV; 1034 } 1035 1036 return 0; 1037 } 1038 1039 static const struct component_master_ops mtk_iommu_com_ops = { 1040 .bind = mtk_iommu_bind, 1041 .unbind = mtk_iommu_unbind, 1042 }; 1043 1044 static int mtk_iommu_mm_dts_parse(struct device *dev, struct component_match **match, 1045 struct mtk_iommu_data *data) 1046 { 1047 struct device_node *larbnode, *smicomm_node, *smi_subcomm_node; 1048 struct platform_device *plarbdev; 1049 struct device_link *link; 1050 int i, larb_nr, ret; 1051 1052 larb_nr = of_count_phandle_with_args(dev->of_node, "mediatek,larbs", NULL); 1053 if (larb_nr < 0) 1054 return larb_nr; 1055 1056 for (i = 0; i < larb_nr; i++) { 1057 u32 id; 1058 1059 larbnode = of_parse_phandle(dev->of_node, "mediatek,larbs", i); 1060 if (!larbnode) 1061 return -EINVAL; 1062 1063 if (!of_device_is_available(larbnode)) { 1064 of_node_put(larbnode); 1065 continue; 1066 } 1067 1068 ret = of_property_read_u32(larbnode, "mediatek,larb-id", &id); 1069 if (ret)/* The id is consecutive if there is no this property */ 1070 id = i; 1071 1072 plarbdev = of_find_device_by_node(larbnode); 1073 if (!plarbdev) { 1074 of_node_put(larbnode); 1075 return -ENODEV; 1076 } 1077 if (!plarbdev->dev.driver) { 1078 of_node_put(larbnode); 1079 return -EPROBE_DEFER; 1080 } 1081 data->larb_imu[id].dev = &plarbdev->dev; 1082 1083 component_match_add_release(dev, match, component_release_of, 1084 component_compare_of, larbnode); 1085 } 1086 1087 /* Get smi-(sub)-common dev from the last larb. */ 1088 smi_subcomm_node = of_parse_phandle(larbnode, "mediatek,smi", 0); 1089 if (!smi_subcomm_node) 1090 return -EINVAL; 1091 1092 /* 1093 * It may have two level smi-common. the node is smi-sub-common if it 1094 * has a new mediatek,smi property. otherwise it is smi-commmon. 1095 */ 1096 smicomm_node = of_parse_phandle(smi_subcomm_node, "mediatek,smi", 0); 1097 if (smicomm_node) 1098 of_node_put(smi_subcomm_node); 1099 else 1100 smicomm_node = smi_subcomm_node; 1101 1102 plarbdev = of_find_device_by_node(smicomm_node); 1103 of_node_put(smicomm_node); 1104 data->smicomm_dev = &plarbdev->dev; 1105 1106 link = device_link_add(data->smicomm_dev, dev, 1107 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME); 1108 if (!link) { 1109 dev_err(dev, "Unable to link %s.\n", dev_name(data->smicomm_dev)); 1110 return -EINVAL; 1111 } 1112 return 0; 1113 } 1114 1115 static int mtk_iommu_probe(struct platform_device *pdev) 1116 { 1117 struct mtk_iommu_data *data; 1118 struct device *dev = &pdev->dev; 1119 struct resource *res; 1120 resource_size_t ioaddr; 1121 struct component_match *match = NULL; 1122 struct regmap *infracfg; 1123 void *protect; 1124 int ret, banks_num, i = 0; 1125 u32 val; 1126 char *p; 1127 struct mtk_iommu_bank_data *bank; 1128 void __iomem *base; 1129 1130 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 1131 if (!data) 1132 return -ENOMEM; 1133 data->dev = dev; 1134 data->plat_data = of_device_get_match_data(dev); 1135 1136 /* Protect memory. HW will access here while translation fault.*/ 1137 protect = devm_kzalloc(dev, MTK_PROTECT_PA_ALIGN * 2, GFP_KERNEL); 1138 if (!protect) 1139 return -ENOMEM; 1140 data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN); 1141 1142 if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE)) { 1143 switch (data->plat_data->m4u_plat) { 1144 case M4U_MT2712: 1145 p = "mediatek,mt2712-infracfg"; 1146 break; 1147 case M4U_MT8173: 1148 p = "mediatek,mt8173-infracfg"; 1149 break; 1150 default: 1151 p = NULL; 1152 } 1153 1154 infracfg = syscon_regmap_lookup_by_compatible(p); 1155 1156 if (IS_ERR(infracfg)) 1157 return PTR_ERR(infracfg); 1158 1159 ret = regmap_read(infracfg, REG_INFRA_MISC, &val); 1160 if (ret) 1161 return ret; 1162 data->enable_4GB = !!(val & F_DDR_4GB_SUPPORT_EN); 1163 } 1164 1165 banks_num = data->plat_data->banks_num; 1166 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1167 if (resource_size(res) < banks_num * MTK_IOMMU_BANK_SZ) { 1168 dev_err(dev, "banknr %d. res %pR is not enough.\n", banks_num, res); 1169 return -EINVAL; 1170 } 1171 base = devm_ioremap_resource(dev, res); 1172 if (IS_ERR(base)) 1173 return PTR_ERR(base); 1174 ioaddr = res->start; 1175 1176 data->bank = devm_kmalloc(dev, banks_num * sizeof(*data->bank), GFP_KERNEL); 1177 if (!data->bank) 1178 return -ENOMEM; 1179 1180 do { 1181 if (!data->plat_data->banks_enable[i]) 1182 continue; 1183 bank = &data->bank[i]; 1184 bank->id = i; 1185 bank->base = base + i * MTK_IOMMU_BANK_SZ; 1186 bank->m4u_dom = NULL; 1187 1188 bank->irq = platform_get_irq(pdev, i); 1189 if (bank->irq < 0) 1190 return bank->irq; 1191 bank->parent_dev = dev; 1192 bank->parent_data = data; 1193 spin_lock_init(&bank->tlb_lock); 1194 } while (++i < banks_num); 1195 1196 if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_BCLK)) { 1197 data->bclk = devm_clk_get(dev, "bclk"); 1198 if (IS_ERR(data->bclk)) 1199 return PTR_ERR(data->bclk); 1200 } 1201 1202 pm_runtime_enable(dev); 1203 1204 if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) { 1205 ret = mtk_iommu_mm_dts_parse(dev, &match, data); 1206 if (ret) { 1207 dev_err(dev, "mm dts parse fail(%d).", ret); 1208 goto out_runtime_disable; 1209 } 1210 } else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA) && 1211 data->plat_data->pericfg_comp_str) { 1212 infracfg = syscon_regmap_lookup_by_compatible(data->plat_data->pericfg_comp_str); 1213 if (IS_ERR(infracfg)) { 1214 ret = PTR_ERR(infracfg); 1215 goto out_runtime_disable; 1216 } 1217 1218 data->pericfg = infracfg; 1219 } 1220 1221 platform_set_drvdata(pdev, data); 1222 mutex_init(&data->mutex); 1223 1224 ret = iommu_device_sysfs_add(&data->iommu, dev, NULL, 1225 "mtk-iommu.%pa", &ioaddr); 1226 if (ret) 1227 goto out_link_remove; 1228 1229 ret = iommu_device_register(&data->iommu, &mtk_iommu_ops, dev); 1230 if (ret) 1231 goto out_sysfs_remove; 1232 1233 if (MTK_IOMMU_HAS_FLAG(data->plat_data, SHARE_PGTABLE)) { 1234 list_add_tail(&data->list, data->plat_data->hw_list); 1235 data->hw_list = data->plat_data->hw_list; 1236 } else { 1237 INIT_LIST_HEAD(&data->hw_list_head); 1238 list_add_tail(&data->list, &data->hw_list_head); 1239 data->hw_list = &data->hw_list_head; 1240 } 1241 1242 if (!iommu_present(&platform_bus_type)) { 1243 ret = bus_set_iommu(&platform_bus_type, &mtk_iommu_ops); 1244 if (ret) 1245 goto out_list_del; 1246 } 1247 1248 if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) { 1249 ret = component_master_add_with_match(dev, &mtk_iommu_com_ops, match); 1250 if (ret) 1251 goto out_bus_set_null; 1252 } else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA) && 1253 MTK_IOMMU_HAS_FLAG(data->plat_data, IFA_IOMMU_PCIE_SUPPORT)) { 1254 #ifdef CONFIG_PCI 1255 if (!iommu_present(&pci_bus_type)) { 1256 ret = bus_set_iommu(&pci_bus_type, &mtk_iommu_ops); 1257 if (ret) /* PCIe fail don't affect platform_bus. */ 1258 goto out_list_del; 1259 } 1260 #endif 1261 } 1262 return ret; 1263 1264 out_bus_set_null: 1265 bus_set_iommu(&platform_bus_type, NULL); 1266 out_list_del: 1267 list_del(&data->list); 1268 iommu_device_unregister(&data->iommu); 1269 out_sysfs_remove: 1270 iommu_device_sysfs_remove(&data->iommu); 1271 out_link_remove: 1272 if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) 1273 device_link_remove(data->smicomm_dev, dev); 1274 out_runtime_disable: 1275 pm_runtime_disable(dev); 1276 return ret; 1277 } 1278 1279 static int mtk_iommu_remove(struct platform_device *pdev) 1280 { 1281 struct mtk_iommu_data *data = platform_get_drvdata(pdev); 1282 struct mtk_iommu_bank_data *bank; 1283 int i; 1284 1285 iommu_device_sysfs_remove(&data->iommu); 1286 iommu_device_unregister(&data->iommu); 1287 1288 list_del(&data->list); 1289 1290 if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) { 1291 device_link_remove(data->smicomm_dev, &pdev->dev); 1292 component_master_del(&pdev->dev, &mtk_iommu_com_ops); 1293 } else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA) && 1294 MTK_IOMMU_HAS_FLAG(data->plat_data, IFA_IOMMU_PCIE_SUPPORT)) { 1295 #ifdef CONFIG_PCI 1296 bus_set_iommu(&pci_bus_type, NULL); 1297 #endif 1298 } 1299 pm_runtime_disable(&pdev->dev); 1300 for (i = 0; i < data->plat_data->banks_num; i++) { 1301 bank = &data->bank[i]; 1302 if (!bank->m4u_dom) 1303 continue; 1304 devm_free_irq(&pdev->dev, bank->irq, bank); 1305 } 1306 return 0; 1307 } 1308 1309 static int __maybe_unused mtk_iommu_runtime_suspend(struct device *dev) 1310 { 1311 struct mtk_iommu_data *data = dev_get_drvdata(dev); 1312 struct mtk_iommu_suspend_reg *reg = &data->reg; 1313 void __iomem *base; 1314 int i = 0; 1315 1316 base = data->bank[i].base; 1317 reg->wr_len_ctrl = readl_relaxed(base + REG_MMU_WR_LEN_CTRL); 1318 reg->misc_ctrl = readl_relaxed(base + REG_MMU_MISC_CTRL); 1319 reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS); 1320 reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG); 1321 reg->vld_pa_rng = readl_relaxed(base + REG_MMU_VLD_PA_RNG); 1322 do { 1323 if (!data->plat_data->banks_enable[i]) 1324 continue; 1325 base = data->bank[i].base; 1326 reg->int_control[i] = readl_relaxed(base + REG_MMU_INT_CONTROL0); 1327 reg->int_main_control[i] = readl_relaxed(base + REG_MMU_INT_MAIN_CONTROL); 1328 reg->ivrp_paddr[i] = readl_relaxed(base + REG_MMU_IVRP_PADDR); 1329 } while (++i < data->plat_data->banks_num); 1330 clk_disable_unprepare(data->bclk); 1331 return 0; 1332 } 1333 1334 static int __maybe_unused mtk_iommu_runtime_resume(struct device *dev) 1335 { 1336 struct mtk_iommu_data *data = dev_get_drvdata(dev); 1337 struct mtk_iommu_suspend_reg *reg = &data->reg; 1338 struct mtk_iommu_domain *m4u_dom; 1339 void __iomem *base; 1340 int ret, i = 0; 1341 1342 ret = clk_prepare_enable(data->bclk); 1343 if (ret) { 1344 dev_err(data->dev, "Failed to enable clk(%d) in resume\n", ret); 1345 return ret; 1346 } 1347 1348 /* 1349 * Uppon first resume, only enable the clk and return, since the values of the 1350 * registers are not yet set. 1351 */ 1352 if (!reg->wr_len_ctrl) 1353 return 0; 1354 1355 base = data->bank[i].base; 1356 writel_relaxed(reg->wr_len_ctrl, base + REG_MMU_WR_LEN_CTRL); 1357 writel_relaxed(reg->misc_ctrl, base + REG_MMU_MISC_CTRL); 1358 writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS); 1359 writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG); 1360 writel_relaxed(reg->vld_pa_rng, base + REG_MMU_VLD_PA_RNG); 1361 do { 1362 m4u_dom = data->bank[i].m4u_dom; 1363 if (!data->plat_data->banks_enable[i] || !m4u_dom) 1364 continue; 1365 base = data->bank[i].base; 1366 writel_relaxed(reg->int_control[i], base + REG_MMU_INT_CONTROL0); 1367 writel_relaxed(reg->int_main_control[i], base + REG_MMU_INT_MAIN_CONTROL); 1368 writel_relaxed(reg->ivrp_paddr[i], base + REG_MMU_IVRP_PADDR); 1369 writel(m4u_dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK, 1370 base + REG_MMU_PT_BASE_ADDR); 1371 } while (++i < data->plat_data->banks_num); 1372 1373 /* 1374 * Users may allocate dma buffer before they call pm_runtime_get, 1375 * in which case it will lack the necessary tlb flush. 1376 * Thus, make sure to update the tlb after each PM resume. 1377 */ 1378 mtk_iommu_tlb_flush_all(data); 1379 return 0; 1380 } 1381 1382 static const struct dev_pm_ops mtk_iommu_pm_ops = { 1383 SET_RUNTIME_PM_OPS(mtk_iommu_runtime_suspend, mtk_iommu_runtime_resume, NULL) 1384 SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1385 pm_runtime_force_resume) 1386 }; 1387 1388 static const struct mtk_iommu_plat_data mt2712_data = { 1389 .m4u_plat = M4U_MT2712, 1390 .flags = HAS_4GB_MODE | HAS_BCLK | HAS_VLD_PA_RNG | SHARE_PGTABLE | 1391 MTK_IOMMU_TYPE_MM, 1392 .hw_list = &m4ulist, 1393 .inv_sel_reg = REG_MMU_INV_SEL_GEN1, 1394 .iova_region = single_domain, 1395 .banks_num = 1, 1396 .banks_enable = {true}, 1397 .iova_region_nr = ARRAY_SIZE(single_domain), 1398 .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}, {6}, {7}}, 1399 }; 1400 1401 static const struct mtk_iommu_plat_data mt6779_data = { 1402 .m4u_plat = M4U_MT6779, 1403 .flags = HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN | WR_THROT_EN | 1404 MTK_IOMMU_TYPE_MM, 1405 .inv_sel_reg = REG_MMU_INV_SEL_GEN2, 1406 .banks_num = 1, 1407 .banks_enable = {true}, 1408 .iova_region = single_domain, 1409 .iova_region_nr = ARRAY_SIZE(single_domain), 1410 .larbid_remap = {{0}, {1}, {2}, {3}, {5}, {7, 8}, {10}, {9}}, 1411 }; 1412 1413 static const struct mtk_iommu_plat_data mt8167_data = { 1414 .m4u_plat = M4U_MT8167, 1415 .flags = RESET_AXI | HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM, 1416 .inv_sel_reg = REG_MMU_INV_SEL_GEN1, 1417 .banks_num = 1, 1418 .banks_enable = {true}, 1419 .iova_region = single_domain, 1420 .iova_region_nr = ARRAY_SIZE(single_domain), 1421 .larbid_remap = {{0}, {1}, {2}}, /* Linear mapping. */ 1422 }; 1423 1424 static const struct mtk_iommu_plat_data mt8173_data = { 1425 .m4u_plat = M4U_MT8173, 1426 .flags = HAS_4GB_MODE | HAS_BCLK | RESET_AXI | 1427 HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM, 1428 .inv_sel_reg = REG_MMU_INV_SEL_GEN1, 1429 .banks_num = 1, 1430 .banks_enable = {true}, 1431 .iova_region = single_domain, 1432 .iova_region_nr = ARRAY_SIZE(single_domain), 1433 .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */ 1434 }; 1435 1436 static const struct mtk_iommu_plat_data mt8183_data = { 1437 .m4u_plat = M4U_MT8183, 1438 .flags = RESET_AXI | MTK_IOMMU_TYPE_MM, 1439 .inv_sel_reg = REG_MMU_INV_SEL_GEN1, 1440 .banks_num = 1, 1441 .banks_enable = {true}, 1442 .iova_region = single_domain, 1443 .iova_region_nr = ARRAY_SIZE(single_domain), 1444 .larbid_remap = {{0}, {4}, {5}, {6}, {7}, {2}, {3}, {1}}, 1445 }; 1446 1447 static const struct mtk_iommu_plat_data mt8186_data_mm = { 1448 .m4u_plat = M4U_MT8186, 1449 .flags = HAS_BCLK | HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN | 1450 WR_THROT_EN | IOVA_34_EN | MTK_IOMMU_TYPE_MM, 1451 .larbid_remap = {{0}, {1, MTK_INVALID_LARBID, 8}, {4}, {7}, {2}, {9, 11, 19, 20}, 1452 {MTK_INVALID_LARBID, 14, 16}, 1453 {MTK_INVALID_LARBID, 13, MTK_INVALID_LARBID, 17}}, 1454 .inv_sel_reg = REG_MMU_INV_SEL_GEN2, 1455 .banks_num = 1, 1456 .banks_enable = {true}, 1457 .iova_region = mt8192_multi_dom, 1458 .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom), 1459 }; 1460 1461 static const struct mtk_iommu_plat_data mt8192_data = { 1462 .m4u_plat = M4U_MT8192, 1463 .flags = HAS_BCLK | HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN | 1464 WR_THROT_EN | IOVA_34_EN | MTK_IOMMU_TYPE_MM, 1465 .inv_sel_reg = REG_MMU_INV_SEL_GEN2, 1466 .banks_num = 1, 1467 .banks_enable = {true}, 1468 .iova_region = mt8192_multi_dom, 1469 .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom), 1470 .larbid_remap = {{0}, {1}, {4, 5}, {7}, {2}, {9, 11, 19, 20}, 1471 {0, 14, 16}, {0, 13, 18, 17}}, 1472 }; 1473 1474 static const struct mtk_iommu_plat_data mt8195_data_infra = { 1475 .m4u_plat = M4U_MT8195, 1476 .flags = WR_THROT_EN | DCM_DISABLE | STD_AXI_MODE | PM_CLK_AO | 1477 MTK_IOMMU_TYPE_INFRA | IFA_IOMMU_PCIE_SUPPORT, 1478 .pericfg_comp_str = "mediatek,mt8195-pericfg_ao", 1479 .inv_sel_reg = REG_MMU_INV_SEL_GEN2, 1480 .banks_num = 5, 1481 .banks_enable = {true, false, false, false, true}, 1482 .banks_portmsk = {[0] = GENMASK(19, 16), /* PCIe */ 1483 [4] = GENMASK(31, 20), /* USB */ 1484 }, 1485 .iova_region = single_domain, 1486 .iova_region_nr = ARRAY_SIZE(single_domain), 1487 }; 1488 1489 static const struct mtk_iommu_plat_data mt8195_data_vdo = { 1490 .m4u_plat = M4U_MT8195, 1491 .flags = HAS_BCLK | HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN | 1492 WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE | MTK_IOMMU_TYPE_MM, 1493 .hw_list = &m4ulist, 1494 .inv_sel_reg = REG_MMU_INV_SEL_GEN2, 1495 .banks_num = 1, 1496 .banks_enable = {true}, 1497 .iova_region = mt8192_multi_dom, 1498 .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom), 1499 .larbid_remap = {{2, 0}, {21}, {24}, {7}, {19}, {9, 10, 11}, 1500 {13, 17, 15/* 17b */, 25}, {5}}, 1501 }; 1502 1503 static const struct mtk_iommu_plat_data mt8195_data_vpp = { 1504 .m4u_plat = M4U_MT8195, 1505 .flags = HAS_BCLK | HAS_SUB_COMM_3BITS | OUT_ORDER_WR_EN | 1506 WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE | MTK_IOMMU_TYPE_MM, 1507 .hw_list = &m4ulist, 1508 .inv_sel_reg = REG_MMU_INV_SEL_GEN2, 1509 .banks_num = 1, 1510 .banks_enable = {true}, 1511 .iova_region = mt8192_multi_dom, 1512 .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom), 1513 .larbid_remap = {{1}, {3}, 1514 {22, MTK_INVALID_LARBID, MTK_INVALID_LARBID, MTK_INVALID_LARBID, 23}, 1515 {8}, {20}, {12}, 1516 /* 16: 16a; 29: 16b; 30: CCUtop0; 31: CCUtop1 */ 1517 {14, 16, 29, 26, 30, 31, 18}, 1518 {4, MTK_INVALID_LARBID, MTK_INVALID_LARBID, MTK_INVALID_LARBID, 6}}, 1519 }; 1520 1521 static const struct of_device_id mtk_iommu_of_ids[] = { 1522 { .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data}, 1523 { .compatible = "mediatek,mt6779-m4u", .data = &mt6779_data}, 1524 { .compatible = "mediatek,mt8167-m4u", .data = &mt8167_data}, 1525 { .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data}, 1526 { .compatible = "mediatek,mt8183-m4u", .data = &mt8183_data}, 1527 { .compatible = "mediatek,mt8186-iommu-mm", .data = &mt8186_data_mm}, /* mm: m4u */ 1528 { .compatible = "mediatek,mt8192-m4u", .data = &mt8192_data}, 1529 { .compatible = "mediatek,mt8195-iommu-infra", .data = &mt8195_data_infra}, 1530 { .compatible = "mediatek,mt8195-iommu-vdo", .data = &mt8195_data_vdo}, 1531 { .compatible = "mediatek,mt8195-iommu-vpp", .data = &mt8195_data_vpp}, 1532 {} 1533 }; 1534 1535 static struct platform_driver mtk_iommu_driver = { 1536 .probe = mtk_iommu_probe, 1537 .remove = mtk_iommu_remove, 1538 .driver = { 1539 .name = "mtk-iommu", 1540 .of_match_table = mtk_iommu_of_ids, 1541 .pm = &mtk_iommu_pm_ops, 1542 } 1543 }; 1544 module_platform_driver(mtk_iommu_driver); 1545 1546 MODULE_DESCRIPTION("IOMMU API for MediaTek M4U implementations"); 1547 MODULE_LICENSE("GPL v2"); 1548