1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * IOMMU API for Renesas VMSA-compatible IPMMU 4 * Author: Laurent Pinchart <laurent.pinchart@ideasonboard.com> 5 * 6 * Copyright (C) 2014-2020 Renesas Electronics Corporation 7 */ 8 9 #include <linux/bitmap.h> 10 #include <linux/delay.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/err.h> 13 #include <linux/export.h> 14 #include <linux/init.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/iopoll.h> 18 #include <linux/io-pgtable.h> 19 #include <linux/iommu.h> 20 #include <linux/of.h> 21 #include <linux/of_platform.h> 22 #include <linux/pci.h> 23 #include <linux/platform_device.h> 24 #include <linux/sizes.h> 25 #include <linux/slab.h> 26 #include <linux/sys_soc.h> 27 28 #if defined(CONFIG_ARM) && !defined(CONFIG_IOMMU_DMA) 29 #include <asm/dma-iommu.h> 30 #else 31 #define arm_iommu_create_mapping(...) NULL 32 #define arm_iommu_attach_device(...) -ENODEV 33 #define arm_iommu_release_mapping(...) do {} while (0) 34 #endif 35 36 #define IPMMU_CTX_MAX 16U 37 #define IPMMU_CTX_INVALID -1 38 39 #define IPMMU_UTLB_MAX 64U 40 41 struct ipmmu_features { 42 bool use_ns_alias_offset; 43 bool has_cache_leaf_nodes; 44 unsigned int number_of_contexts; 45 unsigned int num_utlbs; 46 bool setup_imbuscr; 47 bool twobit_imttbcr_sl0; 48 bool reserved_context; 49 bool cache_snoop; 50 unsigned int ctx_offset_base; 51 unsigned int ctx_offset_stride; 52 unsigned int utlb_offset_base; 53 }; 54 55 struct ipmmu_vmsa_device { 56 struct device *dev; 57 void __iomem *base; 58 struct iommu_device iommu; 59 struct ipmmu_vmsa_device *root; 60 const struct ipmmu_features *features; 61 unsigned int num_ctx; 62 spinlock_t lock; /* Protects ctx and domains[] */ 63 DECLARE_BITMAP(ctx, IPMMU_CTX_MAX); 64 struct ipmmu_vmsa_domain *domains[IPMMU_CTX_MAX]; 65 s8 utlb_ctx[IPMMU_UTLB_MAX]; 66 67 struct dma_iommu_mapping *mapping; 68 }; 69 70 struct ipmmu_vmsa_domain { 71 struct ipmmu_vmsa_device *mmu; 72 struct iommu_domain io_domain; 73 74 struct io_pgtable_cfg cfg; 75 struct io_pgtable_ops *iop; 76 77 unsigned int context_id; 78 struct mutex mutex; /* Protects mappings */ 79 }; 80 81 static struct ipmmu_vmsa_domain *to_vmsa_domain(struct iommu_domain *dom) 82 { 83 return container_of(dom, struct ipmmu_vmsa_domain, io_domain); 84 } 85 86 static struct ipmmu_vmsa_device *to_ipmmu(struct device *dev) 87 { 88 return dev_iommu_priv_get(dev); 89 } 90 91 #define TLB_LOOP_TIMEOUT 100 /* 100us */ 92 93 /* ----------------------------------------------------------------------------- 94 * Registers Definition 95 */ 96 97 #define IM_NS_ALIAS_OFFSET 0x800 98 99 /* MMU "context" registers */ 100 #define IMCTR 0x0000 /* R-Car Gen2/3 */ 101 #define IMCTR_INTEN (1 << 2) /* R-Car Gen2/3 */ 102 #define IMCTR_FLUSH (1 << 1) /* R-Car Gen2/3 */ 103 #define IMCTR_MMUEN (1 << 0) /* R-Car Gen2/3 */ 104 105 #define IMTTBCR 0x0008 /* R-Car Gen2/3 */ 106 #define IMTTBCR_EAE (1 << 31) /* R-Car Gen2/3 */ 107 #define IMTTBCR_SH0_INNER_SHAREABLE (3 << 12) /* R-Car Gen2 only */ 108 #define IMTTBCR_ORGN0_WB_WA (1 << 10) /* R-Car Gen2 only */ 109 #define IMTTBCR_IRGN0_WB_WA (1 << 8) /* R-Car Gen2 only */ 110 #define IMTTBCR_SL0_TWOBIT_LVL_1 (2 << 6) /* R-Car Gen3 only */ 111 #define IMTTBCR_SL0_LVL_1 (1 << 4) /* R-Car Gen2 only */ 112 113 #define IMBUSCR 0x000c /* R-Car Gen2 only */ 114 #define IMBUSCR_DVM (1 << 2) /* R-Car Gen2 only */ 115 #define IMBUSCR_BUSSEL_MASK (3 << 0) /* R-Car Gen2 only */ 116 117 #define IMTTLBR0 0x0010 /* R-Car Gen2/3 */ 118 #define IMTTUBR0 0x0014 /* R-Car Gen2/3 */ 119 120 #define IMSTR 0x0020 /* R-Car Gen2/3 */ 121 #define IMSTR_MHIT (1 << 4) /* R-Car Gen2/3 */ 122 #define IMSTR_ABORT (1 << 2) /* R-Car Gen2/3 */ 123 #define IMSTR_PF (1 << 1) /* R-Car Gen2/3 */ 124 #define IMSTR_TF (1 << 0) /* R-Car Gen2/3 */ 125 126 #define IMMAIR0 0x0028 /* R-Car Gen2/3 */ 127 128 #define IMELAR 0x0030 /* R-Car Gen2/3, IMEAR on R-Car Gen2 */ 129 #define IMEUAR 0x0034 /* R-Car Gen3 only */ 130 131 /* uTLB registers */ 132 #define IMUCTR(n) ((n) < 32 ? IMUCTR0(n) : IMUCTR32(n)) 133 #define IMUCTR0(n) (0x0300 + ((n) * 16)) /* R-Car Gen2/3 */ 134 #define IMUCTR32(n) (0x0600 + (((n) - 32) * 16)) /* R-Car Gen3 only */ 135 #define IMUCTR_TTSEL_MMU(n) ((n) << 4) /* R-Car Gen2/3 */ 136 #define IMUCTR_FLUSH (1 << 1) /* R-Car Gen2/3 */ 137 #define IMUCTR_MMUEN (1 << 0) /* R-Car Gen2/3 */ 138 139 #define IMUASID(n) ((n) < 32 ? IMUASID0(n) : IMUASID32(n)) 140 #define IMUASID0(n) (0x0308 + ((n) * 16)) /* R-Car Gen2/3 */ 141 #define IMUASID32(n) (0x0608 + (((n) - 32) * 16)) /* R-Car Gen3 only */ 142 143 /* ----------------------------------------------------------------------------- 144 * Root device handling 145 */ 146 147 static struct platform_driver ipmmu_driver; 148 149 static bool ipmmu_is_root(struct ipmmu_vmsa_device *mmu) 150 { 151 return mmu->root == mmu; 152 } 153 154 static int __ipmmu_check_device(struct device *dev, void *data) 155 { 156 struct ipmmu_vmsa_device *mmu = dev_get_drvdata(dev); 157 struct ipmmu_vmsa_device **rootp = data; 158 159 if (ipmmu_is_root(mmu)) 160 *rootp = mmu; 161 162 return 0; 163 } 164 165 static struct ipmmu_vmsa_device *ipmmu_find_root(void) 166 { 167 struct ipmmu_vmsa_device *root = NULL; 168 169 return driver_for_each_device(&ipmmu_driver.driver, NULL, &root, 170 __ipmmu_check_device) == 0 ? root : NULL; 171 } 172 173 /* ----------------------------------------------------------------------------- 174 * Read/Write Access 175 */ 176 177 static u32 ipmmu_read(struct ipmmu_vmsa_device *mmu, unsigned int offset) 178 { 179 return ioread32(mmu->base + offset); 180 } 181 182 static void ipmmu_write(struct ipmmu_vmsa_device *mmu, unsigned int offset, 183 u32 data) 184 { 185 iowrite32(data, mmu->base + offset); 186 } 187 188 static unsigned int ipmmu_ctx_reg(struct ipmmu_vmsa_device *mmu, 189 unsigned int context_id, unsigned int reg) 190 { 191 unsigned int base = mmu->features->ctx_offset_base; 192 193 if (context_id > 7) 194 base += 0x800 - 8 * 0x40; 195 196 return base + context_id * mmu->features->ctx_offset_stride + reg; 197 } 198 199 static u32 ipmmu_ctx_read(struct ipmmu_vmsa_device *mmu, 200 unsigned int context_id, unsigned int reg) 201 { 202 return ipmmu_read(mmu, ipmmu_ctx_reg(mmu, context_id, reg)); 203 } 204 205 static void ipmmu_ctx_write(struct ipmmu_vmsa_device *mmu, 206 unsigned int context_id, unsigned int reg, u32 data) 207 { 208 ipmmu_write(mmu, ipmmu_ctx_reg(mmu, context_id, reg), data); 209 } 210 211 static u32 ipmmu_ctx_read_root(struct ipmmu_vmsa_domain *domain, 212 unsigned int reg) 213 { 214 return ipmmu_ctx_read(domain->mmu->root, domain->context_id, reg); 215 } 216 217 static void ipmmu_ctx_write_root(struct ipmmu_vmsa_domain *domain, 218 unsigned int reg, u32 data) 219 { 220 ipmmu_ctx_write(domain->mmu->root, domain->context_id, reg, data); 221 } 222 223 static void ipmmu_ctx_write_all(struct ipmmu_vmsa_domain *domain, 224 unsigned int reg, u32 data) 225 { 226 if (domain->mmu != domain->mmu->root) 227 ipmmu_ctx_write(domain->mmu, domain->context_id, reg, data); 228 229 ipmmu_ctx_write(domain->mmu->root, domain->context_id, reg, data); 230 } 231 232 static u32 ipmmu_utlb_reg(struct ipmmu_vmsa_device *mmu, unsigned int reg) 233 { 234 return mmu->features->utlb_offset_base + reg; 235 } 236 237 static void ipmmu_imuasid_write(struct ipmmu_vmsa_device *mmu, 238 unsigned int utlb, u32 data) 239 { 240 ipmmu_write(mmu, ipmmu_utlb_reg(mmu, IMUASID(utlb)), data); 241 } 242 243 static void ipmmu_imuctr_write(struct ipmmu_vmsa_device *mmu, 244 unsigned int utlb, u32 data) 245 { 246 ipmmu_write(mmu, ipmmu_utlb_reg(mmu, IMUCTR(utlb)), data); 247 } 248 249 /* ----------------------------------------------------------------------------- 250 * TLB and microTLB Management 251 */ 252 253 /* Wait for any pending TLB invalidations to complete */ 254 static void ipmmu_tlb_sync(struct ipmmu_vmsa_domain *domain) 255 { 256 u32 val; 257 258 if (read_poll_timeout_atomic(ipmmu_ctx_read_root, val, 259 !(val & IMCTR_FLUSH), 1, TLB_LOOP_TIMEOUT, 260 false, domain, IMCTR)) 261 dev_err_ratelimited(domain->mmu->dev, 262 "TLB sync timed out -- MMU may be deadlocked\n"); 263 } 264 265 static void ipmmu_tlb_invalidate(struct ipmmu_vmsa_domain *domain) 266 { 267 u32 reg; 268 269 reg = ipmmu_ctx_read_root(domain, IMCTR); 270 reg |= IMCTR_FLUSH; 271 ipmmu_ctx_write_all(domain, IMCTR, reg); 272 273 ipmmu_tlb_sync(domain); 274 } 275 276 /* 277 * Enable MMU translation for the microTLB. 278 */ 279 static void ipmmu_utlb_enable(struct ipmmu_vmsa_domain *domain, 280 unsigned int utlb) 281 { 282 struct ipmmu_vmsa_device *mmu = domain->mmu; 283 284 /* 285 * TODO: Reference-count the microTLB as several bus masters can be 286 * connected to the same microTLB. 287 */ 288 289 /* TODO: What should we set the ASID to ? */ 290 ipmmu_imuasid_write(mmu, utlb, 0); 291 /* TODO: Do we need to flush the microTLB ? */ 292 ipmmu_imuctr_write(mmu, utlb, IMUCTR_TTSEL_MMU(domain->context_id) | 293 IMUCTR_FLUSH | IMUCTR_MMUEN); 294 mmu->utlb_ctx[utlb] = domain->context_id; 295 } 296 297 /* 298 * Disable MMU translation for the microTLB. 299 */ 300 static void ipmmu_utlb_disable(struct ipmmu_vmsa_domain *domain, 301 unsigned int utlb) 302 { 303 struct ipmmu_vmsa_device *mmu = domain->mmu; 304 305 ipmmu_imuctr_write(mmu, utlb, 0); 306 mmu->utlb_ctx[utlb] = IPMMU_CTX_INVALID; 307 } 308 309 static void ipmmu_tlb_flush_all(void *cookie) 310 { 311 struct ipmmu_vmsa_domain *domain = cookie; 312 313 ipmmu_tlb_invalidate(domain); 314 } 315 316 static void ipmmu_tlb_flush(unsigned long iova, size_t size, 317 size_t granule, void *cookie) 318 { 319 ipmmu_tlb_flush_all(cookie); 320 } 321 322 static const struct iommu_flush_ops ipmmu_flush_ops = { 323 .tlb_flush_all = ipmmu_tlb_flush_all, 324 .tlb_flush_walk = ipmmu_tlb_flush, 325 }; 326 327 /* ----------------------------------------------------------------------------- 328 * Domain/Context Management 329 */ 330 331 static int ipmmu_domain_allocate_context(struct ipmmu_vmsa_device *mmu, 332 struct ipmmu_vmsa_domain *domain) 333 { 334 unsigned long flags; 335 int ret; 336 337 spin_lock_irqsave(&mmu->lock, flags); 338 339 ret = find_first_zero_bit(mmu->ctx, mmu->num_ctx); 340 if (ret != mmu->num_ctx) { 341 mmu->domains[ret] = domain; 342 set_bit(ret, mmu->ctx); 343 } else 344 ret = -EBUSY; 345 346 spin_unlock_irqrestore(&mmu->lock, flags); 347 348 return ret; 349 } 350 351 static void ipmmu_domain_free_context(struct ipmmu_vmsa_device *mmu, 352 unsigned int context_id) 353 { 354 unsigned long flags; 355 356 spin_lock_irqsave(&mmu->lock, flags); 357 358 clear_bit(context_id, mmu->ctx); 359 mmu->domains[context_id] = NULL; 360 361 spin_unlock_irqrestore(&mmu->lock, flags); 362 } 363 364 static void ipmmu_domain_setup_context(struct ipmmu_vmsa_domain *domain) 365 { 366 u64 ttbr; 367 u32 tmp; 368 369 /* TTBR0 */ 370 ttbr = domain->cfg.arm_lpae_s1_cfg.ttbr; 371 ipmmu_ctx_write_root(domain, IMTTLBR0, ttbr); 372 ipmmu_ctx_write_root(domain, IMTTUBR0, ttbr >> 32); 373 374 /* 375 * TTBCR 376 * We use long descriptors and allocate the whole 32-bit VA space to 377 * TTBR0. 378 */ 379 if (domain->mmu->features->twobit_imttbcr_sl0) 380 tmp = IMTTBCR_SL0_TWOBIT_LVL_1; 381 else 382 tmp = IMTTBCR_SL0_LVL_1; 383 384 if (domain->mmu->features->cache_snoop) 385 tmp |= IMTTBCR_SH0_INNER_SHAREABLE | IMTTBCR_ORGN0_WB_WA | 386 IMTTBCR_IRGN0_WB_WA; 387 388 ipmmu_ctx_write_root(domain, IMTTBCR, IMTTBCR_EAE | tmp); 389 390 /* MAIR0 */ 391 ipmmu_ctx_write_root(domain, IMMAIR0, 392 domain->cfg.arm_lpae_s1_cfg.mair); 393 394 /* IMBUSCR */ 395 if (domain->mmu->features->setup_imbuscr) 396 ipmmu_ctx_write_root(domain, IMBUSCR, 397 ipmmu_ctx_read_root(domain, IMBUSCR) & 398 ~(IMBUSCR_DVM | IMBUSCR_BUSSEL_MASK)); 399 400 /* 401 * IMSTR 402 * Clear all interrupt flags. 403 */ 404 ipmmu_ctx_write_root(domain, IMSTR, ipmmu_ctx_read_root(domain, IMSTR)); 405 406 /* 407 * IMCTR 408 * Enable the MMU and interrupt generation. The long-descriptor 409 * translation table format doesn't use TEX remapping. Don't enable AF 410 * software management as we have no use for it. Flush the TLB as 411 * required when modifying the context registers. 412 */ 413 ipmmu_ctx_write_all(domain, IMCTR, 414 IMCTR_INTEN | IMCTR_FLUSH | IMCTR_MMUEN); 415 } 416 417 static int ipmmu_domain_init_context(struct ipmmu_vmsa_domain *domain) 418 { 419 int ret; 420 421 /* 422 * Allocate the page table operations. 423 * 424 * VMSA states in section B3.6.3 "Control of Secure or Non-secure memory 425 * access, Long-descriptor format" that the NStable bit being set in a 426 * table descriptor will result in the NStable and NS bits of all child 427 * entries being ignored and considered as being set. The IPMMU seems 428 * not to comply with this, as it generates a secure access page fault 429 * if any of the NStable and NS bits isn't set when running in 430 * non-secure mode. 431 */ 432 domain->cfg.quirks = IO_PGTABLE_QUIRK_ARM_NS; 433 domain->cfg.pgsize_bitmap = domain->io_domain.pgsize_bitmap; 434 domain->cfg.ias = 32; 435 domain->cfg.oas = 40; 436 domain->cfg.tlb = &ipmmu_flush_ops; 437 domain->io_domain.geometry.aperture_end = DMA_BIT_MASK(32); 438 domain->io_domain.geometry.force_aperture = true; 439 /* 440 * TODO: Add support for coherent walk through CCI with DVM and remove 441 * cache handling. For now, delegate it to the io-pgtable code. 442 */ 443 domain->cfg.coherent_walk = false; 444 domain->cfg.iommu_dev = domain->mmu->root->dev; 445 446 /* 447 * Find an unused context. 448 */ 449 ret = ipmmu_domain_allocate_context(domain->mmu->root, domain); 450 if (ret < 0) 451 return ret; 452 453 domain->context_id = ret; 454 455 domain->iop = alloc_io_pgtable_ops(ARM_32_LPAE_S1, &domain->cfg, 456 domain); 457 if (!domain->iop) { 458 ipmmu_domain_free_context(domain->mmu->root, 459 domain->context_id); 460 return -EINVAL; 461 } 462 463 ipmmu_domain_setup_context(domain); 464 return 0; 465 } 466 467 static void ipmmu_domain_destroy_context(struct ipmmu_vmsa_domain *domain) 468 { 469 if (!domain->mmu) 470 return; 471 472 /* 473 * Disable the context. Flush the TLB as required when modifying the 474 * context registers. 475 * 476 * TODO: Is TLB flush really needed ? 477 */ 478 ipmmu_ctx_write_all(domain, IMCTR, IMCTR_FLUSH); 479 ipmmu_tlb_sync(domain); 480 ipmmu_domain_free_context(domain->mmu->root, domain->context_id); 481 } 482 483 /* ----------------------------------------------------------------------------- 484 * Fault Handling 485 */ 486 487 static irqreturn_t ipmmu_domain_irq(struct ipmmu_vmsa_domain *domain) 488 { 489 const u32 err_mask = IMSTR_MHIT | IMSTR_ABORT | IMSTR_PF | IMSTR_TF; 490 struct ipmmu_vmsa_device *mmu = domain->mmu; 491 unsigned long iova; 492 u32 status; 493 494 status = ipmmu_ctx_read_root(domain, IMSTR); 495 if (!(status & err_mask)) 496 return IRQ_NONE; 497 498 iova = ipmmu_ctx_read_root(domain, IMELAR); 499 if (IS_ENABLED(CONFIG_64BIT)) 500 iova |= (u64)ipmmu_ctx_read_root(domain, IMEUAR) << 32; 501 502 /* 503 * Clear the error status flags. Unlike traditional interrupt flag 504 * registers that must be cleared by writing 1, this status register 505 * seems to require 0. The error address register must be read before, 506 * otherwise its value will be 0. 507 */ 508 ipmmu_ctx_write_root(domain, IMSTR, 0); 509 510 /* Log fatal errors. */ 511 if (status & IMSTR_MHIT) 512 dev_err_ratelimited(mmu->dev, "Multiple TLB hits @0x%lx\n", 513 iova); 514 if (status & IMSTR_ABORT) 515 dev_err_ratelimited(mmu->dev, "Page Table Walk Abort @0x%lx\n", 516 iova); 517 518 if (!(status & (IMSTR_PF | IMSTR_TF))) 519 return IRQ_NONE; 520 521 /* 522 * Try to handle page faults and translation faults. 523 * 524 * TODO: We need to look up the faulty device based on the I/O VA. Use 525 * the IOMMU device for now. 526 */ 527 if (!report_iommu_fault(&domain->io_domain, mmu->dev, iova, 0)) 528 return IRQ_HANDLED; 529 530 dev_err_ratelimited(mmu->dev, 531 "Unhandled fault: status 0x%08x iova 0x%lx\n", 532 status, iova); 533 534 return IRQ_HANDLED; 535 } 536 537 static irqreturn_t ipmmu_irq(int irq, void *dev) 538 { 539 struct ipmmu_vmsa_device *mmu = dev; 540 irqreturn_t status = IRQ_NONE; 541 unsigned int i; 542 unsigned long flags; 543 544 spin_lock_irqsave(&mmu->lock, flags); 545 546 /* 547 * Check interrupts for all active contexts. 548 */ 549 for (i = 0; i < mmu->num_ctx; i++) { 550 if (!mmu->domains[i]) 551 continue; 552 if (ipmmu_domain_irq(mmu->domains[i]) == IRQ_HANDLED) 553 status = IRQ_HANDLED; 554 } 555 556 spin_unlock_irqrestore(&mmu->lock, flags); 557 558 return status; 559 } 560 561 /* ----------------------------------------------------------------------------- 562 * IOMMU Operations 563 */ 564 565 static struct iommu_domain *ipmmu_domain_alloc_paging(struct device *dev) 566 { 567 struct ipmmu_vmsa_domain *domain; 568 569 domain = kzalloc(sizeof(*domain), GFP_KERNEL); 570 if (!domain) 571 return NULL; 572 573 mutex_init(&domain->mutex); 574 domain->io_domain.pgsize_bitmap = SZ_1G | SZ_2M | SZ_4K; 575 576 return &domain->io_domain; 577 } 578 579 static void ipmmu_domain_free(struct iommu_domain *io_domain) 580 { 581 struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain); 582 583 /* 584 * Free the domain resources. We assume that all devices have already 585 * been detached. 586 */ 587 ipmmu_domain_destroy_context(domain); 588 free_io_pgtable_ops(domain->iop); 589 kfree(domain); 590 } 591 592 static int ipmmu_attach_device(struct iommu_domain *io_domain, 593 struct device *dev, struct iommu_domain *old) 594 { 595 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 596 struct ipmmu_vmsa_device *mmu = to_ipmmu(dev); 597 struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain); 598 unsigned int i; 599 int ret = 0; 600 601 if (!mmu) { 602 dev_err(dev, "Cannot attach to IPMMU\n"); 603 return -ENXIO; 604 } 605 606 mutex_lock(&domain->mutex); 607 608 if (!domain->mmu) { 609 /* The domain hasn't been used yet, initialize it. */ 610 domain->mmu = mmu; 611 ret = ipmmu_domain_init_context(domain); 612 if (ret < 0) { 613 dev_err(dev, "Unable to initialize IPMMU context\n"); 614 domain->mmu = NULL; 615 } else { 616 dev_info(dev, "Using IPMMU context %u\n", 617 domain->context_id); 618 } 619 } else if (domain->mmu != mmu) { 620 /* 621 * Something is wrong, we can't attach two devices using 622 * different IOMMUs to the same domain. 623 */ 624 ret = -EINVAL; 625 } else 626 dev_info(dev, "Reusing IPMMU context %u\n", domain->context_id); 627 628 mutex_unlock(&domain->mutex); 629 630 if (ret < 0) 631 return ret; 632 633 for (i = 0; i < fwspec->num_ids; ++i) 634 ipmmu_utlb_enable(domain, fwspec->ids[i]); 635 636 return 0; 637 } 638 639 static int ipmmu_iommu_identity_attach(struct iommu_domain *identity_domain, 640 struct device *dev, 641 struct iommu_domain *old) 642 { 643 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 644 struct ipmmu_vmsa_domain *domain; 645 unsigned int i; 646 647 if (old == identity_domain || !old) 648 return 0; 649 650 domain = to_vmsa_domain(old); 651 for (i = 0; i < fwspec->num_ids; ++i) 652 ipmmu_utlb_disable(domain, fwspec->ids[i]); 653 654 /* 655 * TODO: Optimize by disabling the context when no device is attached. 656 */ 657 return 0; 658 } 659 660 static struct iommu_domain_ops ipmmu_iommu_identity_ops = { 661 .attach_dev = ipmmu_iommu_identity_attach, 662 }; 663 664 static struct iommu_domain ipmmu_iommu_identity_domain = { 665 .type = IOMMU_DOMAIN_IDENTITY, 666 .ops = &ipmmu_iommu_identity_ops, 667 }; 668 669 static int ipmmu_map(struct iommu_domain *io_domain, unsigned long iova, 670 phys_addr_t paddr, size_t pgsize, size_t pgcount, 671 int prot, gfp_t gfp, size_t *mapped) 672 { 673 struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain); 674 675 return domain->iop->map_pages(domain->iop, iova, paddr, pgsize, pgcount, 676 prot, gfp, mapped); 677 } 678 679 static size_t ipmmu_unmap(struct iommu_domain *io_domain, unsigned long iova, 680 size_t pgsize, size_t pgcount, 681 struct iommu_iotlb_gather *gather) 682 { 683 struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain); 684 685 return domain->iop->unmap_pages(domain->iop, iova, pgsize, pgcount, gather); 686 } 687 688 static void ipmmu_flush_iotlb_all(struct iommu_domain *io_domain) 689 { 690 struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain); 691 692 if (domain->mmu) 693 ipmmu_tlb_flush_all(domain); 694 } 695 696 static void ipmmu_iotlb_sync(struct iommu_domain *io_domain, 697 struct iommu_iotlb_gather *gather) 698 { 699 ipmmu_flush_iotlb_all(io_domain); 700 } 701 702 static phys_addr_t ipmmu_iova_to_phys(struct iommu_domain *io_domain, 703 dma_addr_t iova) 704 { 705 struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain); 706 707 /* TODO: Is locking needed ? */ 708 709 return domain->iop->iova_to_phys(domain->iop, iova); 710 } 711 712 static int ipmmu_init_platform_device(struct device *dev, 713 const struct of_phandle_args *args) 714 { 715 struct platform_device *ipmmu_pdev; 716 717 ipmmu_pdev = of_find_device_by_node(args->np); 718 if (!ipmmu_pdev) 719 return -ENODEV; 720 721 dev_iommu_priv_set(dev, platform_get_drvdata(ipmmu_pdev)); 722 723 put_device(&ipmmu_pdev->dev); 724 725 return 0; 726 } 727 728 static const struct soc_device_attribute soc_needs_opt_in[] = { 729 { .family = "R-Car Gen3", }, 730 { .family = "R-Car Gen4", }, 731 { .family = "RZ/G2", }, 732 { /* sentinel */ } 733 }; 734 735 static const struct soc_device_attribute soc_denylist[] = { 736 { .soc_id = "r8a774a1", }, 737 { .soc_id = "r8a7795", .revision = "ES2.*" }, 738 { .soc_id = "r8a7796", }, 739 { /* sentinel */ } 740 }; 741 742 static const char * const devices_allowlist[] = { 743 "ee100000.mmc", 744 "ee120000.mmc", 745 "ee140000.mmc", 746 "ee160000.mmc" 747 }; 748 749 static bool ipmmu_device_is_allowed(struct device *dev) 750 { 751 unsigned int i; 752 753 /* 754 * R-Car Gen3/4 and RZ/G2 use the allow list to opt-in devices. 755 * For Other SoCs, this returns true anyway. 756 */ 757 if (!soc_device_match(soc_needs_opt_in)) 758 return true; 759 760 /* Check whether this SoC can use the IPMMU correctly or not */ 761 if (soc_device_match(soc_denylist)) 762 return false; 763 764 /* Check whether this device is a PCI device */ 765 if (dev_is_pci(dev)) 766 return true; 767 768 /* Check whether this device can work with the IPMMU */ 769 for (i = 0; i < ARRAY_SIZE(devices_allowlist); i++) { 770 if (!strcmp(dev_name(dev), devices_allowlist[i])) 771 return true; 772 } 773 774 /* Otherwise, do not allow use of IPMMU */ 775 return false; 776 } 777 778 static int ipmmu_of_xlate(struct device *dev, 779 const struct of_phandle_args *spec) 780 { 781 if (!ipmmu_device_is_allowed(dev)) 782 return -ENODEV; 783 784 iommu_fwspec_add_ids(dev, spec->args, 1); 785 786 /* Initialize once - xlate() will call multiple times */ 787 if (to_ipmmu(dev)) 788 return 0; 789 790 return ipmmu_init_platform_device(dev, spec); 791 } 792 793 static int ipmmu_init_arm_mapping(struct device *dev) 794 { 795 struct ipmmu_vmsa_device *mmu = to_ipmmu(dev); 796 int ret; 797 798 /* 799 * Create the ARM mapping, used by the ARM DMA mapping core to allocate 800 * VAs. This will allocate a corresponding IOMMU domain. 801 * 802 * TODO: 803 * - Create one mapping per context (TLB). 804 * - Make the mapping size configurable ? We currently use a 2GB mapping 805 * at a 1GB offset to ensure that NULL VAs will fault. 806 */ 807 if (!mmu->mapping) { 808 struct dma_iommu_mapping *mapping; 809 810 mapping = arm_iommu_create_mapping(dev, SZ_1G, SZ_2G); 811 if (IS_ERR(mapping)) { 812 dev_err(mmu->dev, "failed to create ARM IOMMU mapping\n"); 813 ret = PTR_ERR(mapping); 814 goto error; 815 } 816 817 mmu->mapping = mapping; 818 } 819 820 /* Attach the ARM VA mapping to the device. */ 821 ret = arm_iommu_attach_device(dev, mmu->mapping); 822 if (ret < 0) { 823 dev_err(dev, "Failed to attach device to VA mapping\n"); 824 goto error; 825 } 826 827 return 0; 828 829 error: 830 if (mmu->mapping) 831 arm_iommu_release_mapping(mmu->mapping); 832 833 return ret; 834 } 835 836 static struct iommu_device *ipmmu_probe_device(struct device *dev) 837 { 838 struct ipmmu_vmsa_device *mmu = to_ipmmu(dev); 839 840 /* 841 * Only let through devices that have been verified in xlate() 842 */ 843 if (!mmu) 844 return ERR_PTR(-ENODEV); 845 846 return &mmu->iommu; 847 } 848 849 static void ipmmu_probe_finalize(struct device *dev) 850 { 851 int ret = 0; 852 853 if (IS_ENABLED(CONFIG_ARM) && !IS_ENABLED(CONFIG_IOMMU_DMA)) 854 ret = ipmmu_init_arm_mapping(dev); 855 856 if (ret) 857 dev_err(dev, "Can't create IOMMU mapping - DMA-OPS will not work\n"); 858 } 859 860 static void ipmmu_release_device(struct device *dev) 861 { 862 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 863 struct ipmmu_vmsa_device *mmu = to_ipmmu(dev); 864 unsigned int i; 865 866 for (i = 0; i < fwspec->num_ids; ++i) { 867 unsigned int utlb = fwspec->ids[i]; 868 869 ipmmu_imuctr_write(mmu, utlb, 0); 870 mmu->utlb_ctx[utlb] = IPMMU_CTX_INVALID; 871 } 872 873 arm_iommu_release_mapping(mmu->mapping); 874 } 875 876 static const struct iommu_ops ipmmu_ops = { 877 .identity_domain = &ipmmu_iommu_identity_domain, 878 .domain_alloc_paging = ipmmu_domain_alloc_paging, 879 .probe_device = ipmmu_probe_device, 880 .release_device = ipmmu_release_device, 881 .probe_finalize = ipmmu_probe_finalize, 882 /* 883 * FIXME: The device grouping is a fixed property of the hardware's 884 * ability to isolate and control DMA, it should not depend on kconfig. 885 */ 886 .device_group = IS_ENABLED(CONFIG_ARM) && !IS_ENABLED(CONFIG_IOMMU_DMA) 887 ? generic_device_group : generic_single_device_group, 888 .of_xlate = ipmmu_of_xlate, 889 .default_domain_ops = &(const struct iommu_domain_ops) { 890 .attach_dev = ipmmu_attach_device, 891 .map_pages = ipmmu_map, 892 .unmap_pages = ipmmu_unmap, 893 .flush_iotlb_all = ipmmu_flush_iotlb_all, 894 .iotlb_sync = ipmmu_iotlb_sync, 895 .iova_to_phys = ipmmu_iova_to_phys, 896 .free = ipmmu_domain_free, 897 } 898 }; 899 900 /* ----------------------------------------------------------------------------- 901 * Probe/remove and init 902 */ 903 904 static void ipmmu_device_reset(struct ipmmu_vmsa_device *mmu) 905 { 906 unsigned int i; 907 908 /* Disable all contexts. */ 909 for (i = 0; i < mmu->num_ctx; ++i) 910 ipmmu_ctx_write(mmu, i, IMCTR, 0); 911 } 912 913 static const struct ipmmu_features ipmmu_features_default = { 914 .use_ns_alias_offset = true, 915 .has_cache_leaf_nodes = false, 916 .number_of_contexts = 1, /* software only tested with one context */ 917 .num_utlbs = 32, 918 .setup_imbuscr = true, 919 .twobit_imttbcr_sl0 = false, 920 .reserved_context = false, 921 .cache_snoop = true, 922 .ctx_offset_base = 0, 923 .ctx_offset_stride = 0x40, 924 .utlb_offset_base = 0, 925 }; 926 927 static const struct ipmmu_features ipmmu_features_rcar_gen3 = { 928 .use_ns_alias_offset = false, 929 .has_cache_leaf_nodes = true, 930 .number_of_contexts = 8, 931 .num_utlbs = 48, 932 .setup_imbuscr = false, 933 .twobit_imttbcr_sl0 = true, 934 .reserved_context = true, 935 .cache_snoop = false, 936 .ctx_offset_base = 0, 937 .ctx_offset_stride = 0x40, 938 .utlb_offset_base = 0, 939 }; 940 941 static const struct ipmmu_features ipmmu_features_rcar_gen4 = { 942 .use_ns_alias_offset = false, 943 .has_cache_leaf_nodes = true, 944 .number_of_contexts = 16, 945 .num_utlbs = 64, 946 .setup_imbuscr = false, 947 .twobit_imttbcr_sl0 = true, 948 .reserved_context = true, 949 .cache_snoop = false, 950 .ctx_offset_base = 0x10000, 951 .ctx_offset_stride = 0x1040, 952 .utlb_offset_base = 0x3000, 953 }; 954 955 static const struct of_device_id ipmmu_of_ids[] = { 956 { 957 .compatible = "renesas,ipmmu-vmsa", 958 .data = &ipmmu_features_default, 959 }, { 960 .compatible = "renesas,ipmmu-r8a774a1", 961 .data = &ipmmu_features_rcar_gen3, 962 }, { 963 .compatible = "renesas,ipmmu-r8a774b1", 964 .data = &ipmmu_features_rcar_gen3, 965 }, { 966 .compatible = "renesas,ipmmu-r8a774c0", 967 .data = &ipmmu_features_rcar_gen3, 968 }, { 969 .compatible = "renesas,ipmmu-r8a774e1", 970 .data = &ipmmu_features_rcar_gen3, 971 }, { 972 .compatible = "renesas,ipmmu-r8a7795", 973 .data = &ipmmu_features_rcar_gen3, 974 }, { 975 .compatible = "renesas,ipmmu-r8a7796", 976 .data = &ipmmu_features_rcar_gen3, 977 }, { 978 .compatible = "renesas,ipmmu-r8a77961", 979 .data = &ipmmu_features_rcar_gen3, 980 }, { 981 .compatible = "renesas,ipmmu-r8a77965", 982 .data = &ipmmu_features_rcar_gen3, 983 }, { 984 .compatible = "renesas,ipmmu-r8a77970", 985 .data = &ipmmu_features_rcar_gen3, 986 }, { 987 .compatible = "renesas,ipmmu-r8a77980", 988 .data = &ipmmu_features_rcar_gen3, 989 }, { 990 .compatible = "renesas,ipmmu-r8a77990", 991 .data = &ipmmu_features_rcar_gen3, 992 }, { 993 .compatible = "renesas,ipmmu-r8a77995", 994 .data = &ipmmu_features_rcar_gen3, 995 }, { 996 .compatible = "renesas,ipmmu-r8a779a0", 997 .data = &ipmmu_features_rcar_gen4, 998 }, { 999 .compatible = "renesas,rcar-gen4-ipmmu-vmsa", 1000 .data = &ipmmu_features_rcar_gen4, 1001 }, { 1002 /* Terminator */ 1003 }, 1004 }; 1005 1006 static int ipmmu_probe(struct platform_device *pdev) 1007 { 1008 struct ipmmu_vmsa_device *mmu; 1009 int irq; 1010 int ret; 1011 1012 mmu = devm_kzalloc(&pdev->dev, sizeof(*mmu), GFP_KERNEL); 1013 if (!mmu) { 1014 dev_err(&pdev->dev, "cannot allocate device data\n"); 1015 return -ENOMEM; 1016 } 1017 1018 mmu->dev = &pdev->dev; 1019 spin_lock_init(&mmu->lock); 1020 bitmap_zero(mmu->ctx, IPMMU_CTX_MAX); 1021 mmu->features = of_device_get_match_data(&pdev->dev); 1022 memset(mmu->utlb_ctx, IPMMU_CTX_INVALID, mmu->features->num_utlbs); 1023 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40)); 1024 if (ret) 1025 return ret; 1026 1027 /* Map I/O memory and request IRQ. */ 1028 mmu->base = devm_platform_ioremap_resource(pdev, 0); 1029 if (IS_ERR(mmu->base)) 1030 return PTR_ERR(mmu->base); 1031 1032 /* 1033 * The IPMMU has two register banks, for secure and non-secure modes. 1034 * The bank mapped at the beginning of the IPMMU address space 1035 * corresponds to the running mode of the CPU. When running in secure 1036 * mode the non-secure register bank is also available at an offset. 1037 * 1038 * Secure mode operation isn't clearly documented and is thus currently 1039 * not implemented in the driver. Furthermore, preliminary tests of 1040 * non-secure operation with the main register bank were not successful. 1041 * Offset the registers base unconditionally to point to the non-secure 1042 * alias space for now. 1043 */ 1044 if (mmu->features->use_ns_alias_offset) 1045 mmu->base += IM_NS_ALIAS_OFFSET; 1046 1047 mmu->num_ctx = min(IPMMU_CTX_MAX, mmu->features->number_of_contexts); 1048 1049 /* 1050 * Determine if this IPMMU instance is a root device by checking for 1051 * the lack of has_cache_leaf_nodes flag or renesas,ipmmu-main property. 1052 */ 1053 if (!mmu->features->has_cache_leaf_nodes || 1054 !of_property_present(pdev->dev.of_node, "renesas,ipmmu-main")) 1055 mmu->root = mmu; 1056 else 1057 mmu->root = ipmmu_find_root(); 1058 1059 /* 1060 * Wait until the root device has been registered for sure. 1061 */ 1062 if (!mmu->root) 1063 return -EPROBE_DEFER; 1064 1065 /* Root devices have mandatory IRQs */ 1066 if (ipmmu_is_root(mmu)) { 1067 irq = platform_get_irq(pdev, 0); 1068 if (irq < 0) 1069 return irq; 1070 1071 ret = devm_request_irq(&pdev->dev, irq, ipmmu_irq, 0, 1072 dev_name(&pdev->dev), mmu); 1073 if (ret < 0) { 1074 dev_err(&pdev->dev, "failed to request IRQ %d\n", irq); 1075 return ret; 1076 } 1077 1078 ipmmu_device_reset(mmu); 1079 1080 if (mmu->features->reserved_context) { 1081 dev_info(&pdev->dev, "IPMMU context 0 is reserved\n"); 1082 set_bit(0, mmu->ctx); 1083 } 1084 } 1085 1086 platform_set_drvdata(pdev, mmu); 1087 /* 1088 * Register the IPMMU to the IOMMU subsystem in the following cases: 1089 * - R-Car Gen2 IPMMU (all devices registered) 1090 * - R-Car Gen3 IPMMU (leaf devices only - skip root IPMMU-MM device) 1091 */ 1092 if (mmu->features->has_cache_leaf_nodes && ipmmu_is_root(mmu)) 1093 return 0; 1094 1095 ret = iommu_device_sysfs_add(&mmu->iommu, &pdev->dev, NULL, "%s", 1096 dev_name(&pdev->dev)); 1097 if (ret) 1098 return ret; 1099 1100 ret = iommu_device_register(&mmu->iommu, &ipmmu_ops, &pdev->dev); 1101 if (ret) 1102 iommu_device_sysfs_remove(&mmu->iommu); 1103 1104 return ret; 1105 } 1106 1107 static void ipmmu_remove(struct platform_device *pdev) 1108 { 1109 struct ipmmu_vmsa_device *mmu = platform_get_drvdata(pdev); 1110 1111 iommu_device_sysfs_remove(&mmu->iommu); 1112 iommu_device_unregister(&mmu->iommu); 1113 1114 arm_iommu_release_mapping(mmu->mapping); 1115 1116 ipmmu_device_reset(mmu); 1117 } 1118 1119 static int ipmmu_resume_noirq(struct device *dev) 1120 { 1121 struct ipmmu_vmsa_device *mmu = dev_get_drvdata(dev); 1122 unsigned int i; 1123 1124 /* Reset root MMU and restore contexts */ 1125 if (ipmmu_is_root(mmu)) { 1126 ipmmu_device_reset(mmu); 1127 1128 for (i = 0; i < mmu->num_ctx; i++) { 1129 if (!mmu->domains[i]) 1130 continue; 1131 1132 ipmmu_domain_setup_context(mmu->domains[i]); 1133 } 1134 } 1135 1136 /* Re-enable active micro-TLBs */ 1137 for (i = 0; i < mmu->features->num_utlbs; i++) { 1138 if (mmu->utlb_ctx[i] == IPMMU_CTX_INVALID) 1139 continue; 1140 1141 ipmmu_utlb_enable(mmu->root->domains[mmu->utlb_ctx[i]], i); 1142 } 1143 1144 return 0; 1145 } 1146 1147 static const struct dev_pm_ops ipmmu_pm = { 1148 NOIRQ_SYSTEM_SLEEP_PM_OPS(NULL, ipmmu_resume_noirq) 1149 }; 1150 1151 static struct platform_driver ipmmu_driver = { 1152 .driver = { 1153 .name = "ipmmu-vmsa", 1154 .of_match_table = ipmmu_of_ids, 1155 .pm = pm_sleep_ptr(&ipmmu_pm), 1156 }, 1157 .probe = ipmmu_probe, 1158 .remove = ipmmu_remove, 1159 }; 1160 builtin_platform_driver(ipmmu_driver); 1161