1 /* 2 * CPU-agnostic ARM page table allocator. 3 * 4 * ARMv7 Short-descriptor format, supporting 5 * - Basic memory attributes 6 * - Simplified access permissions (AP[2:1] model) 7 * - Backwards-compatible TEX remap 8 * - Large pages/supersections (if indicated by the caller) 9 * 10 * Not supporting: 11 * - Legacy access permissions (AP[2:0] model) 12 * 13 * Almost certainly never supporting: 14 * - PXN 15 * - Domains 16 * 17 * This program is free software; you can redistribute it and/or modify 18 * it under the terms of the GNU General Public License version 2 as 19 * published by the Free Software Foundation. 20 * 21 * This program is distributed in the hope that it will be useful, 22 * but WITHOUT ANY WARRANTY; without even the implied warranty of 23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 * GNU General Public License for more details. 25 * 26 * You should have received a copy of the GNU General Public License 27 * along with this program. If not, see <http://www.gnu.org/licenses/>. 28 * 29 * Copyright (C) 2014-2015 ARM Limited 30 * Copyright (c) 2014-2015 MediaTek Inc. 31 */ 32 33 #define pr_fmt(fmt) "arm-v7s io-pgtable: " fmt 34 35 #include <linux/dma-mapping.h> 36 #include <linux/gfp.h> 37 #include <linux/iommu.h> 38 #include <linux/kernel.h> 39 #include <linux/kmemleak.h> 40 #include <linux/sizes.h> 41 #include <linux/slab.h> 42 #include <linux/types.h> 43 44 #include <asm/barrier.h> 45 46 #include "io-pgtable.h" 47 48 /* Struct accessors */ 49 #define io_pgtable_to_data(x) \ 50 container_of((x), struct arm_v7s_io_pgtable, iop) 51 52 #define io_pgtable_ops_to_data(x) \ 53 io_pgtable_to_data(io_pgtable_ops_to_pgtable(x)) 54 55 /* 56 * We have 32 bits total; 12 bits resolved at level 1, 8 bits at level 2, 57 * and 12 bits in a page. With some carefully-chosen coefficients we can 58 * hide the ugly inconsistencies behind these macros and at least let the 59 * rest of the code pretend to be somewhat sane. 60 */ 61 #define ARM_V7S_ADDR_BITS 32 62 #define _ARM_V7S_LVL_BITS(lvl) (16 - (lvl) * 4) 63 #define ARM_V7S_LVL_SHIFT(lvl) (ARM_V7S_ADDR_BITS - (4 + 8 * (lvl))) 64 #define ARM_V7S_TABLE_SHIFT 10 65 66 #define ARM_V7S_PTES_PER_LVL(lvl) (1 << _ARM_V7S_LVL_BITS(lvl)) 67 #define ARM_V7S_TABLE_SIZE(lvl) \ 68 (ARM_V7S_PTES_PER_LVL(lvl) * sizeof(arm_v7s_iopte)) 69 70 #define ARM_V7S_BLOCK_SIZE(lvl) (1UL << ARM_V7S_LVL_SHIFT(lvl)) 71 #define ARM_V7S_LVL_MASK(lvl) ((u32)(~0U << ARM_V7S_LVL_SHIFT(lvl))) 72 #define ARM_V7S_TABLE_MASK ((u32)(~0U << ARM_V7S_TABLE_SHIFT)) 73 #define _ARM_V7S_IDX_MASK(lvl) (ARM_V7S_PTES_PER_LVL(lvl) - 1) 74 #define ARM_V7S_LVL_IDX(addr, lvl) ({ \ 75 int _l = lvl; \ 76 ((u32)(addr) >> ARM_V7S_LVL_SHIFT(_l)) & _ARM_V7S_IDX_MASK(_l); \ 77 }) 78 79 /* 80 * Large page/supersection entries are effectively a block of 16 page/section 81 * entries, along the lines of the LPAE contiguous hint, but all with the 82 * same output address. For want of a better common name we'll call them 83 * "contiguous" versions of their respective page/section entries here, but 84 * noting the distinction (WRT to TLB maintenance) that they represent *one* 85 * entry repeated 16 times, not 16 separate entries (as in the LPAE case). 86 */ 87 #define ARM_V7S_CONT_PAGES 16 88 89 /* PTE type bits: these are all mixed up with XN/PXN bits in most cases */ 90 #define ARM_V7S_PTE_TYPE_TABLE 0x1 91 #define ARM_V7S_PTE_TYPE_PAGE 0x2 92 #define ARM_V7S_PTE_TYPE_CONT_PAGE 0x1 93 94 #define ARM_V7S_PTE_IS_VALID(pte) (((pte) & 0x3) != 0) 95 #define ARM_V7S_PTE_IS_TABLE(pte, lvl) (lvl == 1 && ((pte) & ARM_V7S_PTE_TYPE_TABLE)) 96 97 /* Page table bits */ 98 #define ARM_V7S_ATTR_XN(lvl) BIT(4 * (2 - (lvl))) 99 #define ARM_V7S_ATTR_B BIT(2) 100 #define ARM_V7S_ATTR_C BIT(3) 101 #define ARM_V7S_ATTR_NS_TABLE BIT(3) 102 #define ARM_V7S_ATTR_NS_SECTION BIT(19) 103 104 #define ARM_V7S_CONT_SECTION BIT(18) 105 #define ARM_V7S_CONT_PAGE_XN_SHIFT 15 106 107 /* 108 * The attribute bits are consistently ordered*, but occupy bits [17:10] of 109 * a level 1 PTE vs. bits [11:4] at level 2. Thus we define the individual 110 * fields relative to that 8-bit block, plus a total shift relative to the PTE. 111 */ 112 #define ARM_V7S_ATTR_SHIFT(lvl) (16 - (lvl) * 6) 113 114 #define ARM_V7S_ATTR_MASK 0xff 115 #define ARM_V7S_ATTR_AP0 BIT(0) 116 #define ARM_V7S_ATTR_AP1 BIT(1) 117 #define ARM_V7S_ATTR_AP2 BIT(5) 118 #define ARM_V7S_ATTR_S BIT(6) 119 #define ARM_V7S_ATTR_NG BIT(7) 120 #define ARM_V7S_TEX_SHIFT 2 121 #define ARM_V7S_TEX_MASK 0x7 122 #define ARM_V7S_ATTR_TEX(val) (((val) & ARM_V7S_TEX_MASK) << ARM_V7S_TEX_SHIFT) 123 124 #define ARM_V7S_ATTR_MTK_4GB BIT(9) /* MTK extend it for 4GB mode */ 125 126 /* *well, except for TEX on level 2 large pages, of course :( */ 127 #define ARM_V7S_CONT_PAGE_TEX_SHIFT 6 128 #define ARM_V7S_CONT_PAGE_TEX_MASK (ARM_V7S_TEX_MASK << ARM_V7S_CONT_PAGE_TEX_SHIFT) 129 130 /* Simplified access permissions */ 131 #define ARM_V7S_PTE_AF ARM_V7S_ATTR_AP0 132 #define ARM_V7S_PTE_AP_UNPRIV ARM_V7S_ATTR_AP1 133 #define ARM_V7S_PTE_AP_RDONLY ARM_V7S_ATTR_AP2 134 135 /* Register bits */ 136 #define ARM_V7S_RGN_NC 0 137 #define ARM_V7S_RGN_WBWA 1 138 #define ARM_V7S_RGN_WT 2 139 #define ARM_V7S_RGN_WB 3 140 141 #define ARM_V7S_PRRR_TYPE_DEVICE 1 142 #define ARM_V7S_PRRR_TYPE_NORMAL 2 143 #define ARM_V7S_PRRR_TR(n, type) (((type) & 0x3) << ((n) * 2)) 144 #define ARM_V7S_PRRR_DS0 BIT(16) 145 #define ARM_V7S_PRRR_DS1 BIT(17) 146 #define ARM_V7S_PRRR_NS0 BIT(18) 147 #define ARM_V7S_PRRR_NS1 BIT(19) 148 #define ARM_V7S_PRRR_NOS(n) BIT((n) + 24) 149 150 #define ARM_V7S_NMRR_IR(n, attr) (((attr) & 0x3) << ((n) * 2)) 151 #define ARM_V7S_NMRR_OR(n, attr) (((attr) & 0x3) << ((n) * 2 + 16)) 152 153 #define ARM_V7S_TTBR_S BIT(1) 154 #define ARM_V7S_TTBR_NOS BIT(5) 155 #define ARM_V7S_TTBR_ORGN_ATTR(attr) (((attr) & 0x3) << 3) 156 #define ARM_V7S_TTBR_IRGN_ATTR(attr) \ 157 ((((attr) & 0x1) << 6) | (((attr) & 0x2) >> 1)) 158 159 #define ARM_V7S_TCR_PD1 BIT(5) 160 161 typedef u32 arm_v7s_iopte; 162 163 static bool selftest_running; 164 165 struct arm_v7s_io_pgtable { 166 struct io_pgtable iop; 167 168 arm_v7s_iopte *pgd; 169 struct kmem_cache *l2_tables; 170 }; 171 172 static dma_addr_t __arm_v7s_dma_addr(void *pages) 173 { 174 return (dma_addr_t)virt_to_phys(pages); 175 } 176 177 static arm_v7s_iopte *iopte_deref(arm_v7s_iopte pte, int lvl) 178 { 179 if (ARM_V7S_PTE_IS_TABLE(pte, lvl)) 180 pte &= ARM_V7S_TABLE_MASK; 181 else 182 pte &= ARM_V7S_LVL_MASK(lvl); 183 return phys_to_virt(pte); 184 } 185 186 static void *__arm_v7s_alloc_table(int lvl, gfp_t gfp, 187 struct arm_v7s_io_pgtable *data) 188 { 189 struct device *dev = data->iop.cfg.iommu_dev; 190 dma_addr_t dma; 191 size_t size = ARM_V7S_TABLE_SIZE(lvl); 192 void *table = NULL; 193 194 if (lvl == 1) 195 table = (void *)__get_dma_pages(__GFP_ZERO, get_order(size)); 196 else if (lvl == 2) 197 table = kmem_cache_zalloc(data->l2_tables, gfp | GFP_DMA); 198 if (table && !selftest_running) { 199 dma = dma_map_single(dev, table, size, DMA_TO_DEVICE); 200 if (dma_mapping_error(dev, dma)) 201 goto out_free; 202 /* 203 * We depend on the IOMMU being able to work with any physical 204 * address directly, so if the DMA layer suggests otherwise by 205 * translating or truncating them, that bodes very badly... 206 */ 207 if (dma != virt_to_phys(table)) 208 goto out_unmap; 209 } 210 kmemleak_ignore(table); 211 return table; 212 213 out_unmap: 214 dev_err(dev, "Cannot accommodate DMA translation for IOMMU page tables\n"); 215 dma_unmap_single(dev, dma, size, DMA_TO_DEVICE); 216 out_free: 217 if (lvl == 1) 218 free_pages((unsigned long)table, get_order(size)); 219 else 220 kmem_cache_free(data->l2_tables, table); 221 return NULL; 222 } 223 224 static void __arm_v7s_free_table(void *table, int lvl, 225 struct arm_v7s_io_pgtable *data) 226 { 227 struct device *dev = data->iop.cfg.iommu_dev; 228 size_t size = ARM_V7S_TABLE_SIZE(lvl); 229 230 if (!selftest_running) 231 dma_unmap_single(dev, __arm_v7s_dma_addr(table), size, 232 DMA_TO_DEVICE); 233 if (lvl == 1) 234 free_pages((unsigned long)table, get_order(size)); 235 else 236 kmem_cache_free(data->l2_tables, table); 237 } 238 239 static void __arm_v7s_pte_sync(arm_v7s_iopte *ptep, int num_entries, 240 struct io_pgtable_cfg *cfg) 241 { 242 if (selftest_running) 243 return; 244 245 dma_sync_single_for_device(cfg->iommu_dev, __arm_v7s_dma_addr(ptep), 246 num_entries * sizeof(*ptep), DMA_TO_DEVICE); 247 } 248 static void __arm_v7s_set_pte(arm_v7s_iopte *ptep, arm_v7s_iopte pte, 249 int num_entries, struct io_pgtable_cfg *cfg) 250 { 251 int i; 252 253 for (i = 0; i < num_entries; i++) 254 ptep[i] = pte; 255 256 __arm_v7s_pte_sync(ptep, num_entries, cfg); 257 } 258 259 static arm_v7s_iopte arm_v7s_prot_to_pte(int prot, int lvl, 260 struct io_pgtable_cfg *cfg) 261 { 262 bool ap = !(cfg->quirks & IO_PGTABLE_QUIRK_NO_PERMS); 263 arm_v7s_iopte pte = ARM_V7S_ATTR_NG | ARM_V7S_ATTR_S; 264 265 if (!(prot & IOMMU_MMIO)) 266 pte |= ARM_V7S_ATTR_TEX(1); 267 if (ap) { 268 pte |= ARM_V7S_PTE_AF | ARM_V7S_PTE_AP_UNPRIV; 269 if (!(prot & IOMMU_WRITE)) 270 pte |= ARM_V7S_PTE_AP_RDONLY; 271 } 272 pte <<= ARM_V7S_ATTR_SHIFT(lvl); 273 274 if ((prot & IOMMU_NOEXEC) && ap) 275 pte |= ARM_V7S_ATTR_XN(lvl); 276 if (prot & IOMMU_MMIO) 277 pte |= ARM_V7S_ATTR_B; 278 else if (prot & IOMMU_CACHE) 279 pte |= ARM_V7S_ATTR_B | ARM_V7S_ATTR_C; 280 281 return pte; 282 } 283 284 static int arm_v7s_pte_to_prot(arm_v7s_iopte pte, int lvl) 285 { 286 int prot = IOMMU_READ; 287 arm_v7s_iopte attr = pte >> ARM_V7S_ATTR_SHIFT(lvl); 288 289 if (attr & ARM_V7S_PTE_AP_RDONLY) 290 prot |= IOMMU_WRITE; 291 if ((attr & (ARM_V7S_TEX_MASK << ARM_V7S_TEX_SHIFT)) == 0) 292 prot |= IOMMU_MMIO; 293 else if (pte & ARM_V7S_ATTR_C) 294 prot |= IOMMU_CACHE; 295 296 return prot; 297 } 298 299 static arm_v7s_iopte arm_v7s_pte_to_cont(arm_v7s_iopte pte, int lvl) 300 { 301 if (lvl == 1) { 302 pte |= ARM_V7S_CONT_SECTION; 303 } else if (lvl == 2) { 304 arm_v7s_iopte xn = pte & ARM_V7S_ATTR_XN(lvl); 305 arm_v7s_iopte tex = pte & ARM_V7S_CONT_PAGE_TEX_MASK; 306 307 pte ^= xn | tex | ARM_V7S_PTE_TYPE_PAGE; 308 pte |= (xn << ARM_V7S_CONT_PAGE_XN_SHIFT) | 309 (tex << ARM_V7S_CONT_PAGE_TEX_SHIFT) | 310 ARM_V7S_PTE_TYPE_CONT_PAGE; 311 } 312 return pte; 313 } 314 315 static arm_v7s_iopte arm_v7s_cont_to_pte(arm_v7s_iopte pte, int lvl) 316 { 317 if (lvl == 1) { 318 pte &= ~ARM_V7S_CONT_SECTION; 319 } else if (lvl == 2) { 320 arm_v7s_iopte xn = pte & BIT(ARM_V7S_CONT_PAGE_XN_SHIFT); 321 arm_v7s_iopte tex = pte & (ARM_V7S_CONT_PAGE_TEX_MASK << 322 ARM_V7S_CONT_PAGE_TEX_SHIFT); 323 324 pte ^= xn | tex | ARM_V7S_PTE_TYPE_CONT_PAGE; 325 pte |= (xn >> ARM_V7S_CONT_PAGE_XN_SHIFT) | 326 (tex >> ARM_V7S_CONT_PAGE_TEX_SHIFT) | 327 ARM_V7S_PTE_TYPE_PAGE; 328 } 329 return pte; 330 } 331 332 static bool arm_v7s_pte_is_cont(arm_v7s_iopte pte, int lvl) 333 { 334 if (lvl == 1 && !ARM_V7S_PTE_IS_TABLE(pte, lvl)) 335 return pte & ARM_V7S_CONT_SECTION; 336 else if (lvl == 2) 337 return !(pte & ARM_V7S_PTE_TYPE_PAGE); 338 return false; 339 } 340 341 static int __arm_v7s_unmap(struct arm_v7s_io_pgtable *, unsigned long, 342 size_t, int, arm_v7s_iopte *); 343 344 static int arm_v7s_init_pte(struct arm_v7s_io_pgtable *data, 345 unsigned long iova, phys_addr_t paddr, int prot, 346 int lvl, int num_entries, arm_v7s_iopte *ptep) 347 { 348 struct io_pgtable_cfg *cfg = &data->iop.cfg; 349 arm_v7s_iopte pte = arm_v7s_prot_to_pte(prot, lvl, cfg); 350 int i; 351 352 for (i = 0; i < num_entries; i++) 353 if (ARM_V7S_PTE_IS_TABLE(ptep[i], lvl)) { 354 /* 355 * We need to unmap and free the old table before 356 * overwriting it with a block entry. 357 */ 358 arm_v7s_iopte *tblp; 359 size_t sz = ARM_V7S_BLOCK_SIZE(lvl); 360 361 tblp = ptep - ARM_V7S_LVL_IDX(iova, lvl); 362 if (WARN_ON(__arm_v7s_unmap(data, iova + i * sz, 363 sz, lvl, tblp) != sz)) 364 return -EINVAL; 365 } else if (ptep[i]) { 366 /* We require an unmap first */ 367 WARN_ON(!selftest_running); 368 return -EEXIST; 369 } 370 371 pte |= ARM_V7S_PTE_TYPE_PAGE; 372 if (lvl == 1 && (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS)) 373 pte |= ARM_V7S_ATTR_NS_SECTION; 374 375 if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB) 376 pte |= ARM_V7S_ATTR_MTK_4GB; 377 378 if (num_entries > 1) 379 pte = arm_v7s_pte_to_cont(pte, lvl); 380 381 pte |= paddr & ARM_V7S_LVL_MASK(lvl); 382 383 __arm_v7s_set_pte(ptep, pte, num_entries, cfg); 384 return 0; 385 } 386 387 static int __arm_v7s_map(struct arm_v7s_io_pgtable *data, unsigned long iova, 388 phys_addr_t paddr, size_t size, int prot, 389 int lvl, arm_v7s_iopte *ptep) 390 { 391 struct io_pgtable_cfg *cfg = &data->iop.cfg; 392 arm_v7s_iopte pte, *cptep; 393 int num_entries = size >> ARM_V7S_LVL_SHIFT(lvl); 394 395 /* Find our entry at the current level */ 396 ptep += ARM_V7S_LVL_IDX(iova, lvl); 397 398 /* If we can install a leaf entry at this level, then do so */ 399 if (num_entries) 400 return arm_v7s_init_pte(data, iova, paddr, prot, 401 lvl, num_entries, ptep); 402 403 /* We can't allocate tables at the final level */ 404 if (WARN_ON(lvl == 2)) 405 return -EINVAL; 406 407 /* Grab a pointer to the next level */ 408 pte = *ptep; 409 if (!pte) { 410 cptep = __arm_v7s_alloc_table(lvl + 1, GFP_ATOMIC, data); 411 if (!cptep) 412 return -ENOMEM; 413 414 pte = virt_to_phys(cptep) | ARM_V7S_PTE_TYPE_TABLE; 415 if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS) 416 pte |= ARM_V7S_ATTR_NS_TABLE; 417 418 __arm_v7s_set_pte(ptep, pte, 1, cfg); 419 } else { 420 cptep = iopte_deref(pte, lvl); 421 } 422 423 /* Rinse, repeat */ 424 return __arm_v7s_map(data, iova, paddr, size, prot, lvl + 1, cptep); 425 } 426 427 static int arm_v7s_map(struct io_pgtable_ops *ops, unsigned long iova, 428 phys_addr_t paddr, size_t size, int prot) 429 { 430 struct arm_v7s_io_pgtable *data = io_pgtable_ops_to_data(ops); 431 struct io_pgtable *iop = &data->iop; 432 int ret; 433 434 /* If no access, then nothing to do */ 435 if (!(prot & (IOMMU_READ | IOMMU_WRITE))) 436 return 0; 437 438 ret = __arm_v7s_map(data, iova, paddr, size, prot, 1, data->pgd); 439 /* 440 * Synchronise all PTE updates for the new mapping before there's 441 * a chance for anything to kick off a table walk for the new iova. 442 */ 443 if (iop->cfg.quirks & IO_PGTABLE_QUIRK_TLBI_ON_MAP) { 444 io_pgtable_tlb_add_flush(iop, iova, size, 445 ARM_V7S_BLOCK_SIZE(2), false); 446 io_pgtable_tlb_sync(iop); 447 } else { 448 wmb(); 449 } 450 451 return ret; 452 } 453 454 static void arm_v7s_free_pgtable(struct io_pgtable *iop) 455 { 456 struct arm_v7s_io_pgtable *data = io_pgtable_to_data(iop); 457 int i; 458 459 for (i = 0; i < ARM_V7S_PTES_PER_LVL(1); i++) { 460 arm_v7s_iopte pte = data->pgd[i]; 461 462 if (ARM_V7S_PTE_IS_TABLE(pte, 1)) 463 __arm_v7s_free_table(iopte_deref(pte, 1), 2, data); 464 } 465 __arm_v7s_free_table(data->pgd, 1, data); 466 kmem_cache_destroy(data->l2_tables); 467 kfree(data); 468 } 469 470 static void arm_v7s_split_cont(struct arm_v7s_io_pgtable *data, 471 unsigned long iova, int idx, int lvl, 472 arm_v7s_iopte *ptep) 473 { 474 struct io_pgtable *iop = &data->iop; 475 arm_v7s_iopte pte; 476 size_t size = ARM_V7S_BLOCK_SIZE(lvl); 477 int i; 478 479 ptep -= idx & (ARM_V7S_CONT_PAGES - 1); 480 pte = arm_v7s_cont_to_pte(*ptep, lvl); 481 for (i = 0; i < ARM_V7S_CONT_PAGES; i++) { 482 ptep[i] = pte; 483 pte += size; 484 } 485 486 __arm_v7s_pte_sync(ptep, ARM_V7S_CONT_PAGES, &iop->cfg); 487 488 size *= ARM_V7S_CONT_PAGES; 489 io_pgtable_tlb_add_flush(iop, iova, size, size, true); 490 io_pgtable_tlb_sync(iop); 491 } 492 493 static int arm_v7s_split_blk_unmap(struct arm_v7s_io_pgtable *data, 494 unsigned long iova, size_t size, 495 arm_v7s_iopte *ptep) 496 { 497 unsigned long blk_start, blk_end, blk_size; 498 phys_addr_t blk_paddr; 499 arm_v7s_iopte table = 0; 500 int prot = arm_v7s_pte_to_prot(*ptep, 1); 501 502 blk_size = ARM_V7S_BLOCK_SIZE(1); 503 blk_start = iova & ARM_V7S_LVL_MASK(1); 504 blk_end = blk_start + ARM_V7S_BLOCK_SIZE(1); 505 blk_paddr = *ptep & ARM_V7S_LVL_MASK(1); 506 507 for (; blk_start < blk_end; blk_start += size, blk_paddr += size) { 508 arm_v7s_iopte *tablep; 509 510 /* Unmap! */ 511 if (blk_start == iova) 512 continue; 513 514 /* __arm_v7s_map expects a pointer to the start of the table */ 515 tablep = &table - ARM_V7S_LVL_IDX(blk_start, 1); 516 if (__arm_v7s_map(data, blk_start, blk_paddr, size, prot, 1, 517 tablep) < 0) { 518 if (table) { 519 /* Free the table we allocated */ 520 tablep = iopte_deref(table, 1); 521 __arm_v7s_free_table(tablep, 2, data); 522 } 523 return 0; /* Bytes unmapped */ 524 } 525 } 526 527 __arm_v7s_set_pte(ptep, table, 1, &data->iop.cfg); 528 iova &= ~(blk_size - 1); 529 io_pgtable_tlb_add_flush(&data->iop, iova, blk_size, blk_size, true); 530 return size; 531 } 532 533 static int __arm_v7s_unmap(struct arm_v7s_io_pgtable *data, 534 unsigned long iova, size_t size, int lvl, 535 arm_v7s_iopte *ptep) 536 { 537 arm_v7s_iopte pte[ARM_V7S_CONT_PAGES]; 538 struct io_pgtable *iop = &data->iop; 539 int idx, i = 0, num_entries = size >> ARM_V7S_LVL_SHIFT(lvl); 540 541 /* Something went horribly wrong and we ran out of page table */ 542 if (WARN_ON(lvl > 2)) 543 return 0; 544 545 idx = ARM_V7S_LVL_IDX(iova, lvl); 546 ptep += idx; 547 do { 548 if (WARN_ON(!ARM_V7S_PTE_IS_VALID(ptep[i]))) 549 return 0; 550 pte[i] = ptep[i]; 551 } while (++i < num_entries); 552 553 /* 554 * If we've hit a contiguous 'large page' entry at this level, it 555 * needs splitting first, unless we're unmapping the whole lot. 556 */ 557 if (num_entries <= 1 && arm_v7s_pte_is_cont(pte[0], lvl)) 558 arm_v7s_split_cont(data, iova, idx, lvl, ptep); 559 560 /* If the size matches this level, we're in the right place */ 561 if (num_entries) { 562 size_t blk_size = ARM_V7S_BLOCK_SIZE(lvl); 563 564 __arm_v7s_set_pte(ptep, 0, num_entries, &iop->cfg); 565 566 for (i = 0; i < num_entries; i++) { 567 if (ARM_V7S_PTE_IS_TABLE(pte[i], lvl)) { 568 /* Also flush any partial walks */ 569 io_pgtable_tlb_add_flush(iop, iova, blk_size, 570 ARM_V7S_BLOCK_SIZE(lvl + 1), false); 571 io_pgtable_tlb_sync(iop); 572 ptep = iopte_deref(pte[i], lvl); 573 __arm_v7s_free_table(ptep, lvl + 1, data); 574 } else { 575 io_pgtable_tlb_add_flush(iop, iova, blk_size, 576 blk_size, true); 577 } 578 iova += blk_size; 579 } 580 return size; 581 } else if (lvl == 1 && !ARM_V7S_PTE_IS_TABLE(pte[0], lvl)) { 582 /* 583 * Insert a table at the next level to map the old region, 584 * minus the part we want to unmap 585 */ 586 return arm_v7s_split_blk_unmap(data, iova, size, ptep); 587 } 588 589 /* Keep on walkin' */ 590 ptep = iopte_deref(pte[0], lvl); 591 return __arm_v7s_unmap(data, iova, size, lvl + 1, ptep); 592 } 593 594 static int arm_v7s_unmap(struct io_pgtable_ops *ops, unsigned long iova, 595 size_t size) 596 { 597 struct arm_v7s_io_pgtable *data = io_pgtable_ops_to_data(ops); 598 size_t unmapped; 599 600 unmapped = __arm_v7s_unmap(data, iova, size, 1, data->pgd); 601 if (unmapped) 602 io_pgtable_tlb_sync(&data->iop); 603 604 return unmapped; 605 } 606 607 static phys_addr_t arm_v7s_iova_to_phys(struct io_pgtable_ops *ops, 608 unsigned long iova) 609 { 610 struct arm_v7s_io_pgtable *data = io_pgtable_ops_to_data(ops); 611 arm_v7s_iopte *ptep = data->pgd, pte; 612 int lvl = 0; 613 u32 mask; 614 615 do { 616 pte = ptep[ARM_V7S_LVL_IDX(iova, ++lvl)]; 617 ptep = iopte_deref(pte, lvl); 618 } while (ARM_V7S_PTE_IS_TABLE(pte, lvl)); 619 620 if (!ARM_V7S_PTE_IS_VALID(pte)) 621 return 0; 622 623 mask = ARM_V7S_LVL_MASK(lvl); 624 if (arm_v7s_pte_is_cont(pte, lvl)) 625 mask *= ARM_V7S_CONT_PAGES; 626 return (pte & mask) | (iova & ~mask); 627 } 628 629 static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg, 630 void *cookie) 631 { 632 struct arm_v7s_io_pgtable *data; 633 634 if (cfg->ias > ARM_V7S_ADDR_BITS || cfg->oas > ARM_V7S_ADDR_BITS) 635 return NULL; 636 637 if (cfg->quirks & ~(IO_PGTABLE_QUIRK_ARM_NS | 638 IO_PGTABLE_QUIRK_NO_PERMS | 639 IO_PGTABLE_QUIRK_TLBI_ON_MAP | 640 IO_PGTABLE_QUIRK_ARM_MTK_4GB)) 641 return NULL; 642 643 /* If ARM_MTK_4GB is enabled, the NO_PERMS is also expected. */ 644 if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB && 645 !(cfg->quirks & IO_PGTABLE_QUIRK_NO_PERMS)) 646 return NULL; 647 648 data = kmalloc(sizeof(*data), GFP_KERNEL); 649 if (!data) 650 return NULL; 651 652 data->l2_tables = kmem_cache_create("io-pgtable_armv7s_l2", 653 ARM_V7S_TABLE_SIZE(2), 654 ARM_V7S_TABLE_SIZE(2), 655 SLAB_CACHE_DMA, NULL); 656 if (!data->l2_tables) 657 goto out_free_data; 658 659 data->iop.ops = (struct io_pgtable_ops) { 660 .map = arm_v7s_map, 661 .unmap = arm_v7s_unmap, 662 .iova_to_phys = arm_v7s_iova_to_phys, 663 }; 664 665 /* We have to do this early for __arm_v7s_alloc_table to work... */ 666 data->iop.cfg = *cfg; 667 668 /* 669 * Unless the IOMMU driver indicates supersection support by 670 * having SZ_16M set in the initial bitmap, they won't be used. 671 */ 672 cfg->pgsize_bitmap &= SZ_4K | SZ_64K | SZ_1M | SZ_16M; 673 674 /* TCR: T0SZ=0, disable TTBR1 */ 675 cfg->arm_v7s_cfg.tcr = ARM_V7S_TCR_PD1; 676 677 /* 678 * TEX remap: the indices used map to the closest equivalent types 679 * under the non-TEX-remap interpretation of those attribute bits, 680 * excepting various implementation-defined aspects of shareability. 681 */ 682 cfg->arm_v7s_cfg.prrr = ARM_V7S_PRRR_TR(1, ARM_V7S_PRRR_TYPE_DEVICE) | 683 ARM_V7S_PRRR_TR(4, ARM_V7S_PRRR_TYPE_NORMAL) | 684 ARM_V7S_PRRR_TR(7, ARM_V7S_PRRR_TYPE_NORMAL) | 685 ARM_V7S_PRRR_DS0 | ARM_V7S_PRRR_DS1 | 686 ARM_V7S_PRRR_NS1 | ARM_V7S_PRRR_NOS(7); 687 cfg->arm_v7s_cfg.nmrr = ARM_V7S_NMRR_IR(7, ARM_V7S_RGN_WBWA) | 688 ARM_V7S_NMRR_OR(7, ARM_V7S_RGN_WBWA); 689 690 /* Looking good; allocate a pgd */ 691 data->pgd = __arm_v7s_alloc_table(1, GFP_KERNEL, data); 692 if (!data->pgd) 693 goto out_free_data; 694 695 /* Ensure the empty pgd is visible before any actual TTBR write */ 696 wmb(); 697 698 /* TTBRs */ 699 cfg->arm_v7s_cfg.ttbr[0] = virt_to_phys(data->pgd) | 700 ARM_V7S_TTBR_S | ARM_V7S_TTBR_NOS | 701 ARM_V7S_TTBR_IRGN_ATTR(ARM_V7S_RGN_WBWA) | 702 ARM_V7S_TTBR_ORGN_ATTR(ARM_V7S_RGN_WBWA); 703 cfg->arm_v7s_cfg.ttbr[1] = 0; 704 return &data->iop; 705 706 out_free_data: 707 kmem_cache_destroy(data->l2_tables); 708 kfree(data); 709 return NULL; 710 } 711 712 struct io_pgtable_init_fns io_pgtable_arm_v7s_init_fns = { 713 .alloc = arm_v7s_alloc_pgtable, 714 .free = arm_v7s_free_pgtable, 715 }; 716 717 #ifdef CONFIG_IOMMU_IO_PGTABLE_ARMV7S_SELFTEST 718 719 static struct io_pgtable_cfg *cfg_cookie; 720 721 static void dummy_tlb_flush_all(void *cookie) 722 { 723 WARN_ON(cookie != cfg_cookie); 724 } 725 726 static void dummy_tlb_add_flush(unsigned long iova, size_t size, 727 size_t granule, bool leaf, void *cookie) 728 { 729 WARN_ON(cookie != cfg_cookie); 730 WARN_ON(!(size & cfg_cookie->pgsize_bitmap)); 731 } 732 733 static void dummy_tlb_sync(void *cookie) 734 { 735 WARN_ON(cookie != cfg_cookie); 736 } 737 738 static struct iommu_gather_ops dummy_tlb_ops = { 739 .tlb_flush_all = dummy_tlb_flush_all, 740 .tlb_add_flush = dummy_tlb_add_flush, 741 .tlb_sync = dummy_tlb_sync, 742 }; 743 744 #define __FAIL(ops) ({ \ 745 WARN(1, "selftest: test failed\n"); \ 746 selftest_running = false; \ 747 -EFAULT; \ 748 }) 749 750 static int __init arm_v7s_do_selftests(void) 751 { 752 struct io_pgtable_ops *ops; 753 struct io_pgtable_cfg cfg = { 754 .tlb = &dummy_tlb_ops, 755 .oas = 32, 756 .ias = 32, 757 .quirks = IO_PGTABLE_QUIRK_ARM_NS, 758 .pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M, 759 }; 760 unsigned int iova, size, iova_start; 761 unsigned int i, loopnr = 0; 762 763 selftest_running = true; 764 765 cfg_cookie = &cfg; 766 767 ops = alloc_io_pgtable_ops(ARM_V7S, &cfg, &cfg); 768 if (!ops) { 769 pr_err("selftest: failed to allocate io pgtable ops\n"); 770 return -EINVAL; 771 } 772 773 /* 774 * Initial sanity checks. 775 * Empty page tables shouldn't provide any translations. 776 */ 777 if (ops->iova_to_phys(ops, 42)) 778 return __FAIL(ops); 779 780 if (ops->iova_to_phys(ops, SZ_1G + 42)) 781 return __FAIL(ops); 782 783 if (ops->iova_to_phys(ops, SZ_2G + 42)) 784 return __FAIL(ops); 785 786 /* 787 * Distinct mappings of different granule sizes. 788 */ 789 iova = 0; 790 i = find_first_bit(&cfg.pgsize_bitmap, BITS_PER_LONG); 791 while (i != BITS_PER_LONG) { 792 size = 1UL << i; 793 if (ops->map(ops, iova, iova, size, IOMMU_READ | 794 IOMMU_WRITE | 795 IOMMU_NOEXEC | 796 IOMMU_CACHE)) 797 return __FAIL(ops); 798 799 /* Overlapping mappings */ 800 if (!ops->map(ops, iova, iova + size, size, 801 IOMMU_READ | IOMMU_NOEXEC)) 802 return __FAIL(ops); 803 804 if (ops->iova_to_phys(ops, iova + 42) != (iova + 42)) 805 return __FAIL(ops); 806 807 iova += SZ_16M; 808 i++; 809 i = find_next_bit(&cfg.pgsize_bitmap, BITS_PER_LONG, i); 810 loopnr++; 811 } 812 813 /* Partial unmap */ 814 i = 1; 815 size = 1UL << __ffs(cfg.pgsize_bitmap); 816 while (i < loopnr) { 817 iova_start = i * SZ_16M; 818 if (ops->unmap(ops, iova_start + size, size) != size) 819 return __FAIL(ops); 820 821 /* Remap of partial unmap */ 822 if (ops->map(ops, iova_start + size, size, size, IOMMU_READ)) 823 return __FAIL(ops); 824 825 if (ops->iova_to_phys(ops, iova_start + size + 42) 826 != (size + 42)) 827 return __FAIL(ops); 828 i++; 829 } 830 831 /* Full unmap */ 832 iova = 0; 833 i = find_first_bit(&cfg.pgsize_bitmap, BITS_PER_LONG); 834 while (i != BITS_PER_LONG) { 835 size = 1UL << i; 836 837 if (ops->unmap(ops, iova, size) != size) 838 return __FAIL(ops); 839 840 if (ops->iova_to_phys(ops, iova + 42)) 841 return __FAIL(ops); 842 843 /* Remap full block */ 844 if (ops->map(ops, iova, iova, size, IOMMU_WRITE)) 845 return __FAIL(ops); 846 847 if (ops->iova_to_phys(ops, iova + 42) != (iova + 42)) 848 return __FAIL(ops); 849 850 iova += SZ_16M; 851 i++; 852 i = find_next_bit(&cfg.pgsize_bitmap, BITS_PER_LONG, i); 853 } 854 855 free_io_pgtable_ops(ops); 856 857 selftest_running = false; 858 859 pr_info("self test ok\n"); 860 return 0; 861 } 862 subsys_initcall(arm_v7s_do_selftests); 863 #endif 864