xref: /linux/drivers/iommu/intel/trace.h (revision 07f0148aafe8c95a3a76cd59e9e75b4d78d1d31d)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Intel IOMMU trace support
4  *
5  * Copyright (C) 2019 Intel Corporation
6  *
7  * Author: Lu Baolu <baolu.lu@linux.intel.com>
8  */
9 #undef TRACE_SYSTEM
10 #define TRACE_SYSTEM intel_iommu
11 
12 #if !defined(_TRACE_INTEL_IOMMU_H) || defined(TRACE_HEADER_MULTI_READ)
13 #define _TRACE_INTEL_IOMMU_H
14 
15 #include <linux/tracepoint.h>
16 
17 #include "iommu.h"
18 
19 #define MSG_MAX		256
20 
21 TRACE_EVENT(qi_submit,
22 	TP_PROTO(struct intel_iommu *iommu, u64 qw0, u64 qw1, u64 qw2, u64 qw3),
23 
24 	TP_ARGS(iommu, qw0, qw1, qw2, qw3),
25 
26 	TP_STRUCT__entry(
27 		__field(u64, qw0)
28 		__field(u64, qw1)
29 		__field(u64, qw2)
30 		__field(u64, qw3)
31 		__string(iommu, iommu->name)
32 	),
33 
34 	TP_fast_assign(
35 		__assign_str(iommu, iommu->name);
36 		__entry->qw0 = qw0;
37 		__entry->qw1 = qw1;
38 		__entry->qw2 = qw2;
39 		__entry->qw3 = qw3;
40 	),
41 
42 	TP_printk("%s %s: 0x%llx 0x%llx 0x%llx 0x%llx",
43 		  __print_symbolic(__entry->qw0 & 0xf,
44 				   { QI_CC_TYPE,	"cc_inv" },
45 				   { QI_IOTLB_TYPE,	"iotlb_inv" },
46 				   { QI_DIOTLB_TYPE,	"dev_tlb_inv" },
47 				   { QI_IEC_TYPE,	"iec_inv" },
48 				   { QI_IWD_TYPE,	"inv_wait" },
49 				   { QI_EIOTLB_TYPE,	"p_iotlb_inv" },
50 				   { QI_PC_TYPE,	"pc_inv" },
51 				   { QI_DEIOTLB_TYPE,	"p_dev_tlb_inv" },
52 				   { QI_PGRP_RESP_TYPE,	"page_grp_resp" }),
53 		__get_str(iommu),
54 		__entry->qw0, __entry->qw1, __entry->qw2, __entry->qw3
55 	)
56 );
57 
58 TRACE_EVENT(prq_report,
59 	TP_PROTO(struct intel_iommu *iommu, struct device *dev,
60 		 u64 dw0, u64 dw1, u64 dw2, u64 dw3,
61 		 unsigned long seq),
62 
63 	TP_ARGS(iommu, dev, dw0, dw1, dw2, dw3, seq),
64 
65 	TP_STRUCT__entry(
66 		__field(u64, dw0)
67 		__field(u64, dw1)
68 		__field(u64, dw2)
69 		__field(u64, dw3)
70 		__field(unsigned long, seq)
71 		__string(iommu, iommu->name)
72 		__string(dev, dev_name(dev))
73 		__dynamic_array(char, buff, MSG_MAX)
74 	),
75 
76 	TP_fast_assign(
77 		__entry->dw0 = dw0;
78 		__entry->dw1 = dw1;
79 		__entry->dw2 = dw2;
80 		__entry->dw3 = dw3;
81 		__entry->seq = seq;
82 		__assign_str(iommu, iommu->name);
83 		__assign_str(dev, dev_name(dev));
84 	),
85 
86 	TP_printk("%s/%s seq# %ld: %s",
87 		__get_str(iommu), __get_str(dev), __entry->seq,
88 		decode_prq_descriptor(__get_str(buff), MSG_MAX, __entry->dw0,
89 				      __entry->dw1, __entry->dw2, __entry->dw3)
90 	)
91 );
92 #endif /* _TRACE_INTEL_IOMMU_H */
93 
94 /* This part must be outside protection */
95 #undef TRACE_INCLUDE_PATH
96 #undef TRACE_INCLUDE_FILE
97 #define TRACE_INCLUDE_PATH ../../drivers/iommu/intel/
98 #define TRACE_INCLUDE_FILE trace
99 #include <trace/define_trace.h>
100