1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * nested.c - nested mode translation support 4 * 5 * Copyright (C) 2023 Intel Corporation 6 * 7 * Author: Lu Baolu <baolu.lu@linux.intel.com> 8 * Jacob Pan <jacob.jun.pan@linux.intel.com> 9 * Yi Liu <yi.l.liu@intel.com> 10 */ 11 12 #define pr_fmt(fmt) "DMAR: " fmt 13 14 #include <linux/iommu.h> 15 #include <linux/pci.h> 16 #include <linux/pci-ats.h> 17 18 #include "iommu.h" 19 #include "pasid.h" 20 21 static int intel_nested_attach_dev(struct iommu_domain *domain, 22 struct device *dev) 23 { 24 struct device_domain_info *info = dev_iommu_priv_get(dev); 25 struct dmar_domain *dmar_domain = to_dmar_domain(domain); 26 struct intel_iommu *iommu = info->iommu; 27 unsigned long flags; 28 int ret = 0; 29 30 if (info->domain) 31 device_block_translation(dev); 32 33 if (iommu->agaw < dmar_domain->s2_domain->agaw) { 34 dev_err_ratelimited(dev, "Adjusted guest address width not compatible\n"); 35 return -ENODEV; 36 } 37 38 /* 39 * Stage-1 domain cannot work alone, it is nested on a s2_domain. 40 * The s2_domain will be used in nested translation, hence needs 41 * to ensure the s2_domain is compatible with this IOMMU. 42 */ 43 ret = prepare_domain_attach_device(&dmar_domain->s2_domain->domain, dev); 44 if (ret) { 45 dev_err_ratelimited(dev, "s2 domain is not compatible\n"); 46 return ret; 47 } 48 49 ret = domain_attach_iommu(dmar_domain, iommu); 50 if (ret) { 51 dev_err_ratelimited(dev, "Failed to attach domain to iommu\n"); 52 return ret; 53 } 54 55 ret = cache_tag_assign_domain(dmar_domain, dev, IOMMU_NO_PASID); 56 if (ret) 57 goto detach_iommu; 58 59 ret = intel_pasid_setup_nested(iommu, dev, 60 IOMMU_NO_PASID, dmar_domain); 61 if (ret) 62 goto unassign_tag; 63 64 info->domain = dmar_domain; 65 spin_lock_irqsave(&dmar_domain->lock, flags); 66 list_add(&info->link, &dmar_domain->devices); 67 spin_unlock_irqrestore(&dmar_domain->lock, flags); 68 69 domain_update_iotlb(dmar_domain); 70 71 return 0; 72 unassign_tag: 73 cache_tag_unassign_domain(dmar_domain, dev, IOMMU_NO_PASID); 74 detach_iommu: 75 domain_detach_iommu(dmar_domain, iommu); 76 77 return ret; 78 } 79 80 static void intel_nested_domain_free(struct iommu_domain *domain) 81 { 82 struct dmar_domain *dmar_domain = to_dmar_domain(domain); 83 struct dmar_domain *s2_domain = dmar_domain->s2_domain; 84 85 spin_lock(&s2_domain->s1_lock); 86 list_del(&dmar_domain->s2_link); 87 spin_unlock(&s2_domain->s1_lock); 88 kfree(dmar_domain); 89 } 90 91 static void nested_flush_dev_iotlb(struct dmar_domain *domain, u64 addr, 92 unsigned int mask) 93 { 94 struct device_domain_info *info; 95 unsigned long flags; 96 u16 sid, qdep; 97 98 spin_lock_irqsave(&domain->lock, flags); 99 list_for_each_entry(info, &domain->devices, link) { 100 if (!info->ats_enabled) 101 continue; 102 sid = info->bus << 8 | info->devfn; 103 qdep = info->ats_qdep; 104 qi_flush_dev_iotlb(info->iommu, sid, info->pfsid, 105 qdep, addr, mask); 106 quirk_extra_dev_tlb_flush(info, addr, mask, 107 IOMMU_NO_PASID, qdep); 108 } 109 spin_unlock_irqrestore(&domain->lock, flags); 110 } 111 112 static void intel_nested_flush_cache(struct dmar_domain *domain, u64 addr, 113 u64 npages, bool ih) 114 { 115 struct iommu_domain_info *info; 116 unsigned int mask; 117 unsigned long i; 118 119 xa_for_each(&domain->iommu_array, i, info) 120 qi_flush_piotlb(info->iommu, 121 domain_id_iommu(domain, info->iommu), 122 IOMMU_NO_PASID, addr, npages, ih); 123 124 if (!domain->has_iotlb_device) 125 return; 126 127 if (npages == U64_MAX) 128 mask = 64 - VTD_PAGE_SHIFT; 129 else 130 mask = ilog2(__roundup_pow_of_two(npages)); 131 132 nested_flush_dev_iotlb(domain, addr, mask); 133 } 134 135 static int intel_nested_cache_invalidate_user(struct iommu_domain *domain, 136 struct iommu_user_data_array *array) 137 { 138 struct dmar_domain *dmar_domain = to_dmar_domain(domain); 139 struct iommu_hwpt_vtd_s1_invalidate inv_entry; 140 u32 index, processed = 0; 141 int ret = 0; 142 143 if (array->type != IOMMU_HWPT_INVALIDATE_DATA_VTD_S1) { 144 ret = -EINVAL; 145 goto out; 146 } 147 148 for (index = 0; index < array->entry_num; index++) { 149 ret = iommu_copy_struct_from_user_array(&inv_entry, array, 150 IOMMU_HWPT_INVALIDATE_DATA_VTD_S1, 151 index, __reserved); 152 if (ret) 153 break; 154 155 if ((inv_entry.flags & ~IOMMU_VTD_INV_FLAGS_LEAF) || 156 inv_entry.__reserved) { 157 ret = -EOPNOTSUPP; 158 break; 159 } 160 161 if (!IS_ALIGNED(inv_entry.addr, VTD_PAGE_SIZE) || 162 ((inv_entry.npages == U64_MAX) && inv_entry.addr)) { 163 ret = -EINVAL; 164 break; 165 } 166 167 intel_nested_flush_cache(dmar_domain, inv_entry.addr, 168 inv_entry.npages, 169 inv_entry.flags & IOMMU_VTD_INV_FLAGS_LEAF); 170 processed++; 171 } 172 173 out: 174 array->entry_num = processed; 175 return ret; 176 } 177 178 static const struct iommu_domain_ops intel_nested_domain_ops = { 179 .attach_dev = intel_nested_attach_dev, 180 .free = intel_nested_domain_free, 181 .cache_invalidate_user = intel_nested_cache_invalidate_user, 182 }; 183 184 struct iommu_domain *intel_nested_domain_alloc(struct iommu_domain *parent, 185 const struct iommu_user_data *user_data) 186 { 187 struct dmar_domain *s2_domain = to_dmar_domain(parent); 188 struct iommu_hwpt_vtd_s1 vtd; 189 struct dmar_domain *domain; 190 int ret; 191 192 /* Must be nested domain */ 193 if (user_data->type != IOMMU_HWPT_DATA_VTD_S1) 194 return ERR_PTR(-EOPNOTSUPP); 195 if (parent->ops != intel_iommu_ops.default_domain_ops || 196 !s2_domain->nested_parent) 197 return ERR_PTR(-EINVAL); 198 199 ret = iommu_copy_struct_from_user(&vtd, user_data, 200 IOMMU_HWPT_DATA_VTD_S1, __reserved); 201 if (ret) 202 return ERR_PTR(ret); 203 204 domain = kzalloc(sizeof(*domain), GFP_KERNEL_ACCOUNT); 205 if (!domain) 206 return ERR_PTR(-ENOMEM); 207 208 domain->use_first_level = true; 209 domain->s2_domain = s2_domain; 210 domain->s1_pgtbl = vtd.pgtbl_addr; 211 domain->s1_cfg = vtd; 212 domain->domain.ops = &intel_nested_domain_ops; 213 domain->domain.type = IOMMU_DOMAIN_NESTED; 214 INIT_LIST_HEAD(&domain->devices); 215 INIT_LIST_HEAD(&domain->dev_pasids); 216 INIT_LIST_HEAD(&domain->cache_tags); 217 spin_lock_init(&domain->lock); 218 spin_lock_init(&domain->cache_lock); 219 xa_init(&domain->iommu_array); 220 221 spin_lock(&s2_domain->s1_lock); 222 list_add(&domain->s2_link, &s2_domain->s1_domains); 223 spin_unlock(&s2_domain->s1_lock); 224 225 return &domain->domain; 226 } 227