1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright © 2006-2015, Intel Corporation. 4 * 5 * Authors: Ashok Raj <ashok.raj@intel.com> 6 * Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> 7 * David Woodhouse <David.Woodhouse@intel.com> 8 */ 9 10 #ifndef _INTEL_IOMMU_H_ 11 #define _INTEL_IOMMU_H_ 12 13 #include <linux/types.h> 14 #include <linux/iova.h> 15 #include <linux/io.h> 16 #include <linux/idr.h> 17 #include <linux/mmu_notifier.h> 18 #include <linux/list.h> 19 #include <linux/iommu.h> 20 #include <linux/io-64-nonatomic-lo-hi.h> 21 #include <linux/dmar.h> 22 #include <linux/bitfield.h> 23 #include <linux/xarray.h> 24 #include <linux/perf_event.h> 25 26 #include <asm/cacheflush.h> 27 #include <asm/iommu.h> 28 #include <uapi/linux/iommufd.h> 29 30 /* 31 * VT-d hardware uses 4KiB page size regardless of host page size. 32 */ 33 #define VTD_PAGE_SHIFT (12) 34 #define VTD_PAGE_SIZE (1UL << VTD_PAGE_SHIFT) 35 #define VTD_PAGE_MASK (((u64)-1) << VTD_PAGE_SHIFT) 36 #define VTD_PAGE_ALIGN(addr) (((addr) + VTD_PAGE_SIZE - 1) & VTD_PAGE_MASK) 37 38 #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT) 39 40 #define VTD_STRIDE_SHIFT (9) 41 #define VTD_STRIDE_MASK (((u64)-1) << VTD_STRIDE_SHIFT) 42 43 #define DMA_PTE_READ BIT_ULL(0) 44 #define DMA_PTE_WRITE BIT_ULL(1) 45 #define DMA_PTE_LARGE_PAGE BIT_ULL(7) 46 #define DMA_PTE_SNP BIT_ULL(11) 47 48 #define DMA_FL_PTE_PRESENT BIT_ULL(0) 49 #define DMA_FL_PTE_US BIT_ULL(2) 50 #define DMA_FL_PTE_ACCESS BIT_ULL(5) 51 #define DMA_FL_PTE_DIRTY BIT_ULL(6) 52 #define DMA_FL_PTE_XD BIT_ULL(63) 53 54 #define DMA_SL_PTE_DIRTY_BIT 9 55 #define DMA_SL_PTE_DIRTY BIT_ULL(DMA_SL_PTE_DIRTY_BIT) 56 57 #define ADDR_WIDTH_5LEVEL (57) 58 #define ADDR_WIDTH_4LEVEL (48) 59 60 #define CONTEXT_TT_MULTI_LEVEL 0 61 #define CONTEXT_TT_DEV_IOTLB 1 62 #define CONTEXT_TT_PASS_THROUGH 2 63 #define CONTEXT_PASIDE BIT_ULL(3) 64 65 /* 66 * Intel IOMMU register specification per version 1.0 public spec. 67 */ 68 #define DMAR_VER_REG 0x0 /* Arch version supported by this IOMMU */ 69 #define DMAR_CAP_REG 0x8 /* Hardware supported capabilities */ 70 #define DMAR_ECAP_REG 0x10 /* Extended capabilities supported */ 71 #define DMAR_GCMD_REG 0x18 /* Global command register */ 72 #define DMAR_GSTS_REG 0x1c /* Global status register */ 73 #define DMAR_RTADDR_REG 0x20 /* Root entry table */ 74 #define DMAR_CCMD_REG 0x28 /* Context command reg */ 75 #define DMAR_FSTS_REG 0x34 /* Fault Status register */ 76 #define DMAR_FECTL_REG 0x38 /* Fault control register */ 77 #define DMAR_FEDATA_REG 0x3c /* Fault event interrupt data register */ 78 #define DMAR_FEADDR_REG 0x40 /* Fault event interrupt addr register */ 79 #define DMAR_FEUADDR_REG 0x44 /* Upper address register */ 80 #define DMAR_AFLOG_REG 0x58 /* Advanced Fault control */ 81 #define DMAR_PMEN_REG 0x64 /* Enable Protected Memory Region */ 82 #define DMAR_PLMBASE_REG 0x68 /* PMRR Low addr */ 83 #define DMAR_PLMLIMIT_REG 0x6c /* PMRR low limit */ 84 #define DMAR_PHMBASE_REG 0x70 /* pmrr high base addr */ 85 #define DMAR_PHMLIMIT_REG 0x78 /* pmrr high limit */ 86 #define DMAR_IQH_REG 0x80 /* Invalidation queue head register */ 87 #define DMAR_IQT_REG 0x88 /* Invalidation queue tail register */ 88 #define DMAR_IQ_SHIFT 4 /* Invalidation queue head/tail shift */ 89 #define DMAR_IQA_REG 0x90 /* Invalidation queue addr register */ 90 #define DMAR_ICS_REG 0x9c /* Invalidation complete status register */ 91 #define DMAR_IQER_REG 0xb0 /* Invalidation queue error record register */ 92 #define DMAR_IRTA_REG 0xb8 /* Interrupt remapping table addr register */ 93 #define DMAR_PQH_REG 0xc0 /* Page request queue head register */ 94 #define DMAR_PQT_REG 0xc8 /* Page request queue tail register */ 95 #define DMAR_PQA_REG 0xd0 /* Page request queue address register */ 96 #define DMAR_PRS_REG 0xdc /* Page request status register */ 97 #define DMAR_PECTL_REG 0xe0 /* Page request event control register */ 98 #define DMAR_PEDATA_REG 0xe4 /* Page request event interrupt data register */ 99 #define DMAR_PEADDR_REG 0xe8 /* Page request event interrupt addr register */ 100 #define DMAR_PEUADDR_REG 0xec /* Page request event Upper address register */ 101 #define DMAR_MTRRCAP_REG 0x100 /* MTRR capability register */ 102 #define DMAR_MTRRDEF_REG 0x108 /* MTRR default type register */ 103 #define DMAR_MTRR_FIX64K_00000_REG 0x120 /* MTRR Fixed range registers */ 104 #define DMAR_MTRR_FIX16K_80000_REG 0x128 105 #define DMAR_MTRR_FIX16K_A0000_REG 0x130 106 #define DMAR_MTRR_FIX4K_C0000_REG 0x138 107 #define DMAR_MTRR_FIX4K_C8000_REG 0x140 108 #define DMAR_MTRR_FIX4K_D0000_REG 0x148 109 #define DMAR_MTRR_FIX4K_D8000_REG 0x150 110 #define DMAR_MTRR_FIX4K_E0000_REG 0x158 111 #define DMAR_MTRR_FIX4K_E8000_REG 0x160 112 #define DMAR_MTRR_FIX4K_F0000_REG 0x168 113 #define DMAR_MTRR_FIX4K_F8000_REG 0x170 114 #define DMAR_MTRR_PHYSBASE0_REG 0x180 /* MTRR Variable range registers */ 115 #define DMAR_MTRR_PHYSMASK0_REG 0x188 116 #define DMAR_MTRR_PHYSBASE1_REG 0x190 117 #define DMAR_MTRR_PHYSMASK1_REG 0x198 118 #define DMAR_MTRR_PHYSBASE2_REG 0x1a0 119 #define DMAR_MTRR_PHYSMASK2_REG 0x1a8 120 #define DMAR_MTRR_PHYSBASE3_REG 0x1b0 121 #define DMAR_MTRR_PHYSMASK3_REG 0x1b8 122 #define DMAR_MTRR_PHYSBASE4_REG 0x1c0 123 #define DMAR_MTRR_PHYSMASK4_REG 0x1c8 124 #define DMAR_MTRR_PHYSBASE5_REG 0x1d0 125 #define DMAR_MTRR_PHYSMASK5_REG 0x1d8 126 #define DMAR_MTRR_PHYSBASE6_REG 0x1e0 127 #define DMAR_MTRR_PHYSMASK6_REG 0x1e8 128 #define DMAR_MTRR_PHYSBASE7_REG 0x1f0 129 #define DMAR_MTRR_PHYSMASK7_REG 0x1f8 130 #define DMAR_MTRR_PHYSBASE8_REG 0x200 131 #define DMAR_MTRR_PHYSMASK8_REG 0x208 132 #define DMAR_MTRR_PHYSBASE9_REG 0x210 133 #define DMAR_MTRR_PHYSMASK9_REG 0x218 134 #define DMAR_PERFCAP_REG 0x300 135 #define DMAR_PERFCFGOFF_REG 0x310 136 #define DMAR_PERFOVFOFF_REG 0x318 137 #define DMAR_PERFCNTROFF_REG 0x31c 138 #define DMAR_PERFINTRSTS_REG 0x324 139 #define DMAR_PERFINTRCTL_REG 0x328 140 #define DMAR_PERFEVNTCAP_REG 0x380 141 #define DMAR_ECMD_REG 0x400 142 #define DMAR_ECEO_REG 0x408 143 #define DMAR_ECRSP_REG 0x410 144 #define DMAR_ECCAP_REG 0x430 145 146 #define DMAR_IQER_REG_IQEI(reg) FIELD_GET(GENMASK_ULL(3, 0), reg) 147 #define DMAR_IQER_REG_ITESID(reg) FIELD_GET(GENMASK_ULL(47, 32), reg) 148 #define DMAR_IQER_REG_ICESID(reg) FIELD_GET(GENMASK_ULL(63, 48), reg) 149 150 #define OFFSET_STRIDE (9) 151 152 #define dmar_readq(a) readq(a) 153 #define dmar_writeq(a,v) writeq(v,a) 154 #define dmar_readl(a) readl(a) 155 #define dmar_writel(a, v) writel(v, a) 156 157 #define DMAR_VER_MAJOR(v) (((v) & 0xf0) >> 4) 158 #define DMAR_VER_MINOR(v) ((v) & 0x0f) 159 160 /* 161 * Decoding Capability Register 162 */ 163 #define cap_esrtps(c) (((c) >> 63) & 1) 164 #define cap_esirtps(c) (((c) >> 62) & 1) 165 #define cap_ecmds(c) (((c) >> 61) & 1) 166 #define cap_fl5lp_support(c) (((c) >> 60) & 1) 167 #define cap_pi_support(c) (((c) >> 59) & 1) 168 #define cap_fl1gp_support(c) (((c) >> 56) & 1) 169 #define cap_read_drain(c) (((c) >> 55) & 1) 170 #define cap_write_drain(c) (((c) >> 54) & 1) 171 #define cap_max_amask_val(c) (((c) >> 48) & 0x3f) 172 #define cap_num_fault_regs(c) ((((c) >> 40) & 0xff) + 1) 173 #define cap_pgsel_inv(c) (((c) >> 39) & 1) 174 175 #define cap_super_page_val(c) (((c) >> 34) & 0xf) 176 #define cap_super_offset(c) (((find_first_bit(&cap_super_page_val(c), 4)) \ 177 * OFFSET_STRIDE) + 21) 178 179 #define cap_fault_reg_offset(c) ((((c) >> 24) & 0x3ff) * 16) 180 #define cap_max_fault_reg_offset(c) \ 181 (cap_fault_reg_offset(c) + cap_num_fault_regs(c) * 16) 182 183 #define cap_zlr(c) (((c) >> 22) & 1) 184 #define cap_isoch(c) (((c) >> 23) & 1) 185 #define cap_mgaw(c) ((((c) >> 16) & 0x3f) + 1) 186 #define cap_sagaw(c) (((c) >> 8) & 0x1f) 187 #define cap_caching_mode(c) (((c) >> 7) & 1) 188 #define cap_phmr(c) (((c) >> 6) & 1) 189 #define cap_plmr(c) (((c) >> 5) & 1) 190 #define cap_rwbf(c) (((c) >> 4) & 1) 191 #define cap_afl(c) (((c) >> 3) & 1) 192 #define cap_ndoms(c) (((unsigned long)1) << (4 + 2 * ((c) & 0x7))) 193 /* 194 * Extended Capability Register 195 */ 196 197 #define ecap_pms(e) (((e) >> 51) & 0x1) 198 #define ecap_rps(e) (((e) >> 49) & 0x1) 199 #define ecap_smpwc(e) (((e) >> 48) & 0x1) 200 #define ecap_flts(e) (((e) >> 47) & 0x1) 201 #define ecap_slts(e) (((e) >> 46) & 0x1) 202 #define ecap_slads(e) (((e) >> 45) & 0x1) 203 #define ecap_smts(e) (((e) >> 43) & 0x1) 204 #define ecap_dit(e) (((e) >> 41) & 0x1) 205 #define ecap_pds(e) (((e) >> 42) & 0x1) 206 #define ecap_pasid(e) (((e) >> 40) & 0x1) 207 #define ecap_pss(e) (((e) >> 35) & 0x1f) 208 #define ecap_eafs(e) (((e) >> 34) & 0x1) 209 #define ecap_nwfs(e) (((e) >> 33) & 0x1) 210 #define ecap_srs(e) (((e) >> 31) & 0x1) 211 #define ecap_ers(e) (((e) >> 30) & 0x1) 212 #define ecap_prs(e) (((e) >> 29) & 0x1) 213 #define ecap_broken_pasid(e) (((e) >> 28) & 0x1) 214 #define ecap_dis(e) (((e) >> 27) & 0x1) 215 #define ecap_nest(e) (((e) >> 26) & 0x1) 216 #define ecap_mts(e) (((e) >> 25) & 0x1) 217 #define ecap_iotlb_offset(e) ((((e) >> 8) & 0x3ff) * 16) 218 #define ecap_max_iotlb_offset(e) (ecap_iotlb_offset(e) + 16) 219 #define ecap_coherent(e) ((e) & 0x1) 220 #define ecap_qis(e) ((e) & 0x2) 221 #define ecap_pass_through(e) (((e) >> 6) & 0x1) 222 #define ecap_eim_support(e) (((e) >> 4) & 0x1) 223 #define ecap_ir_support(e) (((e) >> 3) & 0x1) 224 #define ecap_dev_iotlb_support(e) (((e) >> 2) & 0x1) 225 #define ecap_max_handle_mask(e) (((e) >> 20) & 0xf) 226 #define ecap_sc_support(e) (((e) >> 7) & 0x1) /* Snooping Control */ 227 228 /* 229 * Decoding Perf Capability Register 230 */ 231 #define pcap_num_cntr(p) ((p) & 0xffff) 232 #define pcap_cntr_width(p) (((p) >> 16) & 0x7f) 233 #define pcap_num_event_group(p) (((p) >> 24) & 0x1f) 234 #define pcap_filters_mask(p) (((p) >> 32) & 0x1f) 235 #define pcap_interrupt(p) (((p) >> 50) & 0x1) 236 /* The counter stride is calculated as 2 ^ (x+10) bytes */ 237 #define pcap_cntr_stride(p) (1ULL << ((((p) >> 52) & 0x7) + 10)) 238 239 /* 240 * Decoding Perf Event Capability Register 241 */ 242 #define pecap_es(p) ((p) & 0xfffffff) 243 244 /* Virtual command interface capability */ 245 #define vccap_pasid(v) (((v) & DMA_VCS_PAS)) /* PASID allocation */ 246 247 /* IOTLB_REG */ 248 #define DMA_TLB_FLUSH_GRANU_OFFSET 60 249 #define DMA_TLB_GLOBAL_FLUSH (((u64)1) << 60) 250 #define DMA_TLB_DSI_FLUSH (((u64)2) << 60) 251 #define DMA_TLB_PSI_FLUSH (((u64)3) << 60) 252 #define DMA_TLB_IIRG(type) ((type >> 60) & 3) 253 #define DMA_TLB_IAIG(val) (((val) >> 57) & 3) 254 #define DMA_TLB_READ_DRAIN (((u64)1) << 49) 255 #define DMA_TLB_WRITE_DRAIN (((u64)1) << 48) 256 #define DMA_TLB_DID(id) (((u64)((id) & 0xffff)) << 32) 257 #define DMA_TLB_IVT (((u64)1) << 63) 258 #define DMA_TLB_IH_NONLEAF (((u64)1) << 6) 259 #define DMA_TLB_MAX_SIZE (0x3f) 260 261 /* INVALID_DESC */ 262 #define DMA_CCMD_INVL_GRANU_OFFSET 61 263 #define DMA_ID_TLB_GLOBAL_FLUSH (((u64)1) << 4) 264 #define DMA_ID_TLB_DSI_FLUSH (((u64)2) << 4) 265 #define DMA_ID_TLB_PSI_FLUSH (((u64)3) << 4) 266 #define DMA_ID_TLB_READ_DRAIN (((u64)1) << 7) 267 #define DMA_ID_TLB_WRITE_DRAIN (((u64)1) << 6) 268 #define DMA_ID_TLB_DID(id) (((u64)((id & 0xffff) << 16))) 269 #define DMA_ID_TLB_IH_NONLEAF (((u64)1) << 6) 270 #define DMA_ID_TLB_ADDR(addr) (addr) 271 #define DMA_ID_TLB_ADDR_MASK(mask) (mask) 272 273 /* PMEN_REG */ 274 #define DMA_PMEN_EPM (((u32)1)<<31) 275 #define DMA_PMEN_PRS (((u32)1)<<0) 276 277 /* GCMD_REG */ 278 #define DMA_GCMD_TE (((u32)1) << 31) 279 #define DMA_GCMD_SRTP (((u32)1) << 30) 280 #define DMA_GCMD_SFL (((u32)1) << 29) 281 #define DMA_GCMD_EAFL (((u32)1) << 28) 282 #define DMA_GCMD_WBF (((u32)1) << 27) 283 #define DMA_GCMD_QIE (((u32)1) << 26) 284 #define DMA_GCMD_SIRTP (((u32)1) << 24) 285 #define DMA_GCMD_IRE (((u32) 1) << 25) 286 #define DMA_GCMD_CFI (((u32) 1) << 23) 287 288 /* GSTS_REG */ 289 #define DMA_GSTS_TES (((u32)1) << 31) 290 #define DMA_GSTS_RTPS (((u32)1) << 30) 291 #define DMA_GSTS_FLS (((u32)1) << 29) 292 #define DMA_GSTS_AFLS (((u32)1) << 28) 293 #define DMA_GSTS_WBFS (((u32)1) << 27) 294 #define DMA_GSTS_QIES (((u32)1) << 26) 295 #define DMA_GSTS_IRTPS (((u32)1) << 24) 296 #define DMA_GSTS_IRES (((u32)1) << 25) 297 #define DMA_GSTS_CFIS (((u32)1) << 23) 298 299 /* DMA_RTADDR_REG */ 300 #define DMA_RTADDR_SMT (((u64)1) << 10) 301 302 /* CCMD_REG */ 303 #define DMA_CCMD_ICC (((u64)1) << 63) 304 #define DMA_CCMD_GLOBAL_INVL (((u64)1) << 61) 305 #define DMA_CCMD_DOMAIN_INVL (((u64)2) << 61) 306 #define DMA_CCMD_DEVICE_INVL (((u64)3) << 61) 307 #define DMA_CCMD_FM(m) (((u64)((m) & 0x3)) << 32) 308 #define DMA_CCMD_MASK_NOBIT 0 309 #define DMA_CCMD_MASK_1BIT 1 310 #define DMA_CCMD_MASK_2BIT 2 311 #define DMA_CCMD_MASK_3BIT 3 312 #define DMA_CCMD_SID(s) (((u64)((s) & 0xffff)) << 16) 313 #define DMA_CCMD_DID(d) ((u64)((d) & 0xffff)) 314 315 /* ECMD_REG */ 316 #define DMA_MAX_NUM_ECMD 256 317 #define DMA_MAX_NUM_ECMDCAP (DMA_MAX_NUM_ECMD / 64) 318 #define DMA_ECMD_REG_STEP 8 319 #define DMA_ECMD_ENABLE 0xf0 320 #define DMA_ECMD_DISABLE 0xf1 321 #define DMA_ECMD_FREEZE 0xf4 322 #define DMA_ECMD_UNFREEZE 0xf5 323 #define DMA_ECMD_OA_SHIFT 16 324 #define DMA_ECMD_ECRSP_IP 0x1 325 #define DMA_ECMD_ECCAP3 3 326 #define DMA_ECMD_ECCAP3_ECNTS BIT_ULL(48) 327 #define DMA_ECMD_ECCAP3_DCNTS BIT_ULL(49) 328 #define DMA_ECMD_ECCAP3_FCNTS BIT_ULL(52) 329 #define DMA_ECMD_ECCAP3_UFCNTS BIT_ULL(53) 330 #define DMA_ECMD_ECCAP3_ESSENTIAL (DMA_ECMD_ECCAP3_ECNTS | \ 331 DMA_ECMD_ECCAP3_DCNTS | \ 332 DMA_ECMD_ECCAP3_FCNTS | \ 333 DMA_ECMD_ECCAP3_UFCNTS) 334 335 /* FECTL_REG */ 336 #define DMA_FECTL_IM (((u32)1) << 31) 337 338 /* FSTS_REG */ 339 #define DMA_FSTS_PFO (1 << 0) /* Primary Fault Overflow */ 340 #define DMA_FSTS_PPF (1 << 1) /* Primary Pending Fault */ 341 #define DMA_FSTS_IQE (1 << 4) /* Invalidation Queue Error */ 342 #define DMA_FSTS_ICE (1 << 5) /* Invalidation Completion Error */ 343 #define DMA_FSTS_ITE (1 << 6) /* Invalidation Time-out Error */ 344 #define DMA_FSTS_PRO (1 << 7) /* Page Request Overflow */ 345 #define dma_fsts_fault_record_index(s) (((s) >> 8) & 0xff) 346 347 /* FRCD_REG, 32 bits access */ 348 #define DMA_FRCD_F (((u32)1) << 31) 349 #define dma_frcd_type(d) ((d >> 30) & 1) 350 #define dma_frcd_fault_reason(c) (c & 0xff) 351 #define dma_frcd_source_id(c) (c & 0xffff) 352 #define dma_frcd_pasid_value(c) (((c) >> 8) & 0xfffff) 353 #define dma_frcd_pasid_present(c) (((c) >> 31) & 1) 354 /* low 64 bit */ 355 #define dma_frcd_page_addr(d) (d & (((u64)-1) << PAGE_SHIFT)) 356 357 /* PRS_REG */ 358 #define DMA_PRS_PPR ((u32)1) 359 #define DMA_PRS_PRO ((u32)2) 360 361 #define DMA_VCS_PAS ((u64)1) 362 363 /* PERFINTRSTS_REG */ 364 #define DMA_PERFINTRSTS_PIS ((u32)1) 365 366 #define IOMMU_WAIT_OP(iommu, offset, op, cond, sts) \ 367 do { \ 368 cycles_t start_time = get_cycles(); \ 369 while (1) { \ 370 sts = op(iommu->reg + offset); \ 371 if (cond) \ 372 break; \ 373 if (DMAR_OPERATION_TIMEOUT < (get_cycles() - start_time))\ 374 panic("DMAR hardware is malfunctioning\n"); \ 375 cpu_relax(); \ 376 } \ 377 } while (0) 378 379 #define QI_LENGTH 256 /* queue length */ 380 381 enum { 382 QI_FREE, 383 QI_IN_USE, 384 QI_DONE, 385 QI_ABORT 386 }; 387 388 #define QI_CC_TYPE 0x1 389 #define QI_IOTLB_TYPE 0x2 390 #define QI_DIOTLB_TYPE 0x3 391 #define QI_IEC_TYPE 0x4 392 #define QI_IWD_TYPE 0x5 393 #define QI_EIOTLB_TYPE 0x6 394 #define QI_PC_TYPE 0x7 395 #define QI_DEIOTLB_TYPE 0x8 396 #define QI_PGRP_RESP_TYPE 0x9 397 #define QI_PSTRM_RESP_TYPE 0xa 398 399 #define QI_IEC_SELECTIVE (((u64)1) << 4) 400 #define QI_IEC_IIDEX(idx) (((u64)(idx & 0xffff) << 32)) 401 #define QI_IEC_IM(m) (((u64)(m & 0x1f) << 27)) 402 403 #define QI_IWD_STATUS_DATA(d) (((u64)d) << 32) 404 #define QI_IWD_STATUS_WRITE (((u64)1) << 5) 405 #define QI_IWD_FENCE (((u64)1) << 6) 406 #define QI_IWD_PRQ_DRAIN (((u64)1) << 7) 407 408 #define QI_IOTLB_DID(did) (((u64)did) << 16) 409 #define QI_IOTLB_DR(dr) (((u64)dr) << 7) 410 #define QI_IOTLB_DW(dw) (((u64)dw) << 6) 411 #define QI_IOTLB_GRAN(gran) (((u64)gran) >> (DMA_TLB_FLUSH_GRANU_OFFSET-4)) 412 #define QI_IOTLB_ADDR(addr) (((u64)addr) & VTD_PAGE_MASK) 413 #define QI_IOTLB_IH(ih) (((u64)ih) << 6) 414 #define QI_IOTLB_AM(am) (((u8)am) & 0x3f) 415 416 #define QI_CC_FM(fm) (((u64)fm) << 48) 417 #define QI_CC_SID(sid) (((u64)sid) << 32) 418 #define QI_CC_DID(did) (((u64)did) << 16) 419 #define QI_CC_GRAN(gran) (((u64)gran) >> (DMA_CCMD_INVL_GRANU_OFFSET-4)) 420 421 #define QI_DEV_IOTLB_SID(sid) ((u64)((sid) & 0xffff) << 32) 422 #define QI_DEV_IOTLB_QDEP(qdep) (((qdep) & 0x1f) << 16) 423 #define QI_DEV_IOTLB_ADDR(addr) ((u64)(addr) & VTD_PAGE_MASK) 424 #define QI_DEV_IOTLB_PFSID(pfsid) (((u64)(pfsid & 0xf) << 12) | \ 425 ((u64)((pfsid >> 4) & 0xfff) << 52)) 426 #define QI_DEV_IOTLB_SIZE 1 427 #define QI_DEV_IOTLB_MAX_INVS 32 428 429 #define QI_PC_PASID(pasid) (((u64)pasid) << 32) 430 #define QI_PC_DID(did) (((u64)did) << 16) 431 #define QI_PC_GRAN(gran) (((u64)gran) << 4) 432 433 /* PASID cache invalidation granu */ 434 #define QI_PC_ALL_PASIDS 0 435 #define QI_PC_PASID_SEL 1 436 #define QI_PC_GLOBAL 3 437 438 #define QI_EIOTLB_ADDR(addr) ((u64)(addr) & VTD_PAGE_MASK) 439 #define QI_EIOTLB_IH(ih) (((u64)ih) << 6) 440 #define QI_EIOTLB_AM(am) (((u64)am) & 0x3f) 441 #define QI_EIOTLB_PASID(pasid) (((u64)pasid) << 32) 442 #define QI_EIOTLB_DID(did) (((u64)did) << 16) 443 #define QI_EIOTLB_GRAN(gran) (((u64)gran) << 4) 444 445 /* QI Dev-IOTLB inv granu */ 446 #define QI_DEV_IOTLB_GRAN_ALL 1 447 #define QI_DEV_IOTLB_GRAN_PASID_SEL 0 448 449 #define QI_DEV_EIOTLB_ADDR(a) ((u64)(a) & VTD_PAGE_MASK) 450 #define QI_DEV_EIOTLB_SIZE (((u64)1) << 11) 451 #define QI_DEV_EIOTLB_PASID(p) ((u64)((p) & 0xfffff) << 32) 452 #define QI_DEV_EIOTLB_SID(sid) ((u64)((sid) & 0xffff) << 16) 453 #define QI_DEV_EIOTLB_QDEP(qd) ((u64)((qd) & 0x1f) << 4) 454 #define QI_DEV_EIOTLB_PFSID(pfsid) (((u64)(pfsid & 0xf) << 12) | \ 455 ((u64)((pfsid >> 4) & 0xfff) << 52)) 456 #define QI_DEV_EIOTLB_MAX_INVS 32 457 458 /* Page group response descriptor QW0 */ 459 #define QI_PGRP_PASID_P(p) (((u64)(p)) << 4) 460 #define QI_PGRP_RESP_CODE(res) (((u64)(res)) << 12) 461 #define QI_PGRP_DID(rid) (((u64)(rid)) << 16) 462 #define QI_PGRP_PASID(pasid) (((u64)(pasid)) << 32) 463 464 /* Page group response descriptor QW1 */ 465 #define QI_PGRP_LPIG(x) (((u64)(x)) << 2) 466 #define QI_PGRP_IDX(idx) (((u64)(idx)) << 3) 467 468 469 #define QI_RESP_SUCCESS 0x0 470 #define QI_RESP_INVALID 0x1 471 #define QI_RESP_FAILURE 0xf 472 473 #define QI_GRAN_NONG_PASID 2 474 #define QI_GRAN_PSI_PASID 3 475 476 #define qi_shift(iommu) (DMAR_IQ_SHIFT + !!ecap_smts((iommu)->ecap)) 477 478 struct qi_desc { 479 u64 qw0; 480 u64 qw1; 481 u64 qw2; 482 u64 qw3; 483 }; 484 485 struct q_inval { 486 raw_spinlock_t q_lock; 487 void *desc; /* invalidation queue */ 488 int *desc_status; /* desc status */ 489 int free_head; /* first free entry */ 490 int free_tail; /* last free entry */ 491 int free_cnt; 492 }; 493 494 /* Page Request Queue depth */ 495 #define PRQ_ORDER 4 496 #define PRQ_RING_MASK ((0x1000 << PRQ_ORDER) - 0x20) 497 #define PRQ_DEPTH ((0x1000 << PRQ_ORDER) >> 5) 498 499 struct dmar_pci_notify_info; 500 501 #ifdef CONFIG_IRQ_REMAP 502 /* 1MB - maximum possible interrupt remapping table size */ 503 #define INTR_REMAP_PAGE_ORDER 8 504 #define INTR_REMAP_TABLE_REG_SIZE 0xf 505 #define INTR_REMAP_TABLE_REG_SIZE_MASK 0xf 506 507 #define INTR_REMAP_TABLE_ENTRIES 65536 508 509 struct irq_domain; 510 511 struct ir_table { 512 struct irte *base; 513 unsigned long *bitmap; 514 }; 515 516 void intel_irq_remap_add_device(struct dmar_pci_notify_info *info); 517 #else 518 static inline void 519 intel_irq_remap_add_device(struct dmar_pci_notify_info *info) { } 520 #endif 521 522 struct iommu_flush { 523 void (*flush_context)(struct intel_iommu *iommu, u16 did, u16 sid, 524 u8 fm, u64 type); 525 void (*flush_iotlb)(struct intel_iommu *iommu, u16 did, u64 addr, 526 unsigned int size_order, u64 type); 527 }; 528 529 enum { 530 SR_DMAR_FECTL_REG, 531 SR_DMAR_FEDATA_REG, 532 SR_DMAR_FEADDR_REG, 533 SR_DMAR_FEUADDR_REG, 534 MAX_SR_DMAR_REGS 535 }; 536 537 #define VTD_FLAG_TRANS_PRE_ENABLED (1 << 0) 538 #define VTD_FLAG_IRQ_REMAP_PRE_ENABLED (1 << 1) 539 #define VTD_FLAG_SVM_CAPABLE (1 << 2) 540 541 #define sm_supported(iommu) (intel_iommu_sm && ecap_smts((iommu)->ecap)) 542 #define pasid_supported(iommu) (sm_supported(iommu) && \ 543 ecap_pasid((iommu)->ecap)) 544 #define ssads_supported(iommu) (sm_supported(iommu) && \ 545 ecap_slads((iommu)->ecap)) 546 #define nested_supported(iommu) (sm_supported(iommu) && \ 547 ecap_nest((iommu)->ecap)) 548 549 struct pasid_entry; 550 struct pasid_state_entry; 551 struct page_req_dsc; 552 553 /* 554 * 0: Present 555 * 1-11: Reserved 556 * 12-63: Context Ptr (12 - (haw-1)) 557 * 64-127: Reserved 558 */ 559 struct root_entry { 560 u64 lo; 561 u64 hi; 562 }; 563 564 /* 565 * low 64 bits: 566 * 0: present 567 * 1: fault processing disable 568 * 2-3: translation type 569 * 12-63: address space root 570 * high 64 bits: 571 * 0-2: address width 572 * 3-6: aval 573 * 8-23: domain id 574 */ 575 struct context_entry { 576 u64 lo; 577 u64 hi; 578 }; 579 580 struct iommu_domain_info { 581 struct intel_iommu *iommu; 582 unsigned int refcnt; /* Refcount of devices per iommu */ 583 u16 did; /* Domain ids per IOMMU. Use u16 since 584 * domain ids are 16 bit wide according 585 * to VT-d spec, section 9.3 */ 586 }; 587 588 struct dmar_domain { 589 int nid; /* node id */ 590 struct xarray iommu_array; /* Attached IOMMU array */ 591 592 u8 has_iotlb_device: 1; 593 u8 iommu_coherency: 1; /* indicate coherency of iommu access */ 594 u8 force_snooping : 1; /* Create IOPTEs with snoop control */ 595 u8 set_pte_snp:1; 596 u8 use_first_level:1; /* DMA translation for the domain goes 597 * through the first level page table, 598 * otherwise, goes through the second 599 * level. 600 */ 601 u8 dirty_tracking:1; /* Dirty tracking is enabled */ 602 u8 nested_parent:1; /* Has other domains nested on it */ 603 u8 has_mappings:1; /* Has mappings configured through 604 * iommu_map() interface. 605 */ 606 607 spinlock_t lock; /* Protect device tracking lists */ 608 struct list_head devices; /* all devices' list */ 609 struct list_head dev_pasids; /* all attached pasids */ 610 611 spinlock_t cache_lock; /* Protect the cache tag list */ 612 struct list_head cache_tags; /* Cache tag list */ 613 614 int iommu_superpage;/* Level of superpages supported: 615 0 == 4KiB (no superpages), 1 == 2MiB, 616 2 == 1GiB, 3 == 512GiB, 4 == 1TiB */ 617 union { 618 /* DMA remapping domain */ 619 struct { 620 /* virtual address */ 621 struct dma_pte *pgd; 622 /* max guest address width */ 623 int gaw; 624 /* 625 * adjusted guest address width: 626 * 0: level 2 30-bit 627 * 1: level 3 39-bit 628 * 2: level 4 48-bit 629 * 3: level 5 57-bit 630 */ 631 int agaw; 632 /* maximum mapped address */ 633 u64 max_addr; 634 /* Protect the s1_domains list */ 635 spinlock_t s1_lock; 636 /* Track s1_domains nested on this domain */ 637 struct list_head s1_domains; 638 }; 639 640 /* Nested user domain */ 641 struct { 642 /* parent page table which the user domain is nested on */ 643 struct dmar_domain *s2_domain; 644 /* user page table pointer (in GPA) */ 645 unsigned long s1_pgtbl; 646 /* page table attributes */ 647 struct iommu_hwpt_vtd_s1 s1_cfg; 648 /* link to parent domain siblings */ 649 struct list_head s2_link; 650 }; 651 652 /* SVA domain */ 653 struct { 654 struct mmu_notifier notifier; 655 }; 656 }; 657 658 struct iommu_domain domain; /* generic domain data structure for 659 iommu core */ 660 }; 661 662 /* 663 * In theory, the VT-d 4.0 spec can support up to 2 ^ 16 counters. 664 * But in practice, there are only 14 counters for the existing 665 * platform. Setting the max number of counters to 64 should be good 666 * enough for a long time. Also, supporting more than 64 counters 667 * requires more extras, e.g., extra freeze and overflow registers, 668 * which is not necessary for now. 669 */ 670 #define IOMMU_PMU_IDX_MAX 64 671 672 struct iommu_pmu { 673 struct intel_iommu *iommu; 674 u32 num_cntr; /* Number of counters */ 675 u32 num_eg; /* Number of event group */ 676 u32 cntr_width; /* Counter width */ 677 u32 cntr_stride; /* Counter Stride */ 678 u32 filter; /* Bitmask of filter support */ 679 void __iomem *base; /* the PerfMon base address */ 680 void __iomem *cfg_reg; /* counter configuration base address */ 681 void __iomem *cntr_reg; /* counter 0 address*/ 682 void __iomem *overflow; /* overflow status register */ 683 684 u64 *evcap; /* Indicates all supported events */ 685 u32 **cntr_evcap; /* Supported events of each counter. */ 686 687 struct pmu pmu; 688 DECLARE_BITMAP(used_mask, IOMMU_PMU_IDX_MAX); 689 struct perf_event *event_list[IOMMU_PMU_IDX_MAX]; 690 unsigned char irq_name[16]; 691 struct hlist_node cpuhp_node; 692 int cpu; 693 }; 694 695 #define IOMMU_IRQ_ID_OFFSET_PRQ (DMAR_UNITS_SUPPORTED) 696 #define IOMMU_IRQ_ID_OFFSET_PERF (2 * DMAR_UNITS_SUPPORTED) 697 698 struct intel_iommu { 699 void __iomem *reg; /* Pointer to hardware regs, virtual addr */ 700 u64 reg_phys; /* physical address of hw register set */ 701 u64 reg_size; /* size of hw register set */ 702 u64 cap; 703 u64 ecap; 704 u64 vccap; 705 u64 ecmdcap[DMA_MAX_NUM_ECMDCAP]; 706 u32 gcmd; /* Holds TE, EAFL. Don't need SRTP, SFL, WBF */ 707 raw_spinlock_t register_lock; /* protect register handling */ 708 int seq_id; /* sequence id of the iommu */ 709 int agaw; /* agaw of this iommu */ 710 int msagaw; /* max sagaw of this iommu */ 711 unsigned int irq, pr_irq, perf_irq; 712 u16 segment; /* PCI segment# */ 713 unsigned char name[13]; /* Device Name */ 714 715 #ifdef CONFIG_INTEL_IOMMU 716 unsigned long *domain_ids; /* bitmap of domains */ 717 unsigned long *copied_tables; /* bitmap of copied tables */ 718 spinlock_t lock; /* protect context, domain ids */ 719 struct root_entry *root_entry; /* virtual address */ 720 721 struct iommu_flush flush; 722 #endif 723 #ifdef CONFIG_INTEL_IOMMU_SVM 724 struct page_req_dsc *prq; 725 unsigned char prq_name[16]; /* Name for PRQ interrupt */ 726 unsigned long prq_seq_number; 727 struct completion prq_complete; 728 #endif 729 struct iopf_queue *iopf_queue; 730 unsigned char iopfq_name[16]; 731 /* Synchronization between fault report and iommu device release. */ 732 struct mutex iopf_lock; 733 struct q_inval *qi; /* Queued invalidation info */ 734 u32 iommu_state[MAX_SR_DMAR_REGS]; /* Store iommu states between suspend and resume.*/ 735 736 /* rb tree for all probed devices */ 737 struct rb_root device_rbtree; 738 /* protect the device_rbtree */ 739 spinlock_t device_rbtree_lock; 740 741 #ifdef CONFIG_IRQ_REMAP 742 struct ir_table *ir_table; /* Interrupt remapping info */ 743 struct irq_domain *ir_domain; 744 #endif 745 struct iommu_device iommu; /* IOMMU core code handle */ 746 int node; 747 u32 flags; /* Software defined flags */ 748 749 struct dmar_drhd_unit *drhd; 750 void *perf_statistic; 751 752 struct iommu_pmu *pmu; 753 }; 754 755 /* PCI domain-device relationship */ 756 struct device_domain_info { 757 struct list_head link; /* link to domain siblings */ 758 u32 segment; /* PCI segment number */ 759 u8 bus; /* PCI bus number */ 760 u8 devfn; /* PCI devfn number */ 761 u16 pfsid; /* SRIOV physical function source ID */ 762 u8 pasid_supported:3; 763 u8 pasid_enabled:1; 764 u8 pri_supported:1; 765 u8 pri_enabled:1; 766 u8 ats_supported:1; 767 u8 ats_enabled:1; 768 u8 dtlb_extra_inval:1; /* Quirk for devices need extra flush */ 769 u8 ats_qdep; 770 struct device *dev; /* it's NULL for PCIe-to-PCI bridge */ 771 struct intel_iommu *iommu; /* IOMMU used by this device */ 772 struct dmar_domain *domain; /* pointer to domain */ 773 struct pasid_table *pasid_table; /* pasid table */ 774 /* device tracking node(lookup by PCI RID) */ 775 struct rb_node node; 776 #ifdef CONFIG_INTEL_IOMMU_DEBUGFS 777 struct dentry *debugfs_dentry; /* pointer to device directory dentry */ 778 #endif 779 }; 780 781 struct dev_pasid_info { 782 struct list_head link_domain; /* link to domain siblings */ 783 struct device *dev; 784 ioasid_t pasid; 785 #ifdef CONFIG_INTEL_IOMMU_DEBUGFS 786 struct dentry *debugfs_dentry; /* pointer to pasid directory dentry */ 787 #endif 788 }; 789 790 static inline void __iommu_flush_cache( 791 struct intel_iommu *iommu, void *addr, int size) 792 { 793 if (!ecap_coherent(iommu->ecap)) 794 clflush_cache_range(addr, size); 795 } 796 797 /* Convert generic struct iommu_domain to private struct dmar_domain */ 798 static inline struct dmar_domain *to_dmar_domain(struct iommu_domain *dom) 799 { 800 return container_of(dom, struct dmar_domain, domain); 801 } 802 803 /* Retrieve the domain ID which has allocated to the domain */ 804 static inline u16 805 domain_id_iommu(struct dmar_domain *domain, struct intel_iommu *iommu) 806 { 807 struct iommu_domain_info *info = 808 xa_load(&domain->iommu_array, iommu->seq_id); 809 810 return info->did; 811 } 812 813 /* 814 * 0: readable 815 * 1: writable 816 * 2-6: reserved 817 * 7: super page 818 * 8-10: available 819 * 11: snoop behavior 820 * 12-63: Host physical address 821 */ 822 struct dma_pte { 823 u64 val; 824 }; 825 826 static inline void dma_clear_pte(struct dma_pte *pte) 827 { 828 pte->val = 0; 829 } 830 831 static inline u64 dma_pte_addr(struct dma_pte *pte) 832 { 833 #ifdef CONFIG_64BIT 834 return pte->val & VTD_PAGE_MASK & (~DMA_FL_PTE_XD); 835 #else 836 /* Must have a full atomic 64-bit read */ 837 return __cmpxchg64(&pte->val, 0ULL, 0ULL) & 838 VTD_PAGE_MASK & (~DMA_FL_PTE_XD); 839 #endif 840 } 841 842 static inline bool dma_pte_present(struct dma_pte *pte) 843 { 844 return (pte->val & 3) != 0; 845 } 846 847 static inline bool dma_sl_pte_test_and_clear_dirty(struct dma_pte *pte, 848 unsigned long flags) 849 { 850 if (flags & IOMMU_DIRTY_NO_CLEAR) 851 return (pte->val & DMA_SL_PTE_DIRTY) != 0; 852 853 return test_and_clear_bit(DMA_SL_PTE_DIRTY_BIT, 854 (unsigned long *)&pte->val); 855 } 856 857 static inline bool dma_pte_superpage(struct dma_pte *pte) 858 { 859 return (pte->val & DMA_PTE_LARGE_PAGE); 860 } 861 862 static inline bool first_pte_in_page(struct dma_pte *pte) 863 { 864 return IS_ALIGNED((unsigned long)pte, VTD_PAGE_SIZE); 865 } 866 867 static inline int nr_pte_to_next_page(struct dma_pte *pte) 868 { 869 return first_pte_in_page(pte) ? BIT_ULL(VTD_STRIDE_SHIFT) : 870 (struct dma_pte *)ALIGN((unsigned long)pte, VTD_PAGE_SIZE) - pte; 871 } 872 873 static inline bool context_present(struct context_entry *context) 874 { 875 return (context->lo & 1); 876 } 877 878 #define LEVEL_STRIDE (9) 879 #define LEVEL_MASK (((u64)1 << LEVEL_STRIDE) - 1) 880 #define MAX_AGAW_WIDTH (64) 881 #define MAX_AGAW_PFN_WIDTH (MAX_AGAW_WIDTH - VTD_PAGE_SHIFT) 882 883 static inline int agaw_to_level(int agaw) 884 { 885 return agaw + 2; 886 } 887 888 static inline int agaw_to_width(int agaw) 889 { 890 return min_t(int, 30 + agaw * LEVEL_STRIDE, MAX_AGAW_WIDTH); 891 } 892 893 static inline int width_to_agaw(int width) 894 { 895 return DIV_ROUND_UP(width - 30, LEVEL_STRIDE); 896 } 897 898 static inline unsigned int level_to_offset_bits(int level) 899 { 900 return (level - 1) * LEVEL_STRIDE; 901 } 902 903 static inline int pfn_level_offset(u64 pfn, int level) 904 { 905 return (pfn >> level_to_offset_bits(level)) & LEVEL_MASK; 906 } 907 908 static inline u64 level_mask(int level) 909 { 910 return -1ULL << level_to_offset_bits(level); 911 } 912 913 static inline u64 level_size(int level) 914 { 915 return 1ULL << level_to_offset_bits(level); 916 } 917 918 static inline u64 align_to_level(u64 pfn, int level) 919 { 920 return (pfn + level_size(level) - 1) & level_mask(level); 921 } 922 923 static inline unsigned long lvl_to_nr_pages(unsigned int lvl) 924 { 925 return 1UL << min_t(int, (lvl - 1) * LEVEL_STRIDE, MAX_AGAW_PFN_WIDTH); 926 } 927 928 /* VT-d pages must always be _smaller_ than MM pages. Otherwise things 929 are never going to work. */ 930 static inline unsigned long mm_to_dma_pfn_start(unsigned long mm_pfn) 931 { 932 return mm_pfn << (PAGE_SHIFT - VTD_PAGE_SHIFT); 933 } 934 static inline unsigned long mm_to_dma_pfn_end(unsigned long mm_pfn) 935 { 936 return ((mm_pfn + 1) << (PAGE_SHIFT - VTD_PAGE_SHIFT)) - 1; 937 } 938 static inline unsigned long page_to_dma_pfn(struct page *pg) 939 { 940 return mm_to_dma_pfn_start(page_to_pfn(pg)); 941 } 942 static inline unsigned long virt_to_dma_pfn(void *p) 943 { 944 return page_to_dma_pfn(virt_to_page(p)); 945 } 946 947 static inline void context_set_present(struct context_entry *context) 948 { 949 context->lo |= 1; 950 } 951 952 static inline void context_set_fault_enable(struct context_entry *context) 953 { 954 context->lo &= (((u64)-1) << 2) | 1; 955 } 956 957 static inline void context_set_translation_type(struct context_entry *context, 958 unsigned long value) 959 { 960 context->lo &= (((u64)-1) << 4) | 3; 961 context->lo |= (value & 3) << 2; 962 } 963 964 static inline void context_set_address_root(struct context_entry *context, 965 unsigned long value) 966 { 967 context->lo &= ~VTD_PAGE_MASK; 968 context->lo |= value & VTD_PAGE_MASK; 969 } 970 971 static inline void context_set_address_width(struct context_entry *context, 972 unsigned long value) 973 { 974 context->hi |= value & 7; 975 } 976 977 static inline void context_set_domain_id(struct context_entry *context, 978 unsigned long value) 979 { 980 context->hi |= (value & ((1 << 16) - 1)) << 8; 981 } 982 983 static inline void context_set_pasid(struct context_entry *context) 984 { 985 context->lo |= CONTEXT_PASIDE; 986 } 987 988 static inline int context_domain_id(struct context_entry *c) 989 { 990 return((c->hi >> 8) & 0xffff); 991 } 992 993 static inline void context_clear_entry(struct context_entry *context) 994 { 995 context->lo = 0; 996 context->hi = 0; 997 } 998 999 #ifdef CONFIG_INTEL_IOMMU 1000 static inline bool context_copied(struct intel_iommu *iommu, u8 bus, u8 devfn) 1001 { 1002 if (!iommu->copied_tables) 1003 return false; 1004 1005 return test_bit(((long)bus << 8) | devfn, iommu->copied_tables); 1006 } 1007 1008 static inline void 1009 set_context_copied(struct intel_iommu *iommu, u8 bus, u8 devfn) 1010 { 1011 set_bit(((long)bus << 8) | devfn, iommu->copied_tables); 1012 } 1013 1014 static inline void 1015 clear_context_copied(struct intel_iommu *iommu, u8 bus, u8 devfn) 1016 { 1017 clear_bit(((long)bus << 8) | devfn, iommu->copied_tables); 1018 } 1019 #endif /* CONFIG_INTEL_IOMMU */ 1020 1021 /* 1022 * Set the RID_PASID field of a scalable mode context entry. The 1023 * IOMMU hardware will use the PASID value set in this field for 1024 * DMA translations of DMA requests without PASID. 1025 */ 1026 static inline void 1027 context_set_sm_rid2pasid(struct context_entry *context, unsigned long pasid) 1028 { 1029 context->hi |= pasid & ((1 << 20) - 1); 1030 } 1031 1032 /* 1033 * Set the DTE(Device-TLB Enable) field of a scalable mode context 1034 * entry. 1035 */ 1036 static inline void context_set_sm_dte(struct context_entry *context) 1037 { 1038 context->lo |= BIT_ULL(2); 1039 } 1040 1041 /* 1042 * Set the PRE(Page Request Enable) field of a scalable mode context 1043 * entry. 1044 */ 1045 static inline void context_set_sm_pre(struct context_entry *context) 1046 { 1047 context->lo |= BIT_ULL(4); 1048 } 1049 1050 /* Returns a number of VTD pages, but aligned to MM page size */ 1051 static inline unsigned long aligned_nrpages(unsigned long host_addr, size_t size) 1052 { 1053 host_addr &= ~PAGE_MASK; 1054 return PAGE_ALIGN(host_addr + size) >> VTD_PAGE_SHIFT; 1055 } 1056 1057 /* Return a size from number of VTD pages. */ 1058 static inline unsigned long nrpages_to_size(unsigned long npages) 1059 { 1060 return npages << VTD_PAGE_SHIFT; 1061 } 1062 1063 /* Convert value to context PASID directory size field coding. */ 1064 #define context_pdts(pds) (((pds) & 0x7) << 9) 1065 1066 struct dmar_drhd_unit *dmar_find_matched_drhd_unit(struct pci_dev *dev); 1067 1068 int dmar_enable_qi(struct intel_iommu *iommu); 1069 void dmar_disable_qi(struct intel_iommu *iommu); 1070 int dmar_reenable_qi(struct intel_iommu *iommu); 1071 void qi_global_iec(struct intel_iommu *iommu); 1072 1073 void qi_flush_context(struct intel_iommu *iommu, u16 did, 1074 u16 sid, u8 fm, u64 type); 1075 void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr, 1076 unsigned int size_order, u64 type); 1077 void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 pfsid, 1078 u16 qdep, u64 addr, unsigned mask); 1079 1080 void qi_flush_piotlb(struct intel_iommu *iommu, u16 did, u32 pasid, u64 addr, 1081 unsigned long npages, bool ih); 1082 1083 void qi_flush_dev_iotlb_pasid(struct intel_iommu *iommu, u16 sid, u16 pfsid, 1084 u32 pasid, u16 qdep, u64 addr, 1085 unsigned int size_order); 1086 void quirk_extra_dev_tlb_flush(struct device_domain_info *info, 1087 unsigned long address, unsigned long pages, 1088 u32 pasid, u16 qdep); 1089 void qi_flush_pasid_cache(struct intel_iommu *iommu, u16 did, u64 granu, 1090 u32 pasid); 1091 1092 int qi_submit_sync(struct intel_iommu *iommu, struct qi_desc *desc, 1093 unsigned int count, unsigned long options); 1094 /* 1095 * Options used in qi_submit_sync: 1096 * QI_OPT_WAIT_DRAIN - Wait for PRQ drain completion, spec 6.5.2.8. 1097 */ 1098 #define QI_OPT_WAIT_DRAIN BIT(0) 1099 1100 void domain_update_iotlb(struct dmar_domain *domain); 1101 int domain_attach_iommu(struct dmar_domain *domain, struct intel_iommu *iommu); 1102 void domain_detach_iommu(struct dmar_domain *domain, struct intel_iommu *iommu); 1103 void device_block_translation(struct device *dev); 1104 int prepare_domain_attach_device(struct iommu_domain *domain, 1105 struct device *dev); 1106 void domain_update_iommu_cap(struct dmar_domain *domain); 1107 1108 int dmar_ir_support(void); 1109 1110 void iommu_flush_write_buffer(struct intel_iommu *iommu); 1111 struct iommu_domain *intel_nested_domain_alloc(struct iommu_domain *parent, 1112 const struct iommu_user_data *user_data); 1113 struct device *device_rbtree_find(struct intel_iommu *iommu, u16 rid); 1114 1115 enum cache_tag_type { 1116 CACHE_TAG_IOTLB, 1117 CACHE_TAG_DEVTLB, 1118 CACHE_TAG_NESTING_IOTLB, 1119 CACHE_TAG_NESTING_DEVTLB, 1120 }; 1121 1122 struct cache_tag { 1123 struct list_head node; 1124 enum cache_tag_type type; 1125 struct intel_iommu *iommu; 1126 /* 1127 * The @dev field represents the location of the cache. For IOTLB, it 1128 * resides on the IOMMU hardware. @dev stores the device pointer to 1129 * the IOMMU hardware. For DevTLB, it locates in the PCIe endpoint. 1130 * @dev stores the device pointer to that endpoint. 1131 */ 1132 struct device *dev; 1133 u16 domain_id; 1134 ioasid_t pasid; 1135 unsigned int users; 1136 }; 1137 1138 int cache_tag_assign_domain(struct dmar_domain *domain, 1139 struct device *dev, ioasid_t pasid); 1140 void cache_tag_unassign_domain(struct dmar_domain *domain, 1141 struct device *dev, ioasid_t pasid); 1142 void cache_tag_flush_range(struct dmar_domain *domain, unsigned long start, 1143 unsigned long end, int ih); 1144 void cache_tag_flush_all(struct dmar_domain *domain); 1145 void cache_tag_flush_range_np(struct dmar_domain *domain, unsigned long start, 1146 unsigned long end); 1147 1148 #ifdef CONFIG_INTEL_IOMMU_SVM 1149 void intel_svm_check(struct intel_iommu *iommu); 1150 int intel_svm_enable_prq(struct intel_iommu *iommu); 1151 int intel_svm_finish_prq(struct intel_iommu *iommu); 1152 void intel_svm_page_response(struct device *dev, struct iopf_fault *evt, 1153 struct iommu_page_response *msg); 1154 struct iommu_domain *intel_svm_domain_alloc(struct device *dev, 1155 struct mm_struct *mm); 1156 void intel_drain_pasid_prq(struct device *dev, u32 pasid); 1157 #else 1158 static inline void intel_svm_check(struct intel_iommu *iommu) {} 1159 static inline void intel_drain_pasid_prq(struct device *dev, u32 pasid) {} 1160 static inline struct iommu_domain *intel_svm_domain_alloc(struct device *dev, 1161 struct mm_struct *mm) 1162 { 1163 return ERR_PTR(-ENODEV); 1164 } 1165 #endif 1166 1167 #ifdef CONFIG_INTEL_IOMMU_DEBUGFS 1168 void intel_iommu_debugfs_init(void); 1169 void intel_iommu_debugfs_create_dev(struct device_domain_info *info); 1170 void intel_iommu_debugfs_remove_dev(struct device_domain_info *info); 1171 void intel_iommu_debugfs_create_dev_pasid(struct dev_pasid_info *dev_pasid); 1172 void intel_iommu_debugfs_remove_dev_pasid(struct dev_pasid_info *dev_pasid); 1173 #else 1174 static inline void intel_iommu_debugfs_init(void) {} 1175 static inline void intel_iommu_debugfs_create_dev(struct device_domain_info *info) {} 1176 static inline void intel_iommu_debugfs_remove_dev(struct device_domain_info *info) {} 1177 static inline void intel_iommu_debugfs_create_dev_pasid(struct dev_pasid_info *dev_pasid) {} 1178 static inline void intel_iommu_debugfs_remove_dev_pasid(struct dev_pasid_info *dev_pasid) {} 1179 #endif /* CONFIG_INTEL_IOMMU_DEBUGFS */ 1180 1181 extern const struct attribute_group *intel_iommu_groups[]; 1182 struct context_entry *iommu_context_addr(struct intel_iommu *iommu, u8 bus, 1183 u8 devfn, int alloc); 1184 1185 extern const struct iommu_ops intel_iommu_ops; 1186 1187 #ifdef CONFIG_INTEL_IOMMU 1188 extern int intel_iommu_sm; 1189 int iommu_calculate_agaw(struct intel_iommu *iommu); 1190 int iommu_calculate_max_sagaw(struct intel_iommu *iommu); 1191 int ecmd_submit_sync(struct intel_iommu *iommu, u8 ecmd, u64 oa, u64 ob); 1192 1193 static inline bool ecmd_has_pmu_essential(struct intel_iommu *iommu) 1194 { 1195 return (iommu->ecmdcap[DMA_ECMD_ECCAP3] & DMA_ECMD_ECCAP3_ESSENTIAL) == 1196 DMA_ECMD_ECCAP3_ESSENTIAL; 1197 } 1198 1199 extern int dmar_disabled; 1200 extern int intel_iommu_enabled; 1201 #else 1202 static inline int iommu_calculate_agaw(struct intel_iommu *iommu) 1203 { 1204 return 0; 1205 } 1206 static inline int iommu_calculate_max_sagaw(struct intel_iommu *iommu) 1207 { 1208 return 0; 1209 } 1210 #define dmar_disabled (1) 1211 #define intel_iommu_enabled (0) 1212 #define intel_iommu_sm (0) 1213 #endif 1214 1215 static inline const char *decode_prq_descriptor(char *str, size_t size, 1216 u64 dw0, u64 dw1, u64 dw2, u64 dw3) 1217 { 1218 char *buf = str; 1219 int bytes; 1220 1221 bytes = snprintf(buf, size, 1222 "rid=0x%llx addr=0x%llx %c%c%c%c%c pasid=0x%llx index=0x%llx", 1223 FIELD_GET(GENMASK_ULL(31, 16), dw0), 1224 FIELD_GET(GENMASK_ULL(63, 12), dw1), 1225 dw1 & BIT_ULL(0) ? 'r' : '-', 1226 dw1 & BIT_ULL(1) ? 'w' : '-', 1227 dw0 & BIT_ULL(52) ? 'x' : '-', 1228 dw0 & BIT_ULL(53) ? 'p' : '-', 1229 dw1 & BIT_ULL(2) ? 'l' : '-', 1230 FIELD_GET(GENMASK_ULL(51, 32), dw0), 1231 FIELD_GET(GENMASK_ULL(11, 3), dw1)); 1232 1233 /* Private Data */ 1234 if (dw0 & BIT_ULL(9)) { 1235 size -= bytes; 1236 buf += bytes; 1237 snprintf(buf, size, " private=0x%llx/0x%llx\n", dw2, dw3); 1238 } 1239 1240 return str; 1241 } 1242 1243 #endif 1244