1 // SPDX-License-Identifier: GPL-2.0 2 3 /* 4 * Hyper-V stub IOMMU driver. 5 * 6 * Copyright (C) 2019, Microsoft, Inc. 7 * 8 * Author : Lan Tianyu <Tianyu.Lan@microsoft.com> 9 */ 10 11 #include <linux/types.h> 12 #include <linux/interrupt.h> 13 #include <linux/irq.h> 14 #include <linux/iommu.h> 15 #include <linux/module.h> 16 17 #include <asm/apic.h> 18 #include <asm/cpu.h> 19 #include <asm/hw_irq.h> 20 #include <asm/io_apic.h> 21 #include <asm/irq_remapping.h> 22 #include <asm/hypervisor.h> 23 #include <asm/mshyperv.h> 24 25 #include "irq_remapping.h" 26 27 #ifdef CONFIG_IRQ_REMAP 28 29 /* 30 * According 82093AA IO-APIC spec , IO APIC has a 24-entry Interrupt 31 * Redirection Table. Hyper-V exposes one single IO-APIC and so define 32 * 24 IO APIC remmapping entries. 33 */ 34 #define IOAPIC_REMAPPING_ENTRY 24 35 36 static cpumask_t ioapic_max_cpumask = { CPU_BITS_NONE }; 37 static struct irq_domain *ioapic_ir_domain; 38 39 static int hyperv_ir_set_affinity(struct irq_data *data, 40 const struct cpumask *mask, bool force) 41 { 42 struct irq_data *parent = data->parent_data; 43 struct irq_cfg *cfg = irqd_cfg(data); 44 int ret; 45 46 /* Return error If new irq affinity is out of ioapic_max_cpumask. */ 47 if (!cpumask_subset(mask, &ioapic_max_cpumask)) 48 return -EINVAL; 49 50 ret = parent->chip->irq_set_affinity(parent, mask, force); 51 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE) 52 return ret; 53 54 send_cleanup_vector(cfg); 55 56 return 0; 57 } 58 59 static struct irq_chip hyperv_ir_chip = { 60 .name = "HYPERV-IR", 61 .irq_ack = apic_ack_irq, 62 .irq_set_affinity = hyperv_ir_set_affinity, 63 }; 64 65 static int hyperv_irq_remapping_alloc(struct irq_domain *domain, 66 unsigned int virq, unsigned int nr_irqs, 67 void *arg) 68 { 69 struct irq_alloc_info *info = arg; 70 struct irq_data *irq_data; 71 int ret = 0; 72 73 if (!info || info->type != X86_IRQ_ALLOC_TYPE_IOAPIC || nr_irqs > 1) 74 return -EINVAL; 75 76 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg); 77 if (ret < 0) 78 return ret; 79 80 irq_data = irq_domain_get_irq_data(domain, virq); 81 if (!irq_data) { 82 irq_domain_free_irqs_common(domain, virq, nr_irqs); 83 return -EINVAL; 84 } 85 86 irq_data->chip = &hyperv_ir_chip; 87 88 /* 89 * Hypver-V IO APIC irq affinity should be in the scope of 90 * ioapic_max_cpumask because no irq remapping support. 91 */ 92 irq_data_update_affinity(irq_data, &ioapic_max_cpumask); 93 94 return 0; 95 } 96 97 static void hyperv_irq_remapping_free(struct irq_domain *domain, 98 unsigned int virq, unsigned int nr_irqs) 99 { 100 irq_domain_free_irqs_common(domain, virq, nr_irqs); 101 } 102 103 static int hyperv_irq_remapping_select(struct irq_domain *d, 104 struct irq_fwspec *fwspec, 105 enum irq_domain_bus_token bus_token) 106 { 107 /* Claim the only I/O APIC emulated by Hyper-V */ 108 return x86_fwspec_is_ioapic(fwspec); 109 } 110 111 static const struct irq_domain_ops hyperv_ir_domain_ops = { 112 .select = hyperv_irq_remapping_select, 113 .alloc = hyperv_irq_remapping_alloc, 114 .free = hyperv_irq_remapping_free, 115 }; 116 117 static const struct irq_domain_ops hyperv_root_ir_domain_ops; 118 static int __init hyperv_prepare_irq_remapping(void) 119 { 120 struct fwnode_handle *fn; 121 int i; 122 const char *name; 123 const struct irq_domain_ops *ops; 124 125 if (!hypervisor_is_type(X86_HYPER_MS_HYPERV) || 126 x86_init.hyper.msi_ext_dest_id() || 127 !x2apic_supported()) 128 return -ENODEV; 129 130 if (hv_root_partition) { 131 name = "HYPERV-ROOT-IR"; 132 ops = &hyperv_root_ir_domain_ops; 133 } else { 134 name = "HYPERV-IR"; 135 ops = &hyperv_ir_domain_ops; 136 } 137 138 fn = irq_domain_alloc_named_id_fwnode(name, 0); 139 if (!fn) 140 return -ENOMEM; 141 142 ioapic_ir_domain = 143 irq_domain_create_hierarchy(arch_get_ir_parent_domain(), 144 0, IOAPIC_REMAPPING_ENTRY, fn, ops, NULL); 145 146 if (!ioapic_ir_domain) { 147 irq_domain_free_fwnode(fn); 148 return -ENOMEM; 149 } 150 151 if (hv_root_partition) 152 return 0; /* The rest is only relevant to guests */ 153 154 /* 155 * Hyper-V doesn't provide irq remapping function for 156 * IO-APIC and so IO-APIC only accepts 8-bit APIC ID. 157 * Cpu's APIC ID is read from ACPI MADT table and APIC IDs 158 * in the MADT table on Hyper-v are sorted monotonic increasingly. 159 * APIC ID reflects cpu topology. There maybe some APIC ID 160 * gaps when cpu number in a socket is not power of two. Prepare 161 * max cpu affinity for IOAPIC irqs. Scan cpu 0-255 and set cpu 162 * into ioapic_max_cpumask if its APIC ID is less than 256. 163 */ 164 for (i = min_t(unsigned int, num_possible_cpus() - 1, 255); i >= 0; i--) 165 if (cpu_physical_id(i) < 256) 166 cpumask_set_cpu(i, &ioapic_max_cpumask); 167 168 return 0; 169 } 170 171 static int __init hyperv_enable_irq_remapping(void) 172 { 173 return IRQ_REMAP_X2APIC_MODE; 174 } 175 176 struct irq_remap_ops hyperv_irq_remap_ops = { 177 .prepare = hyperv_prepare_irq_remapping, 178 .enable = hyperv_enable_irq_remapping, 179 }; 180 181 /* IRQ remapping domain when Linux runs as the root partition */ 182 struct hyperv_root_ir_data { 183 u8 ioapic_id; 184 bool is_level; 185 struct hv_interrupt_entry entry; 186 }; 187 188 static void 189 hyperv_root_ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg) 190 { 191 u64 status; 192 u32 vector; 193 struct irq_cfg *cfg; 194 int ioapic_id; 195 const struct cpumask *affinity; 196 int cpu; 197 struct hv_interrupt_entry entry; 198 struct hyperv_root_ir_data *data = irq_data->chip_data; 199 struct IO_APIC_route_entry e; 200 201 cfg = irqd_cfg(irq_data); 202 affinity = irq_data_get_effective_affinity_mask(irq_data); 203 cpu = cpumask_first_and(affinity, cpu_online_mask); 204 205 vector = cfg->vector; 206 ioapic_id = data->ioapic_id; 207 208 if (data->entry.source == HV_DEVICE_TYPE_IOAPIC 209 && data->entry.ioapic_rte.as_uint64) { 210 entry = data->entry; 211 212 status = hv_unmap_ioapic_interrupt(ioapic_id, &entry); 213 214 if (status != HV_STATUS_SUCCESS) 215 pr_debug("%s: unexpected unmap status %lld\n", __func__, status); 216 217 data->entry.ioapic_rte.as_uint64 = 0; 218 data->entry.source = 0; /* Invalid source */ 219 } 220 221 222 status = hv_map_ioapic_interrupt(ioapic_id, data->is_level, cpu, 223 vector, &entry); 224 225 if (status != HV_STATUS_SUCCESS) { 226 pr_err("%s: map hypercall failed, status %lld\n", __func__, status); 227 return; 228 } 229 230 data->entry = entry; 231 232 /* Turn it into an IO_APIC_route_entry, and generate MSI MSG. */ 233 e.w1 = entry.ioapic_rte.low_uint32; 234 e.w2 = entry.ioapic_rte.high_uint32; 235 236 memset(msg, 0, sizeof(*msg)); 237 msg->arch_data.vector = e.vector; 238 msg->arch_data.delivery_mode = e.delivery_mode; 239 msg->arch_addr_lo.dest_mode_logical = e.dest_mode_logical; 240 msg->arch_addr_lo.dmar_format = e.ir_format; 241 msg->arch_addr_lo.dmar_index_0_14 = e.ir_index_0_14; 242 } 243 244 static int hyperv_root_ir_set_affinity(struct irq_data *data, 245 const struct cpumask *mask, bool force) 246 { 247 struct irq_data *parent = data->parent_data; 248 struct irq_cfg *cfg = irqd_cfg(data); 249 int ret; 250 251 ret = parent->chip->irq_set_affinity(parent, mask, force); 252 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE) 253 return ret; 254 255 send_cleanup_vector(cfg); 256 257 return 0; 258 } 259 260 static struct irq_chip hyperv_root_ir_chip = { 261 .name = "HYPERV-ROOT-IR", 262 .irq_ack = apic_ack_irq, 263 .irq_set_affinity = hyperv_root_ir_set_affinity, 264 .irq_compose_msi_msg = hyperv_root_ir_compose_msi_msg, 265 }; 266 267 static int hyperv_root_irq_remapping_alloc(struct irq_domain *domain, 268 unsigned int virq, unsigned int nr_irqs, 269 void *arg) 270 { 271 struct irq_alloc_info *info = arg; 272 struct irq_data *irq_data; 273 struct hyperv_root_ir_data *data; 274 int ret = 0; 275 276 if (!info || info->type != X86_IRQ_ALLOC_TYPE_IOAPIC || nr_irqs > 1) 277 return -EINVAL; 278 279 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg); 280 if (ret < 0) 281 return ret; 282 283 data = kzalloc(sizeof(*data), GFP_KERNEL); 284 if (!data) { 285 irq_domain_free_irqs_common(domain, virq, nr_irqs); 286 return -ENOMEM; 287 } 288 289 irq_data = irq_domain_get_irq_data(domain, virq); 290 if (!irq_data) { 291 kfree(data); 292 irq_domain_free_irqs_common(domain, virq, nr_irqs); 293 return -EINVAL; 294 } 295 296 data->ioapic_id = info->devid; 297 data->is_level = info->ioapic.is_level; 298 299 irq_data->chip = &hyperv_root_ir_chip; 300 irq_data->chip_data = data; 301 302 return 0; 303 } 304 305 static void hyperv_root_irq_remapping_free(struct irq_domain *domain, 306 unsigned int virq, unsigned int nr_irqs) 307 { 308 struct irq_data *irq_data; 309 struct hyperv_root_ir_data *data; 310 struct hv_interrupt_entry *e; 311 int i; 312 313 for (i = 0; i < nr_irqs; i++) { 314 irq_data = irq_domain_get_irq_data(domain, virq + i); 315 316 if (irq_data && irq_data->chip_data) { 317 data = irq_data->chip_data; 318 e = &data->entry; 319 320 if (e->source == HV_DEVICE_TYPE_IOAPIC 321 && e->ioapic_rte.as_uint64) 322 hv_unmap_ioapic_interrupt(data->ioapic_id, 323 &data->entry); 324 325 kfree(data); 326 } 327 } 328 329 irq_domain_free_irqs_common(domain, virq, nr_irqs); 330 } 331 332 static const struct irq_domain_ops hyperv_root_ir_domain_ops = { 333 .select = hyperv_irq_remapping_select, 334 .alloc = hyperv_root_irq_remapping_alloc, 335 .free = hyperv_root_irq_remapping_free, 336 }; 337 338 #endif 339