1*e71e0012SJason Gunthorpe /* SPDX-License-Identifier: GPL-2.0-only */ 2*e71e0012SJason Gunthorpe /* 3*e71e0012SJason Gunthorpe * Copyright (c) 2025, NVIDIA CORPORATION & AFFILIATES 4*e71e0012SJason Gunthorpe * 5*e71e0012SJason Gunthorpe */ 6*e71e0012SJason Gunthorpe #ifndef __GENERIC_PT_FMT_DEFS_RISCV_H 7*e71e0012SJason Gunthorpe #define __GENERIC_PT_FMT_DEFS_RISCV_H 8*e71e0012SJason Gunthorpe 9*e71e0012SJason Gunthorpe #include <linux/generic_pt/common.h> 10*e71e0012SJason Gunthorpe #include <linux/types.h> 11*e71e0012SJason Gunthorpe 12*e71e0012SJason Gunthorpe #ifdef PT_RISCV_32BIT 13*e71e0012SJason Gunthorpe typedef u32 pt_riscv_entry_t; 14*e71e0012SJason Gunthorpe #define riscvpt_write_attrs riscv32pt_write_attrs 15*e71e0012SJason Gunthorpe #else 16*e71e0012SJason Gunthorpe typedef u64 pt_riscv_entry_t; 17*e71e0012SJason Gunthorpe #define riscvpt_write_attrs riscv64pt_write_attrs 18*e71e0012SJason Gunthorpe #endif 19*e71e0012SJason Gunthorpe 20*e71e0012SJason Gunthorpe typedef pt_riscv_entry_t pt_vaddr_t; 21*e71e0012SJason Gunthorpe typedef u64 pt_oaddr_t; 22*e71e0012SJason Gunthorpe 23*e71e0012SJason Gunthorpe struct riscvpt_write_attrs { 24*e71e0012SJason Gunthorpe pt_riscv_entry_t descriptor_bits; 25*e71e0012SJason Gunthorpe gfp_t gfp; 26*e71e0012SJason Gunthorpe }; 27*e71e0012SJason Gunthorpe #define pt_write_attrs riscvpt_write_attrs 28*e71e0012SJason Gunthorpe 29*e71e0012SJason Gunthorpe #endif 30