1 /* 2 * This program is free software; you can redistribute it and/or modify 3 * it under the terms of the GNU General Public License, version 2, as 4 * published by the Free Software Foundation. 5 * 6 * This program is distributed in the hope that it will be useful, 7 * but WITHOUT ANY WARRANTY; without even the implied warranty of 8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 9 * GNU General Public License for more details. 10 * 11 * You should have received a copy of the GNU General Public License 12 * along with this program; if not, write to the Free Software 13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 14 * 15 * Copyright (C) 2013 Freescale Semiconductor, Inc. 16 * 17 */ 18 19 #ifndef __FSL_PAMU_H 20 #define __FSL_PAMU_H 21 22 #include <linux/iommu.h> 23 24 #include <asm/fsl_pamu_stash.h> 25 26 /* Bit Field macros 27 * v = bit field variable; m = mask, m##_SHIFT = shift, x = value to load 28 */ 29 #define set_bf(v, m, x) (v = ((v) & ~(m)) | (((x) << m##_SHIFT) & (m))) 30 #define get_bf(v, m) (((v) & (m)) >> m##_SHIFT) 31 32 /* PAMU CCSR space */ 33 #define PAMU_PGC 0x00000000 /* Allows all peripheral accesses */ 34 #define PAMU_PE 0x40000000 /* enable PAMU */ 35 36 /* PAMU_OFFSET to the next pamu space in ccsr */ 37 #define PAMU_OFFSET 0x1000 38 39 #define PAMU_MMAP_REGS_BASE 0 40 41 struct pamu_mmap_regs { 42 u32 ppbah; 43 u32 ppbal; 44 u32 pplah; 45 u32 pplal; 46 u32 spbah; 47 u32 spbal; 48 u32 splah; 49 u32 splal; 50 u32 obah; 51 u32 obal; 52 u32 olah; 53 u32 olal; 54 }; 55 56 /* PAMU Error Registers */ 57 #define PAMU_POES1 0x0040 58 #define PAMU_POES2 0x0044 59 #define PAMU_POEAH 0x0048 60 #define PAMU_POEAL 0x004C 61 #define PAMU_AVS1 0x0050 62 #define PAMU_AVS1_AV 0x1 63 #define PAMU_AVS1_OTV 0x6 64 #define PAMU_AVS1_APV 0x78 65 #define PAMU_AVS1_WAV 0x380 66 #define PAMU_AVS1_LAV 0x1c00 67 #define PAMU_AVS1_GCV 0x2000 68 #define PAMU_AVS1_PDV 0x4000 69 #define PAMU_AV_MASK (PAMU_AVS1_AV | PAMU_AVS1_OTV | PAMU_AVS1_APV | PAMU_AVS1_WAV \ 70 | PAMU_AVS1_LAV | PAMU_AVS1_GCV | PAMU_AVS1_PDV) 71 #define PAMU_AVS1_LIODN_SHIFT 16 72 #define PAMU_LAV_LIODN_NOT_IN_PPAACT 0x400 73 74 #define PAMU_AVS2 0x0054 75 #define PAMU_AVAH 0x0058 76 #define PAMU_AVAL 0x005C 77 #define PAMU_EECTL 0x0060 78 #define PAMU_EEDIS 0x0064 79 #define PAMU_EEINTEN 0x0068 80 #define PAMU_EEDET 0x006C 81 #define PAMU_EEATTR 0x0070 82 #define PAMU_EEAHI 0x0074 83 #define PAMU_EEALO 0x0078 84 #define PAMU_EEDHI 0X007C 85 #define PAMU_EEDLO 0x0080 86 #define PAMU_EECC 0x0084 87 #define PAMU_UDAD 0x0090 88 89 /* PAMU Revision Registers */ 90 #define PAMU_PR1 0x0BF8 91 #define PAMU_PR2 0x0BFC 92 93 /* PAMU version mask */ 94 #define PAMU_PR1_MASK 0xffff 95 96 /* PAMU Capabilities Registers */ 97 #define PAMU_PC1 0x0C00 98 #define PAMU_PC2 0x0C04 99 #define PAMU_PC3 0x0C08 100 #define PAMU_PC4 0x0C0C 101 102 /* PAMU Control Register */ 103 #define PAMU_PC 0x0C10 104 105 /* PAMU control defs */ 106 #define PAMU_CONTROL 0x0C10 107 #define PAMU_PC_PGC 0x80000000 /* PAMU gate closed bit */ 108 #define PAMU_PC_PE 0x40000000 /* PAMU enable bit */ 109 #define PAMU_PC_SPCC 0x00000010 /* sPAACE cache enable */ 110 #define PAMU_PC_PPCC 0x00000001 /* pPAACE cache enable */ 111 #define PAMU_PC_OCE 0x00001000 /* OMT cache enable */ 112 113 #define PAMU_PFA1 0x0C14 114 #define PAMU_PFA2 0x0C18 115 116 #define PAMU_PC2_MLIODN(X) ((X) >> 16) 117 #define PAMU_PC3_MWCE(X) (((X) >> 21) & 0xf) 118 119 /* PAMU Interrupt control and Status Register */ 120 #define PAMU_PICS 0x0C1C 121 #define PAMU_ACCESS_VIOLATION_STAT 0x8 122 #define PAMU_ACCESS_VIOLATION_ENABLE 0x4 123 124 /* PAMU Debug Registers */ 125 #define PAMU_PD1 0x0F00 126 #define PAMU_PD2 0x0F04 127 #define PAMU_PD3 0x0F08 128 #define PAMU_PD4 0x0F0C 129 130 #define PAACE_AP_PERMS_DENIED 0x0 131 #define PAACE_AP_PERMS_QUERY 0x1 132 #define PAACE_AP_PERMS_UPDATE 0x2 133 #define PAACE_AP_PERMS_ALL 0x3 134 135 #define PAACE_DD_TO_HOST 0x0 136 #define PAACE_DD_TO_IO 0x1 137 #define PAACE_PT_PRIMARY 0x0 138 #define PAACE_PT_SECONDARY 0x1 139 #define PAACE_V_INVALID 0x0 140 #define PAACE_V_VALID 0x1 141 #define PAACE_MW_SUBWINDOWS 0x1 142 143 #define PAACE_WSE_4K 0xB 144 #define PAACE_WSE_8K 0xC 145 #define PAACE_WSE_16K 0xD 146 #define PAACE_WSE_32K 0xE 147 #define PAACE_WSE_64K 0xF 148 #define PAACE_WSE_128K 0x10 149 #define PAACE_WSE_256K 0x11 150 #define PAACE_WSE_512K 0x12 151 #define PAACE_WSE_1M 0x13 152 #define PAACE_WSE_2M 0x14 153 #define PAACE_WSE_4M 0x15 154 #define PAACE_WSE_8M 0x16 155 #define PAACE_WSE_16M 0x17 156 #define PAACE_WSE_32M 0x18 157 #define PAACE_WSE_64M 0x19 158 #define PAACE_WSE_128M 0x1A 159 #define PAACE_WSE_256M 0x1B 160 #define PAACE_WSE_512M 0x1C 161 #define PAACE_WSE_1G 0x1D 162 #define PAACE_WSE_2G 0x1E 163 #define PAACE_WSE_4G 0x1F 164 165 #define PAACE_DID_PCI_EXPRESS_1 0x00 166 #define PAACE_DID_PCI_EXPRESS_2 0x01 167 #define PAACE_DID_PCI_EXPRESS_3 0x02 168 #define PAACE_DID_PCI_EXPRESS_4 0x03 169 #define PAACE_DID_LOCAL_BUS 0x04 170 #define PAACE_DID_SRIO 0x0C 171 #define PAACE_DID_MEM_1 0x10 172 #define PAACE_DID_MEM_2 0x11 173 #define PAACE_DID_MEM_3 0x12 174 #define PAACE_DID_MEM_4 0x13 175 #define PAACE_DID_MEM_1_2 0x14 176 #define PAACE_DID_MEM_3_4 0x15 177 #define PAACE_DID_MEM_1_4 0x16 178 #define PAACE_DID_BM_SW_PORTAL 0x18 179 #define PAACE_DID_PAMU 0x1C 180 #define PAACE_DID_CAAM 0x21 181 #define PAACE_DID_QM_SW_PORTAL 0x3C 182 #define PAACE_DID_CORE0_INST 0x80 183 #define PAACE_DID_CORE0_DATA 0x81 184 #define PAACE_DID_CORE1_INST 0x82 185 #define PAACE_DID_CORE1_DATA 0x83 186 #define PAACE_DID_CORE2_INST 0x84 187 #define PAACE_DID_CORE2_DATA 0x85 188 #define PAACE_DID_CORE3_INST 0x86 189 #define PAACE_DID_CORE3_DATA 0x87 190 #define PAACE_DID_CORE4_INST 0x88 191 #define PAACE_DID_CORE4_DATA 0x89 192 #define PAACE_DID_CORE5_INST 0x8A 193 #define PAACE_DID_CORE5_DATA 0x8B 194 #define PAACE_DID_CORE6_INST 0x8C 195 #define PAACE_DID_CORE6_DATA 0x8D 196 #define PAACE_DID_CORE7_INST 0x8E 197 #define PAACE_DID_CORE7_DATA 0x8F 198 #define PAACE_DID_BROADCAST 0xFF 199 200 #define PAACE_ATM_NO_XLATE 0x00 201 #define PAACE_ATM_WINDOW_XLATE 0x01 202 #define PAACE_ATM_PAGE_XLATE 0x02 203 #define PAACE_ATM_WIN_PG_XLATE (PAACE_ATM_WINDOW_XLATE | PAACE_ATM_PAGE_XLATE) 204 #define PAACE_OTM_NO_XLATE 0x00 205 #define PAACE_OTM_IMMEDIATE 0x01 206 #define PAACE_OTM_INDEXED 0x02 207 #define PAACE_OTM_RESERVED 0x03 208 209 #define PAACE_M_COHERENCE_REQ 0x01 210 211 #define PAACE_PID_0 0x0 212 #define PAACE_PID_1 0x1 213 #define PAACE_PID_2 0x2 214 #define PAACE_PID_3 0x3 215 #define PAACE_PID_4 0x4 216 #define PAACE_PID_5 0x5 217 #define PAACE_PID_6 0x6 218 #define PAACE_PID_7 0x7 219 220 #define PAACE_TCEF_FORMAT0_8B 0x00 221 #define PAACE_TCEF_FORMAT1_RSVD 0x01 222 /* 223 * Hard coded value for the PAACT size to accommodate 224 * maximum LIODN value generated by u-boot. 225 */ 226 #define PAACE_NUMBER_ENTRIES 0x500 227 /* Hard coded value for the SPAACT size */ 228 #define SPAACE_NUMBER_ENTRIES 0x800 229 230 #define OME_NUMBER_ENTRIES 16 231 232 /* PAACE Bit Field Defines */ 233 #define PPAACE_AF_WBAL 0xfffff000 234 #define PPAACE_AF_WBAL_SHIFT 12 235 #define PPAACE_AF_WSE 0x00000fc0 236 #define PPAACE_AF_WSE_SHIFT 6 237 #define PPAACE_AF_MW 0x00000020 238 #define PPAACE_AF_MW_SHIFT 5 239 240 #define SPAACE_AF_LIODN 0xffff0000 241 #define SPAACE_AF_LIODN_SHIFT 16 242 243 #define PAACE_AF_AP 0x00000018 244 #define PAACE_AF_AP_SHIFT 3 245 #define PAACE_AF_DD 0x00000004 246 #define PAACE_AF_DD_SHIFT 2 247 #define PAACE_AF_PT 0x00000002 248 #define PAACE_AF_PT_SHIFT 1 249 #define PAACE_AF_V 0x00000001 250 #define PAACE_AF_V_SHIFT 0 251 252 #define PAACE_DA_HOST_CR 0x80 253 #define PAACE_DA_HOST_CR_SHIFT 7 254 255 #define PAACE_IA_CID 0x00FF0000 256 #define PAACE_IA_CID_SHIFT 16 257 #define PAACE_IA_WCE 0x000000F0 258 #define PAACE_IA_WCE_SHIFT 4 259 #define PAACE_IA_ATM 0x0000000C 260 #define PAACE_IA_ATM_SHIFT 2 261 #define PAACE_IA_OTM 0x00000003 262 #define PAACE_IA_OTM_SHIFT 0 263 264 #define PAACE_WIN_TWBAL 0xfffff000 265 #define PAACE_WIN_TWBAL_SHIFT 12 266 #define PAACE_WIN_SWSE 0x00000fc0 267 #define PAACE_WIN_SWSE_SHIFT 6 268 269 /* PAMU Data Structures */ 270 /* primary / secondary paact structure */ 271 struct paace { 272 /* PAACE Offset 0x00 */ 273 u32 wbah; /* only valid for Primary PAACE */ 274 u32 addr_bitfields; /* See P/S PAACE_AF_* */ 275 276 /* PAACE Offset 0x08 */ 277 /* Interpretation of first 32 bits dependent on DD above */ 278 union { 279 struct { 280 /* Destination ID, see PAACE_DID_* defines */ 281 u8 did; 282 /* Partition ID */ 283 u8 pid; 284 /* Snoop ID */ 285 u8 snpid; 286 /* coherency_required : 1 reserved : 7 */ 287 u8 coherency_required; /* See PAACE_DA_* */ 288 } to_host; 289 struct { 290 /* Destination ID, see PAACE_DID_* defines */ 291 u8 did; 292 u8 reserved1; 293 u16 reserved2; 294 } to_io; 295 } domain_attr; 296 297 /* Implementation attributes + window count + address & operation translation modes */ 298 u32 impl_attr; /* See PAACE_IA_* */ 299 300 /* PAACE Offset 0x10 */ 301 /* Translated window base address */ 302 u32 twbah; 303 u32 win_bitfields; /* See PAACE_WIN_* */ 304 305 /* PAACE Offset 0x18 */ 306 /* first secondary paace entry */ 307 u32 fspi; /* only valid for Primary PAACE */ 308 union { 309 struct { 310 u8 ioea; 311 u8 moea; 312 u8 ioeb; 313 u8 moeb; 314 } immed_ot; 315 struct { 316 u16 reserved; 317 u16 omi; 318 } index_ot; 319 } op_encode; 320 321 /* PAACE Offsets 0x20-0x38 */ 322 u32 reserved[8]; /* not currently implemented */ 323 }; 324 325 /* OME : Operation mapping entry 326 * MOE : Mapped Operation Encodings 327 * The operation mapping table is table containing operation mapping entries (OME). 328 * The index of a particular OME is programmed in the PAACE entry for translation 329 * in bound I/O operations corresponding to an LIODN. The OMT is used for translation 330 * specifically in case of the indexed translation mode. Each OME contains a 128 331 * byte mapped operation encoding (MOE), where each byte represents an MOE. 332 */ 333 #define NUM_MOE 128 334 struct ome { 335 u8 moe[NUM_MOE]; 336 } __packed; 337 338 #define PAACT_SIZE (sizeof(struct paace) * PAACE_NUMBER_ENTRIES) 339 #define SPAACT_SIZE (sizeof(struct paace) * SPAACE_NUMBER_ENTRIES) 340 #define OMT_SIZE (sizeof(struct ome) * OME_NUMBER_ENTRIES) 341 342 #define PAMU_PAGE_SHIFT 12 343 #define PAMU_PAGE_SIZE 4096ULL 344 345 #define IOE_READ 0x00 346 #define IOE_READ_IDX 0x00 347 #define IOE_WRITE 0x81 348 #define IOE_WRITE_IDX 0x01 349 #define IOE_EREAD0 0x82 /* Enhanced read type 0 */ 350 #define IOE_EREAD0_IDX 0x02 /* Enhanced read type 0 */ 351 #define IOE_EWRITE0 0x83 /* Enhanced write type 0 */ 352 #define IOE_EWRITE0_IDX 0x03 /* Enhanced write type 0 */ 353 #define IOE_DIRECT0 0x84 /* Directive type 0 */ 354 #define IOE_DIRECT0_IDX 0x04 /* Directive type 0 */ 355 #define IOE_EREAD1 0x85 /* Enhanced read type 1 */ 356 #define IOE_EREAD1_IDX 0x05 /* Enhanced read type 1 */ 357 #define IOE_EWRITE1 0x86 /* Enhanced write type 1 */ 358 #define IOE_EWRITE1_IDX 0x06 /* Enhanced write type 1 */ 359 #define IOE_DIRECT1 0x87 /* Directive type 1 */ 360 #define IOE_DIRECT1_IDX 0x07 /* Directive type 1 */ 361 #define IOE_RAC 0x8c /* Read with Atomic clear */ 362 #define IOE_RAC_IDX 0x0c /* Read with Atomic clear */ 363 #define IOE_RAS 0x8d /* Read with Atomic set */ 364 #define IOE_RAS_IDX 0x0d /* Read with Atomic set */ 365 #define IOE_RAD 0x8e /* Read with Atomic decrement */ 366 #define IOE_RAD_IDX 0x0e /* Read with Atomic decrement */ 367 #define IOE_RAI 0x8f /* Read with Atomic increment */ 368 #define IOE_RAI_IDX 0x0f /* Read with Atomic increment */ 369 370 #define EOE_READ 0x00 371 #define EOE_WRITE 0x01 372 #define EOE_RAC 0x0c /* Read with Atomic clear */ 373 #define EOE_RAS 0x0d /* Read with Atomic set */ 374 #define EOE_RAD 0x0e /* Read with Atomic decrement */ 375 #define EOE_RAI 0x0f /* Read with Atomic increment */ 376 #define EOE_LDEC 0x10 /* Load external cache */ 377 #define EOE_LDECL 0x11 /* Load external cache with stash lock */ 378 #define EOE_LDECPE 0x12 /* Load external cache with preferred exclusive */ 379 #define EOE_LDECPEL 0x13 /* Load external cache with preferred exclusive and lock */ 380 #define EOE_LDECFE 0x14 /* Load external cache with forced exclusive */ 381 #define EOE_LDECFEL 0x15 /* Load external cache with forced exclusive and lock */ 382 #define EOE_RSA 0x16 /* Read with stash allocate */ 383 #define EOE_RSAU 0x17 /* Read with stash allocate and unlock */ 384 #define EOE_READI 0x18 /* Read with invalidate */ 385 #define EOE_RWNITC 0x19 /* Read with no intention to cache */ 386 #define EOE_WCI 0x1a /* Write cache inhibited */ 387 #define EOE_WWSA 0x1b /* Write with stash allocate */ 388 #define EOE_WWSAL 0x1c /* Write with stash allocate and lock */ 389 #define EOE_WWSAO 0x1d /* Write with stash allocate only */ 390 #define EOE_WWSAOL 0x1e /* Write with stash allocate only and lock */ 391 #define EOE_VALID 0x80 392 393 /* Function prototypes */ 394 int pamu_domain_init(void); 395 int pamu_enable_liodn(int liodn); 396 int pamu_disable_liodn(int liodn); 397 void pamu_free_subwins(int liodn); 398 int pamu_config_ppaace(int liodn, phys_addr_t win_addr, phys_addr_t win_size, 399 u32 omi, unsigned long rpn, u32 snoopid, uint32_t stashid, 400 u32 subwin_cnt, int prot); 401 int pamu_config_spaace(int liodn, u32 subwin_cnt, u32 subwin_addr, 402 phys_addr_t subwin_size, u32 omi, unsigned long rpn, 403 uint32_t snoopid, u32 stashid, int enable, int prot); 404 405 u32 get_stash_id(u32 stash_dest_hint, u32 vcpu); 406 void get_ome_index(u32 *omi_index, struct device *dev); 407 int pamu_update_paace_stash(int liodn, u32 subwin, u32 value); 408 int pamu_disable_spaace(int liodn, u32 subwin); 409 u32 pamu_get_max_subwin_cnt(void); 410 411 #endif /* __FSL_PAMU_H */ 412