1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2019, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/acpi.h> 7 #include <linux/adreno-smmu-priv.h> 8 #include <linux/delay.h> 9 #include <linux/of_device.h> 10 #include <linux/firmware/qcom/qcom_scm.h> 11 #include <linux/platform_device.h> 12 #include <linux/pm_runtime.h> 13 14 #include "arm-smmu.h" 15 #include "arm-smmu-qcom.h" 16 17 #define QCOM_DUMMY_VAL -1 18 19 static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu) 20 { 21 return container_of(smmu, struct qcom_smmu, smmu); 22 } 23 24 static void qcom_smmu_tlb_sync(struct arm_smmu_device *smmu, int page, 25 int sync, int status) 26 { 27 unsigned int spin_cnt, delay; 28 u32 reg; 29 30 arm_smmu_writel(smmu, page, sync, QCOM_DUMMY_VAL); 31 for (delay = 1; delay < TLB_LOOP_TIMEOUT; delay *= 2) { 32 for (spin_cnt = TLB_SPIN_COUNT; spin_cnt > 0; spin_cnt--) { 33 reg = arm_smmu_readl(smmu, page, status); 34 if (!(reg & ARM_SMMU_sTLBGSTATUS_GSACTIVE)) 35 return; 36 cpu_relax(); 37 } 38 udelay(delay); 39 } 40 41 qcom_smmu_tlb_sync_debug(smmu); 42 } 43 44 static void qcom_adreno_smmu_write_sctlr(struct arm_smmu_device *smmu, int idx, 45 u32 reg) 46 { 47 struct qcom_smmu *qsmmu = to_qcom_smmu(smmu); 48 49 /* 50 * On the GPU device we want to process subsequent transactions after a 51 * fault to keep the GPU from hanging 52 */ 53 reg |= ARM_SMMU_SCTLR_HUPCF; 54 55 if (qsmmu->stall_enabled & BIT(idx)) 56 reg |= ARM_SMMU_SCTLR_CFCFG; 57 58 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg); 59 } 60 61 static void qcom_adreno_smmu_get_fault_info(const void *cookie, 62 struct adreno_smmu_fault_info *info) 63 { 64 struct arm_smmu_domain *smmu_domain = (void *)cookie; 65 struct arm_smmu_cfg *cfg = &smmu_domain->cfg; 66 struct arm_smmu_device *smmu = smmu_domain->smmu; 67 68 info->fsr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSR); 69 info->fsynr0 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR0); 70 info->fsynr1 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR1); 71 info->far = arm_smmu_cb_readq(smmu, cfg->cbndx, ARM_SMMU_CB_FAR); 72 info->cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(cfg->cbndx)); 73 info->ttbr0 = arm_smmu_cb_readq(smmu, cfg->cbndx, ARM_SMMU_CB_TTBR0); 74 info->contextidr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_CONTEXTIDR); 75 } 76 77 static void qcom_adreno_smmu_set_stall(const void *cookie, bool enabled) 78 { 79 struct arm_smmu_domain *smmu_domain = (void *)cookie; 80 struct arm_smmu_cfg *cfg = &smmu_domain->cfg; 81 struct qcom_smmu *qsmmu = to_qcom_smmu(smmu_domain->smmu); 82 83 if (enabled) 84 qsmmu->stall_enabled |= BIT(cfg->cbndx); 85 else 86 qsmmu->stall_enabled &= ~BIT(cfg->cbndx); 87 } 88 89 static void qcom_adreno_smmu_resume_translation(const void *cookie, bool terminate) 90 { 91 struct arm_smmu_domain *smmu_domain = (void *)cookie; 92 struct arm_smmu_cfg *cfg = &smmu_domain->cfg; 93 struct arm_smmu_device *smmu = smmu_domain->smmu; 94 u32 reg = 0; 95 96 if (terminate) 97 reg |= ARM_SMMU_RESUME_TERMINATE; 98 99 arm_smmu_cb_write(smmu, cfg->cbndx, ARM_SMMU_CB_RESUME, reg); 100 } 101 102 #define QCOM_ADRENO_SMMU_GPU_SID 0 103 104 static bool qcom_adreno_smmu_is_gpu_device(struct device *dev) 105 { 106 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 107 int i; 108 109 /* 110 * The GPU will always use SID 0 so that is a handy way to uniquely 111 * identify it and configure it for per-instance pagetables 112 */ 113 for (i = 0; i < fwspec->num_ids; i++) { 114 u16 sid = FIELD_GET(ARM_SMMU_SMR_ID, fwspec->ids[i]); 115 116 if (sid == QCOM_ADRENO_SMMU_GPU_SID) 117 return true; 118 } 119 120 return false; 121 } 122 123 static const struct io_pgtable_cfg *qcom_adreno_smmu_get_ttbr1_cfg( 124 const void *cookie) 125 { 126 struct arm_smmu_domain *smmu_domain = (void *)cookie; 127 struct io_pgtable *pgtable = 128 io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops); 129 return &pgtable->cfg; 130 } 131 132 /* 133 * Local implementation to configure TTBR0 with the specified pagetable config. 134 * The GPU driver will call this to enable TTBR0 when per-instance pagetables 135 * are active 136 */ 137 138 static int qcom_adreno_smmu_set_ttbr0_cfg(const void *cookie, 139 const struct io_pgtable_cfg *pgtbl_cfg) 140 { 141 struct arm_smmu_domain *smmu_domain = (void *)cookie; 142 struct io_pgtable *pgtable = io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops); 143 struct arm_smmu_cfg *cfg = &smmu_domain->cfg; 144 struct arm_smmu_cb *cb = &smmu_domain->smmu->cbs[cfg->cbndx]; 145 146 /* The domain must have split pagetables already enabled */ 147 if (cb->tcr[0] & ARM_SMMU_TCR_EPD1) 148 return -EINVAL; 149 150 /* If the pagetable config is NULL, disable TTBR0 */ 151 if (!pgtbl_cfg) { 152 /* Do nothing if it is already disabled */ 153 if ((cb->tcr[0] & ARM_SMMU_TCR_EPD0)) 154 return -EINVAL; 155 156 /* Set TCR to the original configuration */ 157 cb->tcr[0] = arm_smmu_lpae_tcr(&pgtable->cfg); 158 cb->ttbr[0] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid); 159 } else { 160 u32 tcr = cb->tcr[0]; 161 162 /* Don't call this again if TTBR0 is already enabled */ 163 if (!(cb->tcr[0] & ARM_SMMU_TCR_EPD0)) 164 return -EINVAL; 165 166 tcr |= arm_smmu_lpae_tcr(pgtbl_cfg); 167 tcr &= ~(ARM_SMMU_TCR_EPD0 | ARM_SMMU_TCR_EPD1); 168 169 cb->tcr[0] = tcr; 170 cb->ttbr[0] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr; 171 cb->ttbr[0] |= FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid); 172 } 173 174 arm_smmu_write_context_bank(smmu_domain->smmu, cb->cfg->cbndx); 175 176 return 0; 177 } 178 179 static int qcom_adreno_smmu_alloc_context_bank(struct arm_smmu_domain *smmu_domain, 180 struct arm_smmu_device *smmu, 181 struct device *dev, int start) 182 { 183 int count; 184 185 /* 186 * Assign context bank 0 to the GPU device so the GPU hardware can 187 * switch pagetables 188 */ 189 if (qcom_adreno_smmu_is_gpu_device(dev)) { 190 start = 0; 191 count = 1; 192 } else { 193 start = 1; 194 count = smmu->num_context_banks; 195 } 196 197 return __arm_smmu_alloc_bitmap(smmu->context_map, start, count); 198 } 199 200 static bool qcom_adreno_can_do_ttbr1(struct arm_smmu_device *smmu) 201 { 202 const struct device_node *np = smmu->dev->of_node; 203 204 if (of_device_is_compatible(np, "qcom,msm8996-smmu-v2")) 205 return false; 206 207 return true; 208 } 209 210 static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain, 211 struct io_pgtable_cfg *pgtbl_cfg, struct device *dev) 212 { 213 struct adreno_smmu_priv *priv; 214 215 smmu_domain->cfg.flush_walk_prefer_tlbiasid = true; 216 217 /* Only enable split pagetables for the GPU device (SID 0) */ 218 if (!qcom_adreno_smmu_is_gpu_device(dev)) 219 return 0; 220 221 /* 222 * All targets that use the qcom,adreno-smmu compatible string *should* 223 * be AARCH64 stage 1 but double check because the arm-smmu code assumes 224 * that is the case when the TTBR1 quirk is enabled 225 */ 226 if (qcom_adreno_can_do_ttbr1(smmu_domain->smmu) && 227 (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) && 228 (smmu_domain->cfg.fmt == ARM_SMMU_CTX_FMT_AARCH64)) 229 pgtbl_cfg->quirks |= IO_PGTABLE_QUIRK_ARM_TTBR1; 230 231 /* 232 * Initialize private interface with GPU: 233 */ 234 235 priv = dev_get_drvdata(dev); 236 priv->cookie = smmu_domain; 237 priv->get_ttbr1_cfg = qcom_adreno_smmu_get_ttbr1_cfg; 238 priv->set_ttbr0_cfg = qcom_adreno_smmu_set_ttbr0_cfg; 239 priv->get_fault_info = qcom_adreno_smmu_get_fault_info; 240 priv->set_stall = qcom_adreno_smmu_set_stall; 241 priv->resume_translation = qcom_adreno_smmu_resume_translation; 242 243 return 0; 244 } 245 246 static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = { 247 { .compatible = "qcom,adreno" }, 248 { .compatible = "qcom,adreno-gmu" }, 249 { .compatible = "qcom,mdp4" }, 250 { .compatible = "qcom,mdss" }, 251 { .compatible = "qcom,qcm2290-mdss" }, 252 { .compatible = "qcom,sc7180-mdss" }, 253 { .compatible = "qcom,sc7180-mss-pil" }, 254 { .compatible = "qcom,sc7280-mdss" }, 255 { .compatible = "qcom,sc7280-mss-pil" }, 256 { .compatible = "qcom,sc8180x-mdss" }, 257 { .compatible = "qcom,sc8280xp-mdss" }, 258 { .compatible = "qcom,sdm670-mdss" }, 259 { .compatible = "qcom,sdm845-mdss" }, 260 { .compatible = "qcom,sdm845-mss-pil" }, 261 { .compatible = "qcom,sm6350-mdss" }, 262 { .compatible = "qcom,sm6375-mdss" }, 263 { .compatible = "qcom,sm8150-mdss" }, 264 { .compatible = "qcom,sm8250-mdss" }, 265 { .compatible = "qcom,x1e80100-mdss" }, 266 { } 267 }; 268 269 static int qcom_smmu_init_context(struct arm_smmu_domain *smmu_domain, 270 struct io_pgtable_cfg *pgtbl_cfg, struct device *dev) 271 { 272 smmu_domain->cfg.flush_walk_prefer_tlbiasid = true; 273 274 return 0; 275 } 276 277 static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu) 278 { 279 struct qcom_smmu *qsmmu = to_qcom_smmu(smmu); 280 unsigned int last_s2cr; 281 u32 reg; 282 u32 smr; 283 int i; 284 285 /* 286 * Some platforms support more than the Arm SMMU architected maximum of 287 * 128 stream matching groups. For unknown reasons, the additional 288 * groups don't exhibit the same behavior as the architected registers, 289 * so limit the groups to 128 until the behavior is fixed for the other 290 * groups. 291 */ 292 if (smmu->num_mapping_groups > 128) { 293 dev_notice(smmu->dev, "\tLimiting the stream matching groups to 128\n"); 294 smmu->num_mapping_groups = 128; 295 } 296 297 last_s2cr = ARM_SMMU_GR0_S2CR(smmu->num_mapping_groups - 1); 298 299 /* 300 * With some firmware versions writes to S2CR of type FAULT are 301 * ignored, and writing BYPASS will end up written as FAULT in the 302 * register. Perform a write to S2CR to detect if this is the case and 303 * if so reserve a context bank to emulate bypass streams. 304 */ 305 reg = FIELD_PREP(ARM_SMMU_S2CR_TYPE, S2CR_TYPE_BYPASS) | 306 FIELD_PREP(ARM_SMMU_S2CR_CBNDX, 0xff) | 307 FIELD_PREP(ARM_SMMU_S2CR_PRIVCFG, S2CR_PRIVCFG_DEFAULT); 308 arm_smmu_gr0_write(smmu, last_s2cr, reg); 309 reg = arm_smmu_gr0_read(smmu, last_s2cr); 310 if (FIELD_GET(ARM_SMMU_S2CR_TYPE, reg) != S2CR_TYPE_BYPASS) { 311 qsmmu->bypass_quirk = true; 312 qsmmu->bypass_cbndx = smmu->num_context_banks - 1; 313 314 set_bit(qsmmu->bypass_cbndx, smmu->context_map); 315 316 arm_smmu_cb_write(smmu, qsmmu->bypass_cbndx, ARM_SMMU_CB_SCTLR, 0); 317 318 reg = FIELD_PREP(ARM_SMMU_CBAR_TYPE, CBAR_TYPE_S1_TRANS_S2_BYPASS); 319 arm_smmu_gr1_write(smmu, ARM_SMMU_GR1_CBAR(qsmmu->bypass_cbndx), reg); 320 } 321 322 for (i = 0; i < smmu->num_mapping_groups; i++) { 323 smr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_SMR(i)); 324 325 if (FIELD_GET(ARM_SMMU_SMR_VALID, smr)) { 326 /* Ignore valid bit for SMR mask extraction. */ 327 smr &= ~ARM_SMMU_SMR_VALID; 328 smmu->smrs[i].id = FIELD_GET(ARM_SMMU_SMR_ID, smr); 329 smmu->smrs[i].mask = FIELD_GET(ARM_SMMU_SMR_MASK, smr); 330 smmu->smrs[i].valid = true; 331 332 smmu->s2crs[i].type = S2CR_TYPE_BYPASS; 333 smmu->s2crs[i].privcfg = S2CR_PRIVCFG_DEFAULT; 334 smmu->s2crs[i].cbndx = 0xff; 335 } 336 } 337 338 return 0; 339 } 340 341 static void qcom_smmu_write_s2cr(struct arm_smmu_device *smmu, int idx) 342 { 343 struct arm_smmu_s2cr *s2cr = smmu->s2crs + idx; 344 struct qcom_smmu *qsmmu = to_qcom_smmu(smmu); 345 u32 cbndx = s2cr->cbndx; 346 u32 type = s2cr->type; 347 u32 reg; 348 349 if (qsmmu->bypass_quirk) { 350 if (type == S2CR_TYPE_BYPASS) { 351 /* 352 * Firmware with quirky S2CR handling will substitute 353 * BYPASS writes with FAULT, so point the stream to the 354 * reserved context bank and ask for translation on the 355 * stream 356 */ 357 type = S2CR_TYPE_TRANS; 358 cbndx = qsmmu->bypass_cbndx; 359 } else if (type == S2CR_TYPE_FAULT) { 360 /* 361 * Firmware with quirky S2CR handling will ignore FAULT 362 * writes, so trick it to write FAULT by asking for a 363 * BYPASS. 364 */ 365 type = S2CR_TYPE_BYPASS; 366 cbndx = 0xff; 367 } 368 } 369 370 reg = FIELD_PREP(ARM_SMMU_S2CR_TYPE, type) | 371 FIELD_PREP(ARM_SMMU_S2CR_CBNDX, cbndx) | 372 FIELD_PREP(ARM_SMMU_S2CR_PRIVCFG, s2cr->privcfg); 373 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_S2CR(idx), reg); 374 } 375 376 static int qcom_smmu_def_domain_type(struct device *dev) 377 { 378 const struct of_device_id *match = 379 of_match_device(qcom_smmu_client_of_match, dev); 380 381 return match ? IOMMU_DOMAIN_IDENTITY : 0; 382 } 383 384 static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu) 385 { 386 int ret; 387 388 arm_mmu500_reset(smmu); 389 390 /* 391 * To address performance degradation in non-real time clients, 392 * such as USB and UFS, turn off wait-for-safe on sdm845 based boards, 393 * such as MTP and db845, whose firmwares implement secure monitor 394 * call handlers to turn on/off the wait-for-safe logic. 395 */ 396 ret = qcom_scm_qsmmu500_wait_safe_toggle(0); 397 if (ret) 398 dev_warn(smmu->dev, "Failed to turn off SAFE logic\n"); 399 400 return ret; 401 } 402 403 static const struct arm_smmu_impl qcom_smmu_v2_impl = { 404 .init_context = qcom_smmu_init_context, 405 .cfg_probe = qcom_smmu_cfg_probe, 406 .def_domain_type = qcom_smmu_def_domain_type, 407 .write_s2cr = qcom_smmu_write_s2cr, 408 .tlb_sync = qcom_smmu_tlb_sync, 409 }; 410 411 static const struct arm_smmu_impl qcom_smmu_500_impl = { 412 .init_context = qcom_smmu_init_context, 413 .cfg_probe = qcom_smmu_cfg_probe, 414 .def_domain_type = qcom_smmu_def_domain_type, 415 .reset = arm_mmu500_reset, 416 .write_s2cr = qcom_smmu_write_s2cr, 417 .tlb_sync = qcom_smmu_tlb_sync, 418 #ifdef CONFIG_ARM_SMMU_QCOM_DEBUG 419 .context_fault = qcom_smmu_context_fault, 420 .context_fault_needs_threaded_irq = true, 421 #endif 422 }; 423 424 static const struct arm_smmu_impl sdm845_smmu_500_impl = { 425 .init_context = qcom_smmu_init_context, 426 .cfg_probe = qcom_smmu_cfg_probe, 427 .def_domain_type = qcom_smmu_def_domain_type, 428 .reset = qcom_sdm845_smmu500_reset, 429 .write_s2cr = qcom_smmu_write_s2cr, 430 .tlb_sync = qcom_smmu_tlb_sync, 431 #ifdef CONFIG_ARM_SMMU_QCOM_DEBUG 432 .context_fault = qcom_smmu_context_fault, 433 .context_fault_needs_threaded_irq = true, 434 #endif 435 }; 436 437 static const struct arm_smmu_impl qcom_adreno_smmu_v2_impl = { 438 .init_context = qcom_adreno_smmu_init_context, 439 .def_domain_type = qcom_smmu_def_domain_type, 440 .alloc_context_bank = qcom_adreno_smmu_alloc_context_bank, 441 .write_sctlr = qcom_adreno_smmu_write_sctlr, 442 .tlb_sync = qcom_smmu_tlb_sync, 443 }; 444 445 static const struct arm_smmu_impl qcom_adreno_smmu_500_impl = { 446 .init_context = qcom_adreno_smmu_init_context, 447 .def_domain_type = qcom_smmu_def_domain_type, 448 .reset = arm_mmu500_reset, 449 .alloc_context_bank = qcom_adreno_smmu_alloc_context_bank, 450 .write_sctlr = qcom_adreno_smmu_write_sctlr, 451 .tlb_sync = qcom_smmu_tlb_sync, 452 }; 453 454 static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu, 455 const struct qcom_smmu_match_data *data) 456 { 457 const struct device_node *np = smmu->dev->of_node; 458 const struct arm_smmu_impl *impl; 459 struct qcom_smmu *qsmmu; 460 461 if (!data) 462 return ERR_PTR(-EINVAL); 463 464 if (np && of_device_is_compatible(np, "qcom,adreno-smmu")) 465 impl = data->adreno_impl; 466 else 467 impl = data->impl; 468 469 if (!impl) 470 return smmu; 471 472 /* Check to make sure qcom_scm has finished probing */ 473 if (!qcom_scm_is_available()) 474 return ERR_PTR(dev_err_probe(smmu->dev, -EPROBE_DEFER, 475 "qcom_scm not ready\n")); 476 477 qsmmu = devm_krealloc(smmu->dev, smmu, sizeof(*qsmmu), GFP_KERNEL); 478 if (!qsmmu) 479 return ERR_PTR(-ENOMEM); 480 481 qsmmu->smmu.impl = impl; 482 qsmmu->cfg = data->cfg; 483 484 return &qsmmu->smmu; 485 } 486 487 /* Implementation Defined Register Space 0 register offsets */ 488 static const u32 qcom_smmu_impl0_reg_offset[] = { 489 [QCOM_SMMU_TBU_PWR_STATUS] = 0x2204, 490 [QCOM_SMMU_STATS_SYNC_INV_TBU_ACK] = 0x25dc, 491 [QCOM_SMMU_MMU2QSS_AND_SAFE_WAIT_CNTR] = 0x2670, 492 }; 493 494 static const struct qcom_smmu_config qcom_smmu_impl0_cfg = { 495 .reg_offset = qcom_smmu_impl0_reg_offset, 496 }; 497 498 /* 499 * It is not yet possible to use MDP SMMU with the bypass quirk on the msm8996, 500 * there are not enough context banks. 501 */ 502 static const struct qcom_smmu_match_data msm8996_smmu_data = { 503 .impl = NULL, 504 .adreno_impl = &qcom_adreno_smmu_v2_impl, 505 }; 506 507 static const struct qcom_smmu_match_data qcom_smmu_v2_data = { 508 .impl = &qcom_smmu_v2_impl, 509 .adreno_impl = &qcom_adreno_smmu_v2_impl, 510 }; 511 512 static const struct qcom_smmu_match_data sdm845_smmu_500_data = { 513 .impl = &sdm845_smmu_500_impl, 514 /* 515 * No need for adreno impl here. On sdm845 the Adreno SMMU is handled 516 * by the separate sdm845-smmu-v2 device. 517 */ 518 /* Also no debug configuration. */ 519 }; 520 521 static const struct qcom_smmu_match_data qcom_smmu_500_impl0_data = { 522 .impl = &qcom_smmu_500_impl, 523 .adreno_impl = &qcom_adreno_smmu_500_impl, 524 .cfg = &qcom_smmu_impl0_cfg, 525 }; 526 527 /* 528 * Do not add any more qcom,SOC-smmu-500 entries to this list, unless they need 529 * special handling and can not be covered by the qcom,smmu-500 entry. 530 */ 531 static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = { 532 { .compatible = "qcom,msm8996-smmu-v2", .data = &msm8996_smmu_data }, 533 { .compatible = "qcom,msm8998-smmu-v2", .data = &qcom_smmu_v2_data }, 534 { .compatible = "qcom,qcm2290-smmu-500", .data = &qcom_smmu_500_impl0_data }, 535 { .compatible = "qcom,qdu1000-smmu-500", .data = &qcom_smmu_500_impl0_data }, 536 { .compatible = "qcom,sc7180-smmu-500", .data = &qcom_smmu_500_impl0_data }, 537 { .compatible = "qcom,sc7180-smmu-v2", .data = &qcom_smmu_v2_data }, 538 { .compatible = "qcom,sc7280-smmu-500", .data = &qcom_smmu_500_impl0_data }, 539 { .compatible = "qcom,sc8180x-smmu-500", .data = &qcom_smmu_500_impl0_data }, 540 { .compatible = "qcom,sc8280xp-smmu-500", .data = &qcom_smmu_500_impl0_data }, 541 { .compatible = "qcom,sdm630-smmu-v2", .data = &qcom_smmu_v2_data }, 542 { .compatible = "qcom,sdm845-smmu-v2", .data = &qcom_smmu_v2_data }, 543 { .compatible = "qcom,sdm845-smmu-500", .data = &sdm845_smmu_500_data }, 544 { .compatible = "qcom,sm6115-smmu-500", .data = &qcom_smmu_500_impl0_data}, 545 { .compatible = "qcom,sm6125-smmu-500", .data = &qcom_smmu_500_impl0_data }, 546 { .compatible = "qcom,sm6350-smmu-v2", .data = &qcom_smmu_v2_data }, 547 { .compatible = "qcom,sm6350-smmu-500", .data = &qcom_smmu_500_impl0_data }, 548 { .compatible = "qcom,sm6375-smmu-v2", .data = &qcom_smmu_v2_data }, 549 { .compatible = "qcom,sm6375-smmu-500", .data = &qcom_smmu_500_impl0_data }, 550 { .compatible = "qcom,sm7150-smmu-v2", .data = &qcom_smmu_v2_data }, 551 { .compatible = "qcom,sm8150-smmu-500", .data = &qcom_smmu_500_impl0_data }, 552 { .compatible = "qcom,sm8250-smmu-500", .data = &qcom_smmu_500_impl0_data }, 553 { .compatible = "qcom,sm8350-smmu-500", .data = &qcom_smmu_500_impl0_data }, 554 { .compatible = "qcom,sm8450-smmu-500", .data = &qcom_smmu_500_impl0_data }, 555 { .compatible = "qcom,smmu-500", .data = &qcom_smmu_500_impl0_data }, 556 { } 557 }; 558 559 #ifdef CONFIG_ACPI 560 static struct acpi_platform_list qcom_acpi_platlist[] = { 561 { "LENOVO", "CB-01 ", 0x8180, ACPI_SIG_IORT, equal, "QCOM SMMU" }, 562 { "QCOM ", "QCOMEDK2", 0x8180, ACPI_SIG_IORT, equal, "QCOM SMMU" }, 563 { } 564 }; 565 #endif 566 567 static int qcom_smmu_tbu_probe(struct platform_device *pdev) 568 { 569 struct device *dev = &pdev->dev; 570 int ret; 571 572 if (IS_ENABLED(CONFIG_ARM_SMMU_QCOM_DEBUG)) { 573 ret = qcom_tbu_probe(pdev); 574 if (ret) 575 return ret; 576 } 577 578 if (dev->pm_domain) { 579 pm_runtime_set_active(dev); 580 pm_runtime_enable(dev); 581 } 582 583 return 0; 584 } 585 586 static const struct of_device_id qcom_smmu_tbu_of_match[] = { 587 { .compatible = "qcom,sc7280-tbu" }, 588 { .compatible = "qcom,sdm845-tbu" }, 589 { } 590 }; 591 592 static struct platform_driver qcom_smmu_tbu_driver = { 593 .driver = { 594 .name = "qcom_tbu", 595 .of_match_table = qcom_smmu_tbu_of_match, 596 }, 597 .probe = qcom_smmu_tbu_probe, 598 }; 599 600 struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu) 601 { 602 const struct device_node *np = smmu->dev->of_node; 603 const struct of_device_id *match; 604 static u8 tbu_registered; 605 606 if (!tbu_registered++) 607 platform_driver_register(&qcom_smmu_tbu_driver); 608 609 #ifdef CONFIG_ACPI 610 if (np == NULL) { 611 /* Match platform for ACPI boot */ 612 if (acpi_match_platform_list(qcom_acpi_platlist) >= 0) 613 return qcom_smmu_create(smmu, &qcom_smmu_500_impl0_data); 614 } 615 #endif 616 617 match = of_match_node(qcom_smmu_impl_of_match, np); 618 if (match) 619 return qcom_smmu_create(smmu, match->data); 620 621 /* 622 * If you hit this WARN_ON() you are missing an entry in the 623 * qcom_smmu_impl_of_match[] table, and GPU per-process page- 624 * tables will be broken. 625 */ 626 WARN(of_device_is_compatible(np, "qcom,adreno-smmu"), 627 "Missing qcom_smmu_impl_of_match entry for: %s", 628 dev_name(smmu->dev)); 629 630 return smmu; 631 } 632