xref: /linux/drivers/iommu/amd/iommu.c (revision b8265621f4888af9494e1d685620871ec81bc33d)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
4  * Author: Joerg Roedel <jroedel@suse.de>
5  *         Leo Duran <leo.duran@amd.com>
6  */
7 
8 #define pr_fmt(fmt)     "AMD-Vi: " fmt
9 #define dev_fmt(fmt)    pr_fmt(fmt)
10 
11 #include <linux/ratelimit.h>
12 #include <linux/pci.h>
13 #include <linux/acpi.h>
14 #include <linux/amba/bus.h>
15 #include <linux/platform_device.h>
16 #include <linux/pci-ats.h>
17 #include <linux/bitmap.h>
18 #include <linux/slab.h>
19 #include <linux/debugfs.h>
20 #include <linux/scatterlist.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/dma-direct.h>
23 #include <linux/dma-iommu.h>
24 #include <linux/iommu-helper.h>
25 #include <linux/delay.h>
26 #include <linux/amd-iommu.h>
27 #include <linux/notifier.h>
28 #include <linux/export.h>
29 #include <linux/irq.h>
30 #include <linux/msi.h>
31 #include <linux/dma-contiguous.h>
32 #include <linux/irqdomain.h>
33 #include <linux/percpu.h>
34 #include <linux/iova.h>
35 #include <asm/irq_remapping.h>
36 #include <asm/io_apic.h>
37 #include <asm/apic.h>
38 #include <asm/hw_irq.h>
39 #include <asm/msidef.h>
40 #include <asm/proto.h>
41 #include <asm/iommu.h>
42 #include <asm/gart.h>
43 #include <asm/dma.h>
44 
45 #include "amd_iommu.h"
46 #include "../irq_remapping.h"
47 
48 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
49 
50 #define LOOP_TIMEOUT	100000
51 
52 /* IO virtual address start page frame number */
53 #define IOVA_START_PFN		(1)
54 #define IOVA_PFN(addr)		((addr) >> PAGE_SHIFT)
55 
56 /* Reserved IOVA ranges */
57 #define MSI_RANGE_START		(0xfee00000)
58 #define MSI_RANGE_END		(0xfeefffff)
59 #define HT_RANGE_START		(0xfd00000000ULL)
60 #define HT_RANGE_END		(0xffffffffffULL)
61 
62 /*
63  * This bitmap is used to advertise the page sizes our hardware support
64  * to the IOMMU core, which will then use this information to split
65  * physically contiguous memory regions it is mapping into page sizes
66  * that we support.
67  *
68  * 512GB Pages are not supported due to a hardware bug
69  */
70 #define AMD_IOMMU_PGSIZES	((~0xFFFUL) & ~(2ULL << 38))
71 
72 #define DEFAULT_PGTABLE_LEVEL	PAGE_MODE_3_LEVEL
73 
74 static DEFINE_SPINLOCK(pd_bitmap_lock);
75 
76 /* List of all available dev_data structures */
77 static LLIST_HEAD(dev_data_list);
78 
79 LIST_HEAD(ioapic_map);
80 LIST_HEAD(hpet_map);
81 LIST_HEAD(acpihid_map);
82 
83 /*
84  * Domain for untranslated devices - only allocated
85  * if iommu=pt passed on kernel cmd line.
86  */
87 const struct iommu_ops amd_iommu_ops;
88 
89 static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
90 int amd_iommu_max_glx_val = -1;
91 
92 /*
93  * general struct to manage commands send to an IOMMU
94  */
95 struct iommu_cmd {
96 	u32 data[4];
97 };
98 
99 struct kmem_cache *amd_iommu_irq_cache;
100 
101 static void update_domain(struct protection_domain *domain);
102 static void detach_device(struct device *dev);
103 static void update_and_flush_device_table(struct protection_domain *domain,
104 					  struct domain_pgtable *pgtable);
105 
106 /****************************************************************************
107  *
108  * Helper functions
109  *
110  ****************************************************************************/
111 
112 static inline u16 get_pci_device_id(struct device *dev)
113 {
114 	struct pci_dev *pdev = to_pci_dev(dev);
115 
116 	return pci_dev_id(pdev);
117 }
118 
119 static inline int get_acpihid_device_id(struct device *dev,
120 					struct acpihid_map_entry **entry)
121 {
122 	struct acpi_device *adev = ACPI_COMPANION(dev);
123 	struct acpihid_map_entry *p;
124 
125 	if (!adev)
126 		return -ENODEV;
127 
128 	list_for_each_entry(p, &acpihid_map, list) {
129 		if (acpi_dev_hid_uid_match(adev, p->hid,
130 					   p->uid[0] ? p->uid : NULL)) {
131 			if (entry)
132 				*entry = p;
133 			return p->devid;
134 		}
135 	}
136 	return -EINVAL;
137 }
138 
139 static inline int get_device_id(struct device *dev)
140 {
141 	int devid;
142 
143 	if (dev_is_pci(dev))
144 		devid = get_pci_device_id(dev);
145 	else
146 		devid = get_acpihid_device_id(dev, NULL);
147 
148 	return devid;
149 }
150 
151 static struct protection_domain *to_pdomain(struct iommu_domain *dom)
152 {
153 	return container_of(dom, struct protection_domain, domain);
154 }
155 
156 static void amd_iommu_domain_get_pgtable(struct protection_domain *domain,
157 					 struct domain_pgtable *pgtable)
158 {
159 	u64 pt_root = atomic64_read(&domain->pt_root);
160 
161 	pgtable->root = (u64 *)(pt_root & PAGE_MASK);
162 	pgtable->mode = pt_root & 7; /* lowest 3 bits encode pgtable mode */
163 }
164 
165 static u64 amd_iommu_domain_encode_pgtable(u64 *root, int mode)
166 {
167 	u64 pt_root;
168 
169 	/* lowest 3 bits encode pgtable mode */
170 	pt_root = mode & 7;
171 	pt_root |= (u64)root;
172 
173 	return pt_root;
174 }
175 
176 static struct iommu_dev_data *alloc_dev_data(u16 devid)
177 {
178 	struct iommu_dev_data *dev_data;
179 
180 	dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
181 	if (!dev_data)
182 		return NULL;
183 
184 	spin_lock_init(&dev_data->lock);
185 	dev_data->devid = devid;
186 	ratelimit_default_init(&dev_data->rs);
187 
188 	llist_add(&dev_data->dev_data_list, &dev_data_list);
189 	return dev_data;
190 }
191 
192 static struct iommu_dev_data *search_dev_data(u16 devid)
193 {
194 	struct iommu_dev_data *dev_data;
195 	struct llist_node *node;
196 
197 	if (llist_empty(&dev_data_list))
198 		return NULL;
199 
200 	node = dev_data_list.first;
201 	llist_for_each_entry(dev_data, node, dev_data_list) {
202 		if (dev_data->devid == devid)
203 			return dev_data;
204 	}
205 
206 	return NULL;
207 }
208 
209 static int clone_alias(struct pci_dev *pdev, u16 alias, void *data)
210 {
211 	u16 devid = pci_dev_id(pdev);
212 
213 	if (devid == alias)
214 		return 0;
215 
216 	amd_iommu_rlookup_table[alias] =
217 		amd_iommu_rlookup_table[devid];
218 	memcpy(amd_iommu_dev_table[alias].data,
219 	       amd_iommu_dev_table[devid].data,
220 	       sizeof(amd_iommu_dev_table[alias].data));
221 
222 	return 0;
223 }
224 
225 static void clone_aliases(struct pci_dev *pdev)
226 {
227 	if (!pdev)
228 		return;
229 
230 	/*
231 	 * The IVRS alias stored in the alias table may not be
232 	 * part of the PCI DMA aliases if it's bus differs
233 	 * from the original device.
234 	 */
235 	clone_alias(pdev, amd_iommu_alias_table[pci_dev_id(pdev)], NULL);
236 
237 	pci_for_each_dma_alias(pdev, clone_alias, NULL);
238 }
239 
240 static struct pci_dev *setup_aliases(struct device *dev)
241 {
242 	struct pci_dev *pdev = to_pci_dev(dev);
243 	u16 ivrs_alias;
244 
245 	/* For ACPI HID devices, there are no aliases */
246 	if (!dev_is_pci(dev))
247 		return NULL;
248 
249 	/*
250 	 * Add the IVRS alias to the pci aliases if it is on the same
251 	 * bus. The IVRS table may know about a quirk that we don't.
252 	 */
253 	ivrs_alias = amd_iommu_alias_table[pci_dev_id(pdev)];
254 	if (ivrs_alias != pci_dev_id(pdev) &&
255 	    PCI_BUS_NUM(ivrs_alias) == pdev->bus->number)
256 		pci_add_dma_alias(pdev, ivrs_alias & 0xff, 1);
257 
258 	clone_aliases(pdev);
259 
260 	return pdev;
261 }
262 
263 static struct iommu_dev_data *find_dev_data(u16 devid)
264 {
265 	struct iommu_dev_data *dev_data;
266 	struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
267 
268 	dev_data = search_dev_data(devid);
269 
270 	if (dev_data == NULL) {
271 		dev_data = alloc_dev_data(devid);
272 		if (!dev_data)
273 			return NULL;
274 
275 		if (translation_pre_enabled(iommu))
276 			dev_data->defer_attach = true;
277 	}
278 
279 	return dev_data;
280 }
281 
282 /*
283 * Find or create an IOMMU group for a acpihid device.
284 */
285 static struct iommu_group *acpihid_device_group(struct device *dev)
286 {
287 	struct acpihid_map_entry *p, *entry = NULL;
288 	int devid;
289 
290 	devid = get_acpihid_device_id(dev, &entry);
291 	if (devid < 0)
292 		return ERR_PTR(devid);
293 
294 	list_for_each_entry(p, &acpihid_map, list) {
295 		if ((devid == p->devid) && p->group)
296 			entry->group = p->group;
297 	}
298 
299 	if (!entry->group)
300 		entry->group = generic_device_group(dev);
301 	else
302 		iommu_group_ref_get(entry->group);
303 
304 	return entry->group;
305 }
306 
307 static bool pci_iommuv2_capable(struct pci_dev *pdev)
308 {
309 	static const int caps[] = {
310 		PCI_EXT_CAP_ID_PRI,
311 		PCI_EXT_CAP_ID_PASID,
312 	};
313 	int i, pos;
314 
315 	if (!pci_ats_supported(pdev))
316 		return false;
317 
318 	for (i = 0; i < 2; ++i) {
319 		pos = pci_find_ext_capability(pdev, caps[i]);
320 		if (pos == 0)
321 			return false;
322 	}
323 
324 	return true;
325 }
326 
327 static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
328 {
329 	struct iommu_dev_data *dev_data;
330 
331 	dev_data = dev_iommu_priv_get(&pdev->dev);
332 
333 	return dev_data->errata & (1 << erratum) ? true : false;
334 }
335 
336 /*
337  * This function checks if the driver got a valid device from the caller to
338  * avoid dereferencing invalid pointers.
339  */
340 static bool check_device(struct device *dev)
341 {
342 	int devid;
343 
344 	if (!dev)
345 		return false;
346 
347 	devid = get_device_id(dev);
348 	if (devid < 0)
349 		return false;
350 
351 	/* Out of our scope? */
352 	if (devid > amd_iommu_last_bdf)
353 		return false;
354 
355 	if (amd_iommu_rlookup_table[devid] == NULL)
356 		return false;
357 
358 	return true;
359 }
360 
361 static int iommu_init_device(struct device *dev)
362 {
363 	struct iommu_dev_data *dev_data;
364 	int devid;
365 
366 	if (dev_iommu_priv_get(dev))
367 		return 0;
368 
369 	devid = get_device_id(dev);
370 	if (devid < 0)
371 		return devid;
372 
373 	dev_data = find_dev_data(devid);
374 	if (!dev_data)
375 		return -ENOMEM;
376 
377 	dev_data->pdev = setup_aliases(dev);
378 
379 	/*
380 	 * By default we use passthrough mode for IOMMUv2 capable device.
381 	 * But if amd_iommu=force_isolation is set (e.g. to debug DMA to
382 	 * invalid address), we ignore the capability for the device so
383 	 * it'll be forced to go into translation mode.
384 	 */
385 	if ((iommu_default_passthrough() || !amd_iommu_force_isolation) &&
386 	    dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) {
387 		struct amd_iommu *iommu;
388 
389 		iommu = amd_iommu_rlookup_table[dev_data->devid];
390 		dev_data->iommu_v2 = iommu->is_iommu_v2;
391 	}
392 
393 	dev_iommu_priv_set(dev, dev_data);
394 
395 	return 0;
396 }
397 
398 static void iommu_ignore_device(struct device *dev)
399 {
400 	int devid;
401 
402 	devid = get_device_id(dev);
403 	if (devid < 0)
404 		return;
405 
406 	amd_iommu_rlookup_table[devid] = NULL;
407 	memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
408 
409 	setup_aliases(dev);
410 }
411 
412 static void amd_iommu_uninit_device(struct device *dev)
413 {
414 	struct iommu_dev_data *dev_data;
415 
416 	dev_data = dev_iommu_priv_get(dev);
417 	if (!dev_data)
418 		return;
419 
420 	if (dev_data->domain)
421 		detach_device(dev);
422 
423 	dev_iommu_priv_set(dev, NULL);
424 
425 	/*
426 	 * We keep dev_data around for unplugged devices and reuse it when the
427 	 * device is re-plugged - not doing so would introduce a ton of races.
428 	 */
429 }
430 
431 /*
432  * Helper function to get the first pte of a large mapping
433  */
434 static u64 *first_pte_l7(u64 *pte, unsigned long *page_size,
435 			 unsigned long *count)
436 {
437 	unsigned long pte_mask, pg_size, cnt;
438 	u64 *fpte;
439 
440 	pg_size  = PTE_PAGE_SIZE(*pte);
441 	cnt      = PAGE_SIZE_PTE_COUNT(pg_size);
442 	pte_mask = ~((cnt << 3) - 1);
443 	fpte     = (u64 *)(((unsigned long)pte) & pte_mask);
444 
445 	if (page_size)
446 		*page_size = pg_size;
447 
448 	if (count)
449 		*count = cnt;
450 
451 	return fpte;
452 }
453 
454 /****************************************************************************
455  *
456  * Interrupt handling functions
457  *
458  ****************************************************************************/
459 
460 static void dump_dte_entry(u16 devid)
461 {
462 	int i;
463 
464 	for (i = 0; i < 4; ++i)
465 		pr_err("DTE[%d]: %016llx\n", i,
466 			amd_iommu_dev_table[devid].data[i]);
467 }
468 
469 static void dump_command(unsigned long phys_addr)
470 {
471 	struct iommu_cmd *cmd = iommu_phys_to_virt(phys_addr);
472 	int i;
473 
474 	for (i = 0; i < 4; ++i)
475 		pr_err("CMD[%d]: %08x\n", i, cmd->data[i]);
476 }
477 
478 static void amd_iommu_report_page_fault(u16 devid, u16 domain_id,
479 					u64 address, int flags)
480 {
481 	struct iommu_dev_data *dev_data = NULL;
482 	struct pci_dev *pdev;
483 
484 	pdev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(devid),
485 					   devid & 0xff);
486 	if (pdev)
487 		dev_data = dev_iommu_priv_get(&pdev->dev);
488 
489 	if (dev_data && __ratelimit(&dev_data->rs)) {
490 		pci_err(pdev, "Event logged [IO_PAGE_FAULT domain=0x%04x address=0x%llx flags=0x%04x]\n",
491 			domain_id, address, flags);
492 	} else if (printk_ratelimit()) {
493 		pr_err("Event logged [IO_PAGE_FAULT device=%02x:%02x.%x domain=0x%04x address=0x%llx flags=0x%04x]\n",
494 			PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
495 			domain_id, address, flags);
496 	}
497 
498 	if (pdev)
499 		pci_dev_put(pdev);
500 }
501 
502 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
503 {
504 	struct device *dev = iommu->iommu.dev;
505 	int type, devid, pasid, flags, tag;
506 	volatile u32 *event = __evt;
507 	int count = 0;
508 	u64 address;
509 
510 retry:
511 	type    = (event[1] >> EVENT_TYPE_SHIFT)  & EVENT_TYPE_MASK;
512 	devid   = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
513 	pasid   = (event[0] & EVENT_DOMID_MASK_HI) |
514 		  (event[1] & EVENT_DOMID_MASK_LO);
515 	flags   = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
516 	address = (u64)(((u64)event[3]) << 32) | event[2];
517 
518 	if (type == 0) {
519 		/* Did we hit the erratum? */
520 		if (++count == LOOP_TIMEOUT) {
521 			pr_err("No event written to event log\n");
522 			return;
523 		}
524 		udelay(1);
525 		goto retry;
526 	}
527 
528 	if (type == EVENT_TYPE_IO_FAULT) {
529 		amd_iommu_report_page_fault(devid, pasid, address, flags);
530 		return;
531 	}
532 
533 	switch (type) {
534 	case EVENT_TYPE_ILL_DEV:
535 		dev_err(dev, "Event logged [ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n",
536 			PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
537 			pasid, address, flags);
538 		dump_dte_entry(devid);
539 		break;
540 	case EVENT_TYPE_DEV_TAB_ERR:
541 		dev_err(dev, "Event logged [DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
542 			"address=0x%llx flags=0x%04x]\n",
543 			PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
544 			address, flags);
545 		break;
546 	case EVENT_TYPE_PAGE_TAB_ERR:
547 		dev_err(dev, "Event logged [PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x pasid=0x%04x address=0x%llx flags=0x%04x]\n",
548 			PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
549 			pasid, address, flags);
550 		break;
551 	case EVENT_TYPE_ILL_CMD:
552 		dev_err(dev, "Event logged [ILLEGAL_COMMAND_ERROR address=0x%llx]\n", address);
553 		dump_command(address);
554 		break;
555 	case EVENT_TYPE_CMD_HARD_ERR:
556 		dev_err(dev, "Event logged [COMMAND_HARDWARE_ERROR address=0x%llx flags=0x%04x]\n",
557 			address, flags);
558 		break;
559 	case EVENT_TYPE_IOTLB_INV_TO:
560 		dev_err(dev, "Event logged [IOTLB_INV_TIMEOUT device=%02x:%02x.%x address=0x%llx]\n",
561 			PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
562 			address);
563 		break;
564 	case EVENT_TYPE_INV_DEV_REQ:
565 		dev_err(dev, "Event logged [INVALID_DEVICE_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n",
566 			PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
567 			pasid, address, flags);
568 		break;
569 	case EVENT_TYPE_INV_PPR_REQ:
570 		pasid = PPR_PASID(*((u64 *)__evt));
571 		tag = event[1] & 0x03FF;
572 		dev_err(dev, "Event logged [INVALID_PPR_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x tag=0x%03x]\n",
573 			PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
574 			pasid, address, flags, tag);
575 		break;
576 	default:
577 		dev_err(dev, "Event logged [UNKNOWN event[0]=0x%08x event[1]=0x%08x event[2]=0x%08x event[3]=0x%08x\n",
578 			event[0], event[1], event[2], event[3]);
579 	}
580 
581 	memset(__evt, 0, 4 * sizeof(u32));
582 }
583 
584 static void iommu_poll_events(struct amd_iommu *iommu)
585 {
586 	u32 head, tail;
587 
588 	head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
589 	tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
590 
591 	while (head != tail) {
592 		iommu_print_event(iommu, iommu->evt_buf + head);
593 		head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE;
594 	}
595 
596 	writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
597 }
598 
599 static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
600 {
601 	struct amd_iommu_fault fault;
602 
603 	if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
604 		pr_err_ratelimited("Unknown PPR request received\n");
605 		return;
606 	}
607 
608 	fault.address   = raw[1];
609 	fault.pasid     = PPR_PASID(raw[0]);
610 	fault.device_id = PPR_DEVID(raw[0]);
611 	fault.tag       = PPR_TAG(raw[0]);
612 	fault.flags     = PPR_FLAGS(raw[0]);
613 
614 	atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
615 }
616 
617 static void iommu_poll_ppr_log(struct amd_iommu *iommu)
618 {
619 	u32 head, tail;
620 
621 	if (iommu->ppr_log == NULL)
622 		return;
623 
624 	head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
625 	tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
626 
627 	while (head != tail) {
628 		volatile u64 *raw;
629 		u64 entry[2];
630 		int i;
631 
632 		raw = (u64 *)(iommu->ppr_log + head);
633 
634 		/*
635 		 * Hardware bug: Interrupt may arrive before the entry is
636 		 * written to memory. If this happens we need to wait for the
637 		 * entry to arrive.
638 		 */
639 		for (i = 0; i < LOOP_TIMEOUT; ++i) {
640 			if (PPR_REQ_TYPE(raw[0]) != 0)
641 				break;
642 			udelay(1);
643 		}
644 
645 		/* Avoid memcpy function-call overhead */
646 		entry[0] = raw[0];
647 		entry[1] = raw[1];
648 
649 		/*
650 		 * To detect the hardware bug we need to clear the entry
651 		 * back to zero.
652 		 */
653 		raw[0] = raw[1] = 0UL;
654 
655 		/* Update head pointer of hardware ring-buffer */
656 		head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
657 		writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
658 
659 		/* Handle PPR entry */
660 		iommu_handle_ppr_entry(iommu, entry);
661 
662 		/* Refresh ring-buffer information */
663 		head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
664 		tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
665 	}
666 }
667 
668 #ifdef CONFIG_IRQ_REMAP
669 static int (*iommu_ga_log_notifier)(u32);
670 
671 int amd_iommu_register_ga_log_notifier(int (*notifier)(u32))
672 {
673 	iommu_ga_log_notifier = notifier;
674 
675 	return 0;
676 }
677 EXPORT_SYMBOL(amd_iommu_register_ga_log_notifier);
678 
679 static void iommu_poll_ga_log(struct amd_iommu *iommu)
680 {
681 	u32 head, tail, cnt = 0;
682 
683 	if (iommu->ga_log == NULL)
684 		return;
685 
686 	head = readl(iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
687 	tail = readl(iommu->mmio_base + MMIO_GA_TAIL_OFFSET);
688 
689 	while (head != tail) {
690 		volatile u64 *raw;
691 		u64 log_entry;
692 
693 		raw = (u64 *)(iommu->ga_log + head);
694 		cnt++;
695 
696 		/* Avoid memcpy function-call overhead */
697 		log_entry = *raw;
698 
699 		/* Update head pointer of hardware ring-buffer */
700 		head = (head + GA_ENTRY_SIZE) % GA_LOG_SIZE;
701 		writel(head, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
702 
703 		/* Handle GA entry */
704 		switch (GA_REQ_TYPE(log_entry)) {
705 		case GA_GUEST_NR:
706 			if (!iommu_ga_log_notifier)
707 				break;
708 
709 			pr_debug("%s: devid=%#x, ga_tag=%#x\n",
710 				 __func__, GA_DEVID(log_entry),
711 				 GA_TAG(log_entry));
712 
713 			if (iommu_ga_log_notifier(GA_TAG(log_entry)) != 0)
714 				pr_err("GA log notifier failed.\n");
715 			break;
716 		default:
717 			break;
718 		}
719 	}
720 }
721 #endif /* CONFIG_IRQ_REMAP */
722 
723 #define AMD_IOMMU_INT_MASK	\
724 	(MMIO_STATUS_EVT_INT_MASK | \
725 	 MMIO_STATUS_PPR_INT_MASK | \
726 	 MMIO_STATUS_GALOG_INT_MASK)
727 
728 irqreturn_t amd_iommu_int_thread(int irq, void *data)
729 {
730 	struct amd_iommu *iommu = (struct amd_iommu *) data;
731 	u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
732 
733 	while (status & AMD_IOMMU_INT_MASK) {
734 		/* Enable EVT and PPR and GA interrupts again */
735 		writel(AMD_IOMMU_INT_MASK,
736 			iommu->mmio_base + MMIO_STATUS_OFFSET);
737 
738 		if (status & MMIO_STATUS_EVT_INT_MASK) {
739 			pr_devel("Processing IOMMU Event Log\n");
740 			iommu_poll_events(iommu);
741 		}
742 
743 		if (status & MMIO_STATUS_PPR_INT_MASK) {
744 			pr_devel("Processing IOMMU PPR Log\n");
745 			iommu_poll_ppr_log(iommu);
746 		}
747 
748 #ifdef CONFIG_IRQ_REMAP
749 		if (status & MMIO_STATUS_GALOG_INT_MASK) {
750 			pr_devel("Processing IOMMU GA Log\n");
751 			iommu_poll_ga_log(iommu);
752 		}
753 #endif
754 
755 		/*
756 		 * Hardware bug: ERBT1312
757 		 * When re-enabling interrupt (by writing 1
758 		 * to clear the bit), the hardware might also try to set
759 		 * the interrupt bit in the event status register.
760 		 * In this scenario, the bit will be set, and disable
761 		 * subsequent interrupts.
762 		 *
763 		 * Workaround: The IOMMU driver should read back the
764 		 * status register and check if the interrupt bits are cleared.
765 		 * If not, driver will need to go through the interrupt handler
766 		 * again and re-clear the bits
767 		 */
768 		status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
769 	}
770 	return IRQ_HANDLED;
771 }
772 
773 irqreturn_t amd_iommu_int_handler(int irq, void *data)
774 {
775 	return IRQ_WAKE_THREAD;
776 }
777 
778 /****************************************************************************
779  *
780  * IOMMU command queuing functions
781  *
782  ****************************************************************************/
783 
784 static int wait_on_sem(volatile u64 *sem)
785 {
786 	int i = 0;
787 
788 	while (*sem == 0 && i < LOOP_TIMEOUT) {
789 		udelay(1);
790 		i += 1;
791 	}
792 
793 	if (i == LOOP_TIMEOUT) {
794 		pr_alert("Completion-Wait loop timed out\n");
795 		return -EIO;
796 	}
797 
798 	return 0;
799 }
800 
801 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
802 			       struct iommu_cmd *cmd)
803 {
804 	u8 *target;
805 	u32 tail;
806 
807 	/* Copy command to buffer */
808 	tail = iommu->cmd_buf_tail;
809 	target = iommu->cmd_buf + tail;
810 	memcpy(target, cmd, sizeof(*cmd));
811 
812 	tail = (tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
813 	iommu->cmd_buf_tail = tail;
814 
815 	/* Tell the IOMMU about it */
816 	writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
817 }
818 
819 static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
820 {
821 	u64 paddr = iommu_virt_to_phys((void *)address);
822 
823 	WARN_ON(address & 0x7ULL);
824 
825 	memset(cmd, 0, sizeof(*cmd));
826 	cmd->data[0] = lower_32_bits(paddr) | CMD_COMPL_WAIT_STORE_MASK;
827 	cmd->data[1] = upper_32_bits(paddr);
828 	cmd->data[2] = 1;
829 	CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
830 }
831 
832 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
833 {
834 	memset(cmd, 0, sizeof(*cmd));
835 	cmd->data[0] = devid;
836 	CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
837 }
838 
839 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
840 				  size_t size, u16 domid, int pde)
841 {
842 	u64 pages;
843 	bool s;
844 
845 	pages = iommu_num_pages(address, size, PAGE_SIZE);
846 	s     = false;
847 
848 	if (pages > 1) {
849 		/*
850 		 * If we have to flush more than one page, flush all
851 		 * TLB entries for this domain
852 		 */
853 		address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
854 		s = true;
855 	}
856 
857 	address &= PAGE_MASK;
858 
859 	memset(cmd, 0, sizeof(*cmd));
860 	cmd->data[1] |= domid;
861 	cmd->data[2]  = lower_32_bits(address);
862 	cmd->data[3]  = upper_32_bits(address);
863 	CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
864 	if (s) /* size bit - we flush more than one 4kb page */
865 		cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
866 	if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
867 		cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
868 }
869 
870 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
871 				  u64 address, size_t size)
872 {
873 	u64 pages;
874 	bool s;
875 
876 	pages = iommu_num_pages(address, size, PAGE_SIZE);
877 	s     = false;
878 
879 	if (pages > 1) {
880 		/*
881 		 * If we have to flush more than one page, flush all
882 		 * TLB entries for this domain
883 		 */
884 		address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
885 		s = true;
886 	}
887 
888 	address &= PAGE_MASK;
889 
890 	memset(cmd, 0, sizeof(*cmd));
891 	cmd->data[0]  = devid;
892 	cmd->data[0] |= (qdep & 0xff) << 24;
893 	cmd->data[1]  = devid;
894 	cmd->data[2]  = lower_32_bits(address);
895 	cmd->data[3]  = upper_32_bits(address);
896 	CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
897 	if (s)
898 		cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
899 }
900 
901 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
902 				  u64 address, bool size)
903 {
904 	memset(cmd, 0, sizeof(*cmd));
905 
906 	address &= ~(0xfffULL);
907 
908 	cmd->data[0]  = pasid;
909 	cmd->data[1]  = domid;
910 	cmd->data[2]  = lower_32_bits(address);
911 	cmd->data[3]  = upper_32_bits(address);
912 	cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
913 	cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
914 	if (size)
915 		cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
916 	CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
917 }
918 
919 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
920 				  int qdep, u64 address, bool size)
921 {
922 	memset(cmd, 0, sizeof(*cmd));
923 
924 	address &= ~(0xfffULL);
925 
926 	cmd->data[0]  = devid;
927 	cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
928 	cmd->data[0] |= (qdep  & 0xff) << 24;
929 	cmd->data[1]  = devid;
930 	cmd->data[1] |= (pasid & 0xff) << 16;
931 	cmd->data[2]  = lower_32_bits(address);
932 	cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
933 	cmd->data[3]  = upper_32_bits(address);
934 	if (size)
935 		cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
936 	CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
937 }
938 
939 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
940 			       int status, int tag, bool gn)
941 {
942 	memset(cmd, 0, sizeof(*cmd));
943 
944 	cmd->data[0]  = devid;
945 	if (gn) {
946 		cmd->data[1]  = pasid;
947 		cmd->data[2]  = CMD_INV_IOMMU_PAGES_GN_MASK;
948 	}
949 	cmd->data[3]  = tag & 0x1ff;
950 	cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
951 
952 	CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
953 }
954 
955 static void build_inv_all(struct iommu_cmd *cmd)
956 {
957 	memset(cmd, 0, sizeof(*cmd));
958 	CMD_SET_TYPE(cmd, CMD_INV_ALL);
959 }
960 
961 static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
962 {
963 	memset(cmd, 0, sizeof(*cmd));
964 	cmd->data[0] = devid;
965 	CMD_SET_TYPE(cmd, CMD_INV_IRT);
966 }
967 
968 /*
969  * Writes the command to the IOMMUs command buffer and informs the
970  * hardware about the new command.
971  */
972 static int __iommu_queue_command_sync(struct amd_iommu *iommu,
973 				      struct iommu_cmd *cmd,
974 				      bool sync)
975 {
976 	unsigned int count = 0;
977 	u32 left, next_tail;
978 
979 	next_tail = (iommu->cmd_buf_tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
980 again:
981 	left      = (iommu->cmd_buf_head - next_tail) % CMD_BUFFER_SIZE;
982 
983 	if (left <= 0x20) {
984 		/* Skip udelay() the first time around */
985 		if (count++) {
986 			if (count == LOOP_TIMEOUT) {
987 				pr_err("Command buffer timeout\n");
988 				return -EIO;
989 			}
990 
991 			udelay(1);
992 		}
993 
994 		/* Update head and recheck remaining space */
995 		iommu->cmd_buf_head = readl(iommu->mmio_base +
996 					    MMIO_CMD_HEAD_OFFSET);
997 
998 		goto again;
999 	}
1000 
1001 	copy_cmd_to_buffer(iommu, cmd);
1002 
1003 	/* Do we need to make sure all commands are processed? */
1004 	iommu->need_sync = sync;
1005 
1006 	return 0;
1007 }
1008 
1009 static int iommu_queue_command_sync(struct amd_iommu *iommu,
1010 				    struct iommu_cmd *cmd,
1011 				    bool sync)
1012 {
1013 	unsigned long flags;
1014 	int ret;
1015 
1016 	raw_spin_lock_irqsave(&iommu->lock, flags);
1017 	ret = __iommu_queue_command_sync(iommu, cmd, sync);
1018 	raw_spin_unlock_irqrestore(&iommu->lock, flags);
1019 
1020 	return ret;
1021 }
1022 
1023 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
1024 {
1025 	return iommu_queue_command_sync(iommu, cmd, true);
1026 }
1027 
1028 /*
1029  * This function queues a completion wait command into the command
1030  * buffer of an IOMMU
1031  */
1032 static int iommu_completion_wait(struct amd_iommu *iommu)
1033 {
1034 	struct iommu_cmd cmd;
1035 	unsigned long flags;
1036 	int ret;
1037 
1038 	if (!iommu->need_sync)
1039 		return 0;
1040 
1041 
1042 	build_completion_wait(&cmd, (u64)&iommu->cmd_sem);
1043 
1044 	raw_spin_lock_irqsave(&iommu->lock, flags);
1045 
1046 	iommu->cmd_sem = 0;
1047 
1048 	ret = __iommu_queue_command_sync(iommu, &cmd, false);
1049 	if (ret)
1050 		goto out_unlock;
1051 
1052 	ret = wait_on_sem(&iommu->cmd_sem);
1053 
1054 out_unlock:
1055 	raw_spin_unlock_irqrestore(&iommu->lock, flags);
1056 
1057 	return ret;
1058 }
1059 
1060 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
1061 {
1062 	struct iommu_cmd cmd;
1063 
1064 	build_inv_dte(&cmd, devid);
1065 
1066 	return iommu_queue_command(iommu, &cmd);
1067 }
1068 
1069 static void amd_iommu_flush_dte_all(struct amd_iommu *iommu)
1070 {
1071 	u32 devid;
1072 
1073 	for (devid = 0; devid <= 0xffff; ++devid)
1074 		iommu_flush_dte(iommu, devid);
1075 
1076 	iommu_completion_wait(iommu);
1077 }
1078 
1079 /*
1080  * This function uses heavy locking and may disable irqs for some time. But
1081  * this is no issue because it is only called during resume.
1082  */
1083 static void amd_iommu_flush_tlb_all(struct amd_iommu *iommu)
1084 {
1085 	u32 dom_id;
1086 
1087 	for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1088 		struct iommu_cmd cmd;
1089 		build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1090 				      dom_id, 1);
1091 		iommu_queue_command(iommu, &cmd);
1092 	}
1093 
1094 	iommu_completion_wait(iommu);
1095 }
1096 
1097 static void amd_iommu_flush_tlb_domid(struct amd_iommu *iommu, u32 dom_id)
1098 {
1099 	struct iommu_cmd cmd;
1100 
1101 	build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1102 			      dom_id, 1);
1103 	iommu_queue_command(iommu, &cmd);
1104 
1105 	iommu_completion_wait(iommu);
1106 }
1107 
1108 static void amd_iommu_flush_all(struct amd_iommu *iommu)
1109 {
1110 	struct iommu_cmd cmd;
1111 
1112 	build_inv_all(&cmd);
1113 
1114 	iommu_queue_command(iommu, &cmd);
1115 	iommu_completion_wait(iommu);
1116 }
1117 
1118 static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1119 {
1120 	struct iommu_cmd cmd;
1121 
1122 	build_inv_irt(&cmd, devid);
1123 
1124 	iommu_queue_command(iommu, &cmd);
1125 }
1126 
1127 static void amd_iommu_flush_irt_all(struct amd_iommu *iommu)
1128 {
1129 	u32 devid;
1130 
1131 	for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1132 		iommu_flush_irt(iommu, devid);
1133 
1134 	iommu_completion_wait(iommu);
1135 }
1136 
1137 void iommu_flush_all_caches(struct amd_iommu *iommu)
1138 {
1139 	if (iommu_feature(iommu, FEATURE_IA)) {
1140 		amd_iommu_flush_all(iommu);
1141 	} else {
1142 		amd_iommu_flush_dte_all(iommu);
1143 		amd_iommu_flush_irt_all(iommu);
1144 		amd_iommu_flush_tlb_all(iommu);
1145 	}
1146 }
1147 
1148 /*
1149  * Command send function for flushing on-device TLB
1150  */
1151 static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1152 			      u64 address, size_t size)
1153 {
1154 	struct amd_iommu *iommu;
1155 	struct iommu_cmd cmd;
1156 	int qdep;
1157 
1158 	qdep     = dev_data->ats.qdep;
1159 	iommu    = amd_iommu_rlookup_table[dev_data->devid];
1160 
1161 	build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
1162 
1163 	return iommu_queue_command(iommu, &cmd);
1164 }
1165 
1166 static int device_flush_dte_alias(struct pci_dev *pdev, u16 alias, void *data)
1167 {
1168 	struct amd_iommu *iommu = data;
1169 
1170 	return iommu_flush_dte(iommu, alias);
1171 }
1172 
1173 /*
1174  * Command send function for invalidating a device table entry
1175  */
1176 static int device_flush_dte(struct iommu_dev_data *dev_data)
1177 {
1178 	struct amd_iommu *iommu;
1179 	u16 alias;
1180 	int ret;
1181 
1182 	iommu = amd_iommu_rlookup_table[dev_data->devid];
1183 
1184 	if (dev_data->pdev)
1185 		ret = pci_for_each_dma_alias(dev_data->pdev,
1186 					     device_flush_dte_alias, iommu);
1187 	else
1188 		ret = iommu_flush_dte(iommu, dev_data->devid);
1189 	if (ret)
1190 		return ret;
1191 
1192 	alias = amd_iommu_alias_table[dev_data->devid];
1193 	if (alias != dev_data->devid) {
1194 		ret = iommu_flush_dte(iommu, alias);
1195 		if (ret)
1196 			return ret;
1197 	}
1198 
1199 	if (dev_data->ats.enabled)
1200 		ret = device_flush_iotlb(dev_data, 0, ~0UL);
1201 
1202 	return ret;
1203 }
1204 
1205 /*
1206  * TLB invalidation function which is called from the mapping functions.
1207  * It invalidates a single PTE if the range to flush is within a single
1208  * page. Otherwise it flushes the whole TLB of the IOMMU.
1209  */
1210 static void __domain_flush_pages(struct protection_domain *domain,
1211 				 u64 address, size_t size, int pde)
1212 {
1213 	struct iommu_dev_data *dev_data;
1214 	struct iommu_cmd cmd;
1215 	int ret = 0, i;
1216 
1217 	build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
1218 
1219 	for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1220 		if (!domain->dev_iommu[i])
1221 			continue;
1222 
1223 		/*
1224 		 * Devices of this domain are behind this IOMMU
1225 		 * We need a TLB flush
1226 		 */
1227 		ret |= iommu_queue_command(amd_iommus[i], &cmd);
1228 	}
1229 
1230 	list_for_each_entry(dev_data, &domain->dev_list, list) {
1231 
1232 		if (!dev_data->ats.enabled)
1233 			continue;
1234 
1235 		ret |= device_flush_iotlb(dev_data, address, size);
1236 	}
1237 
1238 	WARN_ON(ret);
1239 }
1240 
1241 static void domain_flush_pages(struct protection_domain *domain,
1242 			       u64 address, size_t size)
1243 {
1244 	__domain_flush_pages(domain, address, size, 0);
1245 }
1246 
1247 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1248 static void domain_flush_tlb_pde(struct protection_domain *domain)
1249 {
1250 	__domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1251 }
1252 
1253 static void domain_flush_complete(struct protection_domain *domain)
1254 {
1255 	int i;
1256 
1257 	for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1258 		if (domain && !domain->dev_iommu[i])
1259 			continue;
1260 
1261 		/*
1262 		 * Devices of this domain are behind this IOMMU
1263 		 * We need to wait for completion of all commands.
1264 		 */
1265 		iommu_completion_wait(amd_iommus[i]);
1266 	}
1267 }
1268 
1269 /* Flush the not present cache if it exists */
1270 static void domain_flush_np_cache(struct protection_domain *domain,
1271 		dma_addr_t iova, size_t size)
1272 {
1273 	if (unlikely(amd_iommu_np_cache)) {
1274 		unsigned long flags;
1275 
1276 		spin_lock_irqsave(&domain->lock, flags);
1277 		domain_flush_pages(domain, iova, size);
1278 		domain_flush_complete(domain);
1279 		spin_unlock_irqrestore(&domain->lock, flags);
1280 	}
1281 }
1282 
1283 
1284 /*
1285  * This function flushes the DTEs for all devices in domain
1286  */
1287 static void domain_flush_devices(struct protection_domain *domain)
1288 {
1289 	struct iommu_dev_data *dev_data;
1290 
1291 	list_for_each_entry(dev_data, &domain->dev_list, list)
1292 		device_flush_dte(dev_data);
1293 }
1294 
1295 /****************************************************************************
1296  *
1297  * The functions below are used the create the page table mappings for
1298  * unity mapped regions.
1299  *
1300  ****************************************************************************/
1301 
1302 static void free_page_list(struct page *freelist)
1303 {
1304 	while (freelist != NULL) {
1305 		unsigned long p = (unsigned long)page_address(freelist);
1306 		freelist = freelist->freelist;
1307 		free_page(p);
1308 	}
1309 }
1310 
1311 static struct page *free_pt_page(unsigned long pt, struct page *freelist)
1312 {
1313 	struct page *p = virt_to_page((void *)pt);
1314 
1315 	p->freelist = freelist;
1316 
1317 	return p;
1318 }
1319 
1320 #define DEFINE_FREE_PT_FN(LVL, FN)						\
1321 static struct page *free_pt_##LVL (unsigned long __pt, struct page *freelist)	\
1322 {										\
1323 	unsigned long p;							\
1324 	u64 *pt;								\
1325 	int i;									\
1326 										\
1327 	pt = (u64 *)__pt;							\
1328 										\
1329 	for (i = 0; i < 512; ++i) {						\
1330 		/* PTE present? */						\
1331 		if (!IOMMU_PTE_PRESENT(pt[i]))					\
1332 			continue;						\
1333 										\
1334 		/* Large PTE? */						\
1335 		if (PM_PTE_LEVEL(pt[i]) == 0 ||					\
1336 		    PM_PTE_LEVEL(pt[i]) == 7)					\
1337 			continue;						\
1338 										\
1339 		p = (unsigned long)IOMMU_PTE_PAGE(pt[i]);			\
1340 		freelist = FN(p, freelist);					\
1341 	}									\
1342 										\
1343 	return free_pt_page((unsigned long)pt, freelist);			\
1344 }
1345 
1346 DEFINE_FREE_PT_FN(l2, free_pt_page)
1347 DEFINE_FREE_PT_FN(l3, free_pt_l2)
1348 DEFINE_FREE_PT_FN(l4, free_pt_l3)
1349 DEFINE_FREE_PT_FN(l5, free_pt_l4)
1350 DEFINE_FREE_PT_FN(l6, free_pt_l5)
1351 
1352 static struct page *free_sub_pt(unsigned long root, int mode,
1353 				struct page *freelist)
1354 {
1355 	switch (mode) {
1356 	case PAGE_MODE_NONE:
1357 	case PAGE_MODE_7_LEVEL:
1358 		break;
1359 	case PAGE_MODE_1_LEVEL:
1360 		freelist = free_pt_page(root, freelist);
1361 		break;
1362 	case PAGE_MODE_2_LEVEL:
1363 		freelist = free_pt_l2(root, freelist);
1364 		break;
1365 	case PAGE_MODE_3_LEVEL:
1366 		freelist = free_pt_l3(root, freelist);
1367 		break;
1368 	case PAGE_MODE_4_LEVEL:
1369 		freelist = free_pt_l4(root, freelist);
1370 		break;
1371 	case PAGE_MODE_5_LEVEL:
1372 		freelist = free_pt_l5(root, freelist);
1373 		break;
1374 	case PAGE_MODE_6_LEVEL:
1375 		freelist = free_pt_l6(root, freelist);
1376 		break;
1377 	default:
1378 		BUG();
1379 	}
1380 
1381 	return freelist;
1382 }
1383 
1384 static void free_pagetable(struct domain_pgtable *pgtable)
1385 {
1386 	struct page *freelist = NULL;
1387 	unsigned long root;
1388 
1389 	if (pgtable->mode == PAGE_MODE_NONE)
1390 		return;
1391 
1392 	BUG_ON(pgtable->mode < PAGE_MODE_NONE ||
1393 	       pgtable->mode > PAGE_MODE_6_LEVEL);
1394 
1395 	root = (unsigned long)pgtable->root;
1396 	freelist = free_sub_pt(root, pgtable->mode, freelist);
1397 
1398 	free_page_list(freelist);
1399 }
1400 
1401 /*
1402  * This function is used to add another level to an IO page table. Adding
1403  * another level increases the size of the address space by 9 bits to a size up
1404  * to 64 bits.
1405  */
1406 static bool increase_address_space(struct protection_domain *domain,
1407 				   unsigned long address,
1408 				   gfp_t gfp)
1409 {
1410 	struct domain_pgtable pgtable;
1411 	unsigned long flags;
1412 	bool ret = true;
1413 	u64 *pte, root;
1414 
1415 	spin_lock_irqsave(&domain->lock, flags);
1416 
1417 	amd_iommu_domain_get_pgtable(domain, &pgtable);
1418 
1419 	if (address <= PM_LEVEL_SIZE(pgtable.mode))
1420 		goto out;
1421 
1422 	ret = false;
1423 	if (WARN_ON_ONCE(pgtable.mode == PAGE_MODE_6_LEVEL))
1424 		goto out;
1425 
1426 	pte = (void *)get_zeroed_page(gfp);
1427 	if (!pte)
1428 		goto out;
1429 
1430 	*pte = PM_LEVEL_PDE(pgtable.mode, iommu_virt_to_phys(pgtable.root));
1431 
1432 	pgtable.root  = pte;
1433 	pgtable.mode += 1;
1434 	update_and_flush_device_table(domain, &pgtable);
1435 	domain_flush_complete(domain);
1436 
1437 	/*
1438 	 * Device Table needs to be updated and flushed before the new root can
1439 	 * be published.
1440 	 */
1441 	root = amd_iommu_domain_encode_pgtable(pte, pgtable.mode);
1442 	atomic64_set(&domain->pt_root, root);
1443 
1444 	ret = true;
1445 
1446 out:
1447 	spin_unlock_irqrestore(&domain->lock, flags);
1448 
1449 	return ret;
1450 }
1451 
1452 static u64 *alloc_pte(struct protection_domain *domain,
1453 		      unsigned long address,
1454 		      unsigned long page_size,
1455 		      u64 **pte_page,
1456 		      gfp_t gfp,
1457 		      bool *updated)
1458 {
1459 	struct domain_pgtable pgtable;
1460 	int level, end_lvl;
1461 	u64 *pte, *page;
1462 
1463 	BUG_ON(!is_power_of_2(page_size));
1464 
1465 	amd_iommu_domain_get_pgtable(domain, &pgtable);
1466 
1467 	while (address > PM_LEVEL_SIZE(pgtable.mode)) {
1468 		/*
1469 		 * Return an error if there is no memory to update the
1470 		 * page-table.
1471 		 */
1472 		if (!increase_address_space(domain, address, gfp))
1473 			return NULL;
1474 
1475 		/* Read new values to check if update was successful */
1476 		amd_iommu_domain_get_pgtable(domain, &pgtable);
1477 	}
1478 
1479 
1480 	level   = pgtable.mode - 1;
1481 	pte     = &pgtable.root[PM_LEVEL_INDEX(level, address)];
1482 	address = PAGE_SIZE_ALIGN(address, page_size);
1483 	end_lvl = PAGE_SIZE_LEVEL(page_size);
1484 
1485 	while (level > end_lvl) {
1486 		u64 __pte, __npte;
1487 		int pte_level;
1488 
1489 		__pte     = *pte;
1490 		pte_level = PM_PTE_LEVEL(__pte);
1491 
1492 		/*
1493 		 * If we replace a series of large PTEs, we need
1494 		 * to tear down all of them.
1495 		 */
1496 		if (IOMMU_PTE_PRESENT(__pte) &&
1497 		    pte_level == PAGE_MODE_7_LEVEL) {
1498 			unsigned long count, i;
1499 			u64 *lpte;
1500 
1501 			lpte = first_pte_l7(pte, NULL, &count);
1502 
1503 			/*
1504 			 * Unmap the replicated PTEs that still match the
1505 			 * original large mapping
1506 			 */
1507 			for (i = 0; i < count; ++i)
1508 				cmpxchg64(&lpte[i], __pte, 0ULL);
1509 
1510 			*updated = true;
1511 			continue;
1512 		}
1513 
1514 		if (!IOMMU_PTE_PRESENT(__pte) ||
1515 		    pte_level == PAGE_MODE_NONE) {
1516 			page = (u64 *)get_zeroed_page(gfp);
1517 
1518 			if (!page)
1519 				return NULL;
1520 
1521 			__npte = PM_LEVEL_PDE(level, iommu_virt_to_phys(page));
1522 
1523 			/* pte could have been changed somewhere. */
1524 			if (cmpxchg64(pte, __pte, __npte) != __pte)
1525 				free_page((unsigned long)page);
1526 			else if (IOMMU_PTE_PRESENT(__pte))
1527 				*updated = true;
1528 
1529 			continue;
1530 		}
1531 
1532 		/* No level skipping support yet */
1533 		if (pte_level != level)
1534 			return NULL;
1535 
1536 		level -= 1;
1537 
1538 		pte = IOMMU_PTE_PAGE(__pte);
1539 
1540 		if (pte_page && level == end_lvl)
1541 			*pte_page = pte;
1542 
1543 		pte = &pte[PM_LEVEL_INDEX(level, address)];
1544 	}
1545 
1546 	return pte;
1547 }
1548 
1549 /*
1550  * This function checks if there is a PTE for a given dma address. If
1551  * there is one, it returns the pointer to it.
1552  */
1553 static u64 *fetch_pte(struct protection_domain *domain,
1554 		      unsigned long address,
1555 		      unsigned long *page_size)
1556 {
1557 	struct domain_pgtable pgtable;
1558 	int level;
1559 	u64 *pte;
1560 
1561 	*page_size = 0;
1562 
1563 	amd_iommu_domain_get_pgtable(domain, &pgtable);
1564 
1565 	if (address > PM_LEVEL_SIZE(pgtable.mode))
1566 		return NULL;
1567 
1568 	level	   =  pgtable.mode - 1;
1569 	pte	   = &pgtable.root[PM_LEVEL_INDEX(level, address)];
1570 	*page_size =  PTE_LEVEL_PAGE_SIZE(level);
1571 
1572 	while (level > 0) {
1573 
1574 		/* Not Present */
1575 		if (!IOMMU_PTE_PRESENT(*pte))
1576 			return NULL;
1577 
1578 		/* Large PTE */
1579 		if (PM_PTE_LEVEL(*pte) == 7 ||
1580 		    PM_PTE_LEVEL(*pte) == 0)
1581 			break;
1582 
1583 		/* No level skipping support yet */
1584 		if (PM_PTE_LEVEL(*pte) != level)
1585 			return NULL;
1586 
1587 		level -= 1;
1588 
1589 		/* Walk to the next level */
1590 		pte	   = IOMMU_PTE_PAGE(*pte);
1591 		pte	   = &pte[PM_LEVEL_INDEX(level, address)];
1592 		*page_size = PTE_LEVEL_PAGE_SIZE(level);
1593 	}
1594 
1595 	/*
1596 	 * If we have a series of large PTEs, make
1597 	 * sure to return a pointer to the first one.
1598 	 */
1599 	if (PM_PTE_LEVEL(*pte) == PAGE_MODE_7_LEVEL)
1600 		pte = first_pte_l7(pte, page_size, NULL);
1601 
1602 	return pte;
1603 }
1604 
1605 static struct page *free_clear_pte(u64 *pte, u64 pteval, struct page *freelist)
1606 {
1607 	unsigned long pt;
1608 	int mode;
1609 
1610 	while (cmpxchg64(pte, pteval, 0) != pteval) {
1611 		pr_warn("AMD-Vi: IOMMU pte changed since we read it\n");
1612 		pteval = *pte;
1613 	}
1614 
1615 	if (!IOMMU_PTE_PRESENT(pteval))
1616 		return freelist;
1617 
1618 	pt   = (unsigned long)IOMMU_PTE_PAGE(pteval);
1619 	mode = IOMMU_PTE_MODE(pteval);
1620 
1621 	return free_sub_pt(pt, mode, freelist);
1622 }
1623 
1624 /*
1625  * Generic mapping functions. It maps a physical address into a DMA
1626  * address space. It allocates the page table pages if necessary.
1627  * In the future it can be extended to a generic mapping function
1628  * supporting all features of AMD IOMMU page tables like level skipping
1629  * and full 64 bit address spaces.
1630  */
1631 static int iommu_map_page(struct protection_domain *dom,
1632 			  unsigned long bus_addr,
1633 			  unsigned long phys_addr,
1634 			  unsigned long page_size,
1635 			  int prot,
1636 			  gfp_t gfp)
1637 {
1638 	struct page *freelist = NULL;
1639 	bool updated = false;
1640 	u64 __pte, *pte;
1641 	int ret, i, count;
1642 
1643 	BUG_ON(!IS_ALIGNED(bus_addr, page_size));
1644 	BUG_ON(!IS_ALIGNED(phys_addr, page_size));
1645 
1646 	ret = -EINVAL;
1647 	if (!(prot & IOMMU_PROT_MASK))
1648 		goto out;
1649 
1650 	count = PAGE_SIZE_PTE_COUNT(page_size);
1651 	pte   = alloc_pte(dom, bus_addr, page_size, NULL, gfp, &updated);
1652 
1653 	ret = -ENOMEM;
1654 	if (!pte)
1655 		goto out;
1656 
1657 	for (i = 0; i < count; ++i)
1658 		freelist = free_clear_pte(&pte[i], pte[i], freelist);
1659 
1660 	if (freelist != NULL)
1661 		updated = true;
1662 
1663 	if (count > 1) {
1664 		__pte = PAGE_SIZE_PTE(__sme_set(phys_addr), page_size);
1665 		__pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_PR | IOMMU_PTE_FC;
1666 	} else
1667 		__pte = __sme_set(phys_addr) | IOMMU_PTE_PR | IOMMU_PTE_FC;
1668 
1669 	if (prot & IOMMU_PROT_IR)
1670 		__pte |= IOMMU_PTE_IR;
1671 	if (prot & IOMMU_PROT_IW)
1672 		__pte |= IOMMU_PTE_IW;
1673 
1674 	for (i = 0; i < count; ++i)
1675 		pte[i] = __pte;
1676 
1677 	ret = 0;
1678 
1679 out:
1680 	if (updated) {
1681 		unsigned long flags;
1682 
1683 		spin_lock_irqsave(&dom->lock, flags);
1684 		/*
1685 		 * Flush domain TLB(s) and wait for completion. Any Device-Table
1686 		 * Updates and flushing already happened in
1687 		 * increase_address_space().
1688 		 */
1689 		domain_flush_tlb_pde(dom);
1690 		domain_flush_complete(dom);
1691 		spin_unlock_irqrestore(&dom->lock, flags);
1692 	}
1693 
1694 	/* Everything flushed out, free pages now */
1695 	free_page_list(freelist);
1696 
1697 	return ret;
1698 }
1699 
1700 static unsigned long iommu_unmap_page(struct protection_domain *dom,
1701 				      unsigned long bus_addr,
1702 				      unsigned long page_size)
1703 {
1704 	unsigned long long unmapped;
1705 	unsigned long unmap_size;
1706 	u64 *pte;
1707 
1708 	BUG_ON(!is_power_of_2(page_size));
1709 
1710 	unmapped = 0;
1711 
1712 	while (unmapped < page_size) {
1713 
1714 		pte = fetch_pte(dom, bus_addr, &unmap_size);
1715 
1716 		if (pte) {
1717 			int i, count;
1718 
1719 			count = PAGE_SIZE_PTE_COUNT(unmap_size);
1720 			for (i = 0; i < count; i++)
1721 				pte[i] = 0ULL;
1722 		}
1723 
1724 		bus_addr  = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1725 		unmapped += unmap_size;
1726 	}
1727 
1728 	BUG_ON(unmapped && !is_power_of_2(unmapped));
1729 
1730 	return unmapped;
1731 }
1732 
1733 /****************************************************************************
1734  *
1735  * The next functions belong to the domain allocation. A domain is
1736  * allocated for every IOMMU as the default domain. If device isolation
1737  * is enabled, every device get its own domain. The most important thing
1738  * about domains is the page table mapping the DMA address space they
1739  * contain.
1740  *
1741  ****************************************************************************/
1742 
1743 static u16 domain_id_alloc(void)
1744 {
1745 	int id;
1746 
1747 	spin_lock(&pd_bitmap_lock);
1748 	id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1749 	BUG_ON(id == 0);
1750 	if (id > 0 && id < MAX_DOMAIN_ID)
1751 		__set_bit(id, amd_iommu_pd_alloc_bitmap);
1752 	else
1753 		id = 0;
1754 	spin_unlock(&pd_bitmap_lock);
1755 
1756 	return id;
1757 }
1758 
1759 static void domain_id_free(int id)
1760 {
1761 	spin_lock(&pd_bitmap_lock);
1762 	if (id > 0 && id < MAX_DOMAIN_ID)
1763 		__clear_bit(id, amd_iommu_pd_alloc_bitmap);
1764 	spin_unlock(&pd_bitmap_lock);
1765 }
1766 
1767 static void free_gcr3_tbl_level1(u64 *tbl)
1768 {
1769 	u64 *ptr;
1770 	int i;
1771 
1772 	for (i = 0; i < 512; ++i) {
1773 		if (!(tbl[i] & GCR3_VALID))
1774 			continue;
1775 
1776 		ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1777 
1778 		free_page((unsigned long)ptr);
1779 	}
1780 }
1781 
1782 static void free_gcr3_tbl_level2(u64 *tbl)
1783 {
1784 	u64 *ptr;
1785 	int i;
1786 
1787 	for (i = 0; i < 512; ++i) {
1788 		if (!(tbl[i] & GCR3_VALID))
1789 			continue;
1790 
1791 		ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1792 
1793 		free_gcr3_tbl_level1(ptr);
1794 	}
1795 }
1796 
1797 static void free_gcr3_table(struct protection_domain *domain)
1798 {
1799 	if (domain->glx == 2)
1800 		free_gcr3_tbl_level2(domain->gcr3_tbl);
1801 	else if (domain->glx == 1)
1802 		free_gcr3_tbl_level1(domain->gcr3_tbl);
1803 	else
1804 		BUG_ON(domain->glx != 0);
1805 
1806 	free_page((unsigned long)domain->gcr3_tbl);
1807 }
1808 
1809 static void set_dte_entry(u16 devid, struct protection_domain *domain,
1810 			  struct domain_pgtable *pgtable,
1811 			  bool ats, bool ppr)
1812 {
1813 	u64 pte_root = 0;
1814 	u64 flags = 0;
1815 	u32 old_domid;
1816 
1817 	if (pgtable->mode != PAGE_MODE_NONE)
1818 		pte_root = iommu_virt_to_phys(pgtable->root);
1819 
1820 	pte_root |= (pgtable->mode & DEV_ENTRY_MODE_MASK)
1821 		    << DEV_ENTRY_MODE_SHIFT;
1822 	pte_root |= DTE_FLAG_IR | DTE_FLAG_IW | DTE_FLAG_V | DTE_FLAG_TV;
1823 
1824 	flags = amd_iommu_dev_table[devid].data[1];
1825 
1826 	if (ats)
1827 		flags |= DTE_FLAG_IOTLB;
1828 
1829 	if (ppr) {
1830 		struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1831 
1832 		if (iommu_feature(iommu, FEATURE_EPHSUP))
1833 			pte_root |= 1ULL << DEV_ENTRY_PPR;
1834 	}
1835 
1836 	if (domain->flags & PD_IOMMUV2_MASK) {
1837 		u64 gcr3 = iommu_virt_to_phys(domain->gcr3_tbl);
1838 		u64 glx  = domain->glx;
1839 		u64 tmp;
1840 
1841 		pte_root |= DTE_FLAG_GV;
1842 		pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
1843 
1844 		/* First mask out possible old values for GCR3 table */
1845 		tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
1846 		flags    &= ~tmp;
1847 
1848 		tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
1849 		flags    &= ~tmp;
1850 
1851 		/* Encode GCR3 table into DTE */
1852 		tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
1853 		pte_root |= tmp;
1854 
1855 		tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
1856 		flags    |= tmp;
1857 
1858 		tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
1859 		flags    |= tmp;
1860 	}
1861 
1862 	flags &= ~DEV_DOMID_MASK;
1863 	flags |= domain->id;
1864 
1865 	old_domid = amd_iommu_dev_table[devid].data[1] & DEV_DOMID_MASK;
1866 	amd_iommu_dev_table[devid].data[1]  = flags;
1867 	amd_iommu_dev_table[devid].data[0]  = pte_root;
1868 
1869 	/*
1870 	 * A kdump kernel might be replacing a domain ID that was copied from
1871 	 * the previous kernel--if so, it needs to flush the translation cache
1872 	 * entries for the old domain ID that is being overwritten
1873 	 */
1874 	if (old_domid) {
1875 		struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1876 
1877 		amd_iommu_flush_tlb_domid(iommu, old_domid);
1878 	}
1879 }
1880 
1881 static void clear_dte_entry(u16 devid)
1882 {
1883 	/* remove entry from the device table seen by the hardware */
1884 	amd_iommu_dev_table[devid].data[0]  = DTE_FLAG_V | DTE_FLAG_TV;
1885 	amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK;
1886 
1887 	amd_iommu_apply_erratum_63(devid);
1888 }
1889 
1890 static void do_attach(struct iommu_dev_data *dev_data,
1891 		      struct protection_domain *domain)
1892 {
1893 	struct domain_pgtable pgtable;
1894 	struct amd_iommu *iommu;
1895 	bool ats;
1896 
1897 	iommu = amd_iommu_rlookup_table[dev_data->devid];
1898 	ats   = dev_data->ats.enabled;
1899 
1900 	/* Update data structures */
1901 	dev_data->domain = domain;
1902 	list_add(&dev_data->list, &domain->dev_list);
1903 
1904 	/* Do reference counting */
1905 	domain->dev_iommu[iommu->index] += 1;
1906 	domain->dev_cnt                 += 1;
1907 
1908 	/* Update device table */
1909 	amd_iommu_domain_get_pgtable(domain, &pgtable);
1910 	set_dte_entry(dev_data->devid, domain, &pgtable,
1911 		      ats, dev_data->iommu_v2);
1912 	clone_aliases(dev_data->pdev);
1913 
1914 	device_flush_dte(dev_data);
1915 }
1916 
1917 static void do_detach(struct iommu_dev_data *dev_data)
1918 {
1919 	struct protection_domain *domain = dev_data->domain;
1920 	struct amd_iommu *iommu;
1921 
1922 	iommu = amd_iommu_rlookup_table[dev_data->devid];
1923 
1924 	/* Update data structures */
1925 	dev_data->domain = NULL;
1926 	list_del(&dev_data->list);
1927 	clear_dte_entry(dev_data->devid);
1928 	clone_aliases(dev_data->pdev);
1929 
1930 	/* Flush the DTE entry */
1931 	device_flush_dte(dev_data);
1932 
1933 	/* Flush IOTLB */
1934 	domain_flush_tlb_pde(domain);
1935 
1936 	/* Wait for the flushes to finish */
1937 	domain_flush_complete(domain);
1938 
1939 	/* decrease reference counters - needs to happen after the flushes */
1940 	domain->dev_iommu[iommu->index] -= 1;
1941 	domain->dev_cnt                 -= 1;
1942 }
1943 
1944 static void pdev_iommuv2_disable(struct pci_dev *pdev)
1945 {
1946 	pci_disable_ats(pdev);
1947 	pci_disable_pri(pdev);
1948 	pci_disable_pasid(pdev);
1949 }
1950 
1951 /* FIXME: Change generic reset-function to do the same */
1952 static int pri_reset_while_enabled(struct pci_dev *pdev)
1953 {
1954 	u16 control;
1955 	int pos;
1956 
1957 	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
1958 	if (!pos)
1959 		return -EINVAL;
1960 
1961 	pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
1962 	control |= PCI_PRI_CTRL_RESET;
1963 	pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
1964 
1965 	return 0;
1966 }
1967 
1968 static int pdev_iommuv2_enable(struct pci_dev *pdev)
1969 {
1970 	bool reset_enable;
1971 	int reqs, ret;
1972 
1973 	/* FIXME: Hardcode number of outstanding requests for now */
1974 	reqs = 32;
1975 	if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
1976 		reqs = 1;
1977 	reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
1978 
1979 	/* Only allow access to user-accessible pages */
1980 	ret = pci_enable_pasid(pdev, 0);
1981 	if (ret)
1982 		goto out_err;
1983 
1984 	/* First reset the PRI state of the device */
1985 	ret = pci_reset_pri(pdev);
1986 	if (ret)
1987 		goto out_err;
1988 
1989 	/* Enable PRI */
1990 	ret = pci_enable_pri(pdev, reqs);
1991 	if (ret)
1992 		goto out_err;
1993 
1994 	if (reset_enable) {
1995 		ret = pri_reset_while_enabled(pdev);
1996 		if (ret)
1997 			goto out_err;
1998 	}
1999 
2000 	ret = pci_enable_ats(pdev, PAGE_SHIFT);
2001 	if (ret)
2002 		goto out_err;
2003 
2004 	return 0;
2005 
2006 out_err:
2007 	pci_disable_pri(pdev);
2008 	pci_disable_pasid(pdev);
2009 
2010 	return ret;
2011 }
2012 
2013 /*
2014  * If a device is not yet associated with a domain, this function makes the
2015  * device visible in the domain
2016  */
2017 static int attach_device(struct device *dev,
2018 			 struct protection_domain *domain)
2019 {
2020 	struct iommu_dev_data *dev_data;
2021 	struct pci_dev *pdev;
2022 	unsigned long flags;
2023 	int ret;
2024 
2025 	spin_lock_irqsave(&domain->lock, flags);
2026 
2027 	dev_data = dev_iommu_priv_get(dev);
2028 
2029 	spin_lock(&dev_data->lock);
2030 
2031 	ret = -EBUSY;
2032 	if (dev_data->domain != NULL)
2033 		goto out;
2034 
2035 	if (!dev_is_pci(dev))
2036 		goto skip_ats_check;
2037 
2038 	pdev = to_pci_dev(dev);
2039 	if (domain->flags & PD_IOMMUV2_MASK) {
2040 		struct iommu_domain *def_domain = iommu_get_dma_domain(dev);
2041 
2042 		ret = -EINVAL;
2043 		if (def_domain->type != IOMMU_DOMAIN_IDENTITY)
2044 			goto out;
2045 
2046 		if (dev_data->iommu_v2) {
2047 			if (pdev_iommuv2_enable(pdev) != 0)
2048 				goto out;
2049 
2050 			dev_data->ats.enabled = true;
2051 			dev_data->ats.qdep    = pci_ats_queue_depth(pdev);
2052 			dev_data->pri_tlp     = pci_prg_resp_pasid_required(pdev);
2053 		}
2054 	} else if (amd_iommu_iotlb_sup &&
2055 		   pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
2056 		dev_data->ats.enabled = true;
2057 		dev_data->ats.qdep    = pci_ats_queue_depth(pdev);
2058 	}
2059 
2060 skip_ats_check:
2061 	ret = 0;
2062 
2063 	do_attach(dev_data, domain);
2064 
2065 	/*
2066 	 * We might boot into a crash-kernel here. The crashed kernel
2067 	 * left the caches in the IOMMU dirty. So we have to flush
2068 	 * here to evict all dirty stuff.
2069 	 */
2070 	domain_flush_tlb_pde(domain);
2071 
2072 	domain_flush_complete(domain);
2073 
2074 out:
2075 	spin_unlock(&dev_data->lock);
2076 
2077 	spin_unlock_irqrestore(&domain->lock, flags);
2078 
2079 	return ret;
2080 }
2081 
2082 /*
2083  * Removes a device from a protection domain (with devtable_lock held)
2084  */
2085 static void detach_device(struct device *dev)
2086 {
2087 	struct protection_domain *domain;
2088 	struct iommu_dev_data *dev_data;
2089 	unsigned long flags;
2090 
2091 	dev_data = dev_iommu_priv_get(dev);
2092 	domain   = dev_data->domain;
2093 
2094 	spin_lock_irqsave(&domain->lock, flags);
2095 
2096 	spin_lock(&dev_data->lock);
2097 
2098 	/*
2099 	 * First check if the device is still attached. It might already
2100 	 * be detached from its domain because the generic
2101 	 * iommu_detach_group code detached it and we try again here in
2102 	 * our alias handling.
2103 	 */
2104 	if (WARN_ON(!dev_data->domain))
2105 		goto out;
2106 
2107 	do_detach(dev_data);
2108 
2109 	if (!dev_is_pci(dev))
2110 		goto out;
2111 
2112 	if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2)
2113 		pdev_iommuv2_disable(to_pci_dev(dev));
2114 	else if (dev_data->ats.enabled)
2115 		pci_disable_ats(to_pci_dev(dev));
2116 
2117 	dev_data->ats.enabled = false;
2118 
2119 out:
2120 	spin_unlock(&dev_data->lock);
2121 
2122 	spin_unlock_irqrestore(&domain->lock, flags);
2123 }
2124 
2125 static struct iommu_device *amd_iommu_probe_device(struct device *dev)
2126 {
2127 	struct iommu_device *iommu_dev;
2128 	struct amd_iommu *iommu;
2129 	int ret, devid;
2130 
2131 	if (!check_device(dev))
2132 		return ERR_PTR(-ENODEV);
2133 
2134 	devid = get_device_id(dev);
2135 	if (devid < 0)
2136 		return ERR_PTR(devid);
2137 
2138 	iommu = amd_iommu_rlookup_table[devid];
2139 
2140 	if (dev_iommu_priv_get(dev))
2141 		return &iommu->iommu;
2142 
2143 	ret = iommu_init_device(dev);
2144 	if (ret) {
2145 		if (ret != -ENOTSUPP)
2146 			dev_err(dev, "Failed to initialize - trying to proceed anyway\n");
2147 		iommu_dev = ERR_PTR(ret);
2148 		iommu_ignore_device(dev);
2149 	} else {
2150 		iommu_dev = &iommu->iommu;
2151 	}
2152 
2153 	iommu_completion_wait(iommu);
2154 
2155 	return iommu_dev;
2156 }
2157 
2158 static void amd_iommu_probe_finalize(struct device *dev)
2159 {
2160 	struct iommu_domain *domain;
2161 
2162 	/* Domains are initialized for this device - have a look what we ended up with */
2163 	domain = iommu_get_domain_for_dev(dev);
2164 	if (domain->type == IOMMU_DOMAIN_DMA)
2165 		iommu_setup_dma_ops(dev, IOVA_START_PFN << PAGE_SHIFT, 0);
2166 }
2167 
2168 static void amd_iommu_release_device(struct device *dev)
2169 {
2170 	int devid = get_device_id(dev);
2171 	struct amd_iommu *iommu;
2172 
2173 	if (!check_device(dev))
2174 		return;
2175 
2176 	iommu = amd_iommu_rlookup_table[devid];
2177 
2178 	amd_iommu_uninit_device(dev);
2179 	iommu_completion_wait(iommu);
2180 }
2181 
2182 static struct iommu_group *amd_iommu_device_group(struct device *dev)
2183 {
2184 	if (dev_is_pci(dev))
2185 		return pci_device_group(dev);
2186 
2187 	return acpihid_device_group(dev);
2188 }
2189 
2190 static int amd_iommu_domain_get_attr(struct iommu_domain *domain,
2191 		enum iommu_attr attr, void *data)
2192 {
2193 	switch (domain->type) {
2194 	case IOMMU_DOMAIN_UNMANAGED:
2195 		return -ENODEV;
2196 	case IOMMU_DOMAIN_DMA:
2197 		switch (attr) {
2198 		case DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE:
2199 			*(int *)data = !amd_iommu_unmap_flush;
2200 			return 0;
2201 		default:
2202 			return -ENODEV;
2203 		}
2204 		break;
2205 	default:
2206 		return -EINVAL;
2207 	}
2208 }
2209 
2210 /*****************************************************************************
2211  *
2212  * The next functions belong to the dma_ops mapping/unmapping code.
2213  *
2214  *****************************************************************************/
2215 
2216 static void update_device_table(struct protection_domain *domain,
2217 				struct domain_pgtable *pgtable)
2218 {
2219 	struct iommu_dev_data *dev_data;
2220 
2221 	list_for_each_entry(dev_data, &domain->dev_list, list) {
2222 		set_dte_entry(dev_data->devid, domain, pgtable,
2223 			      dev_data->ats.enabled, dev_data->iommu_v2);
2224 		clone_aliases(dev_data->pdev);
2225 	}
2226 }
2227 
2228 static void update_and_flush_device_table(struct protection_domain *domain,
2229 					  struct domain_pgtable *pgtable)
2230 {
2231 	update_device_table(domain, pgtable);
2232 	domain_flush_devices(domain);
2233 }
2234 
2235 static void update_domain(struct protection_domain *domain)
2236 {
2237 	struct domain_pgtable pgtable;
2238 
2239 	/* Update device table */
2240 	amd_iommu_domain_get_pgtable(domain, &pgtable);
2241 	update_and_flush_device_table(domain, &pgtable);
2242 
2243 	/* Flush domain TLB(s) and wait for completion */
2244 	domain_flush_tlb_pde(domain);
2245 	domain_flush_complete(domain);
2246 }
2247 
2248 int __init amd_iommu_init_api(void)
2249 {
2250 	int ret, err = 0;
2251 
2252 	ret = iova_cache_get();
2253 	if (ret)
2254 		return ret;
2255 
2256 	err = bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
2257 	if (err)
2258 		return err;
2259 #ifdef CONFIG_ARM_AMBA
2260 	err = bus_set_iommu(&amba_bustype, &amd_iommu_ops);
2261 	if (err)
2262 		return err;
2263 #endif
2264 	err = bus_set_iommu(&platform_bus_type, &amd_iommu_ops);
2265 	if (err)
2266 		return err;
2267 
2268 	return 0;
2269 }
2270 
2271 int __init amd_iommu_init_dma_ops(void)
2272 {
2273 	swiotlb        = (iommu_default_passthrough() || sme_me_mask) ? 1 : 0;
2274 
2275 	if (amd_iommu_unmap_flush)
2276 		pr_info("IO/TLB flush on unmap enabled\n");
2277 	else
2278 		pr_info("Lazy IO/TLB flushing enabled\n");
2279 
2280 	return 0;
2281 
2282 }
2283 
2284 /*****************************************************************************
2285  *
2286  * The following functions belong to the exported interface of AMD IOMMU
2287  *
2288  * This interface allows access to lower level functions of the IOMMU
2289  * like protection domain handling and assignement of devices to domains
2290  * which is not possible with the dma_ops interface.
2291  *
2292  *****************************************************************************/
2293 
2294 static void cleanup_domain(struct protection_domain *domain)
2295 {
2296 	struct iommu_dev_data *entry;
2297 	unsigned long flags;
2298 
2299 	spin_lock_irqsave(&domain->lock, flags);
2300 
2301 	while (!list_empty(&domain->dev_list)) {
2302 		entry = list_first_entry(&domain->dev_list,
2303 					 struct iommu_dev_data, list);
2304 		BUG_ON(!entry->domain);
2305 		do_detach(entry);
2306 	}
2307 
2308 	spin_unlock_irqrestore(&domain->lock, flags);
2309 }
2310 
2311 static void protection_domain_free(struct protection_domain *domain)
2312 {
2313 	struct domain_pgtable pgtable;
2314 
2315 	if (!domain)
2316 		return;
2317 
2318 	if (domain->id)
2319 		domain_id_free(domain->id);
2320 
2321 	amd_iommu_domain_get_pgtable(domain, &pgtable);
2322 	atomic64_set(&domain->pt_root, 0);
2323 	free_pagetable(&pgtable);
2324 
2325 	kfree(domain);
2326 }
2327 
2328 static int protection_domain_init(struct protection_domain *domain, int mode)
2329 {
2330 	u64 *pt_root = NULL, root;
2331 
2332 	BUG_ON(mode < PAGE_MODE_NONE || mode > PAGE_MODE_6_LEVEL);
2333 
2334 	spin_lock_init(&domain->lock);
2335 	domain->id = domain_id_alloc();
2336 	if (!domain->id)
2337 		return -ENOMEM;
2338 	INIT_LIST_HEAD(&domain->dev_list);
2339 
2340 	if (mode != PAGE_MODE_NONE) {
2341 		pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2342 		if (!pt_root)
2343 			return -ENOMEM;
2344 	}
2345 
2346 	root = amd_iommu_domain_encode_pgtable(pt_root, mode);
2347 	atomic64_set(&domain->pt_root, root);
2348 
2349 	return 0;
2350 }
2351 
2352 static struct protection_domain *protection_domain_alloc(int mode)
2353 {
2354 	struct protection_domain *domain;
2355 
2356 	domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2357 	if (!domain)
2358 		return NULL;
2359 
2360 	if (protection_domain_init(domain, mode))
2361 		goto out_err;
2362 
2363 	return domain;
2364 
2365 out_err:
2366 	kfree(domain);
2367 
2368 	return NULL;
2369 }
2370 
2371 static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
2372 {
2373 	struct protection_domain *domain;
2374 	int mode = DEFAULT_PGTABLE_LEVEL;
2375 
2376 	if (type == IOMMU_DOMAIN_IDENTITY)
2377 		mode = PAGE_MODE_NONE;
2378 
2379 	domain = protection_domain_alloc(mode);
2380 	if (!domain)
2381 		return NULL;
2382 
2383 	domain->domain.geometry.aperture_start = 0;
2384 	domain->domain.geometry.aperture_end   = ~0ULL;
2385 	domain->domain.geometry.force_aperture = true;
2386 
2387 	if (type == IOMMU_DOMAIN_DMA &&
2388 	    iommu_get_dma_cookie(&domain->domain) == -ENOMEM)
2389 		goto free_domain;
2390 
2391 	return &domain->domain;
2392 
2393 free_domain:
2394 	protection_domain_free(domain);
2395 
2396 	return NULL;
2397 }
2398 
2399 static void amd_iommu_domain_free(struct iommu_domain *dom)
2400 {
2401 	struct protection_domain *domain;
2402 
2403 	domain = to_pdomain(dom);
2404 
2405 	if (domain->dev_cnt > 0)
2406 		cleanup_domain(domain);
2407 
2408 	BUG_ON(domain->dev_cnt != 0);
2409 
2410 	if (!dom)
2411 		return;
2412 
2413 	if (dom->type == IOMMU_DOMAIN_DMA)
2414 		iommu_put_dma_cookie(&domain->domain);
2415 
2416 	if (domain->flags & PD_IOMMUV2_MASK)
2417 		free_gcr3_table(domain);
2418 
2419 	protection_domain_free(domain);
2420 }
2421 
2422 static void amd_iommu_detach_device(struct iommu_domain *dom,
2423 				    struct device *dev)
2424 {
2425 	struct iommu_dev_data *dev_data = dev_iommu_priv_get(dev);
2426 	struct amd_iommu *iommu;
2427 	int devid;
2428 
2429 	if (!check_device(dev))
2430 		return;
2431 
2432 	devid = get_device_id(dev);
2433 	if (devid < 0)
2434 		return;
2435 
2436 	if (dev_data->domain != NULL)
2437 		detach_device(dev);
2438 
2439 	iommu = amd_iommu_rlookup_table[devid];
2440 	if (!iommu)
2441 		return;
2442 
2443 #ifdef CONFIG_IRQ_REMAP
2444 	if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
2445 	    (dom->type == IOMMU_DOMAIN_UNMANAGED))
2446 		dev_data->use_vapic = 0;
2447 #endif
2448 
2449 	iommu_completion_wait(iommu);
2450 }
2451 
2452 static int amd_iommu_attach_device(struct iommu_domain *dom,
2453 				   struct device *dev)
2454 {
2455 	struct protection_domain *domain = to_pdomain(dom);
2456 	struct iommu_dev_data *dev_data;
2457 	struct amd_iommu *iommu;
2458 	int ret;
2459 
2460 	if (!check_device(dev))
2461 		return -EINVAL;
2462 
2463 	dev_data = dev_iommu_priv_get(dev);
2464 	dev_data->defer_attach = false;
2465 
2466 	iommu = amd_iommu_rlookup_table[dev_data->devid];
2467 	if (!iommu)
2468 		return -EINVAL;
2469 
2470 	if (dev_data->domain)
2471 		detach_device(dev);
2472 
2473 	ret = attach_device(dev, domain);
2474 
2475 #ifdef CONFIG_IRQ_REMAP
2476 	if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
2477 		if (dom->type == IOMMU_DOMAIN_UNMANAGED)
2478 			dev_data->use_vapic = 1;
2479 		else
2480 			dev_data->use_vapic = 0;
2481 	}
2482 #endif
2483 
2484 	iommu_completion_wait(iommu);
2485 
2486 	return ret;
2487 }
2488 
2489 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
2490 			 phys_addr_t paddr, size_t page_size, int iommu_prot,
2491 			 gfp_t gfp)
2492 {
2493 	struct protection_domain *domain = to_pdomain(dom);
2494 	struct domain_pgtable pgtable;
2495 	int prot = 0;
2496 	int ret;
2497 
2498 	amd_iommu_domain_get_pgtable(domain, &pgtable);
2499 	if (pgtable.mode == PAGE_MODE_NONE)
2500 		return -EINVAL;
2501 
2502 	if (iommu_prot & IOMMU_READ)
2503 		prot |= IOMMU_PROT_IR;
2504 	if (iommu_prot & IOMMU_WRITE)
2505 		prot |= IOMMU_PROT_IW;
2506 
2507 	ret = iommu_map_page(domain, iova, paddr, page_size, prot, gfp);
2508 
2509 	domain_flush_np_cache(domain, iova, page_size);
2510 
2511 	return ret;
2512 }
2513 
2514 static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
2515 			      size_t page_size,
2516 			      struct iommu_iotlb_gather *gather)
2517 {
2518 	struct protection_domain *domain = to_pdomain(dom);
2519 	struct domain_pgtable pgtable;
2520 
2521 	amd_iommu_domain_get_pgtable(domain, &pgtable);
2522 	if (pgtable.mode == PAGE_MODE_NONE)
2523 		return 0;
2524 
2525 	return iommu_unmap_page(domain, iova, page_size);
2526 }
2527 
2528 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
2529 					  dma_addr_t iova)
2530 {
2531 	struct protection_domain *domain = to_pdomain(dom);
2532 	unsigned long offset_mask, pte_pgsize;
2533 	struct domain_pgtable pgtable;
2534 	u64 *pte, __pte;
2535 
2536 	amd_iommu_domain_get_pgtable(domain, &pgtable);
2537 	if (pgtable.mode == PAGE_MODE_NONE)
2538 		return iova;
2539 
2540 	pte = fetch_pte(domain, iova, &pte_pgsize);
2541 
2542 	if (!pte || !IOMMU_PTE_PRESENT(*pte))
2543 		return 0;
2544 
2545 	offset_mask = pte_pgsize - 1;
2546 	__pte	    = __sme_clr(*pte & PM_ADDR_MASK);
2547 
2548 	return (__pte & ~offset_mask) | (iova & offset_mask);
2549 }
2550 
2551 static bool amd_iommu_capable(enum iommu_cap cap)
2552 {
2553 	switch (cap) {
2554 	case IOMMU_CAP_CACHE_COHERENCY:
2555 		return true;
2556 	case IOMMU_CAP_INTR_REMAP:
2557 		return (irq_remapping_enabled == 1);
2558 	case IOMMU_CAP_NOEXEC:
2559 		return false;
2560 	default:
2561 		break;
2562 	}
2563 
2564 	return false;
2565 }
2566 
2567 static void amd_iommu_get_resv_regions(struct device *dev,
2568 				       struct list_head *head)
2569 {
2570 	struct iommu_resv_region *region;
2571 	struct unity_map_entry *entry;
2572 	int devid;
2573 
2574 	devid = get_device_id(dev);
2575 	if (devid < 0)
2576 		return;
2577 
2578 	list_for_each_entry(entry, &amd_iommu_unity_map, list) {
2579 		int type, prot = 0;
2580 		size_t length;
2581 
2582 		if (devid < entry->devid_start || devid > entry->devid_end)
2583 			continue;
2584 
2585 		type   = IOMMU_RESV_DIRECT;
2586 		length = entry->address_end - entry->address_start;
2587 		if (entry->prot & IOMMU_PROT_IR)
2588 			prot |= IOMMU_READ;
2589 		if (entry->prot & IOMMU_PROT_IW)
2590 			prot |= IOMMU_WRITE;
2591 		if (entry->prot & IOMMU_UNITY_MAP_FLAG_EXCL_RANGE)
2592 			/* Exclusion range */
2593 			type = IOMMU_RESV_RESERVED;
2594 
2595 		region = iommu_alloc_resv_region(entry->address_start,
2596 						 length, prot, type);
2597 		if (!region) {
2598 			dev_err(dev, "Out of memory allocating dm-regions\n");
2599 			return;
2600 		}
2601 		list_add_tail(&region->list, head);
2602 	}
2603 
2604 	region = iommu_alloc_resv_region(MSI_RANGE_START,
2605 					 MSI_RANGE_END - MSI_RANGE_START + 1,
2606 					 0, IOMMU_RESV_MSI);
2607 	if (!region)
2608 		return;
2609 	list_add_tail(&region->list, head);
2610 
2611 	region = iommu_alloc_resv_region(HT_RANGE_START,
2612 					 HT_RANGE_END - HT_RANGE_START + 1,
2613 					 0, IOMMU_RESV_RESERVED);
2614 	if (!region)
2615 		return;
2616 	list_add_tail(&region->list, head);
2617 }
2618 
2619 bool amd_iommu_is_attach_deferred(struct iommu_domain *domain,
2620 				  struct device *dev)
2621 {
2622 	struct iommu_dev_data *dev_data = dev_iommu_priv_get(dev);
2623 
2624 	return dev_data->defer_attach;
2625 }
2626 EXPORT_SYMBOL_GPL(amd_iommu_is_attach_deferred);
2627 
2628 static void amd_iommu_flush_iotlb_all(struct iommu_domain *domain)
2629 {
2630 	struct protection_domain *dom = to_pdomain(domain);
2631 	unsigned long flags;
2632 
2633 	spin_lock_irqsave(&dom->lock, flags);
2634 	domain_flush_tlb_pde(dom);
2635 	domain_flush_complete(dom);
2636 	spin_unlock_irqrestore(&dom->lock, flags);
2637 }
2638 
2639 static void amd_iommu_iotlb_sync(struct iommu_domain *domain,
2640 				 struct iommu_iotlb_gather *gather)
2641 {
2642 	amd_iommu_flush_iotlb_all(domain);
2643 }
2644 
2645 static int amd_iommu_def_domain_type(struct device *dev)
2646 {
2647 	struct iommu_dev_data *dev_data;
2648 
2649 	dev_data = dev_iommu_priv_get(dev);
2650 	if (!dev_data)
2651 		return 0;
2652 
2653 	if (dev_data->iommu_v2)
2654 		return IOMMU_DOMAIN_IDENTITY;
2655 
2656 	return 0;
2657 }
2658 
2659 const struct iommu_ops amd_iommu_ops = {
2660 	.capable = amd_iommu_capable,
2661 	.domain_alloc = amd_iommu_domain_alloc,
2662 	.domain_free  = amd_iommu_domain_free,
2663 	.attach_dev = amd_iommu_attach_device,
2664 	.detach_dev = amd_iommu_detach_device,
2665 	.map = amd_iommu_map,
2666 	.unmap = amd_iommu_unmap,
2667 	.iova_to_phys = amd_iommu_iova_to_phys,
2668 	.probe_device = amd_iommu_probe_device,
2669 	.release_device = amd_iommu_release_device,
2670 	.probe_finalize = amd_iommu_probe_finalize,
2671 	.device_group = amd_iommu_device_group,
2672 	.domain_get_attr = amd_iommu_domain_get_attr,
2673 	.get_resv_regions = amd_iommu_get_resv_regions,
2674 	.put_resv_regions = generic_iommu_put_resv_regions,
2675 	.is_attach_deferred = amd_iommu_is_attach_deferred,
2676 	.pgsize_bitmap	= AMD_IOMMU_PGSIZES,
2677 	.flush_iotlb_all = amd_iommu_flush_iotlb_all,
2678 	.iotlb_sync = amd_iommu_iotlb_sync,
2679 	.def_domain_type = amd_iommu_def_domain_type,
2680 };
2681 
2682 /*****************************************************************************
2683  *
2684  * The next functions do a basic initialization of IOMMU for pass through
2685  * mode
2686  *
2687  * In passthrough mode the IOMMU is initialized and enabled but not used for
2688  * DMA-API translation.
2689  *
2690  *****************************************************************************/
2691 
2692 /* IOMMUv2 specific functions */
2693 int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
2694 {
2695 	return atomic_notifier_chain_register(&ppr_notifier, nb);
2696 }
2697 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
2698 
2699 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
2700 {
2701 	return atomic_notifier_chain_unregister(&ppr_notifier, nb);
2702 }
2703 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
2704 
2705 void amd_iommu_domain_direct_map(struct iommu_domain *dom)
2706 {
2707 	struct protection_domain *domain = to_pdomain(dom);
2708 	struct domain_pgtable pgtable;
2709 	unsigned long flags;
2710 
2711 	spin_lock_irqsave(&domain->lock, flags);
2712 
2713 	/* First save pgtable configuration*/
2714 	amd_iommu_domain_get_pgtable(domain, &pgtable);
2715 
2716 	/* Update data structure */
2717 	atomic64_set(&domain->pt_root, 0);
2718 
2719 	/* Make changes visible to IOMMUs */
2720 	update_domain(domain);
2721 
2722 	/* Page-table is not visible to IOMMU anymore, so free it */
2723 	free_pagetable(&pgtable);
2724 
2725 	spin_unlock_irqrestore(&domain->lock, flags);
2726 }
2727 EXPORT_SYMBOL(amd_iommu_domain_direct_map);
2728 
2729 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
2730 {
2731 	struct protection_domain *domain = to_pdomain(dom);
2732 	unsigned long flags;
2733 	int levels, ret;
2734 
2735 	if (pasids <= 0 || pasids > (PASID_MASK + 1))
2736 		return -EINVAL;
2737 
2738 	/* Number of GCR3 table levels required */
2739 	for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
2740 		levels += 1;
2741 
2742 	if (levels > amd_iommu_max_glx_val)
2743 		return -EINVAL;
2744 
2745 	spin_lock_irqsave(&domain->lock, flags);
2746 
2747 	/*
2748 	 * Save us all sanity checks whether devices already in the
2749 	 * domain support IOMMUv2. Just force that the domain has no
2750 	 * devices attached when it is switched into IOMMUv2 mode.
2751 	 */
2752 	ret = -EBUSY;
2753 	if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
2754 		goto out;
2755 
2756 	ret = -ENOMEM;
2757 	domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
2758 	if (domain->gcr3_tbl == NULL)
2759 		goto out;
2760 
2761 	domain->glx      = levels;
2762 	domain->flags   |= PD_IOMMUV2_MASK;
2763 
2764 	update_domain(domain);
2765 
2766 	ret = 0;
2767 
2768 out:
2769 	spin_unlock_irqrestore(&domain->lock, flags);
2770 
2771 	return ret;
2772 }
2773 EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
2774 
2775 static int __flush_pasid(struct protection_domain *domain, int pasid,
2776 			 u64 address, bool size)
2777 {
2778 	struct iommu_dev_data *dev_data;
2779 	struct iommu_cmd cmd;
2780 	int i, ret;
2781 
2782 	if (!(domain->flags & PD_IOMMUV2_MASK))
2783 		return -EINVAL;
2784 
2785 	build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
2786 
2787 	/*
2788 	 * IOMMU TLB needs to be flushed before Device TLB to
2789 	 * prevent device TLB refill from IOMMU TLB
2790 	 */
2791 	for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
2792 		if (domain->dev_iommu[i] == 0)
2793 			continue;
2794 
2795 		ret = iommu_queue_command(amd_iommus[i], &cmd);
2796 		if (ret != 0)
2797 			goto out;
2798 	}
2799 
2800 	/* Wait until IOMMU TLB flushes are complete */
2801 	domain_flush_complete(domain);
2802 
2803 	/* Now flush device TLBs */
2804 	list_for_each_entry(dev_data, &domain->dev_list, list) {
2805 		struct amd_iommu *iommu;
2806 		int qdep;
2807 
2808 		/*
2809 		   There might be non-IOMMUv2 capable devices in an IOMMUv2
2810 		 * domain.
2811 		 */
2812 		if (!dev_data->ats.enabled)
2813 			continue;
2814 
2815 		qdep  = dev_data->ats.qdep;
2816 		iommu = amd_iommu_rlookup_table[dev_data->devid];
2817 
2818 		build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
2819 				      qdep, address, size);
2820 
2821 		ret = iommu_queue_command(iommu, &cmd);
2822 		if (ret != 0)
2823 			goto out;
2824 	}
2825 
2826 	/* Wait until all device TLBs are flushed */
2827 	domain_flush_complete(domain);
2828 
2829 	ret = 0;
2830 
2831 out:
2832 
2833 	return ret;
2834 }
2835 
2836 static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
2837 				  u64 address)
2838 {
2839 	return __flush_pasid(domain, pasid, address, false);
2840 }
2841 
2842 int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
2843 			 u64 address)
2844 {
2845 	struct protection_domain *domain = to_pdomain(dom);
2846 	unsigned long flags;
2847 	int ret;
2848 
2849 	spin_lock_irqsave(&domain->lock, flags);
2850 	ret = __amd_iommu_flush_page(domain, pasid, address);
2851 	spin_unlock_irqrestore(&domain->lock, flags);
2852 
2853 	return ret;
2854 }
2855 EXPORT_SYMBOL(amd_iommu_flush_page);
2856 
2857 static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
2858 {
2859 	return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
2860 			     true);
2861 }
2862 
2863 int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
2864 {
2865 	struct protection_domain *domain = to_pdomain(dom);
2866 	unsigned long flags;
2867 	int ret;
2868 
2869 	spin_lock_irqsave(&domain->lock, flags);
2870 	ret = __amd_iommu_flush_tlb(domain, pasid);
2871 	spin_unlock_irqrestore(&domain->lock, flags);
2872 
2873 	return ret;
2874 }
2875 EXPORT_SYMBOL(amd_iommu_flush_tlb);
2876 
2877 static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
2878 {
2879 	int index;
2880 	u64 *pte;
2881 
2882 	while (true) {
2883 
2884 		index = (pasid >> (9 * level)) & 0x1ff;
2885 		pte   = &root[index];
2886 
2887 		if (level == 0)
2888 			break;
2889 
2890 		if (!(*pte & GCR3_VALID)) {
2891 			if (!alloc)
2892 				return NULL;
2893 
2894 			root = (void *)get_zeroed_page(GFP_ATOMIC);
2895 			if (root == NULL)
2896 				return NULL;
2897 
2898 			*pte = iommu_virt_to_phys(root) | GCR3_VALID;
2899 		}
2900 
2901 		root = iommu_phys_to_virt(*pte & PAGE_MASK);
2902 
2903 		level -= 1;
2904 	}
2905 
2906 	return pte;
2907 }
2908 
2909 static int __set_gcr3(struct protection_domain *domain, int pasid,
2910 		      unsigned long cr3)
2911 {
2912 	struct domain_pgtable pgtable;
2913 	u64 *pte;
2914 
2915 	amd_iommu_domain_get_pgtable(domain, &pgtable);
2916 	if (pgtable.mode != PAGE_MODE_NONE)
2917 		return -EINVAL;
2918 
2919 	pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
2920 	if (pte == NULL)
2921 		return -ENOMEM;
2922 
2923 	*pte = (cr3 & PAGE_MASK) | GCR3_VALID;
2924 
2925 	return __amd_iommu_flush_tlb(domain, pasid);
2926 }
2927 
2928 static int __clear_gcr3(struct protection_domain *domain, int pasid)
2929 {
2930 	struct domain_pgtable pgtable;
2931 	u64 *pte;
2932 
2933 	amd_iommu_domain_get_pgtable(domain, &pgtable);
2934 	if (pgtable.mode != PAGE_MODE_NONE)
2935 		return -EINVAL;
2936 
2937 	pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
2938 	if (pte == NULL)
2939 		return 0;
2940 
2941 	*pte = 0;
2942 
2943 	return __amd_iommu_flush_tlb(domain, pasid);
2944 }
2945 
2946 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
2947 			      unsigned long cr3)
2948 {
2949 	struct protection_domain *domain = to_pdomain(dom);
2950 	unsigned long flags;
2951 	int ret;
2952 
2953 	spin_lock_irqsave(&domain->lock, flags);
2954 	ret = __set_gcr3(domain, pasid, cr3);
2955 	spin_unlock_irqrestore(&domain->lock, flags);
2956 
2957 	return ret;
2958 }
2959 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
2960 
2961 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
2962 {
2963 	struct protection_domain *domain = to_pdomain(dom);
2964 	unsigned long flags;
2965 	int ret;
2966 
2967 	spin_lock_irqsave(&domain->lock, flags);
2968 	ret = __clear_gcr3(domain, pasid);
2969 	spin_unlock_irqrestore(&domain->lock, flags);
2970 
2971 	return ret;
2972 }
2973 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
2974 
2975 int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
2976 			   int status, int tag)
2977 {
2978 	struct iommu_dev_data *dev_data;
2979 	struct amd_iommu *iommu;
2980 	struct iommu_cmd cmd;
2981 
2982 	dev_data = dev_iommu_priv_get(&pdev->dev);
2983 	iommu    = amd_iommu_rlookup_table[dev_data->devid];
2984 
2985 	build_complete_ppr(&cmd, dev_data->devid, pasid, status,
2986 			   tag, dev_data->pri_tlp);
2987 
2988 	return iommu_queue_command(iommu, &cmd);
2989 }
2990 EXPORT_SYMBOL(amd_iommu_complete_ppr);
2991 
2992 struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
2993 {
2994 	struct protection_domain *pdomain;
2995 	struct iommu_dev_data *dev_data;
2996 	struct device *dev = &pdev->dev;
2997 	struct iommu_domain *io_domain;
2998 
2999 	if (!check_device(dev))
3000 		return NULL;
3001 
3002 	dev_data  = dev_iommu_priv_get(&pdev->dev);
3003 	pdomain   = dev_data->domain;
3004 	io_domain = iommu_get_domain_for_dev(dev);
3005 
3006 	if (pdomain == NULL && dev_data->defer_attach) {
3007 		dev_data->defer_attach = false;
3008 		pdomain = to_pdomain(io_domain);
3009 		attach_device(dev, pdomain);
3010 	}
3011 
3012 	if (pdomain == NULL)
3013 		return NULL;
3014 
3015 	if (io_domain->type != IOMMU_DOMAIN_DMA)
3016 		return NULL;
3017 
3018 	/* Only return IOMMUv2 domains */
3019 	if (!(pdomain->flags & PD_IOMMUV2_MASK))
3020 		return NULL;
3021 
3022 	return &pdomain->domain;
3023 }
3024 EXPORT_SYMBOL(amd_iommu_get_v2_domain);
3025 
3026 void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3027 {
3028 	struct iommu_dev_data *dev_data;
3029 
3030 	if (!amd_iommu_v2_supported())
3031 		return;
3032 
3033 	dev_data = dev_iommu_priv_get(&pdev->dev);
3034 	dev_data->errata |= (1 << erratum);
3035 }
3036 EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
3037 
3038 int amd_iommu_device_info(struct pci_dev *pdev,
3039                           struct amd_iommu_device_info *info)
3040 {
3041 	int max_pasids;
3042 	int pos;
3043 
3044 	if (pdev == NULL || info == NULL)
3045 		return -EINVAL;
3046 
3047 	if (!amd_iommu_v2_supported())
3048 		return -EINVAL;
3049 
3050 	memset(info, 0, sizeof(*info));
3051 
3052 	if (pci_ats_supported(pdev))
3053 		info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3054 
3055 	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3056 	if (pos)
3057 		info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3058 
3059 	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3060 	if (pos) {
3061 		int features;
3062 
3063 		max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3064 		max_pasids = min(max_pasids, (1 << 20));
3065 
3066 		info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3067 		info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3068 
3069 		features = pci_pasid_features(pdev);
3070 		if (features & PCI_PASID_CAP_EXEC)
3071 			info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3072 		if (features & PCI_PASID_CAP_PRIV)
3073 			info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3074 	}
3075 
3076 	return 0;
3077 }
3078 EXPORT_SYMBOL(amd_iommu_device_info);
3079 
3080 #ifdef CONFIG_IRQ_REMAP
3081 
3082 /*****************************************************************************
3083  *
3084  * Interrupt Remapping Implementation
3085  *
3086  *****************************************************************************/
3087 
3088 static struct irq_chip amd_ir_chip;
3089 static DEFINE_SPINLOCK(iommu_table_lock);
3090 
3091 static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
3092 {
3093 	u64 dte;
3094 
3095 	dte	= amd_iommu_dev_table[devid].data[2];
3096 	dte	&= ~DTE_IRQ_PHYS_ADDR_MASK;
3097 	dte	|= iommu_virt_to_phys(table->table);
3098 	dte	|= DTE_IRQ_REMAP_INTCTL;
3099 	dte	|= DTE_IRQ_TABLE_LEN;
3100 	dte	|= DTE_IRQ_REMAP_ENABLE;
3101 
3102 	amd_iommu_dev_table[devid].data[2] = dte;
3103 }
3104 
3105 static struct irq_remap_table *get_irq_table(u16 devid)
3106 {
3107 	struct irq_remap_table *table;
3108 
3109 	if (WARN_ONCE(!amd_iommu_rlookup_table[devid],
3110 		      "%s: no iommu for devid %x\n", __func__, devid))
3111 		return NULL;
3112 
3113 	table = irq_lookup_table[devid];
3114 	if (WARN_ONCE(!table, "%s: no table for devid %x\n", __func__, devid))
3115 		return NULL;
3116 
3117 	return table;
3118 }
3119 
3120 static struct irq_remap_table *__alloc_irq_table(void)
3121 {
3122 	struct irq_remap_table *table;
3123 
3124 	table = kzalloc(sizeof(*table), GFP_KERNEL);
3125 	if (!table)
3126 		return NULL;
3127 
3128 	table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_KERNEL);
3129 	if (!table->table) {
3130 		kfree(table);
3131 		return NULL;
3132 	}
3133 	raw_spin_lock_init(&table->lock);
3134 
3135 	if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
3136 		memset(table->table, 0,
3137 		       MAX_IRQS_PER_TABLE * sizeof(u32));
3138 	else
3139 		memset(table->table, 0,
3140 		       (MAX_IRQS_PER_TABLE * (sizeof(u64) * 2)));
3141 	return table;
3142 }
3143 
3144 static void set_remap_table_entry(struct amd_iommu *iommu, u16 devid,
3145 				  struct irq_remap_table *table)
3146 {
3147 	irq_lookup_table[devid] = table;
3148 	set_dte_irq_entry(devid, table);
3149 	iommu_flush_dte(iommu, devid);
3150 }
3151 
3152 static int set_remap_table_entry_alias(struct pci_dev *pdev, u16 alias,
3153 				       void *data)
3154 {
3155 	struct irq_remap_table *table = data;
3156 
3157 	irq_lookup_table[alias] = table;
3158 	set_dte_irq_entry(alias, table);
3159 
3160 	iommu_flush_dte(amd_iommu_rlookup_table[alias], alias);
3161 
3162 	return 0;
3163 }
3164 
3165 static struct irq_remap_table *alloc_irq_table(u16 devid, struct pci_dev *pdev)
3166 {
3167 	struct irq_remap_table *table = NULL;
3168 	struct irq_remap_table *new_table = NULL;
3169 	struct amd_iommu *iommu;
3170 	unsigned long flags;
3171 	u16 alias;
3172 
3173 	spin_lock_irqsave(&iommu_table_lock, flags);
3174 
3175 	iommu = amd_iommu_rlookup_table[devid];
3176 	if (!iommu)
3177 		goto out_unlock;
3178 
3179 	table = irq_lookup_table[devid];
3180 	if (table)
3181 		goto out_unlock;
3182 
3183 	alias = amd_iommu_alias_table[devid];
3184 	table = irq_lookup_table[alias];
3185 	if (table) {
3186 		set_remap_table_entry(iommu, devid, table);
3187 		goto out_wait;
3188 	}
3189 	spin_unlock_irqrestore(&iommu_table_lock, flags);
3190 
3191 	/* Nothing there yet, allocate new irq remapping table */
3192 	new_table = __alloc_irq_table();
3193 	if (!new_table)
3194 		return NULL;
3195 
3196 	spin_lock_irqsave(&iommu_table_lock, flags);
3197 
3198 	table = irq_lookup_table[devid];
3199 	if (table)
3200 		goto out_unlock;
3201 
3202 	table = irq_lookup_table[alias];
3203 	if (table) {
3204 		set_remap_table_entry(iommu, devid, table);
3205 		goto out_wait;
3206 	}
3207 
3208 	table = new_table;
3209 	new_table = NULL;
3210 
3211 	if (pdev)
3212 		pci_for_each_dma_alias(pdev, set_remap_table_entry_alias,
3213 				       table);
3214 	else
3215 		set_remap_table_entry(iommu, devid, table);
3216 
3217 	if (devid != alias)
3218 		set_remap_table_entry(iommu, alias, table);
3219 
3220 out_wait:
3221 	iommu_completion_wait(iommu);
3222 
3223 out_unlock:
3224 	spin_unlock_irqrestore(&iommu_table_lock, flags);
3225 
3226 	if (new_table) {
3227 		kmem_cache_free(amd_iommu_irq_cache, new_table->table);
3228 		kfree(new_table);
3229 	}
3230 	return table;
3231 }
3232 
3233 static int alloc_irq_index(u16 devid, int count, bool align,
3234 			   struct pci_dev *pdev)
3235 {
3236 	struct irq_remap_table *table;
3237 	int index, c, alignment = 1;
3238 	unsigned long flags;
3239 	struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
3240 
3241 	if (!iommu)
3242 		return -ENODEV;
3243 
3244 	table = alloc_irq_table(devid, pdev);
3245 	if (!table)
3246 		return -ENODEV;
3247 
3248 	if (align)
3249 		alignment = roundup_pow_of_two(count);
3250 
3251 	raw_spin_lock_irqsave(&table->lock, flags);
3252 
3253 	/* Scan table for free entries */
3254 	for (index = ALIGN(table->min_index, alignment), c = 0;
3255 	     index < MAX_IRQS_PER_TABLE;) {
3256 		if (!iommu->irte_ops->is_allocated(table, index)) {
3257 			c += 1;
3258 		} else {
3259 			c     = 0;
3260 			index = ALIGN(index + 1, alignment);
3261 			continue;
3262 		}
3263 
3264 		if (c == count)	{
3265 			for (; c != 0; --c)
3266 				iommu->irte_ops->set_allocated(table, index - c + 1);
3267 
3268 			index -= count - 1;
3269 			goto out;
3270 		}
3271 
3272 		index++;
3273 	}
3274 
3275 	index = -ENOSPC;
3276 
3277 out:
3278 	raw_spin_unlock_irqrestore(&table->lock, flags);
3279 
3280 	return index;
3281 }
3282 
3283 static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte,
3284 			  struct amd_ir_data *data)
3285 {
3286 	struct irq_remap_table *table;
3287 	struct amd_iommu *iommu;
3288 	unsigned long flags;
3289 	struct irte_ga *entry;
3290 
3291 	iommu = amd_iommu_rlookup_table[devid];
3292 	if (iommu == NULL)
3293 		return -EINVAL;
3294 
3295 	table = get_irq_table(devid);
3296 	if (!table)
3297 		return -ENOMEM;
3298 
3299 	raw_spin_lock_irqsave(&table->lock, flags);
3300 
3301 	entry = (struct irte_ga *)table->table;
3302 	entry = &entry[index];
3303 	entry->lo.fields_remap.valid = 0;
3304 	entry->hi.val = irte->hi.val;
3305 	entry->lo.val = irte->lo.val;
3306 	entry->lo.fields_remap.valid = 1;
3307 	if (data)
3308 		data->ref = entry;
3309 
3310 	raw_spin_unlock_irqrestore(&table->lock, flags);
3311 
3312 	iommu_flush_irt(iommu, devid);
3313 	iommu_completion_wait(iommu);
3314 
3315 	return 0;
3316 }
3317 
3318 static int modify_irte(u16 devid, int index, union irte *irte)
3319 {
3320 	struct irq_remap_table *table;
3321 	struct amd_iommu *iommu;
3322 	unsigned long flags;
3323 
3324 	iommu = amd_iommu_rlookup_table[devid];
3325 	if (iommu == NULL)
3326 		return -EINVAL;
3327 
3328 	table = get_irq_table(devid);
3329 	if (!table)
3330 		return -ENOMEM;
3331 
3332 	raw_spin_lock_irqsave(&table->lock, flags);
3333 	table->table[index] = irte->val;
3334 	raw_spin_unlock_irqrestore(&table->lock, flags);
3335 
3336 	iommu_flush_irt(iommu, devid);
3337 	iommu_completion_wait(iommu);
3338 
3339 	return 0;
3340 }
3341 
3342 static void free_irte(u16 devid, int index)
3343 {
3344 	struct irq_remap_table *table;
3345 	struct amd_iommu *iommu;
3346 	unsigned long flags;
3347 
3348 	iommu = amd_iommu_rlookup_table[devid];
3349 	if (iommu == NULL)
3350 		return;
3351 
3352 	table = get_irq_table(devid);
3353 	if (!table)
3354 		return;
3355 
3356 	raw_spin_lock_irqsave(&table->lock, flags);
3357 	iommu->irte_ops->clear_allocated(table, index);
3358 	raw_spin_unlock_irqrestore(&table->lock, flags);
3359 
3360 	iommu_flush_irt(iommu, devid);
3361 	iommu_completion_wait(iommu);
3362 }
3363 
3364 static void irte_prepare(void *entry,
3365 			 u32 delivery_mode, u32 dest_mode,
3366 			 u8 vector, u32 dest_apicid, int devid)
3367 {
3368 	union irte *irte = (union irte *) entry;
3369 
3370 	irte->val                = 0;
3371 	irte->fields.vector      = vector;
3372 	irte->fields.int_type    = delivery_mode;
3373 	irte->fields.destination = dest_apicid;
3374 	irte->fields.dm          = dest_mode;
3375 	irte->fields.valid       = 1;
3376 }
3377 
3378 static void irte_ga_prepare(void *entry,
3379 			    u32 delivery_mode, u32 dest_mode,
3380 			    u8 vector, u32 dest_apicid, int devid)
3381 {
3382 	struct irte_ga *irte = (struct irte_ga *) entry;
3383 
3384 	irte->lo.val                      = 0;
3385 	irte->hi.val                      = 0;
3386 	irte->lo.fields_remap.int_type    = delivery_mode;
3387 	irte->lo.fields_remap.dm          = dest_mode;
3388 	irte->hi.fields.vector            = vector;
3389 	irte->lo.fields_remap.destination = APICID_TO_IRTE_DEST_LO(dest_apicid);
3390 	irte->hi.fields.destination       = APICID_TO_IRTE_DEST_HI(dest_apicid);
3391 	irte->lo.fields_remap.valid       = 1;
3392 }
3393 
3394 static void irte_activate(void *entry, u16 devid, u16 index)
3395 {
3396 	union irte *irte = (union irte *) entry;
3397 
3398 	irte->fields.valid = 1;
3399 	modify_irte(devid, index, irte);
3400 }
3401 
3402 static void irte_ga_activate(void *entry, u16 devid, u16 index)
3403 {
3404 	struct irte_ga *irte = (struct irte_ga *) entry;
3405 
3406 	irte->lo.fields_remap.valid = 1;
3407 	modify_irte_ga(devid, index, irte, NULL);
3408 }
3409 
3410 static void irte_deactivate(void *entry, u16 devid, u16 index)
3411 {
3412 	union irte *irte = (union irte *) entry;
3413 
3414 	irte->fields.valid = 0;
3415 	modify_irte(devid, index, irte);
3416 }
3417 
3418 static void irte_ga_deactivate(void *entry, u16 devid, u16 index)
3419 {
3420 	struct irte_ga *irte = (struct irte_ga *) entry;
3421 
3422 	irte->lo.fields_remap.valid = 0;
3423 	modify_irte_ga(devid, index, irte, NULL);
3424 }
3425 
3426 static void irte_set_affinity(void *entry, u16 devid, u16 index,
3427 			      u8 vector, u32 dest_apicid)
3428 {
3429 	union irte *irte = (union irte *) entry;
3430 
3431 	irte->fields.vector = vector;
3432 	irte->fields.destination = dest_apicid;
3433 	modify_irte(devid, index, irte);
3434 }
3435 
3436 static void irte_ga_set_affinity(void *entry, u16 devid, u16 index,
3437 				 u8 vector, u32 dest_apicid)
3438 {
3439 	struct irte_ga *irte = (struct irte_ga *) entry;
3440 
3441 	if (!irte->lo.fields_remap.guest_mode) {
3442 		irte->hi.fields.vector = vector;
3443 		irte->lo.fields_remap.destination =
3444 					APICID_TO_IRTE_DEST_LO(dest_apicid);
3445 		irte->hi.fields.destination =
3446 					APICID_TO_IRTE_DEST_HI(dest_apicid);
3447 		modify_irte_ga(devid, index, irte, NULL);
3448 	}
3449 }
3450 
3451 #define IRTE_ALLOCATED (~1U)
3452 static void irte_set_allocated(struct irq_remap_table *table, int index)
3453 {
3454 	table->table[index] = IRTE_ALLOCATED;
3455 }
3456 
3457 static void irte_ga_set_allocated(struct irq_remap_table *table, int index)
3458 {
3459 	struct irte_ga *ptr = (struct irte_ga *)table->table;
3460 	struct irte_ga *irte = &ptr[index];
3461 
3462 	memset(&irte->lo.val, 0, sizeof(u64));
3463 	memset(&irte->hi.val, 0, sizeof(u64));
3464 	irte->hi.fields.vector = 0xff;
3465 }
3466 
3467 static bool irte_is_allocated(struct irq_remap_table *table, int index)
3468 {
3469 	union irte *ptr = (union irte *)table->table;
3470 	union irte *irte = &ptr[index];
3471 
3472 	return irte->val != 0;
3473 }
3474 
3475 static bool irte_ga_is_allocated(struct irq_remap_table *table, int index)
3476 {
3477 	struct irte_ga *ptr = (struct irte_ga *)table->table;
3478 	struct irte_ga *irte = &ptr[index];
3479 
3480 	return irte->hi.fields.vector != 0;
3481 }
3482 
3483 static void irte_clear_allocated(struct irq_remap_table *table, int index)
3484 {
3485 	table->table[index] = 0;
3486 }
3487 
3488 static void irte_ga_clear_allocated(struct irq_remap_table *table, int index)
3489 {
3490 	struct irte_ga *ptr = (struct irte_ga *)table->table;
3491 	struct irte_ga *irte = &ptr[index];
3492 
3493 	memset(&irte->lo.val, 0, sizeof(u64));
3494 	memset(&irte->hi.val, 0, sizeof(u64));
3495 }
3496 
3497 static int get_devid(struct irq_alloc_info *info)
3498 {
3499 	int devid = -1;
3500 
3501 	switch (info->type) {
3502 	case X86_IRQ_ALLOC_TYPE_IOAPIC:
3503 		devid     = get_ioapic_devid(info->ioapic_id);
3504 		break;
3505 	case X86_IRQ_ALLOC_TYPE_HPET:
3506 		devid     = get_hpet_devid(info->hpet_id);
3507 		break;
3508 	case X86_IRQ_ALLOC_TYPE_MSI:
3509 	case X86_IRQ_ALLOC_TYPE_MSIX:
3510 		devid = get_device_id(&info->msi_dev->dev);
3511 		break;
3512 	default:
3513 		BUG_ON(1);
3514 		break;
3515 	}
3516 
3517 	return devid;
3518 }
3519 
3520 static struct irq_domain *get_ir_irq_domain(struct irq_alloc_info *info)
3521 {
3522 	struct amd_iommu *iommu;
3523 	int devid;
3524 
3525 	if (!info)
3526 		return NULL;
3527 
3528 	devid = get_devid(info);
3529 	if (devid >= 0) {
3530 		iommu = amd_iommu_rlookup_table[devid];
3531 		if (iommu)
3532 			return iommu->ir_domain;
3533 	}
3534 
3535 	return NULL;
3536 }
3537 
3538 static struct irq_domain *get_irq_domain(struct irq_alloc_info *info)
3539 {
3540 	struct amd_iommu *iommu;
3541 	int devid;
3542 
3543 	if (!info)
3544 		return NULL;
3545 
3546 	switch (info->type) {
3547 	case X86_IRQ_ALLOC_TYPE_MSI:
3548 	case X86_IRQ_ALLOC_TYPE_MSIX:
3549 		devid = get_device_id(&info->msi_dev->dev);
3550 		if (devid < 0)
3551 			return NULL;
3552 
3553 		iommu = amd_iommu_rlookup_table[devid];
3554 		if (iommu)
3555 			return iommu->msi_domain;
3556 		break;
3557 	default:
3558 		break;
3559 	}
3560 
3561 	return NULL;
3562 }
3563 
3564 struct irq_remap_ops amd_iommu_irq_ops = {
3565 	.prepare		= amd_iommu_prepare,
3566 	.enable			= amd_iommu_enable,
3567 	.disable		= amd_iommu_disable,
3568 	.reenable		= amd_iommu_reenable,
3569 	.enable_faulting	= amd_iommu_enable_faulting,
3570 	.get_ir_irq_domain	= get_ir_irq_domain,
3571 	.get_irq_domain		= get_irq_domain,
3572 };
3573 
3574 static void irq_remapping_prepare_irte(struct amd_ir_data *data,
3575 				       struct irq_cfg *irq_cfg,
3576 				       struct irq_alloc_info *info,
3577 				       int devid, int index, int sub_handle)
3578 {
3579 	struct irq_2_irte *irte_info = &data->irq_2_irte;
3580 	struct msi_msg *msg = &data->msi_entry;
3581 	struct IO_APIC_route_entry *entry;
3582 	struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
3583 
3584 	if (!iommu)
3585 		return;
3586 
3587 	data->irq_2_irte.devid = devid;
3588 	data->irq_2_irte.index = index + sub_handle;
3589 	iommu->irte_ops->prepare(data->entry, apic->irq_delivery_mode,
3590 				 apic->irq_dest_mode, irq_cfg->vector,
3591 				 irq_cfg->dest_apicid, devid);
3592 
3593 	switch (info->type) {
3594 	case X86_IRQ_ALLOC_TYPE_IOAPIC:
3595 		/* Setup IOAPIC entry */
3596 		entry = info->ioapic_entry;
3597 		info->ioapic_entry = NULL;
3598 		memset(entry, 0, sizeof(*entry));
3599 		entry->vector        = index;
3600 		entry->mask          = 0;
3601 		entry->trigger       = info->ioapic_trigger;
3602 		entry->polarity      = info->ioapic_polarity;
3603 		/* Mask level triggered irqs. */
3604 		if (info->ioapic_trigger)
3605 			entry->mask = 1;
3606 		break;
3607 
3608 	case X86_IRQ_ALLOC_TYPE_HPET:
3609 	case X86_IRQ_ALLOC_TYPE_MSI:
3610 	case X86_IRQ_ALLOC_TYPE_MSIX:
3611 		msg->address_hi = MSI_ADDR_BASE_HI;
3612 		msg->address_lo = MSI_ADDR_BASE_LO;
3613 		msg->data = irte_info->index;
3614 		break;
3615 
3616 	default:
3617 		BUG_ON(1);
3618 		break;
3619 	}
3620 }
3621 
3622 struct amd_irte_ops irte_32_ops = {
3623 	.prepare = irte_prepare,
3624 	.activate = irte_activate,
3625 	.deactivate = irte_deactivate,
3626 	.set_affinity = irte_set_affinity,
3627 	.set_allocated = irte_set_allocated,
3628 	.is_allocated = irte_is_allocated,
3629 	.clear_allocated = irte_clear_allocated,
3630 };
3631 
3632 struct amd_irte_ops irte_128_ops = {
3633 	.prepare = irte_ga_prepare,
3634 	.activate = irte_ga_activate,
3635 	.deactivate = irte_ga_deactivate,
3636 	.set_affinity = irte_ga_set_affinity,
3637 	.set_allocated = irte_ga_set_allocated,
3638 	.is_allocated = irte_ga_is_allocated,
3639 	.clear_allocated = irte_ga_clear_allocated,
3640 };
3641 
3642 static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq,
3643 			       unsigned int nr_irqs, void *arg)
3644 {
3645 	struct irq_alloc_info *info = arg;
3646 	struct irq_data *irq_data;
3647 	struct amd_ir_data *data = NULL;
3648 	struct irq_cfg *cfg;
3649 	int i, ret, devid;
3650 	int index;
3651 
3652 	if (!info)
3653 		return -EINVAL;
3654 	if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI &&
3655 	    info->type != X86_IRQ_ALLOC_TYPE_MSIX)
3656 		return -EINVAL;
3657 
3658 	/*
3659 	 * With IRQ remapping enabled, don't need contiguous CPU vectors
3660 	 * to support multiple MSI interrupts.
3661 	 */
3662 	if (info->type == X86_IRQ_ALLOC_TYPE_MSI)
3663 		info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
3664 
3665 	devid = get_devid(info);
3666 	if (devid < 0)
3667 		return -EINVAL;
3668 
3669 	ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
3670 	if (ret < 0)
3671 		return ret;
3672 
3673 	if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) {
3674 		struct irq_remap_table *table;
3675 		struct amd_iommu *iommu;
3676 
3677 		table = alloc_irq_table(devid, NULL);
3678 		if (table) {
3679 			if (!table->min_index) {
3680 				/*
3681 				 * Keep the first 32 indexes free for IOAPIC
3682 				 * interrupts.
3683 				 */
3684 				table->min_index = 32;
3685 				iommu = amd_iommu_rlookup_table[devid];
3686 				for (i = 0; i < 32; ++i)
3687 					iommu->irte_ops->set_allocated(table, i);
3688 			}
3689 			WARN_ON(table->min_index != 32);
3690 			index = info->ioapic_pin;
3691 		} else {
3692 			index = -ENOMEM;
3693 		}
3694 	} else if (info->type == X86_IRQ_ALLOC_TYPE_MSI ||
3695 		   info->type == X86_IRQ_ALLOC_TYPE_MSIX) {
3696 		bool align = (info->type == X86_IRQ_ALLOC_TYPE_MSI);
3697 
3698 		index = alloc_irq_index(devid, nr_irqs, align, info->msi_dev);
3699 	} else {
3700 		index = alloc_irq_index(devid, nr_irqs, false, NULL);
3701 	}
3702 
3703 	if (index < 0) {
3704 		pr_warn("Failed to allocate IRTE\n");
3705 		ret = index;
3706 		goto out_free_parent;
3707 	}
3708 
3709 	for (i = 0; i < nr_irqs; i++) {
3710 		irq_data = irq_domain_get_irq_data(domain, virq + i);
3711 		cfg = irqd_cfg(irq_data);
3712 		if (!irq_data || !cfg) {
3713 			ret = -EINVAL;
3714 			goto out_free_data;
3715 		}
3716 
3717 		ret = -ENOMEM;
3718 		data = kzalloc(sizeof(*data), GFP_KERNEL);
3719 		if (!data)
3720 			goto out_free_data;
3721 
3722 		if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
3723 			data->entry = kzalloc(sizeof(union irte), GFP_KERNEL);
3724 		else
3725 			data->entry = kzalloc(sizeof(struct irte_ga),
3726 						     GFP_KERNEL);
3727 		if (!data->entry) {
3728 			kfree(data);
3729 			goto out_free_data;
3730 		}
3731 
3732 		irq_data->hwirq = (devid << 16) + i;
3733 		irq_data->chip_data = data;
3734 		irq_data->chip = &amd_ir_chip;
3735 		irq_remapping_prepare_irte(data, cfg, info, devid, index, i);
3736 		irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
3737 	}
3738 
3739 	return 0;
3740 
3741 out_free_data:
3742 	for (i--; i >= 0; i--) {
3743 		irq_data = irq_domain_get_irq_data(domain, virq + i);
3744 		if (irq_data)
3745 			kfree(irq_data->chip_data);
3746 	}
3747 	for (i = 0; i < nr_irqs; i++)
3748 		free_irte(devid, index + i);
3749 out_free_parent:
3750 	irq_domain_free_irqs_common(domain, virq, nr_irqs);
3751 	return ret;
3752 }
3753 
3754 static void irq_remapping_free(struct irq_domain *domain, unsigned int virq,
3755 			       unsigned int nr_irqs)
3756 {
3757 	struct irq_2_irte *irte_info;
3758 	struct irq_data *irq_data;
3759 	struct amd_ir_data *data;
3760 	int i;
3761 
3762 	for (i = 0; i < nr_irqs; i++) {
3763 		irq_data = irq_domain_get_irq_data(domain, virq  + i);
3764 		if (irq_data && irq_data->chip_data) {
3765 			data = irq_data->chip_data;
3766 			irte_info = &data->irq_2_irte;
3767 			free_irte(irte_info->devid, irte_info->index);
3768 			kfree(data->entry);
3769 			kfree(data);
3770 		}
3771 	}
3772 	irq_domain_free_irqs_common(domain, virq, nr_irqs);
3773 }
3774 
3775 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
3776 			       struct amd_ir_data *ir_data,
3777 			       struct irq_2_irte *irte_info,
3778 			       struct irq_cfg *cfg);
3779 
3780 static int irq_remapping_activate(struct irq_domain *domain,
3781 				  struct irq_data *irq_data, bool reserve)
3782 {
3783 	struct amd_ir_data *data = irq_data->chip_data;
3784 	struct irq_2_irte *irte_info = &data->irq_2_irte;
3785 	struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
3786 	struct irq_cfg *cfg = irqd_cfg(irq_data);
3787 
3788 	if (!iommu)
3789 		return 0;
3790 
3791 	iommu->irte_ops->activate(data->entry, irte_info->devid,
3792 				  irte_info->index);
3793 	amd_ir_update_irte(irq_data, iommu, data, irte_info, cfg);
3794 	return 0;
3795 }
3796 
3797 static void irq_remapping_deactivate(struct irq_domain *domain,
3798 				     struct irq_data *irq_data)
3799 {
3800 	struct amd_ir_data *data = irq_data->chip_data;
3801 	struct irq_2_irte *irte_info = &data->irq_2_irte;
3802 	struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
3803 
3804 	if (iommu)
3805 		iommu->irte_ops->deactivate(data->entry, irte_info->devid,
3806 					    irte_info->index);
3807 }
3808 
3809 static const struct irq_domain_ops amd_ir_domain_ops = {
3810 	.alloc = irq_remapping_alloc,
3811 	.free = irq_remapping_free,
3812 	.activate = irq_remapping_activate,
3813 	.deactivate = irq_remapping_deactivate,
3814 };
3815 
3816 int amd_iommu_activate_guest_mode(void *data)
3817 {
3818 	struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
3819 	struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
3820 
3821 	if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
3822 	    !entry || entry->lo.fields_vapic.guest_mode)
3823 		return 0;
3824 
3825 	entry->lo.val = 0;
3826 	entry->hi.val = 0;
3827 
3828 	entry->lo.fields_vapic.guest_mode  = 1;
3829 	entry->lo.fields_vapic.ga_log_intr = 1;
3830 	entry->hi.fields.ga_root_ptr       = ir_data->ga_root_ptr;
3831 	entry->hi.fields.vector            = ir_data->ga_vector;
3832 	entry->lo.fields_vapic.ga_tag      = ir_data->ga_tag;
3833 
3834 	return modify_irte_ga(ir_data->irq_2_irte.devid,
3835 			      ir_data->irq_2_irte.index, entry, ir_data);
3836 }
3837 EXPORT_SYMBOL(amd_iommu_activate_guest_mode);
3838 
3839 int amd_iommu_deactivate_guest_mode(void *data)
3840 {
3841 	struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
3842 	struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
3843 	struct irq_cfg *cfg = ir_data->cfg;
3844 
3845 	if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
3846 	    !entry || !entry->lo.fields_vapic.guest_mode)
3847 		return 0;
3848 
3849 	entry->lo.val = 0;
3850 	entry->hi.val = 0;
3851 
3852 	entry->lo.fields_remap.dm          = apic->irq_dest_mode;
3853 	entry->lo.fields_remap.int_type    = apic->irq_delivery_mode;
3854 	entry->hi.fields.vector            = cfg->vector;
3855 	entry->lo.fields_remap.destination =
3856 				APICID_TO_IRTE_DEST_LO(cfg->dest_apicid);
3857 	entry->hi.fields.destination =
3858 				APICID_TO_IRTE_DEST_HI(cfg->dest_apicid);
3859 
3860 	return modify_irte_ga(ir_data->irq_2_irte.devid,
3861 			      ir_data->irq_2_irte.index, entry, ir_data);
3862 }
3863 EXPORT_SYMBOL(amd_iommu_deactivate_guest_mode);
3864 
3865 static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info)
3866 {
3867 	int ret;
3868 	struct amd_iommu *iommu;
3869 	struct amd_iommu_pi_data *pi_data = vcpu_info;
3870 	struct vcpu_data *vcpu_pi_info = pi_data->vcpu_data;
3871 	struct amd_ir_data *ir_data = data->chip_data;
3872 	struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
3873 	struct iommu_dev_data *dev_data = search_dev_data(irte_info->devid);
3874 
3875 	/* Note:
3876 	 * This device has never been set up for guest mode.
3877 	 * we should not modify the IRTE
3878 	 */
3879 	if (!dev_data || !dev_data->use_vapic)
3880 		return 0;
3881 
3882 	ir_data->cfg = irqd_cfg(data);
3883 	pi_data->ir_data = ir_data;
3884 
3885 	/* Note:
3886 	 * SVM tries to set up for VAPIC mode, but we are in
3887 	 * legacy mode. So, we force legacy mode instead.
3888 	 */
3889 	if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
3890 		pr_debug("%s: Fall back to using intr legacy remap\n",
3891 			 __func__);
3892 		pi_data->is_guest_mode = false;
3893 	}
3894 
3895 	iommu = amd_iommu_rlookup_table[irte_info->devid];
3896 	if (iommu == NULL)
3897 		return -EINVAL;
3898 
3899 	pi_data->prev_ga_tag = ir_data->cached_ga_tag;
3900 	if (pi_data->is_guest_mode) {
3901 		ir_data->ga_root_ptr = (pi_data->base >> 12);
3902 		ir_data->ga_vector = vcpu_pi_info->vector;
3903 		ir_data->ga_tag = pi_data->ga_tag;
3904 		ret = amd_iommu_activate_guest_mode(ir_data);
3905 		if (!ret)
3906 			ir_data->cached_ga_tag = pi_data->ga_tag;
3907 	} else {
3908 		ret = amd_iommu_deactivate_guest_mode(ir_data);
3909 
3910 		/*
3911 		 * This communicates the ga_tag back to the caller
3912 		 * so that it can do all the necessary clean up.
3913 		 */
3914 		if (!ret)
3915 			ir_data->cached_ga_tag = 0;
3916 	}
3917 
3918 	return ret;
3919 }
3920 
3921 
3922 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
3923 			       struct amd_ir_data *ir_data,
3924 			       struct irq_2_irte *irte_info,
3925 			       struct irq_cfg *cfg)
3926 {
3927 
3928 	/*
3929 	 * Atomically updates the IRTE with the new destination, vector
3930 	 * and flushes the interrupt entry cache.
3931 	 */
3932 	iommu->irte_ops->set_affinity(ir_data->entry, irte_info->devid,
3933 				      irte_info->index, cfg->vector,
3934 				      cfg->dest_apicid);
3935 }
3936 
3937 static int amd_ir_set_affinity(struct irq_data *data,
3938 			       const struct cpumask *mask, bool force)
3939 {
3940 	struct amd_ir_data *ir_data = data->chip_data;
3941 	struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
3942 	struct irq_cfg *cfg = irqd_cfg(data);
3943 	struct irq_data *parent = data->parent_data;
3944 	struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
3945 	int ret;
3946 
3947 	if (!iommu)
3948 		return -ENODEV;
3949 
3950 	ret = parent->chip->irq_set_affinity(parent, mask, force);
3951 	if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
3952 		return ret;
3953 
3954 	amd_ir_update_irte(data, iommu, ir_data, irte_info, cfg);
3955 	/*
3956 	 * After this point, all the interrupts will start arriving
3957 	 * at the new destination. So, time to cleanup the previous
3958 	 * vector allocation.
3959 	 */
3960 	send_cleanup_vector(cfg);
3961 
3962 	return IRQ_SET_MASK_OK_DONE;
3963 }
3964 
3965 static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg)
3966 {
3967 	struct amd_ir_data *ir_data = irq_data->chip_data;
3968 
3969 	*msg = ir_data->msi_entry;
3970 }
3971 
3972 static struct irq_chip amd_ir_chip = {
3973 	.name			= "AMD-IR",
3974 	.irq_ack		= apic_ack_irq,
3975 	.irq_set_affinity	= amd_ir_set_affinity,
3976 	.irq_set_vcpu_affinity	= amd_ir_set_vcpu_affinity,
3977 	.irq_compose_msi_msg	= ir_compose_msi_msg,
3978 };
3979 
3980 int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
3981 {
3982 	struct fwnode_handle *fn;
3983 
3984 	fn = irq_domain_alloc_named_id_fwnode("AMD-IR", iommu->index);
3985 	if (!fn)
3986 		return -ENOMEM;
3987 	iommu->ir_domain = irq_domain_create_tree(fn, &amd_ir_domain_ops, iommu);
3988 	if (!iommu->ir_domain) {
3989 		irq_domain_free_fwnode(fn);
3990 		return -ENOMEM;
3991 	}
3992 
3993 	iommu->ir_domain->parent = arch_get_ir_parent_domain();
3994 	iommu->msi_domain = arch_create_remap_msi_irq_domain(iommu->ir_domain,
3995 							     "AMD-IR-MSI",
3996 							     iommu->index);
3997 	return 0;
3998 }
3999 
4000 int amd_iommu_update_ga(int cpu, bool is_run, void *data)
4001 {
4002 	unsigned long flags;
4003 	struct amd_iommu *iommu;
4004 	struct irq_remap_table *table;
4005 	struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
4006 	int devid = ir_data->irq_2_irte.devid;
4007 	struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
4008 	struct irte_ga *ref = (struct irte_ga *) ir_data->ref;
4009 
4010 	if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
4011 	    !ref || !entry || !entry->lo.fields_vapic.guest_mode)
4012 		return 0;
4013 
4014 	iommu = amd_iommu_rlookup_table[devid];
4015 	if (!iommu)
4016 		return -ENODEV;
4017 
4018 	table = get_irq_table(devid);
4019 	if (!table)
4020 		return -ENODEV;
4021 
4022 	raw_spin_lock_irqsave(&table->lock, flags);
4023 
4024 	if (ref->lo.fields_vapic.guest_mode) {
4025 		if (cpu >= 0) {
4026 			ref->lo.fields_vapic.destination =
4027 						APICID_TO_IRTE_DEST_LO(cpu);
4028 			ref->hi.fields.destination =
4029 						APICID_TO_IRTE_DEST_HI(cpu);
4030 		}
4031 		ref->lo.fields_vapic.is_run = is_run;
4032 		barrier();
4033 	}
4034 
4035 	raw_spin_unlock_irqrestore(&table->lock, flags);
4036 
4037 	iommu_flush_irt(iommu, devid);
4038 	iommu_completion_wait(iommu);
4039 	return 0;
4040 }
4041 EXPORT_SYMBOL(amd_iommu_update_ga);
4042 #endif
4043