1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. 4 * Author: Joerg Roedel <jroedel@suse.de> 5 * Leo Duran <leo.duran@amd.com> 6 */ 7 8 #define pr_fmt(fmt) "AMD-Vi: " fmt 9 #define dev_fmt(fmt) pr_fmt(fmt) 10 11 #include <linux/pci.h> 12 #include <linux/acpi.h> 13 #include <linux/list.h> 14 #include <linux/bitmap.h> 15 #include <linux/syscore_ops.h> 16 #include <linux/interrupt.h> 17 #include <linux/msi.h> 18 #include <linux/irq.h> 19 #include <linux/amd-iommu.h> 20 #include <linux/export.h> 21 #include <linux/kmemleak.h> 22 #include <linux/cc_platform.h> 23 #include <linux/iopoll.h> 24 #include <asm/pci-direct.h> 25 #include <asm/iommu.h> 26 #include <asm/apic.h> 27 #include <asm/gart.h> 28 #include <asm/x86_init.h> 29 #include <asm/io_apic.h> 30 #include <asm/irq_remapping.h> 31 #include <asm/set_memory.h> 32 #include <asm/sev.h> 33 34 #include <linux/crash_dump.h> 35 36 #include "amd_iommu.h" 37 #include "../irq_remapping.h" 38 #include "../iommu-pages.h" 39 40 /* 41 * definitions for the ACPI scanning code 42 */ 43 #define IVRS_HEADER_LENGTH 48 44 45 #define ACPI_IVHD_TYPE_MAX_SUPPORTED 0x40 46 #define ACPI_IVMD_TYPE_ALL 0x20 47 #define ACPI_IVMD_TYPE 0x21 48 #define ACPI_IVMD_TYPE_RANGE 0x22 49 50 #define IVHD_DEV_ALL 0x01 51 #define IVHD_DEV_SELECT 0x02 52 #define IVHD_DEV_SELECT_RANGE_START 0x03 53 #define IVHD_DEV_RANGE_END 0x04 54 #define IVHD_DEV_ALIAS 0x42 55 #define IVHD_DEV_ALIAS_RANGE 0x43 56 #define IVHD_DEV_EXT_SELECT 0x46 57 #define IVHD_DEV_EXT_SELECT_RANGE 0x47 58 #define IVHD_DEV_SPECIAL 0x48 59 #define IVHD_DEV_ACPI_HID 0xf0 60 61 #define UID_NOT_PRESENT 0 62 #define UID_IS_INTEGER 1 63 #define UID_IS_CHARACTER 2 64 65 #define IVHD_SPECIAL_IOAPIC 1 66 #define IVHD_SPECIAL_HPET 2 67 68 #define IVHD_FLAG_HT_TUN_EN_MASK 0x01 69 #define IVHD_FLAG_PASSPW_EN_MASK 0x02 70 #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04 71 #define IVHD_FLAG_ISOC_EN_MASK 0x08 72 73 #define IVMD_FLAG_EXCL_RANGE 0x08 74 #define IVMD_FLAG_IW 0x04 75 #define IVMD_FLAG_IR 0x02 76 #define IVMD_FLAG_UNITY_MAP 0x01 77 78 #define ACPI_DEVFLAG_INITPASS 0x01 79 #define ACPI_DEVFLAG_EXTINT 0x02 80 #define ACPI_DEVFLAG_NMI 0x04 81 #define ACPI_DEVFLAG_SYSMGT1 0x10 82 #define ACPI_DEVFLAG_SYSMGT2 0x20 83 #define ACPI_DEVFLAG_LINT0 0x40 84 #define ACPI_DEVFLAG_LINT1 0x80 85 #define ACPI_DEVFLAG_ATSDIS 0x10000000 86 87 #define IVRS_GET_SBDF_ID(seg, bus, dev, fn) (((seg & 0xffff) << 16) | ((bus & 0xff) << 8) \ 88 | ((dev & 0x1f) << 3) | (fn & 0x7)) 89 90 /* 91 * ACPI table definitions 92 * 93 * These data structures are laid over the table to parse the important values 94 * out of it. 95 */ 96 97 /* 98 * structure describing one IOMMU in the ACPI table. Typically followed by one 99 * or more ivhd_entrys. 100 */ 101 struct ivhd_header { 102 u8 type; 103 u8 flags; 104 u16 length; 105 u16 devid; 106 u16 cap_ptr; 107 u64 mmio_phys; 108 u16 pci_seg; 109 u16 info; 110 u32 efr_attr; 111 112 /* Following only valid on IVHD type 11h and 40h */ 113 u64 efr_reg; /* Exact copy of MMIO_EXT_FEATURES */ 114 u64 efr_reg2; 115 } __attribute__((packed)); 116 117 /* 118 * A device entry describing which devices a specific IOMMU translates and 119 * which requestor ids they use. 120 */ 121 struct ivhd_entry { 122 u8 type; 123 u16 devid; 124 u8 flags; 125 struct_group(ext_hid, 126 u32 ext; 127 u32 hidh; 128 ); 129 u64 cid; 130 u8 uidf; 131 u8 uidl; 132 u8 uid; 133 } __attribute__((packed)); 134 135 /* 136 * An AMD IOMMU memory definition structure. It defines things like exclusion 137 * ranges for devices and regions that should be unity mapped. 138 */ 139 struct ivmd_header { 140 u8 type; 141 u8 flags; 142 u16 length; 143 u16 devid; 144 u16 aux; 145 u16 pci_seg; 146 u8 resv[6]; 147 u64 range_start; 148 u64 range_length; 149 } __attribute__((packed)); 150 151 bool amd_iommu_dump; 152 bool amd_iommu_irq_remap __read_mostly; 153 154 enum protection_domain_mode amd_iommu_pgtable = PD_MODE_V1; 155 /* Guest page table level */ 156 int amd_iommu_gpt_level = PAGE_MODE_4_LEVEL; 157 158 int amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC; 159 static int amd_iommu_xt_mode = IRQ_REMAP_XAPIC_MODE; 160 161 static bool amd_iommu_detected; 162 static bool amd_iommu_disabled __initdata; 163 static bool amd_iommu_force_enable __initdata; 164 static bool amd_iommu_irtcachedis; 165 static int amd_iommu_target_ivhd_type; 166 167 /* Global EFR and EFR2 registers */ 168 u64 amd_iommu_efr; 169 u64 amd_iommu_efr2; 170 171 /* SNP is enabled on the system? */ 172 bool amd_iommu_snp_en; 173 EXPORT_SYMBOL(amd_iommu_snp_en); 174 175 LIST_HEAD(amd_iommu_pci_seg_list); /* list of all PCI segments */ 176 LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the system */ 177 LIST_HEAD(amd_ivhd_dev_flags_list); /* list of all IVHD device entry settings */ 178 179 /* Number of IOMMUs present in the system */ 180 static int amd_iommus_present; 181 182 /* IOMMUs have a non-present cache? */ 183 bool amd_iommu_np_cache __read_mostly; 184 bool amd_iommu_iotlb_sup __read_mostly = true; 185 186 static bool amd_iommu_pc_present __read_mostly; 187 bool amdr_ivrs_remap_support __read_mostly; 188 189 bool amd_iommu_force_isolation __read_mostly; 190 191 unsigned long amd_iommu_pgsize_bitmap __ro_after_init = AMD_IOMMU_PGSIZES; 192 193 enum iommu_init_state { 194 IOMMU_START_STATE, 195 IOMMU_IVRS_DETECTED, 196 IOMMU_ACPI_FINISHED, 197 IOMMU_ENABLED, 198 IOMMU_PCI_INIT, 199 IOMMU_INTERRUPTS_EN, 200 IOMMU_INITIALIZED, 201 IOMMU_NOT_FOUND, 202 IOMMU_INIT_ERROR, 203 IOMMU_CMDLINE_DISABLED, 204 }; 205 206 /* Early ioapic and hpet maps from kernel command line */ 207 #define EARLY_MAP_SIZE 4 208 static struct devid_map __initdata early_ioapic_map[EARLY_MAP_SIZE]; 209 static struct devid_map __initdata early_hpet_map[EARLY_MAP_SIZE]; 210 static struct acpihid_map_entry __initdata early_acpihid_map[EARLY_MAP_SIZE]; 211 212 static int __initdata early_ioapic_map_size; 213 static int __initdata early_hpet_map_size; 214 static int __initdata early_acpihid_map_size; 215 216 static bool __initdata cmdline_maps; 217 218 static enum iommu_init_state init_state = IOMMU_START_STATE; 219 220 static int amd_iommu_enable_interrupts(void); 221 static void init_device_table_dma(struct amd_iommu_pci_seg *pci_seg); 222 223 static bool amd_iommu_pre_enabled = true; 224 225 static u32 amd_iommu_ivinfo __initdata; 226 227 bool translation_pre_enabled(struct amd_iommu *iommu) 228 { 229 return (iommu->flags & AMD_IOMMU_FLAG_TRANS_PRE_ENABLED); 230 } 231 232 static void clear_translation_pre_enabled(struct amd_iommu *iommu) 233 { 234 iommu->flags &= ~AMD_IOMMU_FLAG_TRANS_PRE_ENABLED; 235 } 236 237 static void init_translation_status(struct amd_iommu *iommu) 238 { 239 u64 ctrl; 240 241 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); 242 if (ctrl & (1<<CONTROL_IOMMU_EN)) 243 iommu->flags |= AMD_IOMMU_FLAG_TRANS_PRE_ENABLED; 244 } 245 246 int amd_iommu_get_num_iommus(void) 247 { 248 return amd_iommus_present; 249 } 250 251 bool amd_iommu_ht_range_ignore(void) 252 { 253 return check_feature2(FEATURE_HT_RANGE_IGNORE); 254 } 255 256 /* 257 * Iterate through all the IOMMUs to get common EFR 258 * masks among all IOMMUs and warn if found inconsistency. 259 */ 260 static __init void get_global_efr(void) 261 { 262 struct amd_iommu *iommu; 263 264 for_each_iommu(iommu) { 265 u64 tmp = iommu->features; 266 u64 tmp2 = iommu->features2; 267 268 if (list_is_first(&iommu->list, &amd_iommu_list)) { 269 amd_iommu_efr = tmp; 270 amd_iommu_efr2 = tmp2; 271 continue; 272 } 273 274 if (amd_iommu_efr == tmp && 275 amd_iommu_efr2 == tmp2) 276 continue; 277 278 pr_err(FW_BUG 279 "Found inconsistent EFR/EFR2 %#llx,%#llx (global %#llx,%#llx) on iommu%d (%04x:%02x:%02x.%01x).\n", 280 tmp, tmp2, amd_iommu_efr, amd_iommu_efr2, 281 iommu->index, iommu->pci_seg->id, 282 PCI_BUS_NUM(iommu->devid), PCI_SLOT(iommu->devid), 283 PCI_FUNC(iommu->devid)); 284 285 amd_iommu_efr &= tmp; 286 amd_iommu_efr2 &= tmp2; 287 } 288 289 pr_info("Using global IVHD EFR:%#llx, EFR2:%#llx\n", amd_iommu_efr, amd_iommu_efr2); 290 } 291 292 /* 293 * For IVHD type 0x11/0x40, EFR is also available via IVHD. 294 * Default to IVHD EFR since it is available sooner 295 * (i.e. before PCI init). 296 */ 297 static void __init early_iommu_features_init(struct amd_iommu *iommu, 298 struct ivhd_header *h) 299 { 300 if (amd_iommu_ivinfo & IOMMU_IVINFO_EFRSUP) { 301 iommu->features = h->efr_reg; 302 iommu->features2 = h->efr_reg2; 303 } 304 if (amd_iommu_ivinfo & IOMMU_IVINFO_DMA_REMAP) 305 amdr_ivrs_remap_support = true; 306 } 307 308 /* Access to l1 and l2 indexed register spaces */ 309 310 static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address) 311 { 312 u32 val; 313 314 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16)); 315 pci_read_config_dword(iommu->dev, 0xfc, &val); 316 return val; 317 } 318 319 static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val) 320 { 321 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31)); 322 pci_write_config_dword(iommu->dev, 0xfc, val); 323 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16)); 324 } 325 326 static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address) 327 { 328 u32 val; 329 330 pci_write_config_dword(iommu->dev, 0xf0, address); 331 pci_read_config_dword(iommu->dev, 0xf4, &val); 332 return val; 333 } 334 335 static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val) 336 { 337 pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8)); 338 pci_write_config_dword(iommu->dev, 0xf4, val); 339 } 340 341 /**************************************************************************** 342 * 343 * AMD IOMMU MMIO register space handling functions 344 * 345 * These functions are used to program the IOMMU device registers in 346 * MMIO space required for that driver. 347 * 348 ****************************************************************************/ 349 350 /* 351 * This function set the exclusion range in the IOMMU. DMA accesses to the 352 * exclusion range are passed through untranslated 353 */ 354 static void iommu_set_exclusion_range(struct amd_iommu *iommu) 355 { 356 u64 start = iommu->exclusion_start & PAGE_MASK; 357 u64 limit = (start + iommu->exclusion_length - 1) & PAGE_MASK; 358 u64 entry; 359 360 if (!iommu->exclusion_start) 361 return; 362 363 entry = start | MMIO_EXCL_ENABLE_MASK; 364 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, 365 &entry, sizeof(entry)); 366 367 entry = limit; 368 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, 369 &entry, sizeof(entry)); 370 } 371 372 static void iommu_set_cwwb_range(struct amd_iommu *iommu) 373 { 374 u64 start = iommu_virt_to_phys((void *)iommu->cmd_sem); 375 u64 entry = start & PM_ADDR_MASK; 376 377 if (!check_feature(FEATURE_SNP)) 378 return; 379 380 /* Note: 381 * Re-purpose Exclusion base/limit registers for Completion wait 382 * write-back base/limit. 383 */ 384 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, 385 &entry, sizeof(entry)); 386 387 /* Note: 388 * Default to 4 Kbytes, which can be specified by setting base 389 * address equal to the limit address. 390 */ 391 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, 392 &entry, sizeof(entry)); 393 } 394 395 /* Programs the physical address of the device table into the IOMMU hardware */ 396 static void iommu_set_device_table(struct amd_iommu *iommu) 397 { 398 u64 entry; 399 u32 dev_table_size = iommu->pci_seg->dev_table_size; 400 void *dev_table = (void *)get_dev_table(iommu); 401 402 BUG_ON(iommu->mmio_base == NULL); 403 404 entry = iommu_virt_to_phys(dev_table); 405 entry |= (dev_table_size >> 12) - 1; 406 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET, 407 &entry, sizeof(entry)); 408 } 409 410 static void iommu_feature_set(struct amd_iommu *iommu, u64 val, u64 mask, u8 shift) 411 { 412 u64 ctrl; 413 414 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); 415 mask <<= shift; 416 ctrl &= ~mask; 417 ctrl |= (val << shift) & mask; 418 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); 419 } 420 421 /* Generic functions to enable/disable certain features of the IOMMU. */ 422 void iommu_feature_enable(struct amd_iommu *iommu, u8 bit) 423 { 424 iommu_feature_set(iommu, 1ULL, 1ULL, bit); 425 } 426 427 static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit) 428 { 429 iommu_feature_set(iommu, 0ULL, 1ULL, bit); 430 } 431 432 /* Function to enable the hardware */ 433 static void iommu_enable(struct amd_iommu *iommu) 434 { 435 iommu_feature_enable(iommu, CONTROL_IOMMU_EN); 436 } 437 438 static void iommu_disable(struct amd_iommu *iommu) 439 { 440 if (!iommu->mmio_base) 441 return; 442 443 /* Disable command buffer */ 444 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); 445 446 /* Disable event logging and event interrupts */ 447 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN); 448 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN); 449 450 /* Disable IOMMU GA_LOG */ 451 iommu_feature_disable(iommu, CONTROL_GALOG_EN); 452 iommu_feature_disable(iommu, CONTROL_GAINT_EN); 453 454 /* Disable IOMMU PPR logging */ 455 iommu_feature_disable(iommu, CONTROL_PPRLOG_EN); 456 iommu_feature_disable(iommu, CONTROL_PPRINT_EN); 457 458 /* Disable IOMMU hardware itself */ 459 iommu_feature_disable(iommu, CONTROL_IOMMU_EN); 460 461 /* Clear IRTE cache disabling bit */ 462 iommu_feature_disable(iommu, CONTROL_IRTCACHEDIS); 463 } 464 465 /* 466 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in 467 * the system has one. 468 */ 469 static u8 __iomem * __init iommu_map_mmio_space(u64 address, u64 end) 470 { 471 if (!request_mem_region(address, end, "amd_iommu")) { 472 pr_err("Can not reserve memory region %llx-%llx for mmio\n", 473 address, end); 474 pr_err("This is a BIOS bug. Please contact your hardware vendor\n"); 475 return NULL; 476 } 477 478 return (u8 __iomem *)ioremap(address, end); 479 } 480 481 static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu) 482 { 483 if (iommu->mmio_base) 484 iounmap(iommu->mmio_base); 485 release_mem_region(iommu->mmio_phys, iommu->mmio_phys_end); 486 } 487 488 static inline u32 get_ivhd_header_size(struct ivhd_header *h) 489 { 490 u32 size = 0; 491 492 switch (h->type) { 493 case 0x10: 494 size = 24; 495 break; 496 case 0x11: 497 case 0x40: 498 size = 40; 499 break; 500 } 501 return size; 502 } 503 504 /**************************************************************************** 505 * 506 * The functions below belong to the first pass of AMD IOMMU ACPI table 507 * parsing. In this pass we try to find out the highest device id this 508 * code has to handle. Upon this information the size of the shared data 509 * structures is determined later. 510 * 511 ****************************************************************************/ 512 513 /* 514 * This function calculates the length of a given IVHD entry 515 */ 516 static inline int ivhd_entry_length(u8 *ivhd) 517 { 518 u32 type = ((struct ivhd_entry *)ivhd)->type; 519 520 if (type < 0x80) { 521 return 0x04 << (*ivhd >> 6); 522 } else if (type == IVHD_DEV_ACPI_HID) { 523 /* For ACPI_HID, offset 21 is uid len */ 524 return *((u8 *)ivhd + 21) + 22; 525 } 526 return 0; 527 } 528 529 /* 530 * After reading the highest device id from the IOMMU PCI capability header 531 * this function looks if there is a higher device id defined in the ACPI table 532 */ 533 static int __init find_last_devid_from_ivhd(struct ivhd_header *h) 534 { 535 u8 *p = (void *)h, *end = (void *)h; 536 struct ivhd_entry *dev; 537 int last_devid = -EINVAL; 538 539 u32 ivhd_size = get_ivhd_header_size(h); 540 541 if (!ivhd_size) { 542 pr_err("Unsupported IVHD type %#x\n", h->type); 543 return -EINVAL; 544 } 545 546 p += ivhd_size; 547 end += h->length; 548 549 while (p < end) { 550 dev = (struct ivhd_entry *)p; 551 switch (dev->type) { 552 case IVHD_DEV_ALL: 553 /* Use maximum BDF value for DEV_ALL */ 554 return 0xffff; 555 case IVHD_DEV_SELECT: 556 case IVHD_DEV_RANGE_END: 557 case IVHD_DEV_ALIAS: 558 case IVHD_DEV_EXT_SELECT: 559 /* all the above subfield types refer to device ids */ 560 if (dev->devid > last_devid) 561 last_devid = dev->devid; 562 break; 563 default: 564 break; 565 } 566 p += ivhd_entry_length(p); 567 } 568 569 WARN_ON(p != end); 570 571 return last_devid; 572 } 573 574 static int __init check_ivrs_checksum(struct acpi_table_header *table) 575 { 576 int i; 577 u8 checksum = 0, *p = (u8 *)table; 578 579 for (i = 0; i < table->length; ++i) 580 checksum += p[i]; 581 if (checksum != 0) { 582 /* ACPI table corrupt */ 583 pr_err(FW_BUG "IVRS invalid checksum\n"); 584 return -ENODEV; 585 } 586 587 return 0; 588 } 589 590 /* 591 * Iterate over all IVHD entries in the ACPI table and find the highest device 592 * id which we need to handle. This is the first of three functions which parse 593 * the ACPI table. So we check the checksum here. 594 */ 595 static int __init find_last_devid_acpi(struct acpi_table_header *table, u16 pci_seg) 596 { 597 u8 *p = (u8 *)table, *end = (u8 *)table; 598 struct ivhd_header *h; 599 int last_devid, last_bdf = 0; 600 601 p += IVRS_HEADER_LENGTH; 602 603 end += table->length; 604 while (p < end) { 605 h = (struct ivhd_header *)p; 606 if (h->pci_seg == pci_seg && 607 h->type == amd_iommu_target_ivhd_type) { 608 last_devid = find_last_devid_from_ivhd(h); 609 610 if (last_devid < 0) 611 return -EINVAL; 612 if (last_devid > last_bdf) 613 last_bdf = last_devid; 614 } 615 p += h->length; 616 } 617 WARN_ON(p != end); 618 619 return last_bdf; 620 } 621 622 /**************************************************************************** 623 * 624 * The following functions belong to the code path which parses the ACPI table 625 * the second time. In this ACPI parsing iteration we allocate IOMMU specific 626 * data structures, initialize the per PCI segment device/alias/rlookup table 627 * and also basically initialize the hardware. 628 * 629 ****************************************************************************/ 630 631 /* Allocate per PCI segment device table */ 632 static inline int __init alloc_dev_table(struct amd_iommu_pci_seg *pci_seg) 633 { 634 pci_seg->dev_table = iommu_alloc_pages_sz(GFP_KERNEL | GFP_DMA32, 635 pci_seg->dev_table_size); 636 if (!pci_seg->dev_table) 637 return -ENOMEM; 638 639 return 0; 640 } 641 642 static inline void free_dev_table(struct amd_iommu_pci_seg *pci_seg) 643 { 644 iommu_free_pages(pci_seg->dev_table); 645 pci_seg->dev_table = NULL; 646 } 647 648 /* Allocate per PCI segment IOMMU rlookup table. */ 649 static inline int __init alloc_rlookup_table(struct amd_iommu_pci_seg *pci_seg) 650 { 651 pci_seg->rlookup_table = kvcalloc(pci_seg->last_bdf + 1, 652 sizeof(*pci_seg->rlookup_table), 653 GFP_KERNEL); 654 if (pci_seg->rlookup_table == NULL) 655 return -ENOMEM; 656 657 return 0; 658 } 659 660 static inline void free_rlookup_table(struct amd_iommu_pci_seg *pci_seg) 661 { 662 kvfree(pci_seg->rlookup_table); 663 pci_seg->rlookup_table = NULL; 664 } 665 666 static inline int __init alloc_irq_lookup_table(struct amd_iommu_pci_seg *pci_seg) 667 { 668 pci_seg->irq_lookup_table = kvcalloc(pci_seg->last_bdf + 1, 669 sizeof(*pci_seg->irq_lookup_table), 670 GFP_KERNEL); 671 if (pci_seg->irq_lookup_table == NULL) 672 return -ENOMEM; 673 674 return 0; 675 } 676 677 static inline void free_irq_lookup_table(struct amd_iommu_pci_seg *pci_seg) 678 { 679 kvfree(pci_seg->irq_lookup_table); 680 pci_seg->irq_lookup_table = NULL; 681 } 682 683 static int __init alloc_alias_table(struct amd_iommu_pci_seg *pci_seg) 684 { 685 int i; 686 687 pci_seg->alias_table = kvmalloc_array(pci_seg->last_bdf + 1, 688 sizeof(*pci_seg->alias_table), 689 GFP_KERNEL); 690 if (!pci_seg->alias_table) 691 return -ENOMEM; 692 693 /* 694 * let all alias entries point to itself 695 */ 696 for (i = 0; i <= pci_seg->last_bdf; ++i) 697 pci_seg->alias_table[i] = i; 698 699 return 0; 700 } 701 702 static void __init free_alias_table(struct amd_iommu_pci_seg *pci_seg) 703 { 704 kvfree(pci_seg->alias_table); 705 pci_seg->alias_table = NULL; 706 } 707 708 /* 709 * Allocates the command buffer. This buffer is per AMD IOMMU. We can 710 * write commands to that buffer later and the IOMMU will execute them 711 * asynchronously 712 */ 713 static int __init alloc_command_buffer(struct amd_iommu *iommu) 714 { 715 iommu->cmd_buf = iommu_alloc_pages_sz(GFP_KERNEL, CMD_BUFFER_SIZE); 716 717 return iommu->cmd_buf ? 0 : -ENOMEM; 718 } 719 720 /* 721 * Interrupt handler has processed all pending events and adjusted head 722 * and tail pointer. Reset overflow mask and restart logging again. 723 */ 724 void amd_iommu_restart_log(struct amd_iommu *iommu, const char *evt_type, 725 u8 cntrl_intr, u8 cntrl_log, 726 u32 status_run_mask, u32 status_overflow_mask) 727 { 728 u32 status; 729 730 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); 731 if (status & status_run_mask) 732 return; 733 734 pr_info_ratelimited("IOMMU %s log restarting\n", evt_type); 735 736 iommu_feature_disable(iommu, cntrl_log); 737 iommu_feature_disable(iommu, cntrl_intr); 738 739 writel(status_overflow_mask, iommu->mmio_base + MMIO_STATUS_OFFSET); 740 741 iommu_feature_enable(iommu, cntrl_intr); 742 iommu_feature_enable(iommu, cntrl_log); 743 } 744 745 /* 746 * This function restarts event logging in case the IOMMU experienced 747 * an event log buffer overflow. 748 */ 749 void amd_iommu_restart_event_logging(struct amd_iommu *iommu) 750 { 751 amd_iommu_restart_log(iommu, "Event", CONTROL_EVT_INT_EN, 752 CONTROL_EVT_LOG_EN, MMIO_STATUS_EVT_RUN_MASK, 753 MMIO_STATUS_EVT_OVERFLOW_MASK); 754 } 755 756 /* 757 * This function restarts event logging in case the IOMMU experienced 758 * GA log overflow. 759 */ 760 void amd_iommu_restart_ga_log(struct amd_iommu *iommu) 761 { 762 amd_iommu_restart_log(iommu, "GA", CONTROL_GAINT_EN, 763 CONTROL_GALOG_EN, MMIO_STATUS_GALOG_RUN_MASK, 764 MMIO_STATUS_GALOG_OVERFLOW_MASK); 765 } 766 767 /* 768 * This function resets the command buffer if the IOMMU stopped fetching 769 * commands from it. 770 */ 771 static void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu) 772 { 773 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); 774 775 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); 776 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); 777 iommu->cmd_buf_head = 0; 778 iommu->cmd_buf_tail = 0; 779 780 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN); 781 } 782 783 /* 784 * This function writes the command buffer address to the hardware and 785 * enables it. 786 */ 787 static void iommu_enable_command_buffer(struct amd_iommu *iommu) 788 { 789 u64 entry; 790 791 BUG_ON(iommu->cmd_buf == NULL); 792 793 entry = iommu_virt_to_phys(iommu->cmd_buf); 794 entry |= MMIO_CMD_SIZE_512; 795 796 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET, 797 &entry, sizeof(entry)); 798 799 amd_iommu_reset_cmd_buffer(iommu); 800 } 801 802 /* 803 * This function disables the command buffer 804 */ 805 static void iommu_disable_command_buffer(struct amd_iommu *iommu) 806 { 807 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); 808 } 809 810 static void __init free_command_buffer(struct amd_iommu *iommu) 811 { 812 iommu_free_pages(iommu->cmd_buf); 813 } 814 815 void *__init iommu_alloc_4k_pages(struct amd_iommu *iommu, gfp_t gfp, 816 size_t size) 817 { 818 void *buf; 819 820 size = PAGE_ALIGN(size); 821 buf = iommu_alloc_pages_sz(gfp, size); 822 if (!buf) 823 return NULL; 824 if (check_feature(FEATURE_SNP) && 825 set_memory_4k((unsigned long)buf, size / PAGE_SIZE)) { 826 iommu_free_pages(buf); 827 return NULL; 828 } 829 830 return buf; 831 } 832 833 /* allocates the memory where the IOMMU will log its events to */ 834 static int __init alloc_event_buffer(struct amd_iommu *iommu) 835 { 836 iommu->evt_buf = iommu_alloc_4k_pages(iommu, GFP_KERNEL, 837 EVT_BUFFER_SIZE); 838 839 return iommu->evt_buf ? 0 : -ENOMEM; 840 } 841 842 static void iommu_enable_event_buffer(struct amd_iommu *iommu) 843 { 844 u64 entry; 845 846 BUG_ON(iommu->evt_buf == NULL); 847 848 entry = iommu_virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK; 849 850 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET, 851 &entry, sizeof(entry)); 852 853 /* set head and tail to zero manually */ 854 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); 855 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); 856 857 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN); 858 } 859 860 /* 861 * This function disables the event log buffer 862 */ 863 static void iommu_disable_event_buffer(struct amd_iommu *iommu) 864 { 865 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN); 866 } 867 868 static void __init free_event_buffer(struct amd_iommu *iommu) 869 { 870 iommu_free_pages(iommu->evt_buf); 871 } 872 873 static void free_ga_log(struct amd_iommu *iommu) 874 { 875 #ifdef CONFIG_IRQ_REMAP 876 iommu_free_pages(iommu->ga_log); 877 iommu_free_pages(iommu->ga_log_tail); 878 #endif 879 } 880 881 #ifdef CONFIG_IRQ_REMAP 882 static int iommu_ga_log_enable(struct amd_iommu *iommu) 883 { 884 u32 status, i; 885 u64 entry; 886 887 if (!iommu->ga_log) 888 return -EINVAL; 889 890 entry = iommu_virt_to_phys(iommu->ga_log) | GA_LOG_SIZE_512; 891 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_BASE_OFFSET, 892 &entry, sizeof(entry)); 893 entry = (iommu_virt_to_phys(iommu->ga_log_tail) & 894 (BIT_ULL(52)-1)) & ~7ULL; 895 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_TAIL_OFFSET, 896 &entry, sizeof(entry)); 897 writel(0x00, iommu->mmio_base + MMIO_GA_HEAD_OFFSET); 898 writel(0x00, iommu->mmio_base + MMIO_GA_TAIL_OFFSET); 899 900 901 iommu_feature_enable(iommu, CONTROL_GAINT_EN); 902 iommu_feature_enable(iommu, CONTROL_GALOG_EN); 903 904 for (i = 0; i < MMIO_STATUS_TIMEOUT; ++i) { 905 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); 906 if (status & (MMIO_STATUS_GALOG_RUN_MASK)) 907 break; 908 udelay(10); 909 } 910 911 if (WARN_ON(i >= MMIO_STATUS_TIMEOUT)) 912 return -EINVAL; 913 914 return 0; 915 } 916 917 static int iommu_init_ga_log(struct amd_iommu *iommu) 918 { 919 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) 920 return 0; 921 922 iommu->ga_log = iommu_alloc_pages_sz(GFP_KERNEL, GA_LOG_SIZE); 923 if (!iommu->ga_log) 924 goto err_out; 925 926 iommu->ga_log_tail = iommu_alloc_pages_sz(GFP_KERNEL, 8); 927 if (!iommu->ga_log_tail) 928 goto err_out; 929 930 return 0; 931 err_out: 932 free_ga_log(iommu); 933 return -EINVAL; 934 } 935 #endif /* CONFIG_IRQ_REMAP */ 936 937 static int __init alloc_cwwb_sem(struct amd_iommu *iommu) 938 { 939 iommu->cmd_sem = iommu_alloc_4k_pages(iommu, GFP_KERNEL, 1); 940 941 return iommu->cmd_sem ? 0 : -ENOMEM; 942 } 943 944 static void __init free_cwwb_sem(struct amd_iommu *iommu) 945 { 946 if (iommu->cmd_sem) 947 iommu_free_pages((void *)iommu->cmd_sem); 948 } 949 950 static void iommu_enable_xt(struct amd_iommu *iommu) 951 { 952 #ifdef CONFIG_IRQ_REMAP 953 /* 954 * XT mode (32-bit APIC destination ID) requires 955 * GA mode (128-bit IRTE support) as a prerequisite. 956 */ 957 if (AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir) && 958 amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE) 959 iommu_feature_enable(iommu, CONTROL_XT_EN); 960 #endif /* CONFIG_IRQ_REMAP */ 961 } 962 963 static void iommu_enable_gt(struct amd_iommu *iommu) 964 { 965 if (!check_feature(FEATURE_GT)) 966 return; 967 968 iommu_feature_enable(iommu, CONTROL_GT_EN); 969 } 970 971 /* sets a specific bit in the device table entry. */ 972 static void set_dte_bit(struct dev_table_entry *dte, u8 bit) 973 { 974 int i = (bit >> 6) & 0x03; 975 int _bit = bit & 0x3f; 976 977 dte->data[i] |= (1UL << _bit); 978 } 979 980 static bool __copy_device_table(struct amd_iommu *iommu) 981 { 982 u64 int_ctl, int_tab_len, entry = 0; 983 struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg; 984 struct dev_table_entry *old_devtb = NULL; 985 u32 lo, hi, devid, old_devtb_size; 986 phys_addr_t old_devtb_phys; 987 u16 dom_id, dte_v, irq_v; 988 u64 tmp; 989 990 /* Each IOMMU use separate device table with the same size */ 991 lo = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET); 992 hi = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET + 4); 993 entry = (((u64) hi) << 32) + lo; 994 995 old_devtb_size = ((entry & ~PAGE_MASK) + 1) << 12; 996 if (old_devtb_size != pci_seg->dev_table_size) { 997 pr_err("The device table size of IOMMU:%d is not expected!\n", 998 iommu->index); 999 return false; 1000 } 1001 1002 /* 1003 * When SME is enabled in the first kernel, the entry includes the 1004 * memory encryption mask(sme_me_mask), we must remove the memory 1005 * encryption mask to obtain the true physical address in kdump kernel. 1006 */ 1007 old_devtb_phys = __sme_clr(entry) & PAGE_MASK; 1008 1009 if (old_devtb_phys >= 0x100000000ULL) { 1010 pr_err("The address of old device table is above 4G, not trustworthy!\n"); 1011 return false; 1012 } 1013 old_devtb = (cc_platform_has(CC_ATTR_HOST_MEM_ENCRYPT) && is_kdump_kernel()) 1014 ? (__force void *)ioremap_encrypted(old_devtb_phys, 1015 pci_seg->dev_table_size) 1016 : memremap(old_devtb_phys, pci_seg->dev_table_size, MEMREMAP_WB); 1017 1018 if (!old_devtb) 1019 return false; 1020 1021 pci_seg->old_dev_tbl_cpy = iommu_alloc_pages_sz( 1022 GFP_KERNEL | GFP_DMA32, pci_seg->dev_table_size); 1023 if (pci_seg->old_dev_tbl_cpy == NULL) { 1024 pr_err("Failed to allocate memory for copying old device table!\n"); 1025 memunmap(old_devtb); 1026 return false; 1027 } 1028 1029 for (devid = 0; devid <= pci_seg->last_bdf; ++devid) { 1030 pci_seg->old_dev_tbl_cpy[devid] = old_devtb[devid]; 1031 dom_id = old_devtb[devid].data[1] & DEV_DOMID_MASK; 1032 dte_v = old_devtb[devid].data[0] & DTE_FLAG_V; 1033 1034 if (dte_v && dom_id) { 1035 pci_seg->old_dev_tbl_cpy[devid].data[0] = old_devtb[devid].data[0]; 1036 pci_seg->old_dev_tbl_cpy[devid].data[1] = old_devtb[devid].data[1]; 1037 /* Reserve the Domain IDs used by previous kernel */ 1038 if (ida_alloc_range(&pdom_ids, dom_id, dom_id, GFP_ATOMIC) != dom_id) { 1039 pr_err("Failed to reserve domain ID 0x%x\n", dom_id); 1040 memunmap(old_devtb); 1041 return false; 1042 } 1043 /* If gcr3 table existed, mask it out */ 1044 if (old_devtb[devid].data[0] & DTE_FLAG_GV) { 1045 tmp = (DTE_GCR3_30_15 | DTE_GCR3_51_31); 1046 pci_seg->old_dev_tbl_cpy[devid].data[1] &= ~tmp; 1047 tmp = (DTE_GCR3_14_12 | DTE_FLAG_GV); 1048 pci_seg->old_dev_tbl_cpy[devid].data[0] &= ~tmp; 1049 } 1050 } 1051 1052 irq_v = old_devtb[devid].data[2] & DTE_IRQ_REMAP_ENABLE; 1053 int_ctl = old_devtb[devid].data[2] & DTE_IRQ_REMAP_INTCTL_MASK; 1054 int_tab_len = old_devtb[devid].data[2] & DTE_INTTABLEN_MASK; 1055 if (irq_v && (int_ctl || int_tab_len)) { 1056 if ((int_ctl != DTE_IRQ_REMAP_INTCTL) || 1057 (int_tab_len != DTE_INTTABLEN_512 && 1058 int_tab_len != DTE_INTTABLEN_2K)) { 1059 pr_err("Wrong old irq remapping flag: %#x\n", devid); 1060 memunmap(old_devtb); 1061 return false; 1062 } 1063 1064 pci_seg->old_dev_tbl_cpy[devid].data[2] = old_devtb[devid].data[2]; 1065 } 1066 } 1067 memunmap(old_devtb); 1068 1069 return true; 1070 } 1071 1072 static bool copy_device_table(void) 1073 { 1074 struct amd_iommu *iommu; 1075 struct amd_iommu_pci_seg *pci_seg; 1076 1077 if (!amd_iommu_pre_enabled) 1078 return false; 1079 1080 pr_warn("Translation is already enabled - trying to copy translation structures\n"); 1081 1082 /* 1083 * All IOMMUs within PCI segment shares common device table. 1084 * Hence copy device table only once per PCI segment. 1085 */ 1086 for_each_pci_segment(pci_seg) { 1087 for_each_iommu(iommu) { 1088 if (pci_seg->id != iommu->pci_seg->id) 1089 continue; 1090 if (!__copy_device_table(iommu)) 1091 return false; 1092 break; 1093 } 1094 } 1095 1096 return true; 1097 } 1098 1099 struct dev_table_entry *amd_iommu_get_ivhd_dte_flags(u16 segid, u16 devid) 1100 { 1101 struct ivhd_dte_flags *e; 1102 unsigned int best_len = UINT_MAX; 1103 struct dev_table_entry *dte = NULL; 1104 1105 for_each_ivhd_dte_flags(e) { 1106 /* 1107 * Need to go through the whole list to find the smallest range, 1108 * which contains the devid. 1109 */ 1110 if ((e->segid == segid) && 1111 (e->devid_first <= devid) && (devid <= e->devid_last)) { 1112 unsigned int len = e->devid_last - e->devid_first; 1113 1114 if (len < best_len) { 1115 dte = &(e->dte); 1116 best_len = len; 1117 } 1118 } 1119 } 1120 return dte; 1121 } 1122 1123 static bool search_ivhd_dte_flags(u16 segid, u16 first, u16 last) 1124 { 1125 struct ivhd_dte_flags *e; 1126 1127 for_each_ivhd_dte_flags(e) { 1128 if ((e->segid == segid) && 1129 (e->devid_first == first) && 1130 (e->devid_last == last)) 1131 return true; 1132 } 1133 return false; 1134 } 1135 1136 /* 1137 * This function takes the device specific flags read from the ACPI 1138 * table and sets up the device table entry with that information 1139 */ 1140 static void __init 1141 set_dev_entry_from_acpi_range(struct amd_iommu *iommu, u16 first, u16 last, 1142 u32 flags, u32 ext_flags) 1143 { 1144 int i; 1145 struct dev_table_entry dte = {}; 1146 1147 /* Parse IVHD DTE setting flags and store information */ 1148 if (flags) { 1149 struct ivhd_dte_flags *d; 1150 1151 if (search_ivhd_dte_flags(iommu->pci_seg->id, first, last)) 1152 return; 1153 1154 d = kzalloc(sizeof(struct ivhd_dte_flags), GFP_KERNEL); 1155 if (!d) 1156 return; 1157 1158 pr_debug("%s: devid range %#x:%#x\n", __func__, first, last); 1159 1160 if (flags & ACPI_DEVFLAG_INITPASS) 1161 set_dte_bit(&dte, DEV_ENTRY_INIT_PASS); 1162 if (flags & ACPI_DEVFLAG_EXTINT) 1163 set_dte_bit(&dte, DEV_ENTRY_EINT_PASS); 1164 if (flags & ACPI_DEVFLAG_NMI) 1165 set_dte_bit(&dte, DEV_ENTRY_NMI_PASS); 1166 if (flags & ACPI_DEVFLAG_SYSMGT1) 1167 set_dte_bit(&dte, DEV_ENTRY_SYSMGT1); 1168 if (flags & ACPI_DEVFLAG_SYSMGT2) 1169 set_dte_bit(&dte, DEV_ENTRY_SYSMGT2); 1170 if (flags & ACPI_DEVFLAG_LINT0) 1171 set_dte_bit(&dte, DEV_ENTRY_LINT0_PASS); 1172 if (flags & ACPI_DEVFLAG_LINT1) 1173 set_dte_bit(&dte, DEV_ENTRY_LINT1_PASS); 1174 1175 /* Apply erratum 63, which needs info in initial_dte */ 1176 if (FIELD_GET(DTE_DATA1_SYSMGT_MASK, dte.data[1]) == 0x1) 1177 dte.data[0] |= DTE_FLAG_IW; 1178 1179 memcpy(&d->dte, &dte, sizeof(dte)); 1180 d->segid = iommu->pci_seg->id; 1181 d->devid_first = first; 1182 d->devid_last = last; 1183 list_add_tail(&d->list, &amd_ivhd_dev_flags_list); 1184 } 1185 1186 for (i = first; i <= last; i++) { 1187 if (flags) { 1188 struct dev_table_entry *dev_table = get_dev_table(iommu); 1189 1190 memcpy(&dev_table[i], &dte, sizeof(dte)); 1191 } 1192 amd_iommu_set_rlookup_table(iommu, i); 1193 } 1194 } 1195 1196 static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu, 1197 u16 devid, u32 flags, u32 ext_flags) 1198 { 1199 set_dev_entry_from_acpi_range(iommu, devid, devid, flags, ext_flags); 1200 } 1201 1202 int __init add_special_device(u8 type, u8 id, u32 *devid, bool cmd_line) 1203 { 1204 struct devid_map *entry; 1205 struct list_head *list; 1206 1207 if (type == IVHD_SPECIAL_IOAPIC) 1208 list = &ioapic_map; 1209 else if (type == IVHD_SPECIAL_HPET) 1210 list = &hpet_map; 1211 else 1212 return -EINVAL; 1213 1214 list_for_each_entry(entry, list, list) { 1215 if (!(entry->id == id && entry->cmd_line)) 1216 continue; 1217 1218 pr_info("Command-line override present for %s id %d - ignoring\n", 1219 type == IVHD_SPECIAL_IOAPIC ? "IOAPIC" : "HPET", id); 1220 1221 *devid = entry->devid; 1222 1223 return 0; 1224 } 1225 1226 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 1227 if (!entry) 1228 return -ENOMEM; 1229 1230 entry->id = id; 1231 entry->devid = *devid; 1232 entry->cmd_line = cmd_line; 1233 1234 list_add_tail(&entry->list, list); 1235 1236 return 0; 1237 } 1238 1239 static int __init add_acpi_hid_device(u8 *hid, u8 *uid, u32 *devid, 1240 bool cmd_line) 1241 { 1242 struct acpihid_map_entry *entry; 1243 struct list_head *list = &acpihid_map; 1244 1245 list_for_each_entry(entry, list, list) { 1246 if (strcmp(entry->hid, hid) || 1247 (*uid && *entry->uid && strcmp(entry->uid, uid)) || 1248 !entry->cmd_line) 1249 continue; 1250 1251 pr_info("Command-line override for hid:%s uid:%s\n", 1252 hid, uid); 1253 *devid = entry->devid; 1254 return 0; 1255 } 1256 1257 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 1258 if (!entry) 1259 return -ENOMEM; 1260 1261 memcpy(entry->uid, uid, strlen(uid)); 1262 memcpy(entry->hid, hid, strlen(hid)); 1263 entry->devid = *devid; 1264 entry->cmd_line = cmd_line; 1265 entry->root_devid = (entry->devid & (~0x7)); 1266 1267 pr_info("%s, add hid:%s, uid:%s, rdevid:%#x\n", 1268 entry->cmd_line ? "cmd" : "ivrs", 1269 entry->hid, entry->uid, entry->root_devid); 1270 1271 list_add_tail(&entry->list, list); 1272 return 0; 1273 } 1274 1275 static int __init add_early_maps(void) 1276 { 1277 int i, ret; 1278 1279 for (i = 0; i < early_ioapic_map_size; ++i) { 1280 ret = add_special_device(IVHD_SPECIAL_IOAPIC, 1281 early_ioapic_map[i].id, 1282 &early_ioapic_map[i].devid, 1283 early_ioapic_map[i].cmd_line); 1284 if (ret) 1285 return ret; 1286 } 1287 1288 for (i = 0; i < early_hpet_map_size; ++i) { 1289 ret = add_special_device(IVHD_SPECIAL_HPET, 1290 early_hpet_map[i].id, 1291 &early_hpet_map[i].devid, 1292 early_hpet_map[i].cmd_line); 1293 if (ret) 1294 return ret; 1295 } 1296 1297 for (i = 0; i < early_acpihid_map_size; ++i) { 1298 ret = add_acpi_hid_device(early_acpihid_map[i].hid, 1299 early_acpihid_map[i].uid, 1300 &early_acpihid_map[i].devid, 1301 early_acpihid_map[i].cmd_line); 1302 if (ret) 1303 return ret; 1304 } 1305 1306 return 0; 1307 } 1308 1309 /* 1310 * Takes a pointer to an AMD IOMMU entry in the ACPI table and 1311 * initializes the hardware and our data structures with it. 1312 */ 1313 static int __init init_iommu_from_acpi(struct amd_iommu *iommu, 1314 struct ivhd_header *h) 1315 { 1316 u8 *p = (u8 *)h; 1317 u8 *end = p, flags = 0; 1318 u16 devid = 0, devid_start = 0, devid_to = 0, seg_id; 1319 u32 dev_i, ext_flags = 0; 1320 bool alias = false; 1321 struct ivhd_entry *e; 1322 struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg; 1323 u32 ivhd_size; 1324 int ret; 1325 1326 1327 ret = add_early_maps(); 1328 if (ret) 1329 return ret; 1330 1331 amd_iommu_apply_ivrs_quirks(); 1332 1333 /* 1334 * First save the recommended feature enable bits from ACPI 1335 */ 1336 iommu->acpi_flags = h->flags; 1337 1338 /* 1339 * Done. Now parse the device entries 1340 */ 1341 ivhd_size = get_ivhd_header_size(h); 1342 if (!ivhd_size) { 1343 pr_err("Unsupported IVHD type %#x\n", h->type); 1344 return -EINVAL; 1345 } 1346 1347 p += ivhd_size; 1348 1349 end += h->length; 1350 1351 1352 while (p < end) { 1353 e = (struct ivhd_entry *)p; 1354 seg_id = pci_seg->id; 1355 1356 switch (e->type) { 1357 case IVHD_DEV_ALL: 1358 1359 DUMP_printk(" DEV_ALL\t\t\tsetting: %#02x\n", e->flags); 1360 set_dev_entry_from_acpi_range(iommu, 0, pci_seg->last_bdf, e->flags, 0); 1361 break; 1362 case IVHD_DEV_SELECT: 1363 1364 DUMP_printk(" DEV_SELECT\t\t\tdevid: %04x:%02x:%02x.%x flags: %#02x\n", 1365 seg_id, PCI_BUS_NUM(e->devid), 1366 PCI_SLOT(e->devid), 1367 PCI_FUNC(e->devid), 1368 e->flags); 1369 1370 devid = e->devid; 1371 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); 1372 break; 1373 case IVHD_DEV_SELECT_RANGE_START: 1374 1375 DUMP_printk(" DEV_SELECT_RANGE_START\tdevid: %04x:%02x:%02x.%x flags: %#02x\n", 1376 seg_id, PCI_BUS_NUM(e->devid), 1377 PCI_SLOT(e->devid), 1378 PCI_FUNC(e->devid), 1379 e->flags); 1380 1381 devid_start = e->devid; 1382 flags = e->flags; 1383 ext_flags = 0; 1384 alias = false; 1385 break; 1386 case IVHD_DEV_ALIAS: 1387 1388 DUMP_printk(" DEV_ALIAS\t\t\tdevid: %04x:%02x:%02x.%x flags: %#02x devid_to: %02x:%02x.%x\n", 1389 seg_id, PCI_BUS_NUM(e->devid), 1390 PCI_SLOT(e->devid), 1391 PCI_FUNC(e->devid), 1392 e->flags, 1393 PCI_BUS_NUM(e->ext >> 8), 1394 PCI_SLOT(e->ext >> 8), 1395 PCI_FUNC(e->ext >> 8)); 1396 1397 devid = e->devid; 1398 devid_to = e->ext >> 8; 1399 set_dev_entry_from_acpi(iommu, devid , e->flags, 0); 1400 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0); 1401 pci_seg->alias_table[devid] = devid_to; 1402 break; 1403 case IVHD_DEV_ALIAS_RANGE: 1404 1405 DUMP_printk(" DEV_ALIAS_RANGE\t\tdevid: %04x:%02x:%02x.%x flags: %#02x devid_to: %04x:%02x:%02x.%x\n", 1406 seg_id, PCI_BUS_NUM(e->devid), 1407 PCI_SLOT(e->devid), 1408 PCI_FUNC(e->devid), 1409 e->flags, 1410 seg_id, PCI_BUS_NUM(e->ext >> 8), 1411 PCI_SLOT(e->ext >> 8), 1412 PCI_FUNC(e->ext >> 8)); 1413 1414 devid_start = e->devid; 1415 flags = e->flags; 1416 devid_to = e->ext >> 8; 1417 ext_flags = 0; 1418 alias = true; 1419 break; 1420 case IVHD_DEV_EXT_SELECT: 1421 1422 DUMP_printk(" DEV_EXT_SELECT\t\tdevid: %04x:%02x:%02x.%x flags: %#02x ext: %08x\n", 1423 seg_id, PCI_BUS_NUM(e->devid), 1424 PCI_SLOT(e->devid), 1425 PCI_FUNC(e->devid), 1426 e->flags, e->ext); 1427 1428 devid = e->devid; 1429 set_dev_entry_from_acpi(iommu, devid, e->flags, 1430 e->ext); 1431 break; 1432 case IVHD_DEV_EXT_SELECT_RANGE: 1433 1434 DUMP_printk(" DEV_EXT_SELECT_RANGE\tdevid: %04x:%02x:%02x.%x flags: %#02x ext: %08x\n", 1435 seg_id, PCI_BUS_NUM(e->devid), 1436 PCI_SLOT(e->devid), 1437 PCI_FUNC(e->devid), 1438 e->flags, e->ext); 1439 1440 devid_start = e->devid; 1441 flags = e->flags; 1442 ext_flags = e->ext; 1443 alias = false; 1444 break; 1445 case IVHD_DEV_RANGE_END: 1446 1447 DUMP_printk(" DEV_RANGE_END\t\tdevid: %04x:%02x:%02x.%x\n", 1448 seg_id, PCI_BUS_NUM(e->devid), 1449 PCI_SLOT(e->devid), 1450 PCI_FUNC(e->devid)); 1451 1452 devid = e->devid; 1453 for (dev_i = devid_start; dev_i <= devid; ++dev_i) { 1454 if (alias) 1455 pci_seg->alias_table[dev_i] = devid_to; 1456 } 1457 set_dev_entry_from_acpi_range(iommu, devid_start, devid, flags, ext_flags); 1458 set_dev_entry_from_acpi(iommu, devid_to, flags, ext_flags); 1459 break; 1460 case IVHD_DEV_SPECIAL: { 1461 u8 handle, type; 1462 const char *var; 1463 u32 devid; 1464 int ret; 1465 1466 handle = e->ext & 0xff; 1467 devid = PCI_SEG_DEVID_TO_SBDF(seg_id, (e->ext >> 8)); 1468 type = (e->ext >> 24) & 0xff; 1469 1470 if (type == IVHD_SPECIAL_IOAPIC) 1471 var = "IOAPIC"; 1472 else if (type == IVHD_SPECIAL_HPET) 1473 var = "HPET"; 1474 else 1475 var = "UNKNOWN"; 1476 1477 DUMP_printk(" DEV_SPECIAL(%s[%d])\t\tdevid: %04x:%02x:%02x.%x, flags: %#02x\n", 1478 var, (int)handle, 1479 seg_id, PCI_BUS_NUM(devid), 1480 PCI_SLOT(devid), 1481 PCI_FUNC(devid), 1482 e->flags); 1483 1484 ret = add_special_device(type, handle, &devid, false); 1485 if (ret) 1486 return ret; 1487 1488 /* 1489 * add_special_device might update the devid in case a 1490 * command-line override is present. So call 1491 * set_dev_entry_from_acpi after add_special_device. 1492 */ 1493 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); 1494 1495 break; 1496 } 1497 case IVHD_DEV_ACPI_HID: { 1498 u32 devid; 1499 u8 hid[ACPIHID_HID_LEN]; 1500 u8 uid[ACPIHID_UID_LEN]; 1501 int ret; 1502 1503 if (h->type != 0x40) { 1504 pr_err(FW_BUG "Invalid IVHD device type %#x\n", 1505 e->type); 1506 break; 1507 } 1508 1509 BUILD_BUG_ON(sizeof(e->ext_hid) != ACPIHID_HID_LEN - 1); 1510 memcpy(hid, &e->ext_hid, ACPIHID_HID_LEN - 1); 1511 hid[ACPIHID_HID_LEN - 1] = '\0'; 1512 1513 if (!(*hid)) { 1514 pr_err(FW_BUG "Invalid HID.\n"); 1515 break; 1516 } 1517 1518 uid[0] = '\0'; 1519 switch (e->uidf) { 1520 case UID_NOT_PRESENT: 1521 1522 if (e->uidl != 0) 1523 pr_warn(FW_BUG "Invalid UID length.\n"); 1524 1525 break; 1526 case UID_IS_INTEGER: 1527 1528 sprintf(uid, "%d", e->uid); 1529 1530 break; 1531 case UID_IS_CHARACTER: 1532 1533 memcpy(uid, &e->uid, e->uidl); 1534 uid[e->uidl] = '\0'; 1535 1536 break; 1537 default: 1538 break; 1539 } 1540 1541 devid = PCI_SEG_DEVID_TO_SBDF(seg_id, e->devid); 1542 DUMP_printk(" DEV_ACPI_HID(%s[%s])\t\tdevid: %04x:%02x:%02x.%x, flags: %#02x\n", 1543 hid, uid, seg_id, 1544 PCI_BUS_NUM(devid), 1545 PCI_SLOT(devid), 1546 PCI_FUNC(devid), 1547 e->flags); 1548 1549 flags = e->flags; 1550 1551 ret = add_acpi_hid_device(hid, uid, &devid, false); 1552 if (ret) 1553 return ret; 1554 1555 /* 1556 * add_special_device might update the devid in case a 1557 * command-line override is present. So call 1558 * set_dev_entry_from_acpi after add_special_device. 1559 */ 1560 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); 1561 1562 break; 1563 } 1564 default: 1565 break; 1566 } 1567 1568 p += ivhd_entry_length(p); 1569 } 1570 1571 return 0; 1572 } 1573 1574 /* Allocate PCI segment data structure */ 1575 static struct amd_iommu_pci_seg *__init alloc_pci_segment(u16 id, 1576 struct acpi_table_header *ivrs_base) 1577 { 1578 struct amd_iommu_pci_seg *pci_seg; 1579 int last_bdf; 1580 1581 /* 1582 * First parse ACPI tables to find the largest Bus/Dev/Func we need to 1583 * handle in this PCI segment. Upon this information the shared data 1584 * structures for the PCI segments in the system will be allocated. 1585 */ 1586 last_bdf = find_last_devid_acpi(ivrs_base, id); 1587 if (last_bdf < 0) 1588 return NULL; 1589 1590 pci_seg = kzalloc(sizeof(struct amd_iommu_pci_seg), GFP_KERNEL); 1591 if (pci_seg == NULL) 1592 return NULL; 1593 1594 pci_seg->last_bdf = last_bdf; 1595 DUMP_printk("PCI segment : 0x%0x, last bdf : 0x%04x\n", id, last_bdf); 1596 pci_seg->dev_table_size = 1597 max(roundup_pow_of_two((last_bdf + 1) * DEV_TABLE_ENTRY_SIZE), 1598 SZ_4K); 1599 1600 pci_seg->id = id; 1601 init_llist_head(&pci_seg->dev_data_list); 1602 INIT_LIST_HEAD(&pci_seg->unity_map); 1603 list_add_tail(&pci_seg->list, &amd_iommu_pci_seg_list); 1604 1605 if (alloc_dev_table(pci_seg)) 1606 return NULL; 1607 if (alloc_alias_table(pci_seg)) 1608 return NULL; 1609 if (alloc_rlookup_table(pci_seg)) 1610 return NULL; 1611 1612 return pci_seg; 1613 } 1614 1615 static struct amd_iommu_pci_seg *__init get_pci_segment(u16 id, 1616 struct acpi_table_header *ivrs_base) 1617 { 1618 struct amd_iommu_pci_seg *pci_seg; 1619 1620 for_each_pci_segment(pci_seg) { 1621 if (pci_seg->id == id) 1622 return pci_seg; 1623 } 1624 1625 return alloc_pci_segment(id, ivrs_base); 1626 } 1627 1628 static void __init free_pci_segments(void) 1629 { 1630 struct amd_iommu_pci_seg *pci_seg, *next; 1631 1632 for_each_pci_segment_safe(pci_seg, next) { 1633 list_del(&pci_seg->list); 1634 free_irq_lookup_table(pci_seg); 1635 free_rlookup_table(pci_seg); 1636 free_alias_table(pci_seg); 1637 free_dev_table(pci_seg); 1638 kfree(pci_seg); 1639 } 1640 } 1641 1642 static void __init free_sysfs(struct amd_iommu *iommu) 1643 { 1644 if (iommu->iommu.dev) { 1645 iommu_device_unregister(&iommu->iommu); 1646 iommu_device_sysfs_remove(&iommu->iommu); 1647 } 1648 } 1649 1650 static void __init free_iommu_one(struct amd_iommu *iommu) 1651 { 1652 free_sysfs(iommu); 1653 free_cwwb_sem(iommu); 1654 free_command_buffer(iommu); 1655 free_event_buffer(iommu); 1656 amd_iommu_free_ppr_log(iommu); 1657 free_ga_log(iommu); 1658 iommu_unmap_mmio_space(iommu); 1659 amd_iommu_iopf_uninit(iommu); 1660 } 1661 1662 static void __init free_iommu_all(void) 1663 { 1664 struct amd_iommu *iommu, *next; 1665 1666 for_each_iommu_safe(iommu, next) { 1667 list_del(&iommu->list); 1668 free_iommu_one(iommu); 1669 kfree(iommu); 1670 } 1671 } 1672 1673 /* 1674 * Family15h Model 10h-1fh erratum 746 (IOMMU Logging May Stall Translations) 1675 * Workaround: 1676 * BIOS should disable L2B micellaneous clock gating by setting 1677 * L2_L2B_CK_GATE_CONTROL[CKGateL2BMiscDisable](D0F2xF4_x90[2]) = 1b 1678 */ 1679 static void amd_iommu_erratum_746_workaround(struct amd_iommu *iommu) 1680 { 1681 u32 value; 1682 1683 if ((boot_cpu_data.x86 != 0x15) || 1684 (boot_cpu_data.x86_model < 0x10) || 1685 (boot_cpu_data.x86_model > 0x1f)) 1686 return; 1687 1688 pci_write_config_dword(iommu->dev, 0xf0, 0x90); 1689 pci_read_config_dword(iommu->dev, 0xf4, &value); 1690 1691 if (value & BIT(2)) 1692 return; 1693 1694 /* Select NB indirect register 0x90 and enable writing */ 1695 pci_write_config_dword(iommu->dev, 0xf0, 0x90 | (1 << 8)); 1696 1697 pci_write_config_dword(iommu->dev, 0xf4, value | 0x4); 1698 pci_info(iommu->dev, "Applying erratum 746 workaround\n"); 1699 1700 /* Clear the enable writing bit */ 1701 pci_write_config_dword(iommu->dev, 0xf0, 0x90); 1702 } 1703 1704 /* 1705 * Family15h Model 30h-3fh (IOMMU Mishandles ATS Write Permission) 1706 * Workaround: 1707 * BIOS should enable ATS write permission check by setting 1708 * L2_DEBUG_3[AtsIgnoreIWDis](D0F2xF4_x47[0]) = 1b 1709 */ 1710 static void amd_iommu_ats_write_check_workaround(struct amd_iommu *iommu) 1711 { 1712 u32 value; 1713 1714 if ((boot_cpu_data.x86 != 0x15) || 1715 (boot_cpu_data.x86_model < 0x30) || 1716 (boot_cpu_data.x86_model > 0x3f)) 1717 return; 1718 1719 /* Test L2_DEBUG_3[AtsIgnoreIWDis] == 1 */ 1720 value = iommu_read_l2(iommu, 0x47); 1721 1722 if (value & BIT(0)) 1723 return; 1724 1725 /* Set L2_DEBUG_3[AtsIgnoreIWDis] = 1 */ 1726 iommu_write_l2(iommu, 0x47, value | BIT(0)); 1727 1728 pci_info(iommu->dev, "Applying ATS write check workaround\n"); 1729 } 1730 1731 /* 1732 * This function glues the initialization function for one IOMMU 1733 * together and also allocates the command buffer and programs the 1734 * hardware. It does NOT enable the IOMMU. This is done afterwards. 1735 */ 1736 static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h, 1737 struct acpi_table_header *ivrs_base) 1738 { 1739 struct amd_iommu_pci_seg *pci_seg; 1740 1741 pci_seg = get_pci_segment(h->pci_seg, ivrs_base); 1742 if (pci_seg == NULL) 1743 return -ENOMEM; 1744 iommu->pci_seg = pci_seg; 1745 1746 raw_spin_lock_init(&iommu->lock); 1747 atomic64_set(&iommu->cmd_sem_val, 0); 1748 1749 /* Add IOMMU to internal data structures */ 1750 list_add_tail(&iommu->list, &amd_iommu_list); 1751 iommu->index = amd_iommus_present++; 1752 1753 if (unlikely(iommu->index >= MAX_IOMMUS)) { 1754 WARN(1, "System has more IOMMUs than supported by this driver\n"); 1755 return -ENOSYS; 1756 } 1757 1758 /* 1759 * Copy data from ACPI table entry to the iommu struct 1760 */ 1761 iommu->devid = h->devid; 1762 iommu->cap_ptr = h->cap_ptr; 1763 iommu->mmio_phys = h->mmio_phys; 1764 1765 switch (h->type) { 1766 case 0x10: 1767 /* Check if IVHD EFR contains proper max banks/counters */ 1768 if ((h->efr_attr != 0) && 1769 ((h->efr_attr & (0xF << 13)) != 0) && 1770 ((h->efr_attr & (0x3F << 17)) != 0)) 1771 iommu->mmio_phys_end = MMIO_REG_END_OFFSET; 1772 else 1773 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET; 1774 1775 /* GAM requires GA mode. */ 1776 if ((h->efr_attr & (0x1 << IOMMU_FEAT_GASUP_SHIFT)) == 0) 1777 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY; 1778 break; 1779 case 0x11: 1780 case 0x40: 1781 if (h->efr_reg & (1 << 9)) 1782 iommu->mmio_phys_end = MMIO_REG_END_OFFSET; 1783 else 1784 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET; 1785 1786 /* XT and GAM require GA mode. */ 1787 if ((h->efr_reg & (0x1 << IOMMU_EFR_GASUP_SHIFT)) == 0) { 1788 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY; 1789 break; 1790 } 1791 1792 if (h->efr_reg & BIT(IOMMU_EFR_XTSUP_SHIFT)) 1793 amd_iommu_xt_mode = IRQ_REMAP_X2APIC_MODE; 1794 1795 early_iommu_features_init(iommu, h); 1796 1797 break; 1798 default: 1799 return -EINVAL; 1800 } 1801 1802 iommu->mmio_base = iommu_map_mmio_space(iommu->mmio_phys, 1803 iommu->mmio_phys_end); 1804 if (!iommu->mmio_base) 1805 return -ENOMEM; 1806 1807 return init_iommu_from_acpi(iommu, h); 1808 } 1809 1810 static int __init init_iommu_one_late(struct amd_iommu *iommu) 1811 { 1812 int ret; 1813 1814 if (alloc_cwwb_sem(iommu)) 1815 return -ENOMEM; 1816 1817 if (alloc_command_buffer(iommu)) 1818 return -ENOMEM; 1819 1820 if (alloc_event_buffer(iommu)) 1821 return -ENOMEM; 1822 1823 iommu->int_enabled = false; 1824 1825 init_translation_status(iommu); 1826 if (translation_pre_enabled(iommu) && !is_kdump_kernel()) { 1827 iommu_disable(iommu); 1828 clear_translation_pre_enabled(iommu); 1829 pr_warn("Translation was enabled for IOMMU:%d but we are not in kdump mode\n", 1830 iommu->index); 1831 } 1832 if (amd_iommu_pre_enabled) 1833 amd_iommu_pre_enabled = translation_pre_enabled(iommu); 1834 1835 if (amd_iommu_irq_remap) { 1836 ret = amd_iommu_create_irq_domain(iommu); 1837 if (ret) 1838 return ret; 1839 } 1840 1841 /* 1842 * Make sure IOMMU is not considered to translate itself. The IVRS 1843 * table tells us so, but this is a lie! 1844 */ 1845 iommu->pci_seg->rlookup_table[iommu->devid] = NULL; 1846 1847 return 0; 1848 } 1849 1850 /** 1851 * get_highest_supported_ivhd_type - Look up the appropriate IVHD type 1852 * @ivrs: Pointer to the IVRS header 1853 * 1854 * This function search through all IVDB of the maximum supported IVHD 1855 */ 1856 static u8 get_highest_supported_ivhd_type(struct acpi_table_header *ivrs) 1857 { 1858 u8 *base = (u8 *)ivrs; 1859 struct ivhd_header *ivhd = (struct ivhd_header *) 1860 (base + IVRS_HEADER_LENGTH); 1861 u8 last_type = ivhd->type; 1862 u16 devid = ivhd->devid; 1863 1864 while (((u8 *)ivhd - base < ivrs->length) && 1865 (ivhd->type <= ACPI_IVHD_TYPE_MAX_SUPPORTED)) { 1866 u8 *p = (u8 *) ivhd; 1867 1868 if (ivhd->devid == devid) 1869 last_type = ivhd->type; 1870 ivhd = (struct ivhd_header *)(p + ivhd->length); 1871 } 1872 1873 return last_type; 1874 } 1875 1876 /* 1877 * Iterates over all IOMMU entries in the ACPI table, allocates the 1878 * IOMMU structure and initializes it with init_iommu_one() 1879 */ 1880 static int __init init_iommu_all(struct acpi_table_header *table) 1881 { 1882 u8 *p = (u8 *)table, *end = (u8 *)table; 1883 struct ivhd_header *h; 1884 struct amd_iommu *iommu; 1885 int ret; 1886 1887 end += table->length; 1888 p += IVRS_HEADER_LENGTH; 1889 1890 /* Phase 1: Process all IVHD blocks */ 1891 while (p < end) { 1892 h = (struct ivhd_header *)p; 1893 if (*p == amd_iommu_target_ivhd_type) { 1894 1895 DUMP_printk("device: %04x:%02x:%02x.%01x cap: %04x " 1896 "flags: %01x info %04x\n", 1897 h->pci_seg, PCI_BUS_NUM(h->devid), 1898 PCI_SLOT(h->devid), PCI_FUNC(h->devid), 1899 h->cap_ptr, h->flags, h->info); 1900 DUMP_printk(" mmio-addr: %016llx\n", 1901 h->mmio_phys); 1902 1903 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL); 1904 if (iommu == NULL) 1905 return -ENOMEM; 1906 1907 ret = init_iommu_one(iommu, h, table); 1908 if (ret) 1909 return ret; 1910 } 1911 p += h->length; 1912 1913 } 1914 WARN_ON(p != end); 1915 1916 /* Phase 2 : Early feature support check */ 1917 get_global_efr(); 1918 1919 /* Phase 3 : Enabling IOMMU features */ 1920 for_each_iommu(iommu) { 1921 ret = init_iommu_one_late(iommu); 1922 if (ret) 1923 return ret; 1924 } 1925 1926 return 0; 1927 } 1928 1929 static void init_iommu_perf_ctr(struct amd_iommu *iommu) 1930 { 1931 u64 val; 1932 struct pci_dev *pdev = iommu->dev; 1933 1934 if (!check_feature(FEATURE_PC)) 1935 return; 1936 1937 amd_iommu_pc_present = true; 1938 1939 pci_info(pdev, "IOMMU performance counters supported\n"); 1940 1941 val = readl(iommu->mmio_base + MMIO_CNTR_CONF_OFFSET); 1942 iommu->max_banks = (u8) ((val >> 12) & 0x3f); 1943 iommu->max_counters = (u8) ((val >> 7) & 0xf); 1944 1945 return; 1946 } 1947 1948 static ssize_t amd_iommu_show_cap(struct device *dev, 1949 struct device_attribute *attr, 1950 char *buf) 1951 { 1952 struct amd_iommu *iommu = dev_to_amd_iommu(dev); 1953 return sysfs_emit(buf, "%x\n", iommu->cap); 1954 } 1955 static DEVICE_ATTR(cap, S_IRUGO, amd_iommu_show_cap, NULL); 1956 1957 static ssize_t amd_iommu_show_features(struct device *dev, 1958 struct device_attribute *attr, 1959 char *buf) 1960 { 1961 return sysfs_emit(buf, "%llx:%llx\n", amd_iommu_efr, amd_iommu_efr2); 1962 } 1963 static DEVICE_ATTR(features, S_IRUGO, amd_iommu_show_features, NULL); 1964 1965 static struct attribute *amd_iommu_attrs[] = { 1966 &dev_attr_cap.attr, 1967 &dev_attr_features.attr, 1968 NULL, 1969 }; 1970 1971 static struct attribute_group amd_iommu_group = { 1972 .name = "amd-iommu", 1973 .attrs = amd_iommu_attrs, 1974 }; 1975 1976 static const struct attribute_group *amd_iommu_groups[] = { 1977 &amd_iommu_group, 1978 NULL, 1979 }; 1980 1981 /* 1982 * Note: IVHD 0x11 and 0x40 also contains exact copy 1983 * of the IOMMU Extended Feature Register [MMIO Offset 0030h]. 1984 * Default to EFR in IVHD since it is available sooner (i.e. before PCI init). 1985 */ 1986 static void __init late_iommu_features_init(struct amd_iommu *iommu) 1987 { 1988 u64 features, features2; 1989 1990 if (!(iommu->cap & (1 << IOMMU_CAP_EFR))) 1991 return; 1992 1993 /* read extended feature bits */ 1994 features = readq(iommu->mmio_base + MMIO_EXT_FEATURES); 1995 features2 = readq(iommu->mmio_base + MMIO_EXT_FEATURES2); 1996 1997 if (!amd_iommu_efr) { 1998 amd_iommu_efr = features; 1999 amd_iommu_efr2 = features2; 2000 return; 2001 } 2002 2003 /* 2004 * Sanity check and warn if EFR values from 2005 * IVHD and MMIO conflict. 2006 */ 2007 if (features != amd_iommu_efr || 2008 features2 != amd_iommu_efr2) { 2009 pr_warn(FW_WARN 2010 "EFR mismatch. Use IVHD EFR (%#llx : %#llx), EFR2 (%#llx : %#llx).\n", 2011 features, amd_iommu_efr, 2012 features2, amd_iommu_efr2); 2013 } 2014 } 2015 2016 static int __init iommu_init_pci(struct amd_iommu *iommu) 2017 { 2018 int cap_ptr = iommu->cap_ptr; 2019 int ret; 2020 2021 iommu->dev = pci_get_domain_bus_and_slot(iommu->pci_seg->id, 2022 PCI_BUS_NUM(iommu->devid), 2023 iommu->devid & 0xff); 2024 if (!iommu->dev) 2025 return -ENODEV; 2026 2027 /* Prevent binding other PCI device drivers to IOMMU devices */ 2028 iommu->dev->match_driver = false; 2029 2030 /* ACPI _PRT won't have an IRQ for IOMMU */ 2031 iommu->dev->irq_managed = 1; 2032 2033 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET, 2034 &iommu->cap); 2035 2036 if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB))) 2037 amd_iommu_iotlb_sup = false; 2038 2039 late_iommu_features_init(iommu); 2040 2041 if (check_feature(FEATURE_GT)) { 2042 int glxval; 2043 u64 pasmax; 2044 2045 pasmax = FIELD_GET(FEATURE_PASMAX, amd_iommu_efr); 2046 iommu->iommu.max_pasids = (1 << (pasmax + 1)) - 1; 2047 2048 BUG_ON(iommu->iommu.max_pasids & ~PASID_MASK); 2049 2050 glxval = FIELD_GET(FEATURE_GLX, amd_iommu_efr); 2051 2052 if (amd_iommu_max_glx_val == -1) 2053 amd_iommu_max_glx_val = glxval; 2054 else 2055 amd_iommu_max_glx_val = min(amd_iommu_max_glx_val, glxval); 2056 2057 iommu_enable_gt(iommu); 2058 } 2059 2060 if (check_feature(FEATURE_PPR) && amd_iommu_alloc_ppr_log(iommu)) 2061 return -ENOMEM; 2062 2063 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE)) { 2064 pr_info("Using strict mode due to virtualization\n"); 2065 iommu_set_dma_strict(); 2066 amd_iommu_np_cache = true; 2067 } 2068 2069 init_iommu_perf_ctr(iommu); 2070 2071 if (is_rd890_iommu(iommu->dev)) { 2072 int i, j; 2073 2074 iommu->root_pdev = 2075 pci_get_domain_bus_and_slot(iommu->pci_seg->id, 2076 iommu->dev->bus->number, 2077 PCI_DEVFN(0, 0)); 2078 2079 /* 2080 * Some rd890 systems may not be fully reconfigured by the 2081 * BIOS, so it's necessary for us to store this information so 2082 * it can be reprogrammed on resume 2083 */ 2084 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4, 2085 &iommu->stored_addr_lo); 2086 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8, 2087 &iommu->stored_addr_hi); 2088 2089 /* Low bit locks writes to configuration space */ 2090 iommu->stored_addr_lo &= ~1; 2091 2092 for (i = 0; i < 6; i++) 2093 for (j = 0; j < 0x12; j++) 2094 iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j); 2095 2096 for (i = 0; i < 0x83; i++) 2097 iommu->stored_l2[i] = iommu_read_l2(iommu, i); 2098 } 2099 2100 amd_iommu_erratum_746_workaround(iommu); 2101 amd_iommu_ats_write_check_workaround(iommu); 2102 2103 ret = iommu_device_sysfs_add(&iommu->iommu, &iommu->dev->dev, 2104 amd_iommu_groups, "ivhd%d", iommu->index); 2105 if (ret) 2106 return ret; 2107 2108 /* 2109 * Allocate per IOMMU IOPF queue here so that in attach device path, 2110 * PRI capable device can be added to IOPF queue 2111 */ 2112 if (amd_iommu_gt_ppr_supported()) { 2113 ret = amd_iommu_iopf_init(iommu); 2114 if (ret) 2115 return ret; 2116 } 2117 2118 iommu_device_register(&iommu->iommu, &amd_iommu_ops, NULL); 2119 2120 return pci_enable_device(iommu->dev); 2121 } 2122 2123 static void print_iommu_info(void) 2124 { 2125 int i; 2126 static const char * const feat_str[] = { 2127 "PreF", "PPR", "X2APIC", "NX", "GT", "[5]", 2128 "IA", "GA", "HE", "PC" 2129 }; 2130 2131 if (amd_iommu_efr) { 2132 pr_info("Extended features (%#llx, %#llx):", amd_iommu_efr, amd_iommu_efr2); 2133 2134 for (i = 0; i < ARRAY_SIZE(feat_str); ++i) { 2135 if (check_feature(1ULL << i)) 2136 pr_cont(" %s", feat_str[i]); 2137 } 2138 2139 if (check_feature(FEATURE_GAM_VAPIC)) 2140 pr_cont(" GA_vAPIC"); 2141 2142 if (check_feature(FEATURE_SNP)) 2143 pr_cont(" SNP"); 2144 2145 pr_cont("\n"); 2146 } 2147 2148 if (irq_remapping_enabled) { 2149 pr_info("Interrupt remapping enabled\n"); 2150 if (amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE) 2151 pr_info("X2APIC enabled\n"); 2152 } 2153 if (amd_iommu_pgtable == PD_MODE_V2) { 2154 pr_info("V2 page table enabled (Paging mode : %d level)\n", 2155 amd_iommu_gpt_level); 2156 } 2157 } 2158 2159 static int __init amd_iommu_init_pci(void) 2160 { 2161 struct amd_iommu *iommu; 2162 struct amd_iommu_pci_seg *pci_seg; 2163 int ret; 2164 2165 /* Init global identity domain before registering IOMMU */ 2166 amd_iommu_init_identity_domain(); 2167 2168 for_each_iommu(iommu) { 2169 ret = iommu_init_pci(iommu); 2170 if (ret) { 2171 pr_err("IOMMU%d: Failed to initialize IOMMU Hardware (error=%d)!\n", 2172 iommu->index, ret); 2173 goto out; 2174 } 2175 /* Need to setup range after PCI init */ 2176 iommu_set_cwwb_range(iommu); 2177 } 2178 2179 /* 2180 * Order is important here to make sure any unity map requirements are 2181 * fulfilled. The unity mappings are created and written to the device 2182 * table during the iommu_init_pci() call. 2183 * 2184 * After that we call init_device_table_dma() to make sure any 2185 * uninitialized DTE will block DMA, and in the end we flush the caches 2186 * of all IOMMUs to make sure the changes to the device table are 2187 * active. 2188 */ 2189 for_each_pci_segment(pci_seg) 2190 init_device_table_dma(pci_seg); 2191 2192 for_each_iommu(iommu) 2193 amd_iommu_flush_all_caches(iommu); 2194 2195 print_iommu_info(); 2196 2197 out: 2198 return ret; 2199 } 2200 2201 /**************************************************************************** 2202 * 2203 * The following functions initialize the MSI interrupts for all IOMMUs 2204 * in the system. It's a bit challenging because there could be multiple 2205 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per 2206 * pci_dev. 2207 * 2208 ****************************************************************************/ 2209 2210 static int iommu_setup_msi(struct amd_iommu *iommu) 2211 { 2212 int r; 2213 2214 r = pci_enable_msi(iommu->dev); 2215 if (r) 2216 return r; 2217 2218 r = request_threaded_irq(iommu->dev->irq, 2219 amd_iommu_int_handler, 2220 amd_iommu_int_thread, 2221 0, "AMD-Vi", 2222 iommu); 2223 2224 if (r) { 2225 pci_disable_msi(iommu->dev); 2226 return r; 2227 } 2228 2229 return 0; 2230 } 2231 2232 union intcapxt { 2233 u64 capxt; 2234 struct { 2235 u64 reserved_0 : 2, 2236 dest_mode_logical : 1, 2237 reserved_1 : 5, 2238 destid_0_23 : 24, 2239 vector : 8, 2240 reserved_2 : 16, 2241 destid_24_31 : 8; 2242 }; 2243 } __attribute__ ((packed)); 2244 2245 2246 static struct irq_chip intcapxt_controller; 2247 2248 static int intcapxt_irqdomain_activate(struct irq_domain *domain, 2249 struct irq_data *irqd, bool reserve) 2250 { 2251 return 0; 2252 } 2253 2254 static void intcapxt_irqdomain_deactivate(struct irq_domain *domain, 2255 struct irq_data *irqd) 2256 { 2257 } 2258 2259 2260 static int intcapxt_irqdomain_alloc(struct irq_domain *domain, unsigned int virq, 2261 unsigned int nr_irqs, void *arg) 2262 { 2263 struct irq_alloc_info *info = arg; 2264 int i, ret; 2265 2266 if (!info || info->type != X86_IRQ_ALLOC_TYPE_AMDVI) 2267 return -EINVAL; 2268 2269 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg); 2270 if (ret < 0) 2271 return ret; 2272 2273 for (i = virq; i < virq + nr_irqs; i++) { 2274 struct irq_data *irqd = irq_domain_get_irq_data(domain, i); 2275 2276 irqd->chip = &intcapxt_controller; 2277 irqd->hwirq = info->hwirq; 2278 irqd->chip_data = info->data; 2279 __irq_set_handler(i, handle_edge_irq, 0, "edge"); 2280 } 2281 2282 return ret; 2283 } 2284 2285 static void intcapxt_irqdomain_free(struct irq_domain *domain, unsigned int virq, 2286 unsigned int nr_irqs) 2287 { 2288 irq_domain_free_irqs_top(domain, virq, nr_irqs); 2289 } 2290 2291 2292 static void intcapxt_unmask_irq(struct irq_data *irqd) 2293 { 2294 struct amd_iommu *iommu = irqd->chip_data; 2295 struct irq_cfg *cfg = irqd_cfg(irqd); 2296 union intcapxt xt; 2297 2298 xt.capxt = 0ULL; 2299 xt.dest_mode_logical = apic->dest_mode_logical; 2300 xt.vector = cfg->vector; 2301 xt.destid_0_23 = cfg->dest_apicid & GENMASK(23, 0); 2302 xt.destid_24_31 = cfg->dest_apicid >> 24; 2303 2304 writeq(xt.capxt, iommu->mmio_base + irqd->hwirq); 2305 } 2306 2307 static void intcapxt_mask_irq(struct irq_data *irqd) 2308 { 2309 struct amd_iommu *iommu = irqd->chip_data; 2310 2311 writeq(0, iommu->mmio_base + irqd->hwirq); 2312 } 2313 2314 2315 static int intcapxt_set_affinity(struct irq_data *irqd, 2316 const struct cpumask *mask, bool force) 2317 { 2318 struct irq_data *parent = irqd->parent_data; 2319 int ret; 2320 2321 ret = parent->chip->irq_set_affinity(parent, mask, force); 2322 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE) 2323 return ret; 2324 return 0; 2325 } 2326 2327 static int intcapxt_set_wake(struct irq_data *irqd, unsigned int on) 2328 { 2329 return on ? -EOPNOTSUPP : 0; 2330 } 2331 2332 static struct irq_chip intcapxt_controller = { 2333 .name = "IOMMU-MSI", 2334 .irq_unmask = intcapxt_unmask_irq, 2335 .irq_mask = intcapxt_mask_irq, 2336 .irq_ack = irq_chip_ack_parent, 2337 .irq_retrigger = irq_chip_retrigger_hierarchy, 2338 .irq_set_affinity = intcapxt_set_affinity, 2339 .irq_set_wake = intcapxt_set_wake, 2340 .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_MOVE_DEFERRED, 2341 }; 2342 2343 static const struct irq_domain_ops intcapxt_domain_ops = { 2344 .alloc = intcapxt_irqdomain_alloc, 2345 .free = intcapxt_irqdomain_free, 2346 .activate = intcapxt_irqdomain_activate, 2347 .deactivate = intcapxt_irqdomain_deactivate, 2348 }; 2349 2350 2351 static struct irq_domain *iommu_irqdomain; 2352 2353 static struct irq_domain *iommu_get_irqdomain(void) 2354 { 2355 struct fwnode_handle *fn; 2356 2357 /* No need for locking here (yet) as the init is single-threaded */ 2358 if (iommu_irqdomain) 2359 return iommu_irqdomain; 2360 2361 fn = irq_domain_alloc_named_fwnode("AMD-Vi-MSI"); 2362 if (!fn) 2363 return NULL; 2364 2365 iommu_irqdomain = irq_domain_create_hierarchy(x86_vector_domain, 0, 0, 2366 fn, &intcapxt_domain_ops, 2367 NULL); 2368 if (!iommu_irqdomain) 2369 irq_domain_free_fwnode(fn); 2370 2371 return iommu_irqdomain; 2372 } 2373 2374 static int __iommu_setup_intcapxt(struct amd_iommu *iommu, const char *devname, 2375 int hwirq, irq_handler_t thread_fn) 2376 { 2377 struct irq_domain *domain; 2378 struct irq_alloc_info info; 2379 int irq, ret; 2380 int node = dev_to_node(&iommu->dev->dev); 2381 2382 domain = iommu_get_irqdomain(); 2383 if (!domain) 2384 return -ENXIO; 2385 2386 init_irq_alloc_info(&info, NULL); 2387 info.type = X86_IRQ_ALLOC_TYPE_AMDVI; 2388 info.data = iommu; 2389 info.hwirq = hwirq; 2390 2391 irq = irq_domain_alloc_irqs(domain, 1, node, &info); 2392 if (irq < 0) { 2393 irq_domain_remove(domain); 2394 return irq; 2395 } 2396 2397 ret = request_threaded_irq(irq, amd_iommu_int_handler, 2398 thread_fn, 0, devname, iommu); 2399 if (ret) { 2400 irq_domain_free_irqs(irq, 1); 2401 irq_domain_remove(domain); 2402 return ret; 2403 } 2404 2405 return 0; 2406 } 2407 2408 static int iommu_setup_intcapxt(struct amd_iommu *iommu) 2409 { 2410 int ret; 2411 2412 snprintf(iommu->evt_irq_name, sizeof(iommu->evt_irq_name), 2413 "AMD-Vi%d-Evt", iommu->index); 2414 ret = __iommu_setup_intcapxt(iommu, iommu->evt_irq_name, 2415 MMIO_INTCAPXT_EVT_OFFSET, 2416 amd_iommu_int_thread_evtlog); 2417 if (ret) 2418 return ret; 2419 2420 snprintf(iommu->ppr_irq_name, sizeof(iommu->ppr_irq_name), 2421 "AMD-Vi%d-PPR", iommu->index); 2422 ret = __iommu_setup_intcapxt(iommu, iommu->ppr_irq_name, 2423 MMIO_INTCAPXT_PPR_OFFSET, 2424 amd_iommu_int_thread_pprlog); 2425 if (ret) 2426 return ret; 2427 2428 #ifdef CONFIG_IRQ_REMAP 2429 snprintf(iommu->ga_irq_name, sizeof(iommu->ga_irq_name), 2430 "AMD-Vi%d-GA", iommu->index); 2431 ret = __iommu_setup_intcapxt(iommu, iommu->ga_irq_name, 2432 MMIO_INTCAPXT_GALOG_OFFSET, 2433 amd_iommu_int_thread_galog); 2434 #endif 2435 2436 return ret; 2437 } 2438 2439 static int iommu_init_irq(struct amd_iommu *iommu) 2440 { 2441 int ret; 2442 2443 if (iommu->int_enabled) 2444 goto enable_faults; 2445 2446 if (amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE) 2447 ret = iommu_setup_intcapxt(iommu); 2448 else if (iommu->dev->msi_cap) 2449 ret = iommu_setup_msi(iommu); 2450 else 2451 ret = -ENODEV; 2452 2453 if (ret) 2454 return ret; 2455 2456 iommu->int_enabled = true; 2457 enable_faults: 2458 2459 if (amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE) 2460 iommu_feature_enable(iommu, CONTROL_INTCAPXT_EN); 2461 2462 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN); 2463 2464 return 0; 2465 } 2466 2467 /**************************************************************************** 2468 * 2469 * The next functions belong to the third pass of parsing the ACPI 2470 * table. In this last pass the memory mapping requirements are 2471 * gathered (like exclusion and unity mapping ranges). 2472 * 2473 ****************************************************************************/ 2474 2475 static void __init free_unity_maps(void) 2476 { 2477 struct unity_map_entry *entry, *next; 2478 struct amd_iommu_pci_seg *p, *pci_seg; 2479 2480 for_each_pci_segment_safe(pci_seg, p) { 2481 list_for_each_entry_safe(entry, next, &pci_seg->unity_map, list) { 2482 list_del(&entry->list); 2483 kfree(entry); 2484 } 2485 } 2486 } 2487 2488 /* called for unity map ACPI definition */ 2489 static int __init init_unity_map_range(struct ivmd_header *m, 2490 struct acpi_table_header *ivrs_base) 2491 { 2492 struct unity_map_entry *e = NULL; 2493 struct amd_iommu_pci_seg *pci_seg; 2494 char *s; 2495 2496 pci_seg = get_pci_segment(m->pci_seg, ivrs_base); 2497 if (pci_seg == NULL) 2498 return -ENOMEM; 2499 2500 e = kzalloc(sizeof(*e), GFP_KERNEL); 2501 if (e == NULL) 2502 return -ENOMEM; 2503 2504 switch (m->type) { 2505 default: 2506 kfree(e); 2507 return 0; 2508 case ACPI_IVMD_TYPE: 2509 s = "IVMD_TYPEi\t\t\t"; 2510 e->devid_start = e->devid_end = m->devid; 2511 break; 2512 case ACPI_IVMD_TYPE_ALL: 2513 s = "IVMD_TYPE_ALL\t\t"; 2514 e->devid_start = 0; 2515 e->devid_end = pci_seg->last_bdf; 2516 break; 2517 case ACPI_IVMD_TYPE_RANGE: 2518 s = "IVMD_TYPE_RANGE\t\t"; 2519 e->devid_start = m->devid; 2520 e->devid_end = m->aux; 2521 break; 2522 } 2523 e->address_start = PAGE_ALIGN(m->range_start); 2524 e->address_end = e->address_start + PAGE_ALIGN(m->range_length); 2525 e->prot = m->flags >> 1; 2526 2527 /* 2528 * Treat per-device exclusion ranges as r/w unity-mapped regions 2529 * since some buggy BIOSes might lead to the overwritten exclusion 2530 * range (exclusion_start and exclusion_length members). This 2531 * happens when there are multiple exclusion ranges (IVMD entries) 2532 * defined in ACPI table. 2533 */ 2534 if (m->flags & IVMD_FLAG_EXCL_RANGE) 2535 e->prot = (IVMD_FLAG_IW | IVMD_FLAG_IR) >> 1; 2536 2537 DUMP_printk("%s devid_start: %04x:%02x:%02x.%x devid_end: " 2538 "%04x:%02x:%02x.%x range_start: %016llx range_end: %016llx" 2539 " flags: %x\n", s, m->pci_seg, 2540 PCI_BUS_NUM(e->devid_start), PCI_SLOT(e->devid_start), 2541 PCI_FUNC(e->devid_start), m->pci_seg, 2542 PCI_BUS_NUM(e->devid_end), 2543 PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end), 2544 e->address_start, e->address_end, m->flags); 2545 2546 list_add_tail(&e->list, &pci_seg->unity_map); 2547 2548 return 0; 2549 } 2550 2551 /* iterates over all memory definitions we find in the ACPI table */ 2552 static int __init init_memory_definitions(struct acpi_table_header *table) 2553 { 2554 u8 *p = (u8 *)table, *end = (u8 *)table; 2555 struct ivmd_header *m; 2556 2557 end += table->length; 2558 p += IVRS_HEADER_LENGTH; 2559 2560 while (p < end) { 2561 m = (struct ivmd_header *)p; 2562 if (m->flags & (IVMD_FLAG_UNITY_MAP | IVMD_FLAG_EXCL_RANGE)) 2563 init_unity_map_range(m, table); 2564 2565 p += m->length; 2566 } 2567 2568 return 0; 2569 } 2570 2571 /* 2572 * Init the device table to not allow DMA access for devices 2573 */ 2574 static void init_device_table_dma(struct amd_iommu_pci_seg *pci_seg) 2575 { 2576 u32 devid; 2577 struct dev_table_entry *dev_table = pci_seg->dev_table; 2578 2579 if (dev_table == NULL) 2580 return; 2581 2582 for (devid = 0; devid <= pci_seg->last_bdf; ++devid) { 2583 set_dte_bit(&dev_table[devid], DEV_ENTRY_VALID); 2584 if (!amd_iommu_snp_en) 2585 set_dte_bit(&dev_table[devid], DEV_ENTRY_TRANSLATION); 2586 } 2587 } 2588 2589 static void __init uninit_device_table_dma(struct amd_iommu_pci_seg *pci_seg) 2590 { 2591 u32 devid; 2592 struct dev_table_entry *dev_table = pci_seg->dev_table; 2593 2594 if (dev_table == NULL) 2595 return; 2596 2597 for (devid = 0; devid <= pci_seg->last_bdf; ++devid) { 2598 dev_table[devid].data[0] = 0ULL; 2599 dev_table[devid].data[1] = 0ULL; 2600 } 2601 } 2602 2603 static void init_device_table(void) 2604 { 2605 struct amd_iommu_pci_seg *pci_seg; 2606 u32 devid; 2607 2608 if (!amd_iommu_irq_remap) 2609 return; 2610 2611 for_each_pci_segment(pci_seg) { 2612 for (devid = 0; devid <= pci_seg->last_bdf; ++devid) 2613 set_dte_bit(&pci_seg->dev_table[devid], DEV_ENTRY_IRQ_TBL_EN); 2614 } 2615 } 2616 2617 static void iommu_init_flags(struct amd_iommu *iommu) 2618 { 2619 iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ? 2620 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) : 2621 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN); 2622 2623 iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ? 2624 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) : 2625 iommu_feature_disable(iommu, CONTROL_PASSPW_EN); 2626 2627 iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ? 2628 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) : 2629 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN); 2630 2631 iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ? 2632 iommu_feature_enable(iommu, CONTROL_ISOC_EN) : 2633 iommu_feature_disable(iommu, CONTROL_ISOC_EN); 2634 2635 /* 2636 * make IOMMU memory accesses cache coherent 2637 */ 2638 iommu_feature_enable(iommu, CONTROL_COHERENT_EN); 2639 2640 /* Set IOTLB invalidation timeout to 1s */ 2641 iommu_feature_set(iommu, CTRL_INV_TO_1S, CTRL_INV_TO_MASK, CONTROL_INV_TIMEOUT); 2642 2643 /* Enable Enhanced Peripheral Page Request Handling */ 2644 if (check_feature(FEATURE_EPHSUP)) 2645 iommu_feature_enable(iommu, CONTROL_EPH_EN); 2646 } 2647 2648 static void iommu_apply_resume_quirks(struct amd_iommu *iommu) 2649 { 2650 int i, j; 2651 u32 ioc_feature_control; 2652 struct pci_dev *pdev = iommu->root_pdev; 2653 2654 /* RD890 BIOSes may not have completely reconfigured the iommu */ 2655 if (!is_rd890_iommu(iommu->dev) || !pdev) 2656 return; 2657 2658 /* 2659 * First, we need to ensure that the iommu is enabled. This is 2660 * controlled by a register in the northbridge 2661 */ 2662 2663 /* Select Northbridge indirect register 0x75 and enable writing */ 2664 pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7)); 2665 pci_read_config_dword(pdev, 0x64, &ioc_feature_control); 2666 2667 /* Enable the iommu */ 2668 if (!(ioc_feature_control & 0x1)) 2669 pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1); 2670 2671 /* Restore the iommu BAR */ 2672 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4, 2673 iommu->stored_addr_lo); 2674 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8, 2675 iommu->stored_addr_hi); 2676 2677 /* Restore the l1 indirect regs for each of the 6 l1s */ 2678 for (i = 0; i < 6; i++) 2679 for (j = 0; j < 0x12; j++) 2680 iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]); 2681 2682 /* Restore the l2 indirect regs */ 2683 for (i = 0; i < 0x83; i++) 2684 iommu_write_l2(iommu, i, iommu->stored_l2[i]); 2685 2686 /* Lock PCI setup registers */ 2687 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4, 2688 iommu->stored_addr_lo | 1); 2689 } 2690 2691 static void iommu_enable_ga(struct amd_iommu *iommu) 2692 { 2693 #ifdef CONFIG_IRQ_REMAP 2694 switch (amd_iommu_guest_ir) { 2695 case AMD_IOMMU_GUEST_IR_VAPIC: 2696 case AMD_IOMMU_GUEST_IR_LEGACY_GA: 2697 iommu_feature_enable(iommu, CONTROL_GA_EN); 2698 iommu->irte_ops = &irte_128_ops; 2699 break; 2700 default: 2701 iommu->irte_ops = &irte_32_ops; 2702 break; 2703 } 2704 #endif 2705 } 2706 2707 static void iommu_disable_irtcachedis(struct amd_iommu *iommu) 2708 { 2709 iommu_feature_disable(iommu, CONTROL_IRTCACHEDIS); 2710 } 2711 2712 static void iommu_enable_irtcachedis(struct amd_iommu *iommu) 2713 { 2714 u64 ctrl; 2715 2716 if (!amd_iommu_irtcachedis) 2717 return; 2718 2719 /* 2720 * Note: 2721 * The support for IRTCacheDis feature is dertermined by 2722 * checking if the bit is writable. 2723 */ 2724 iommu_feature_enable(iommu, CONTROL_IRTCACHEDIS); 2725 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); 2726 ctrl &= (1ULL << CONTROL_IRTCACHEDIS); 2727 if (ctrl) 2728 iommu->irtcachedis_enabled = true; 2729 pr_info("iommu%d (%#06x) : IRT cache is %s\n", 2730 iommu->index, iommu->devid, 2731 iommu->irtcachedis_enabled ? "disabled" : "enabled"); 2732 } 2733 2734 static void iommu_enable_2k_int(struct amd_iommu *iommu) 2735 { 2736 if (!FEATURE_NUM_INT_REMAP_SUP_2K(amd_iommu_efr2)) 2737 return; 2738 2739 iommu_feature_set(iommu, 2740 CONTROL_NUM_INT_REMAP_MODE_2K, 2741 CONTROL_NUM_INT_REMAP_MODE_MASK, 2742 CONTROL_NUM_INT_REMAP_MODE); 2743 } 2744 2745 static void early_enable_iommu(struct amd_iommu *iommu) 2746 { 2747 iommu_disable(iommu); 2748 iommu_init_flags(iommu); 2749 iommu_set_device_table(iommu); 2750 iommu_enable_command_buffer(iommu); 2751 iommu_enable_event_buffer(iommu); 2752 iommu_set_exclusion_range(iommu); 2753 iommu_enable_gt(iommu); 2754 iommu_enable_ga(iommu); 2755 iommu_enable_xt(iommu); 2756 iommu_enable_irtcachedis(iommu); 2757 iommu_enable_2k_int(iommu); 2758 iommu_enable(iommu); 2759 amd_iommu_flush_all_caches(iommu); 2760 } 2761 2762 /* 2763 * This function finally enables all IOMMUs found in the system after 2764 * they have been initialized. 2765 * 2766 * Or if in kdump kernel and IOMMUs are all pre-enabled, try to copy 2767 * the old content of device table entries. Not this case or copy failed, 2768 * just continue as normal kernel does. 2769 */ 2770 static void early_enable_iommus(void) 2771 { 2772 struct amd_iommu *iommu; 2773 struct amd_iommu_pci_seg *pci_seg; 2774 2775 if (!copy_device_table()) { 2776 /* 2777 * If come here because of failure in copying device table from old 2778 * kernel with all IOMMUs enabled, print error message and try to 2779 * free allocated old_dev_tbl_cpy. 2780 */ 2781 if (amd_iommu_pre_enabled) 2782 pr_err("Failed to copy DEV table from previous kernel.\n"); 2783 2784 for_each_pci_segment(pci_seg) { 2785 if (pci_seg->old_dev_tbl_cpy != NULL) { 2786 iommu_free_pages(pci_seg->old_dev_tbl_cpy); 2787 pci_seg->old_dev_tbl_cpy = NULL; 2788 } 2789 } 2790 2791 for_each_iommu(iommu) { 2792 clear_translation_pre_enabled(iommu); 2793 early_enable_iommu(iommu); 2794 } 2795 } else { 2796 pr_info("Copied DEV table from previous kernel.\n"); 2797 2798 for_each_pci_segment(pci_seg) { 2799 iommu_free_pages(pci_seg->dev_table); 2800 pci_seg->dev_table = pci_seg->old_dev_tbl_cpy; 2801 } 2802 2803 for_each_iommu(iommu) { 2804 iommu_disable_command_buffer(iommu); 2805 iommu_disable_event_buffer(iommu); 2806 iommu_disable_irtcachedis(iommu); 2807 iommu_enable_command_buffer(iommu); 2808 iommu_enable_event_buffer(iommu); 2809 iommu_enable_ga(iommu); 2810 iommu_enable_xt(iommu); 2811 iommu_enable_irtcachedis(iommu); 2812 iommu_enable_2k_int(iommu); 2813 iommu_set_device_table(iommu); 2814 amd_iommu_flush_all_caches(iommu); 2815 } 2816 } 2817 } 2818 2819 static void enable_iommus_ppr(void) 2820 { 2821 struct amd_iommu *iommu; 2822 2823 if (!amd_iommu_gt_ppr_supported()) 2824 return; 2825 2826 for_each_iommu(iommu) 2827 amd_iommu_enable_ppr_log(iommu); 2828 } 2829 2830 static void enable_iommus_vapic(void) 2831 { 2832 #ifdef CONFIG_IRQ_REMAP 2833 u32 status, i; 2834 struct amd_iommu *iommu; 2835 2836 for_each_iommu(iommu) { 2837 /* 2838 * Disable GALog if already running. It could have been enabled 2839 * in the previous boot before kdump. 2840 */ 2841 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); 2842 if (!(status & MMIO_STATUS_GALOG_RUN_MASK)) 2843 continue; 2844 2845 iommu_feature_disable(iommu, CONTROL_GALOG_EN); 2846 iommu_feature_disable(iommu, CONTROL_GAINT_EN); 2847 2848 /* 2849 * Need to set and poll check the GALOGRun bit to zero before 2850 * we can set/ modify GA Log registers safely. 2851 */ 2852 for (i = 0; i < MMIO_STATUS_TIMEOUT; ++i) { 2853 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); 2854 if (!(status & MMIO_STATUS_GALOG_RUN_MASK)) 2855 break; 2856 udelay(10); 2857 } 2858 2859 if (WARN_ON(i >= MMIO_STATUS_TIMEOUT)) 2860 return; 2861 } 2862 2863 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) && 2864 !check_feature(FEATURE_GAM_VAPIC)) { 2865 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY_GA; 2866 return; 2867 } 2868 2869 if (amd_iommu_snp_en && 2870 !FEATURE_SNPAVICSUP_GAM(amd_iommu_efr2)) { 2871 pr_warn("Force to disable Virtual APIC due to SNP\n"); 2872 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY_GA; 2873 return; 2874 } 2875 2876 /* Enabling GAM and SNPAVIC support */ 2877 for_each_iommu(iommu) { 2878 if (iommu_init_ga_log(iommu) || 2879 iommu_ga_log_enable(iommu)) 2880 return; 2881 2882 iommu_feature_enable(iommu, CONTROL_GAM_EN); 2883 if (amd_iommu_snp_en) 2884 iommu_feature_enable(iommu, CONTROL_SNPAVIC_EN); 2885 } 2886 2887 amd_iommu_irq_ops.capability |= (1 << IRQ_POSTING_CAP); 2888 pr_info("Virtual APIC enabled\n"); 2889 #endif 2890 } 2891 2892 static void disable_iommus(void) 2893 { 2894 struct amd_iommu *iommu; 2895 2896 for_each_iommu(iommu) 2897 iommu_disable(iommu); 2898 2899 #ifdef CONFIG_IRQ_REMAP 2900 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) 2901 amd_iommu_irq_ops.capability &= ~(1 << IRQ_POSTING_CAP); 2902 #endif 2903 } 2904 2905 /* 2906 * Suspend/Resume support 2907 * disable suspend until real resume implemented 2908 */ 2909 2910 static void amd_iommu_resume(void) 2911 { 2912 struct amd_iommu *iommu; 2913 2914 for_each_iommu(iommu) 2915 iommu_apply_resume_quirks(iommu); 2916 2917 /* re-load the hardware */ 2918 for_each_iommu(iommu) 2919 early_enable_iommu(iommu); 2920 2921 amd_iommu_enable_interrupts(); 2922 } 2923 2924 static int amd_iommu_suspend(void) 2925 { 2926 /* disable IOMMUs to go out of the way for BIOS */ 2927 disable_iommus(); 2928 2929 return 0; 2930 } 2931 2932 static struct syscore_ops amd_iommu_syscore_ops = { 2933 .suspend = amd_iommu_suspend, 2934 .resume = amd_iommu_resume, 2935 }; 2936 2937 static void __init free_iommu_resources(void) 2938 { 2939 free_iommu_all(); 2940 free_pci_segments(); 2941 } 2942 2943 /* SB IOAPIC is always on this device in AMD systems */ 2944 #define IOAPIC_SB_DEVID ((0x00 << 8) | PCI_DEVFN(0x14, 0)) 2945 2946 static bool __init check_ioapic_information(void) 2947 { 2948 const char *fw_bug = FW_BUG; 2949 bool ret, has_sb_ioapic; 2950 int idx; 2951 2952 has_sb_ioapic = false; 2953 ret = false; 2954 2955 /* 2956 * If we have map overrides on the kernel command line the 2957 * messages in this function might not describe firmware bugs 2958 * anymore - so be careful 2959 */ 2960 if (cmdline_maps) 2961 fw_bug = ""; 2962 2963 for (idx = 0; idx < nr_ioapics; idx++) { 2964 int devid, id = mpc_ioapic_id(idx); 2965 2966 devid = get_ioapic_devid(id); 2967 if (devid < 0) { 2968 pr_err("%s: IOAPIC[%d] not in IVRS table\n", 2969 fw_bug, id); 2970 ret = false; 2971 } else if (devid == IOAPIC_SB_DEVID) { 2972 has_sb_ioapic = true; 2973 ret = true; 2974 } 2975 } 2976 2977 if (!has_sb_ioapic) { 2978 /* 2979 * We expect the SB IOAPIC to be listed in the IVRS 2980 * table. The system timer is connected to the SB IOAPIC 2981 * and if we don't have it in the list the system will 2982 * panic at boot time. This situation usually happens 2983 * when the BIOS is buggy and provides us the wrong 2984 * device id for the IOAPIC in the system. 2985 */ 2986 pr_err("%s: No southbridge IOAPIC found\n", fw_bug); 2987 } 2988 2989 if (!ret) 2990 pr_err("Disabling interrupt remapping\n"); 2991 2992 return ret; 2993 } 2994 2995 static void __init free_dma_resources(void) 2996 { 2997 ida_destroy(&pdom_ids); 2998 2999 free_unity_maps(); 3000 } 3001 3002 static void __init ivinfo_init(void *ivrs) 3003 { 3004 amd_iommu_ivinfo = *((u32 *)(ivrs + IOMMU_IVINFO_OFFSET)); 3005 } 3006 3007 /* 3008 * This is the hardware init function for AMD IOMMU in the system. 3009 * This function is called either from amd_iommu_init or from the interrupt 3010 * remapping setup code. 3011 * 3012 * This function basically parses the ACPI table for AMD IOMMU (IVRS) 3013 * four times: 3014 * 3015 * 1 pass) Discover the most comprehensive IVHD type to use. 3016 * 3017 * 2 pass) Find the highest PCI device id the driver has to handle. 3018 * Upon this information the size of the data structures is 3019 * determined that needs to be allocated. 3020 * 3021 * 3 pass) Initialize the data structures just allocated with the 3022 * information in the ACPI table about available AMD IOMMUs 3023 * in the system. It also maps the PCI devices in the 3024 * system to specific IOMMUs 3025 * 3026 * 4 pass) After the basic data structures are allocated and 3027 * initialized we update them with information about memory 3028 * remapping requirements parsed out of the ACPI table in 3029 * this last pass. 3030 * 3031 * After everything is set up the IOMMUs are enabled and the necessary 3032 * hotplug and suspend notifiers are registered. 3033 */ 3034 static int __init early_amd_iommu_init(void) 3035 { 3036 struct acpi_table_header *ivrs_base; 3037 int ret; 3038 acpi_status status; 3039 3040 if (!amd_iommu_detected) 3041 return -ENODEV; 3042 3043 status = acpi_get_table("IVRS", 0, &ivrs_base); 3044 if (status == AE_NOT_FOUND) 3045 return -ENODEV; 3046 else if (ACPI_FAILURE(status)) { 3047 const char *err = acpi_format_exception(status); 3048 pr_err("IVRS table error: %s\n", err); 3049 return -EINVAL; 3050 } 3051 3052 if (!boot_cpu_has(X86_FEATURE_CX16)) { 3053 pr_err("Failed to initialize. The CMPXCHG16B feature is required.\n"); 3054 return -EINVAL; 3055 } 3056 3057 /* 3058 * Validate checksum here so we don't need to do it when 3059 * we actually parse the table 3060 */ 3061 ret = check_ivrs_checksum(ivrs_base); 3062 if (ret) 3063 goto out; 3064 3065 ivinfo_init(ivrs_base); 3066 3067 amd_iommu_target_ivhd_type = get_highest_supported_ivhd_type(ivrs_base); 3068 DUMP_printk("Using IVHD type %#x\n", amd_iommu_target_ivhd_type); 3069 3070 /* 3071 * now the data structures are allocated and basically initialized 3072 * start the real acpi table scan 3073 */ 3074 ret = init_iommu_all(ivrs_base); 3075 if (ret) 3076 goto out; 3077 3078 /* 5 level guest page table */ 3079 if (cpu_feature_enabled(X86_FEATURE_LA57) && 3080 FIELD_GET(FEATURE_GATS, amd_iommu_efr) == GUEST_PGTABLE_5_LEVEL) 3081 amd_iommu_gpt_level = PAGE_MODE_5_LEVEL; 3082 3083 if (amd_iommu_pgtable == PD_MODE_V2) { 3084 if (!amd_iommu_v2_pgtbl_supported()) { 3085 pr_warn("Cannot enable v2 page table for DMA-API. Fallback to v1.\n"); 3086 amd_iommu_pgtable = PD_MODE_V1; 3087 } 3088 } 3089 3090 /* Disable any previously enabled IOMMUs */ 3091 if (!is_kdump_kernel() || amd_iommu_disabled) 3092 disable_iommus(); 3093 3094 if (amd_iommu_irq_remap) 3095 amd_iommu_irq_remap = check_ioapic_information(); 3096 3097 if (amd_iommu_irq_remap) { 3098 struct amd_iommu_pci_seg *pci_seg; 3099 ret = -ENOMEM; 3100 for_each_pci_segment(pci_seg) { 3101 if (alloc_irq_lookup_table(pci_seg)) 3102 goto out; 3103 } 3104 } 3105 3106 ret = init_memory_definitions(ivrs_base); 3107 if (ret) 3108 goto out; 3109 3110 /* init the device table */ 3111 init_device_table(); 3112 3113 out: 3114 /* Don't leak any ACPI memory */ 3115 acpi_put_table(ivrs_base); 3116 3117 return ret; 3118 } 3119 3120 static int amd_iommu_enable_interrupts(void) 3121 { 3122 struct amd_iommu *iommu; 3123 int ret = 0; 3124 3125 for_each_iommu(iommu) { 3126 ret = iommu_init_irq(iommu); 3127 if (ret) 3128 goto out; 3129 } 3130 3131 /* 3132 * Interrupt handler is ready to process interrupts. Enable 3133 * PPR and GA log interrupt for all IOMMUs. 3134 */ 3135 enable_iommus_vapic(); 3136 enable_iommus_ppr(); 3137 3138 out: 3139 return ret; 3140 } 3141 3142 static bool __init detect_ivrs(void) 3143 { 3144 struct acpi_table_header *ivrs_base; 3145 acpi_status status; 3146 int i; 3147 3148 status = acpi_get_table("IVRS", 0, &ivrs_base); 3149 if (status == AE_NOT_FOUND) 3150 return false; 3151 else if (ACPI_FAILURE(status)) { 3152 const char *err = acpi_format_exception(status); 3153 pr_err("IVRS table error: %s\n", err); 3154 return false; 3155 } 3156 3157 acpi_put_table(ivrs_base); 3158 3159 if (amd_iommu_force_enable) 3160 goto out; 3161 3162 /* Don't use IOMMU if there is Stoney Ridge graphics */ 3163 for (i = 0; i < 32; i++) { 3164 u32 pci_id; 3165 3166 pci_id = read_pci_config(0, i, 0, 0); 3167 if ((pci_id & 0xffff) == 0x1002 && (pci_id >> 16) == 0x98e4) { 3168 pr_info("Disable IOMMU on Stoney Ridge\n"); 3169 return false; 3170 } 3171 } 3172 3173 out: 3174 /* Make sure ACS will be enabled during PCI probe */ 3175 pci_request_acs(); 3176 3177 return true; 3178 } 3179 3180 static __init void iommu_snp_enable(void) 3181 { 3182 #ifdef CONFIG_KVM_AMD_SEV 3183 if (!cc_platform_has(CC_ATTR_HOST_SEV_SNP)) 3184 return; 3185 /* 3186 * The SNP support requires that IOMMU must be enabled, and is 3187 * configured with V1 page table (DTE[Mode] = 0 is not supported). 3188 */ 3189 if (no_iommu || iommu_default_passthrough()) { 3190 pr_warn("SNP: IOMMU disabled or configured in passthrough mode, SNP cannot be supported.\n"); 3191 goto disable_snp; 3192 } 3193 3194 if (amd_iommu_pgtable != PD_MODE_V1) { 3195 pr_warn("SNP: IOMMU is configured with V2 page table mode, SNP cannot be supported.\n"); 3196 goto disable_snp; 3197 } 3198 3199 amd_iommu_snp_en = check_feature(FEATURE_SNP); 3200 if (!amd_iommu_snp_en) { 3201 pr_warn("SNP: IOMMU SNP feature not enabled, SNP cannot be supported.\n"); 3202 goto disable_snp; 3203 } 3204 3205 /* 3206 * Enable host SNP support once SNP support is checked on IOMMU. 3207 */ 3208 if (snp_rmptable_init()) { 3209 pr_warn("SNP: RMP initialization failed, SNP cannot be supported.\n"); 3210 goto disable_snp; 3211 } 3212 3213 pr_info("IOMMU SNP support enabled.\n"); 3214 return; 3215 3216 disable_snp: 3217 cc_platform_clear(CC_ATTR_HOST_SEV_SNP); 3218 #endif 3219 } 3220 3221 /**************************************************************************** 3222 * 3223 * AMD IOMMU Initialization State Machine 3224 * 3225 ****************************************************************************/ 3226 3227 static int __init state_next(void) 3228 { 3229 int ret = 0; 3230 3231 switch (init_state) { 3232 case IOMMU_START_STATE: 3233 if (!detect_ivrs()) { 3234 init_state = IOMMU_NOT_FOUND; 3235 ret = -ENODEV; 3236 } else { 3237 init_state = IOMMU_IVRS_DETECTED; 3238 } 3239 break; 3240 case IOMMU_IVRS_DETECTED: 3241 if (amd_iommu_disabled) { 3242 init_state = IOMMU_CMDLINE_DISABLED; 3243 ret = -EINVAL; 3244 } else { 3245 ret = early_amd_iommu_init(); 3246 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_ACPI_FINISHED; 3247 } 3248 break; 3249 case IOMMU_ACPI_FINISHED: 3250 early_enable_iommus(); 3251 x86_platform.iommu_shutdown = disable_iommus; 3252 init_state = IOMMU_ENABLED; 3253 break; 3254 case IOMMU_ENABLED: 3255 register_syscore_ops(&amd_iommu_syscore_ops); 3256 iommu_snp_enable(); 3257 ret = amd_iommu_init_pci(); 3258 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_PCI_INIT; 3259 break; 3260 case IOMMU_PCI_INIT: 3261 ret = amd_iommu_enable_interrupts(); 3262 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_INTERRUPTS_EN; 3263 break; 3264 case IOMMU_INTERRUPTS_EN: 3265 init_state = IOMMU_INITIALIZED; 3266 break; 3267 case IOMMU_INITIALIZED: 3268 /* Nothing to do */ 3269 break; 3270 case IOMMU_NOT_FOUND: 3271 case IOMMU_INIT_ERROR: 3272 case IOMMU_CMDLINE_DISABLED: 3273 /* Error states => do nothing */ 3274 ret = -EINVAL; 3275 break; 3276 default: 3277 /* Unknown state */ 3278 BUG(); 3279 } 3280 3281 if (ret) { 3282 free_dma_resources(); 3283 if (!irq_remapping_enabled) { 3284 disable_iommus(); 3285 free_iommu_resources(); 3286 } else { 3287 struct amd_iommu *iommu; 3288 struct amd_iommu_pci_seg *pci_seg; 3289 3290 for_each_pci_segment(pci_seg) 3291 uninit_device_table_dma(pci_seg); 3292 3293 for_each_iommu(iommu) 3294 amd_iommu_flush_all_caches(iommu); 3295 } 3296 } 3297 return ret; 3298 } 3299 3300 static int __init iommu_go_to_state(enum iommu_init_state state) 3301 { 3302 int ret = -EINVAL; 3303 3304 while (init_state != state) { 3305 if (init_state == IOMMU_NOT_FOUND || 3306 init_state == IOMMU_INIT_ERROR || 3307 init_state == IOMMU_CMDLINE_DISABLED) 3308 break; 3309 ret = state_next(); 3310 } 3311 3312 /* 3313 * SNP platform initilazation requires IOMMUs to be fully configured. 3314 * If the SNP support on IOMMUs has NOT been checked, simply mark SNP 3315 * as unsupported. If the SNP support on IOMMUs has been checked and 3316 * host SNP support enabled but RMP enforcement has not been enabled 3317 * in IOMMUs, then the system is in a half-baked state, but can limp 3318 * along as all memory should be Hypervisor-Owned in the RMP. WARN, 3319 * but leave SNP as "supported" to avoid confusing the kernel. 3320 */ 3321 if (ret && cc_platform_has(CC_ATTR_HOST_SEV_SNP) && 3322 !WARN_ON_ONCE(amd_iommu_snp_en)) 3323 cc_platform_clear(CC_ATTR_HOST_SEV_SNP); 3324 3325 return ret; 3326 } 3327 3328 #ifdef CONFIG_IRQ_REMAP 3329 int __init amd_iommu_prepare(void) 3330 { 3331 int ret; 3332 3333 amd_iommu_irq_remap = true; 3334 3335 ret = iommu_go_to_state(IOMMU_ACPI_FINISHED); 3336 if (ret) { 3337 amd_iommu_irq_remap = false; 3338 return ret; 3339 } 3340 3341 return amd_iommu_irq_remap ? 0 : -ENODEV; 3342 } 3343 3344 int __init amd_iommu_enable(void) 3345 { 3346 int ret; 3347 3348 ret = iommu_go_to_state(IOMMU_ENABLED); 3349 if (ret) 3350 return ret; 3351 3352 irq_remapping_enabled = 1; 3353 return amd_iommu_xt_mode; 3354 } 3355 3356 void amd_iommu_disable(void) 3357 { 3358 amd_iommu_suspend(); 3359 } 3360 3361 int amd_iommu_reenable(int mode) 3362 { 3363 amd_iommu_resume(); 3364 3365 return 0; 3366 } 3367 3368 int amd_iommu_enable_faulting(unsigned int cpu) 3369 { 3370 /* We enable MSI later when PCI is initialized */ 3371 return 0; 3372 } 3373 #endif 3374 3375 /* 3376 * This is the core init function for AMD IOMMU hardware in the system. 3377 * This function is called from the generic x86 DMA layer initialization 3378 * code. 3379 */ 3380 static int __init amd_iommu_init(void) 3381 { 3382 struct amd_iommu *iommu; 3383 int ret; 3384 3385 ret = iommu_go_to_state(IOMMU_INITIALIZED); 3386 #ifdef CONFIG_GART_IOMMU 3387 if (ret && list_empty(&amd_iommu_list)) { 3388 /* 3389 * We failed to initialize the AMD IOMMU - try fallback 3390 * to GART if possible. 3391 */ 3392 gart_iommu_init(); 3393 } 3394 #endif 3395 3396 for_each_iommu(iommu) 3397 amd_iommu_debugfs_setup(iommu); 3398 3399 return ret; 3400 } 3401 3402 static bool amd_iommu_sme_check(void) 3403 { 3404 if (!cc_platform_has(CC_ATTR_HOST_MEM_ENCRYPT) || 3405 (boot_cpu_data.x86 != 0x17)) 3406 return true; 3407 3408 /* For Fam17h, a specific level of support is required */ 3409 if (boot_cpu_data.microcode >= 0x08001205) 3410 return true; 3411 3412 if ((boot_cpu_data.microcode >= 0x08001126) && 3413 (boot_cpu_data.microcode <= 0x080011ff)) 3414 return true; 3415 3416 pr_notice("IOMMU not currently supported when SME is active\n"); 3417 3418 return false; 3419 } 3420 3421 /**************************************************************************** 3422 * 3423 * Early detect code. This code runs at IOMMU detection time in the DMA 3424 * layer. It just looks if there is an IVRS ACPI table to detect AMD 3425 * IOMMUs 3426 * 3427 ****************************************************************************/ 3428 void __init amd_iommu_detect(void) 3429 { 3430 int ret; 3431 3432 if (no_iommu || (iommu_detected && !gart_iommu_aperture)) 3433 goto disable_snp; 3434 3435 if (!amd_iommu_sme_check()) 3436 goto disable_snp; 3437 3438 ret = iommu_go_to_state(IOMMU_IVRS_DETECTED); 3439 if (ret) 3440 goto disable_snp; 3441 3442 amd_iommu_detected = true; 3443 iommu_detected = 1; 3444 x86_init.iommu.iommu_init = amd_iommu_init; 3445 return; 3446 3447 disable_snp: 3448 if (cc_platform_has(CC_ATTR_HOST_SEV_SNP)) 3449 cc_platform_clear(CC_ATTR_HOST_SEV_SNP); 3450 } 3451 3452 /**************************************************************************** 3453 * 3454 * Parsing functions for the AMD IOMMU specific kernel command line 3455 * options. 3456 * 3457 ****************************************************************************/ 3458 3459 static int __init parse_amd_iommu_dump(char *str) 3460 { 3461 amd_iommu_dump = true; 3462 3463 return 1; 3464 } 3465 3466 static int __init parse_amd_iommu_intr(char *str) 3467 { 3468 for (; *str; ++str) { 3469 if (strncmp(str, "legacy", 6) == 0) { 3470 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY_GA; 3471 break; 3472 } 3473 if (strncmp(str, "vapic", 5) == 0) { 3474 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC; 3475 break; 3476 } 3477 } 3478 return 1; 3479 } 3480 3481 static int __init parse_amd_iommu_options(char *str) 3482 { 3483 if (!str) 3484 return -EINVAL; 3485 3486 while (*str) { 3487 if (strncmp(str, "fullflush", 9) == 0) { 3488 pr_warn("amd_iommu=fullflush deprecated; use iommu.strict=1 instead\n"); 3489 iommu_set_dma_strict(); 3490 } else if (strncmp(str, "force_enable", 12) == 0) { 3491 amd_iommu_force_enable = true; 3492 } else if (strncmp(str, "off", 3) == 0) { 3493 amd_iommu_disabled = true; 3494 } else if (strncmp(str, "force_isolation", 15) == 0) { 3495 amd_iommu_force_isolation = true; 3496 } else if (strncmp(str, "pgtbl_v1", 8) == 0) { 3497 amd_iommu_pgtable = PD_MODE_V1; 3498 } else if (strncmp(str, "pgtbl_v2", 8) == 0) { 3499 amd_iommu_pgtable = PD_MODE_V2; 3500 } else if (strncmp(str, "irtcachedis", 11) == 0) { 3501 amd_iommu_irtcachedis = true; 3502 } else if (strncmp(str, "nohugepages", 11) == 0) { 3503 pr_info("Restricting V1 page-sizes to 4KiB"); 3504 amd_iommu_pgsize_bitmap = AMD_IOMMU_PGSIZES_4K; 3505 } else if (strncmp(str, "v2_pgsizes_only", 15) == 0) { 3506 pr_info("Restricting V1 page-sizes to 4KiB/2MiB/1GiB"); 3507 amd_iommu_pgsize_bitmap = AMD_IOMMU_PGSIZES_V2; 3508 } else { 3509 pr_notice("Unknown option - '%s'\n", str); 3510 } 3511 3512 str += strcspn(str, ","); 3513 while (*str == ',') 3514 str++; 3515 } 3516 3517 return 1; 3518 } 3519 3520 static int __init parse_ivrs_ioapic(char *str) 3521 { 3522 u32 seg = 0, bus, dev, fn; 3523 int id, i; 3524 u32 devid; 3525 3526 if (sscanf(str, "=%d@%x:%x.%x", &id, &bus, &dev, &fn) == 4 || 3527 sscanf(str, "=%d@%x:%x:%x.%x", &id, &seg, &bus, &dev, &fn) == 5) 3528 goto found; 3529 3530 if (sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn) == 4 || 3531 sscanf(str, "[%d]=%x:%x:%x.%x", &id, &seg, &bus, &dev, &fn) == 5) { 3532 pr_warn("ivrs_ioapic%s option format deprecated; use ivrs_ioapic=%d@%04x:%02x:%02x.%d instead\n", 3533 str, id, seg, bus, dev, fn); 3534 goto found; 3535 } 3536 3537 pr_err("Invalid command line: ivrs_ioapic%s\n", str); 3538 return 1; 3539 3540 found: 3541 if (early_ioapic_map_size == EARLY_MAP_SIZE) { 3542 pr_err("Early IOAPIC map overflow - ignoring ivrs_ioapic%s\n", 3543 str); 3544 return 1; 3545 } 3546 3547 devid = IVRS_GET_SBDF_ID(seg, bus, dev, fn); 3548 3549 cmdline_maps = true; 3550 i = early_ioapic_map_size++; 3551 early_ioapic_map[i].id = id; 3552 early_ioapic_map[i].devid = devid; 3553 early_ioapic_map[i].cmd_line = true; 3554 3555 return 1; 3556 } 3557 3558 static int __init parse_ivrs_hpet(char *str) 3559 { 3560 u32 seg = 0, bus, dev, fn; 3561 int id, i; 3562 u32 devid; 3563 3564 if (sscanf(str, "=%d@%x:%x.%x", &id, &bus, &dev, &fn) == 4 || 3565 sscanf(str, "=%d@%x:%x:%x.%x", &id, &seg, &bus, &dev, &fn) == 5) 3566 goto found; 3567 3568 if (sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn) == 4 || 3569 sscanf(str, "[%d]=%x:%x:%x.%x", &id, &seg, &bus, &dev, &fn) == 5) { 3570 pr_warn("ivrs_hpet%s option format deprecated; use ivrs_hpet=%d@%04x:%02x:%02x.%d instead\n", 3571 str, id, seg, bus, dev, fn); 3572 goto found; 3573 } 3574 3575 pr_err("Invalid command line: ivrs_hpet%s\n", str); 3576 return 1; 3577 3578 found: 3579 if (early_hpet_map_size == EARLY_MAP_SIZE) { 3580 pr_err("Early HPET map overflow - ignoring ivrs_hpet%s\n", 3581 str); 3582 return 1; 3583 } 3584 3585 devid = IVRS_GET_SBDF_ID(seg, bus, dev, fn); 3586 3587 cmdline_maps = true; 3588 i = early_hpet_map_size++; 3589 early_hpet_map[i].id = id; 3590 early_hpet_map[i].devid = devid; 3591 early_hpet_map[i].cmd_line = true; 3592 3593 return 1; 3594 } 3595 3596 #define ACPIID_LEN (ACPIHID_UID_LEN + ACPIHID_HID_LEN) 3597 3598 static int __init parse_ivrs_acpihid(char *str) 3599 { 3600 u32 seg = 0, bus, dev, fn; 3601 char *hid, *uid, *p, *addr; 3602 char acpiid[ACPIID_LEN] = {0}; 3603 int i; 3604 3605 addr = strchr(str, '@'); 3606 if (!addr) { 3607 addr = strchr(str, '='); 3608 if (!addr) 3609 goto not_found; 3610 3611 ++addr; 3612 3613 if (strlen(addr) > ACPIID_LEN) 3614 goto not_found; 3615 3616 if (sscanf(str, "[%x:%x.%x]=%s", &bus, &dev, &fn, acpiid) == 4 || 3617 sscanf(str, "[%x:%x:%x.%x]=%s", &seg, &bus, &dev, &fn, acpiid) == 5) { 3618 pr_warn("ivrs_acpihid%s option format deprecated; use ivrs_acpihid=%s@%04x:%02x:%02x.%d instead\n", 3619 str, acpiid, seg, bus, dev, fn); 3620 goto found; 3621 } 3622 goto not_found; 3623 } 3624 3625 /* We have the '@', make it the terminator to get just the acpiid */ 3626 *addr++ = 0; 3627 3628 if (strlen(str) > ACPIID_LEN + 1) 3629 goto not_found; 3630 3631 if (sscanf(str, "=%s", acpiid) != 1) 3632 goto not_found; 3633 3634 if (sscanf(addr, "%x:%x.%x", &bus, &dev, &fn) == 3 || 3635 sscanf(addr, "%x:%x:%x.%x", &seg, &bus, &dev, &fn) == 4) 3636 goto found; 3637 3638 not_found: 3639 pr_err("Invalid command line: ivrs_acpihid%s\n", str); 3640 return 1; 3641 3642 found: 3643 p = acpiid; 3644 hid = strsep(&p, ":"); 3645 uid = p; 3646 3647 if (!hid || !(*hid) || !uid) { 3648 pr_err("Invalid command line: hid or uid\n"); 3649 return 1; 3650 } 3651 3652 /* 3653 * Ignore leading zeroes after ':', so e.g., AMDI0095:00 3654 * will match AMDI0095:0 in the second strcmp in acpi_dev_hid_uid_match 3655 */ 3656 while (*uid == '0' && *(uid + 1)) 3657 uid++; 3658 3659 if (strlen(hid) >= ACPIHID_HID_LEN) { 3660 pr_err("Invalid command line: hid is too long\n"); 3661 return 1; 3662 } else if (strlen(uid) >= ACPIHID_UID_LEN) { 3663 pr_err("Invalid command line: uid is too long\n"); 3664 return 1; 3665 } 3666 3667 i = early_acpihid_map_size++; 3668 memcpy(early_acpihid_map[i].hid, hid, strlen(hid)); 3669 memcpy(early_acpihid_map[i].uid, uid, strlen(uid)); 3670 early_acpihid_map[i].devid = IVRS_GET_SBDF_ID(seg, bus, dev, fn); 3671 early_acpihid_map[i].cmd_line = true; 3672 3673 return 1; 3674 } 3675 3676 __setup("amd_iommu_dump", parse_amd_iommu_dump); 3677 __setup("amd_iommu=", parse_amd_iommu_options); 3678 __setup("amd_iommu_intr=", parse_amd_iommu_intr); 3679 __setup("ivrs_ioapic", parse_ivrs_ioapic); 3680 __setup("ivrs_hpet", parse_ivrs_hpet); 3681 __setup("ivrs_acpihid", parse_ivrs_acpihid); 3682 3683 bool amd_iommu_pasid_supported(void) 3684 { 3685 /* CPU page table size should match IOMMU guest page table size */ 3686 if (cpu_feature_enabled(X86_FEATURE_LA57) && 3687 amd_iommu_gpt_level != PAGE_MODE_5_LEVEL) 3688 return false; 3689 3690 /* 3691 * Since DTE[Mode]=0 is prohibited on SNP-enabled system 3692 * (i.e. EFR[SNPSup]=1), IOMMUv2 page table cannot be used without 3693 * setting up IOMMUv1 page table. 3694 */ 3695 return amd_iommu_gt_ppr_supported() && !amd_iommu_snp_en; 3696 } 3697 3698 struct amd_iommu *get_amd_iommu(unsigned int idx) 3699 { 3700 unsigned int i = 0; 3701 struct amd_iommu *iommu; 3702 3703 for_each_iommu(iommu) 3704 if (i++ == idx) 3705 return iommu; 3706 return NULL; 3707 } 3708 3709 /**************************************************************************** 3710 * 3711 * IOMMU EFR Performance Counter support functionality. This code allows 3712 * access to the IOMMU PC functionality. 3713 * 3714 ****************************************************************************/ 3715 3716 u8 amd_iommu_pc_get_max_banks(unsigned int idx) 3717 { 3718 struct amd_iommu *iommu = get_amd_iommu(idx); 3719 3720 if (iommu) 3721 return iommu->max_banks; 3722 3723 return 0; 3724 } 3725 3726 bool amd_iommu_pc_supported(void) 3727 { 3728 return amd_iommu_pc_present; 3729 } 3730 3731 u8 amd_iommu_pc_get_max_counters(unsigned int idx) 3732 { 3733 struct amd_iommu *iommu = get_amd_iommu(idx); 3734 3735 if (iommu) 3736 return iommu->max_counters; 3737 3738 return 0; 3739 } 3740 3741 static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, 3742 u8 fxn, u64 *value, bool is_write) 3743 { 3744 u32 offset; 3745 u32 max_offset_lim; 3746 3747 /* Make sure the IOMMU PC resource is available */ 3748 if (!amd_iommu_pc_present) 3749 return -ENODEV; 3750 3751 /* Check for valid iommu and pc register indexing */ 3752 if (WARN_ON(!iommu || (fxn > 0x28) || (fxn & 7))) 3753 return -ENODEV; 3754 3755 offset = (u32)(((0x40 | bank) << 12) | (cntr << 8) | fxn); 3756 3757 /* Limit the offset to the hw defined mmio region aperture */ 3758 max_offset_lim = (u32)(((0x40 | iommu->max_banks) << 12) | 3759 (iommu->max_counters << 8) | 0x28); 3760 if ((offset < MMIO_CNTR_REG_OFFSET) || 3761 (offset > max_offset_lim)) 3762 return -EINVAL; 3763 3764 if (is_write) { 3765 u64 val = *value & GENMASK_ULL(47, 0); 3766 3767 writel((u32)val, iommu->mmio_base + offset); 3768 writel((val >> 32), iommu->mmio_base + offset + 4); 3769 } else { 3770 *value = readl(iommu->mmio_base + offset + 4); 3771 *value <<= 32; 3772 *value |= readl(iommu->mmio_base + offset); 3773 *value &= GENMASK_ULL(47, 0); 3774 } 3775 3776 return 0; 3777 } 3778 3779 int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value) 3780 { 3781 if (!iommu) 3782 return -EINVAL; 3783 3784 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, false); 3785 } 3786 3787 int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value) 3788 { 3789 if (!iommu) 3790 return -EINVAL; 3791 3792 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, true); 3793 } 3794 3795 #ifdef CONFIG_KVM_AMD_SEV 3796 static int iommu_page_make_shared(void *page) 3797 { 3798 unsigned long paddr, pfn; 3799 3800 paddr = iommu_virt_to_phys(page); 3801 /* Cbit maybe set in the paddr */ 3802 pfn = __sme_clr(paddr) >> PAGE_SHIFT; 3803 3804 if (!(pfn % PTRS_PER_PMD)) { 3805 int ret, level; 3806 bool assigned; 3807 3808 ret = snp_lookup_rmpentry(pfn, &assigned, &level); 3809 if (ret) { 3810 pr_warn("IOMMU PFN %lx RMP lookup failed, ret %d\n", pfn, ret); 3811 return ret; 3812 } 3813 3814 if (!assigned) { 3815 pr_warn("IOMMU PFN %lx not assigned in RMP table\n", pfn); 3816 return -EINVAL; 3817 } 3818 3819 if (level > PG_LEVEL_4K) { 3820 ret = psmash(pfn); 3821 if (!ret) 3822 goto done; 3823 3824 pr_warn("PSMASH failed for IOMMU PFN %lx huge RMP entry, ret: %d, level: %d\n", 3825 pfn, ret, level); 3826 return ret; 3827 } 3828 } 3829 3830 done: 3831 return rmp_make_shared(pfn, PG_LEVEL_4K); 3832 } 3833 3834 static int iommu_make_shared(void *va, size_t size) 3835 { 3836 void *page; 3837 int ret; 3838 3839 if (!va) 3840 return 0; 3841 3842 for (page = va; page < (va + size); page += PAGE_SIZE) { 3843 ret = iommu_page_make_shared(page); 3844 if (ret) 3845 return ret; 3846 } 3847 3848 return 0; 3849 } 3850 3851 int amd_iommu_snp_disable(void) 3852 { 3853 struct amd_iommu *iommu; 3854 int ret; 3855 3856 if (!amd_iommu_snp_en) 3857 return 0; 3858 3859 for_each_iommu(iommu) { 3860 ret = iommu_make_shared(iommu->evt_buf, EVT_BUFFER_SIZE); 3861 if (ret) 3862 return ret; 3863 3864 ret = iommu_make_shared(iommu->ppr_log, PPR_LOG_SIZE); 3865 if (ret) 3866 return ret; 3867 3868 ret = iommu_make_shared((void *)iommu->cmd_sem, PAGE_SIZE); 3869 if (ret) 3870 return ret; 3871 } 3872 3873 return 0; 3874 } 3875 EXPORT_SYMBOL_GPL(amd_iommu_snp_disable); 3876 #endif 3877