1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. 4 * Author: Joerg Roedel <jroedel@suse.de> 5 * Leo Duran <leo.duran@amd.com> 6 */ 7 8 #define pr_fmt(fmt) "AMD-Vi: " fmt 9 #define dev_fmt(fmt) pr_fmt(fmt) 10 11 #include <linux/pci.h> 12 #include <linux/acpi.h> 13 #include <linux/list.h> 14 #include <linux/bitmap.h> 15 #include <linux/slab.h> 16 #include <linux/syscore_ops.h> 17 #include <linux/interrupt.h> 18 #include <linux/msi.h> 19 #include <linux/irq.h> 20 #include <linux/amd-iommu.h> 21 #include <linux/export.h> 22 #include <linux/kmemleak.h> 23 #include <linux/cc_platform.h> 24 #include <linux/iopoll.h> 25 #include <asm/pci-direct.h> 26 #include <asm/iommu.h> 27 #include <asm/apic.h> 28 #include <asm/gart.h> 29 #include <asm/x86_init.h> 30 #include <asm/io_apic.h> 31 #include <asm/irq_remapping.h> 32 #include <asm/set_memory.h> 33 #include <asm/sev.h> 34 35 #include <linux/crash_dump.h> 36 37 #include "amd_iommu.h" 38 #include "../irq_remapping.h" 39 #include "../iommu-pages.h" 40 41 /* 42 * definitions for the ACPI scanning code 43 */ 44 #define IVRS_HEADER_LENGTH 48 45 46 #define ACPI_IVHD_TYPE_MAX_SUPPORTED 0x40 47 #define ACPI_IVMD_TYPE_ALL 0x20 48 #define ACPI_IVMD_TYPE 0x21 49 #define ACPI_IVMD_TYPE_RANGE 0x22 50 51 #define IVHD_DEV_ALL 0x01 52 #define IVHD_DEV_SELECT 0x02 53 #define IVHD_DEV_SELECT_RANGE_START 0x03 54 #define IVHD_DEV_RANGE_END 0x04 55 #define IVHD_DEV_ALIAS 0x42 56 #define IVHD_DEV_ALIAS_RANGE 0x43 57 #define IVHD_DEV_EXT_SELECT 0x46 58 #define IVHD_DEV_EXT_SELECT_RANGE 0x47 59 #define IVHD_DEV_SPECIAL 0x48 60 #define IVHD_DEV_ACPI_HID 0xf0 61 62 #define UID_NOT_PRESENT 0 63 #define UID_IS_INTEGER 1 64 #define UID_IS_CHARACTER 2 65 66 #define IVHD_SPECIAL_IOAPIC 1 67 #define IVHD_SPECIAL_HPET 2 68 69 #define IVHD_FLAG_HT_TUN_EN_MASK 0x01 70 #define IVHD_FLAG_PASSPW_EN_MASK 0x02 71 #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04 72 #define IVHD_FLAG_ISOC_EN_MASK 0x08 73 74 #define IVMD_FLAG_EXCL_RANGE 0x08 75 #define IVMD_FLAG_IW 0x04 76 #define IVMD_FLAG_IR 0x02 77 #define IVMD_FLAG_UNITY_MAP 0x01 78 79 #define ACPI_DEVFLAG_INITPASS 0x01 80 #define ACPI_DEVFLAG_EXTINT 0x02 81 #define ACPI_DEVFLAG_NMI 0x04 82 #define ACPI_DEVFLAG_SYSMGT1 0x10 83 #define ACPI_DEVFLAG_SYSMGT2 0x20 84 #define ACPI_DEVFLAG_LINT0 0x40 85 #define ACPI_DEVFLAG_LINT1 0x80 86 #define ACPI_DEVFLAG_ATSDIS 0x10000000 87 88 #define IVRS_GET_SBDF_ID(seg, bus, dev, fn) (((seg & 0xffff) << 16) | ((bus & 0xff) << 8) \ 89 | ((dev & 0x1f) << 3) | (fn & 0x7)) 90 91 /* 92 * ACPI table definitions 93 * 94 * These data structures are laid over the table to parse the important values 95 * out of it. 96 */ 97 98 /* 99 * structure describing one IOMMU in the ACPI table. Typically followed by one 100 * or more ivhd_entrys. 101 */ 102 struct ivhd_header { 103 u8 type; 104 u8 flags; 105 u16 length; 106 u16 devid; 107 u16 cap_ptr; 108 u64 mmio_phys; 109 u16 pci_seg; 110 u16 info; 111 u32 efr_attr; 112 113 /* Following only valid on IVHD type 11h and 40h */ 114 u64 efr_reg; /* Exact copy of MMIO_EXT_FEATURES */ 115 u64 efr_reg2; 116 } __attribute__((packed)); 117 118 /* 119 * A device entry describing which devices a specific IOMMU translates and 120 * which requestor ids they use. 121 */ 122 struct ivhd_entry { 123 u8 type; 124 u16 devid; 125 u8 flags; 126 struct_group(ext_hid, 127 u32 ext; 128 u32 hidh; 129 ); 130 u64 cid; 131 u8 uidf; 132 u8 uidl; 133 u8 uid; 134 } __attribute__((packed)); 135 136 /* 137 * An AMD IOMMU memory definition structure. It defines things like exclusion 138 * ranges for devices and regions that should be unity mapped. 139 */ 140 struct ivmd_header { 141 u8 type; 142 u8 flags; 143 u16 length; 144 u16 devid; 145 u16 aux; 146 u16 pci_seg; 147 u8 resv[6]; 148 u64 range_start; 149 u64 range_length; 150 } __attribute__((packed)); 151 152 bool amd_iommu_dump; 153 bool amd_iommu_irq_remap __read_mostly; 154 155 enum io_pgtable_fmt amd_iommu_pgtable = AMD_IOMMU_V1; 156 /* Guest page table level */ 157 int amd_iommu_gpt_level = PAGE_MODE_4_LEVEL; 158 159 int amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC; 160 static int amd_iommu_xt_mode = IRQ_REMAP_XAPIC_MODE; 161 162 static bool amd_iommu_detected; 163 static bool amd_iommu_disabled __initdata; 164 static bool amd_iommu_force_enable __initdata; 165 static bool amd_iommu_irtcachedis; 166 static int amd_iommu_target_ivhd_type; 167 168 /* Global EFR and EFR2 registers */ 169 u64 amd_iommu_efr; 170 u64 amd_iommu_efr2; 171 172 /* SNP is enabled on the system? */ 173 bool amd_iommu_snp_en; 174 EXPORT_SYMBOL(amd_iommu_snp_en); 175 176 LIST_HEAD(amd_iommu_pci_seg_list); /* list of all PCI segments */ 177 LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the 178 system */ 179 180 /* Number of IOMMUs present in the system */ 181 static int amd_iommus_present; 182 183 /* IOMMUs have a non-present cache? */ 184 bool amd_iommu_np_cache __read_mostly; 185 bool amd_iommu_iotlb_sup __read_mostly = true; 186 187 static bool amd_iommu_pc_present __read_mostly; 188 bool amdr_ivrs_remap_support __read_mostly; 189 190 bool amd_iommu_force_isolation __read_mostly; 191 192 unsigned long amd_iommu_pgsize_bitmap __ro_after_init = AMD_IOMMU_PGSIZES; 193 194 enum iommu_init_state { 195 IOMMU_START_STATE, 196 IOMMU_IVRS_DETECTED, 197 IOMMU_ACPI_FINISHED, 198 IOMMU_ENABLED, 199 IOMMU_PCI_INIT, 200 IOMMU_INTERRUPTS_EN, 201 IOMMU_INITIALIZED, 202 IOMMU_NOT_FOUND, 203 IOMMU_INIT_ERROR, 204 IOMMU_CMDLINE_DISABLED, 205 }; 206 207 /* Early ioapic and hpet maps from kernel command line */ 208 #define EARLY_MAP_SIZE 4 209 static struct devid_map __initdata early_ioapic_map[EARLY_MAP_SIZE]; 210 static struct devid_map __initdata early_hpet_map[EARLY_MAP_SIZE]; 211 static struct acpihid_map_entry __initdata early_acpihid_map[EARLY_MAP_SIZE]; 212 213 static int __initdata early_ioapic_map_size; 214 static int __initdata early_hpet_map_size; 215 static int __initdata early_acpihid_map_size; 216 217 static bool __initdata cmdline_maps; 218 219 static enum iommu_init_state init_state = IOMMU_START_STATE; 220 221 static int amd_iommu_enable_interrupts(void); 222 static int __init iommu_go_to_state(enum iommu_init_state state); 223 static void init_device_table_dma(struct amd_iommu_pci_seg *pci_seg); 224 225 static bool amd_iommu_pre_enabled = true; 226 227 static u32 amd_iommu_ivinfo __initdata; 228 229 bool translation_pre_enabled(struct amd_iommu *iommu) 230 { 231 return (iommu->flags & AMD_IOMMU_FLAG_TRANS_PRE_ENABLED); 232 } 233 234 static void clear_translation_pre_enabled(struct amd_iommu *iommu) 235 { 236 iommu->flags &= ~AMD_IOMMU_FLAG_TRANS_PRE_ENABLED; 237 } 238 239 static void init_translation_status(struct amd_iommu *iommu) 240 { 241 u64 ctrl; 242 243 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); 244 if (ctrl & (1<<CONTROL_IOMMU_EN)) 245 iommu->flags |= AMD_IOMMU_FLAG_TRANS_PRE_ENABLED; 246 } 247 248 static inline unsigned long tbl_size(int entry_size, int last_bdf) 249 { 250 unsigned shift = PAGE_SHIFT + 251 get_order((last_bdf + 1) * entry_size); 252 253 return 1UL << shift; 254 } 255 256 int amd_iommu_get_num_iommus(void) 257 { 258 return amd_iommus_present; 259 } 260 261 /* 262 * Iterate through all the IOMMUs to get common EFR 263 * masks among all IOMMUs and warn if found inconsistency. 264 */ 265 static __init void get_global_efr(void) 266 { 267 struct amd_iommu *iommu; 268 269 for_each_iommu(iommu) { 270 u64 tmp = iommu->features; 271 u64 tmp2 = iommu->features2; 272 273 if (list_is_first(&iommu->list, &amd_iommu_list)) { 274 amd_iommu_efr = tmp; 275 amd_iommu_efr2 = tmp2; 276 continue; 277 } 278 279 if (amd_iommu_efr == tmp && 280 amd_iommu_efr2 == tmp2) 281 continue; 282 283 pr_err(FW_BUG 284 "Found inconsistent EFR/EFR2 %#llx,%#llx (global %#llx,%#llx) on iommu%d (%04x:%02x:%02x.%01x).\n", 285 tmp, tmp2, amd_iommu_efr, amd_iommu_efr2, 286 iommu->index, iommu->pci_seg->id, 287 PCI_BUS_NUM(iommu->devid), PCI_SLOT(iommu->devid), 288 PCI_FUNC(iommu->devid)); 289 290 amd_iommu_efr &= tmp; 291 amd_iommu_efr2 &= tmp2; 292 } 293 294 pr_info("Using global IVHD EFR:%#llx, EFR2:%#llx\n", amd_iommu_efr, amd_iommu_efr2); 295 } 296 297 /* 298 * For IVHD type 0x11/0x40, EFR is also available via IVHD. 299 * Default to IVHD EFR since it is available sooner 300 * (i.e. before PCI init). 301 */ 302 static void __init early_iommu_features_init(struct amd_iommu *iommu, 303 struct ivhd_header *h) 304 { 305 if (amd_iommu_ivinfo & IOMMU_IVINFO_EFRSUP) { 306 iommu->features = h->efr_reg; 307 iommu->features2 = h->efr_reg2; 308 } 309 if (amd_iommu_ivinfo & IOMMU_IVINFO_DMA_REMAP) 310 amdr_ivrs_remap_support = true; 311 } 312 313 /* Access to l1 and l2 indexed register spaces */ 314 315 static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address) 316 { 317 u32 val; 318 319 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16)); 320 pci_read_config_dword(iommu->dev, 0xfc, &val); 321 return val; 322 } 323 324 static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val) 325 { 326 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31)); 327 pci_write_config_dword(iommu->dev, 0xfc, val); 328 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16)); 329 } 330 331 static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address) 332 { 333 u32 val; 334 335 pci_write_config_dword(iommu->dev, 0xf0, address); 336 pci_read_config_dword(iommu->dev, 0xf4, &val); 337 return val; 338 } 339 340 static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val) 341 { 342 pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8)); 343 pci_write_config_dword(iommu->dev, 0xf4, val); 344 } 345 346 /**************************************************************************** 347 * 348 * AMD IOMMU MMIO register space handling functions 349 * 350 * These functions are used to program the IOMMU device registers in 351 * MMIO space required for that driver. 352 * 353 ****************************************************************************/ 354 355 /* 356 * This function set the exclusion range in the IOMMU. DMA accesses to the 357 * exclusion range are passed through untranslated 358 */ 359 static void iommu_set_exclusion_range(struct amd_iommu *iommu) 360 { 361 u64 start = iommu->exclusion_start & PAGE_MASK; 362 u64 limit = (start + iommu->exclusion_length - 1) & PAGE_MASK; 363 u64 entry; 364 365 if (!iommu->exclusion_start) 366 return; 367 368 entry = start | MMIO_EXCL_ENABLE_MASK; 369 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, 370 &entry, sizeof(entry)); 371 372 entry = limit; 373 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, 374 &entry, sizeof(entry)); 375 } 376 377 static void iommu_set_cwwb_range(struct amd_iommu *iommu) 378 { 379 u64 start = iommu_virt_to_phys((void *)iommu->cmd_sem); 380 u64 entry = start & PM_ADDR_MASK; 381 382 if (!check_feature(FEATURE_SNP)) 383 return; 384 385 /* Note: 386 * Re-purpose Exclusion base/limit registers for Completion wait 387 * write-back base/limit. 388 */ 389 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, 390 &entry, sizeof(entry)); 391 392 /* Note: 393 * Default to 4 Kbytes, which can be specified by setting base 394 * address equal to the limit address. 395 */ 396 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, 397 &entry, sizeof(entry)); 398 } 399 400 /* Programs the physical address of the device table into the IOMMU hardware */ 401 static void iommu_set_device_table(struct amd_iommu *iommu) 402 { 403 u64 entry; 404 u32 dev_table_size = iommu->pci_seg->dev_table_size; 405 void *dev_table = (void *)get_dev_table(iommu); 406 407 BUG_ON(iommu->mmio_base == NULL); 408 409 entry = iommu_virt_to_phys(dev_table); 410 entry |= (dev_table_size >> 12) - 1; 411 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET, 412 &entry, sizeof(entry)); 413 } 414 415 /* Generic functions to enable/disable certain features of the IOMMU. */ 416 void iommu_feature_enable(struct amd_iommu *iommu, u8 bit) 417 { 418 u64 ctrl; 419 420 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); 421 ctrl |= (1ULL << bit); 422 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); 423 } 424 425 static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit) 426 { 427 u64 ctrl; 428 429 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); 430 ctrl &= ~(1ULL << bit); 431 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); 432 } 433 434 static void iommu_set_inv_tlb_timeout(struct amd_iommu *iommu, int timeout) 435 { 436 u64 ctrl; 437 438 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); 439 ctrl &= ~CTRL_INV_TO_MASK; 440 ctrl |= (timeout << CONTROL_INV_TIMEOUT) & CTRL_INV_TO_MASK; 441 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); 442 } 443 444 /* Function to enable the hardware */ 445 static void iommu_enable(struct amd_iommu *iommu) 446 { 447 iommu_feature_enable(iommu, CONTROL_IOMMU_EN); 448 } 449 450 static void iommu_disable(struct amd_iommu *iommu) 451 { 452 if (!iommu->mmio_base) 453 return; 454 455 /* Disable command buffer */ 456 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); 457 458 /* Disable event logging and event interrupts */ 459 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN); 460 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN); 461 462 /* Disable IOMMU GA_LOG */ 463 iommu_feature_disable(iommu, CONTROL_GALOG_EN); 464 iommu_feature_disable(iommu, CONTROL_GAINT_EN); 465 466 /* Disable IOMMU PPR logging */ 467 iommu_feature_disable(iommu, CONTROL_PPRLOG_EN); 468 iommu_feature_disable(iommu, CONTROL_PPRINT_EN); 469 470 /* Disable IOMMU hardware itself */ 471 iommu_feature_disable(iommu, CONTROL_IOMMU_EN); 472 473 /* Clear IRTE cache disabling bit */ 474 iommu_feature_disable(iommu, CONTROL_IRTCACHEDIS); 475 } 476 477 /* 478 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in 479 * the system has one. 480 */ 481 static u8 __iomem * __init iommu_map_mmio_space(u64 address, u64 end) 482 { 483 if (!request_mem_region(address, end, "amd_iommu")) { 484 pr_err("Can not reserve memory region %llx-%llx for mmio\n", 485 address, end); 486 pr_err("This is a BIOS bug. Please contact your hardware vendor\n"); 487 return NULL; 488 } 489 490 return (u8 __iomem *)ioremap(address, end); 491 } 492 493 static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu) 494 { 495 if (iommu->mmio_base) 496 iounmap(iommu->mmio_base); 497 release_mem_region(iommu->mmio_phys, iommu->mmio_phys_end); 498 } 499 500 static inline u32 get_ivhd_header_size(struct ivhd_header *h) 501 { 502 u32 size = 0; 503 504 switch (h->type) { 505 case 0x10: 506 size = 24; 507 break; 508 case 0x11: 509 case 0x40: 510 size = 40; 511 break; 512 } 513 return size; 514 } 515 516 /**************************************************************************** 517 * 518 * The functions below belong to the first pass of AMD IOMMU ACPI table 519 * parsing. In this pass we try to find out the highest device id this 520 * code has to handle. Upon this information the size of the shared data 521 * structures is determined later. 522 * 523 ****************************************************************************/ 524 525 /* 526 * This function calculates the length of a given IVHD entry 527 */ 528 static inline int ivhd_entry_length(u8 *ivhd) 529 { 530 u32 type = ((struct ivhd_entry *)ivhd)->type; 531 532 if (type < 0x80) { 533 return 0x04 << (*ivhd >> 6); 534 } else if (type == IVHD_DEV_ACPI_HID) { 535 /* For ACPI_HID, offset 21 is uid len */ 536 return *((u8 *)ivhd + 21) + 22; 537 } 538 return 0; 539 } 540 541 /* 542 * After reading the highest device id from the IOMMU PCI capability header 543 * this function looks if there is a higher device id defined in the ACPI table 544 */ 545 static int __init find_last_devid_from_ivhd(struct ivhd_header *h) 546 { 547 u8 *p = (void *)h, *end = (void *)h; 548 struct ivhd_entry *dev; 549 int last_devid = -EINVAL; 550 551 u32 ivhd_size = get_ivhd_header_size(h); 552 553 if (!ivhd_size) { 554 pr_err("Unsupported IVHD type %#x\n", h->type); 555 return -EINVAL; 556 } 557 558 p += ivhd_size; 559 end += h->length; 560 561 while (p < end) { 562 dev = (struct ivhd_entry *)p; 563 switch (dev->type) { 564 case IVHD_DEV_ALL: 565 /* Use maximum BDF value for DEV_ALL */ 566 return 0xffff; 567 case IVHD_DEV_SELECT: 568 case IVHD_DEV_RANGE_END: 569 case IVHD_DEV_ALIAS: 570 case IVHD_DEV_EXT_SELECT: 571 /* all the above subfield types refer to device ids */ 572 if (dev->devid > last_devid) 573 last_devid = dev->devid; 574 break; 575 default: 576 break; 577 } 578 p += ivhd_entry_length(p); 579 } 580 581 WARN_ON(p != end); 582 583 return last_devid; 584 } 585 586 static int __init check_ivrs_checksum(struct acpi_table_header *table) 587 { 588 int i; 589 u8 checksum = 0, *p = (u8 *)table; 590 591 for (i = 0; i < table->length; ++i) 592 checksum += p[i]; 593 if (checksum != 0) { 594 /* ACPI table corrupt */ 595 pr_err(FW_BUG "IVRS invalid checksum\n"); 596 return -ENODEV; 597 } 598 599 return 0; 600 } 601 602 /* 603 * Iterate over all IVHD entries in the ACPI table and find the highest device 604 * id which we need to handle. This is the first of three functions which parse 605 * the ACPI table. So we check the checksum here. 606 */ 607 static int __init find_last_devid_acpi(struct acpi_table_header *table, u16 pci_seg) 608 { 609 u8 *p = (u8 *)table, *end = (u8 *)table; 610 struct ivhd_header *h; 611 int last_devid, last_bdf = 0; 612 613 p += IVRS_HEADER_LENGTH; 614 615 end += table->length; 616 while (p < end) { 617 h = (struct ivhd_header *)p; 618 if (h->pci_seg == pci_seg && 619 h->type == amd_iommu_target_ivhd_type) { 620 last_devid = find_last_devid_from_ivhd(h); 621 622 if (last_devid < 0) 623 return -EINVAL; 624 if (last_devid > last_bdf) 625 last_bdf = last_devid; 626 } 627 p += h->length; 628 } 629 WARN_ON(p != end); 630 631 return last_bdf; 632 } 633 634 /**************************************************************************** 635 * 636 * The following functions belong to the code path which parses the ACPI table 637 * the second time. In this ACPI parsing iteration we allocate IOMMU specific 638 * data structures, initialize the per PCI segment device/alias/rlookup table 639 * and also basically initialize the hardware. 640 * 641 ****************************************************************************/ 642 643 /* Allocate per PCI segment device table */ 644 static inline int __init alloc_dev_table(struct amd_iommu_pci_seg *pci_seg) 645 { 646 pci_seg->dev_table = iommu_alloc_pages(GFP_KERNEL | GFP_DMA32, 647 get_order(pci_seg->dev_table_size)); 648 if (!pci_seg->dev_table) 649 return -ENOMEM; 650 651 return 0; 652 } 653 654 static inline void free_dev_table(struct amd_iommu_pci_seg *pci_seg) 655 { 656 iommu_free_pages(pci_seg->dev_table, 657 get_order(pci_seg->dev_table_size)); 658 pci_seg->dev_table = NULL; 659 } 660 661 /* Allocate per PCI segment IOMMU rlookup table. */ 662 static inline int __init alloc_rlookup_table(struct amd_iommu_pci_seg *pci_seg) 663 { 664 pci_seg->rlookup_table = iommu_alloc_pages(GFP_KERNEL, 665 get_order(pci_seg->rlookup_table_size)); 666 if (pci_seg->rlookup_table == NULL) 667 return -ENOMEM; 668 669 return 0; 670 } 671 672 static inline void free_rlookup_table(struct amd_iommu_pci_seg *pci_seg) 673 { 674 iommu_free_pages(pci_seg->rlookup_table, 675 get_order(pci_seg->rlookup_table_size)); 676 pci_seg->rlookup_table = NULL; 677 } 678 679 static inline int __init alloc_irq_lookup_table(struct amd_iommu_pci_seg *pci_seg) 680 { 681 pci_seg->irq_lookup_table = iommu_alloc_pages(GFP_KERNEL, 682 get_order(pci_seg->rlookup_table_size)); 683 kmemleak_alloc(pci_seg->irq_lookup_table, 684 pci_seg->rlookup_table_size, 1, GFP_KERNEL); 685 if (pci_seg->irq_lookup_table == NULL) 686 return -ENOMEM; 687 688 return 0; 689 } 690 691 static inline void free_irq_lookup_table(struct amd_iommu_pci_seg *pci_seg) 692 { 693 kmemleak_free(pci_seg->irq_lookup_table); 694 iommu_free_pages(pci_seg->irq_lookup_table, 695 get_order(pci_seg->rlookup_table_size)); 696 pci_seg->irq_lookup_table = NULL; 697 } 698 699 static int __init alloc_alias_table(struct amd_iommu_pci_seg *pci_seg) 700 { 701 int i; 702 703 pci_seg->alias_table = iommu_alloc_pages(GFP_KERNEL, 704 get_order(pci_seg->alias_table_size)); 705 if (!pci_seg->alias_table) 706 return -ENOMEM; 707 708 /* 709 * let all alias entries point to itself 710 */ 711 for (i = 0; i <= pci_seg->last_bdf; ++i) 712 pci_seg->alias_table[i] = i; 713 714 return 0; 715 } 716 717 static void __init free_alias_table(struct amd_iommu_pci_seg *pci_seg) 718 { 719 iommu_free_pages(pci_seg->alias_table, 720 get_order(pci_seg->alias_table_size)); 721 pci_seg->alias_table = NULL; 722 } 723 724 /* 725 * Allocates the command buffer. This buffer is per AMD IOMMU. We can 726 * write commands to that buffer later and the IOMMU will execute them 727 * asynchronously 728 */ 729 static int __init alloc_command_buffer(struct amd_iommu *iommu) 730 { 731 iommu->cmd_buf = iommu_alloc_pages(GFP_KERNEL, 732 get_order(CMD_BUFFER_SIZE)); 733 734 return iommu->cmd_buf ? 0 : -ENOMEM; 735 } 736 737 /* 738 * Interrupt handler has processed all pending events and adjusted head 739 * and tail pointer. Reset overflow mask and restart logging again. 740 */ 741 void amd_iommu_restart_log(struct amd_iommu *iommu, const char *evt_type, 742 u8 cntrl_intr, u8 cntrl_log, 743 u32 status_run_mask, u32 status_overflow_mask) 744 { 745 u32 status; 746 747 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); 748 if (status & status_run_mask) 749 return; 750 751 pr_info_ratelimited("IOMMU %s log restarting\n", evt_type); 752 753 iommu_feature_disable(iommu, cntrl_log); 754 iommu_feature_disable(iommu, cntrl_intr); 755 756 writel(status_overflow_mask, iommu->mmio_base + MMIO_STATUS_OFFSET); 757 758 iommu_feature_enable(iommu, cntrl_intr); 759 iommu_feature_enable(iommu, cntrl_log); 760 } 761 762 /* 763 * This function restarts event logging in case the IOMMU experienced 764 * an event log buffer overflow. 765 */ 766 void amd_iommu_restart_event_logging(struct amd_iommu *iommu) 767 { 768 amd_iommu_restart_log(iommu, "Event", CONTROL_EVT_INT_EN, 769 CONTROL_EVT_LOG_EN, MMIO_STATUS_EVT_RUN_MASK, 770 MMIO_STATUS_EVT_OVERFLOW_MASK); 771 } 772 773 /* 774 * This function restarts event logging in case the IOMMU experienced 775 * GA log overflow. 776 */ 777 void amd_iommu_restart_ga_log(struct amd_iommu *iommu) 778 { 779 amd_iommu_restart_log(iommu, "GA", CONTROL_GAINT_EN, 780 CONTROL_GALOG_EN, MMIO_STATUS_GALOG_RUN_MASK, 781 MMIO_STATUS_GALOG_OVERFLOW_MASK); 782 } 783 784 /* 785 * This function resets the command buffer if the IOMMU stopped fetching 786 * commands from it. 787 */ 788 static void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu) 789 { 790 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); 791 792 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); 793 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); 794 iommu->cmd_buf_head = 0; 795 iommu->cmd_buf_tail = 0; 796 797 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN); 798 } 799 800 /* 801 * This function writes the command buffer address to the hardware and 802 * enables it. 803 */ 804 static void iommu_enable_command_buffer(struct amd_iommu *iommu) 805 { 806 u64 entry; 807 808 BUG_ON(iommu->cmd_buf == NULL); 809 810 entry = iommu_virt_to_phys(iommu->cmd_buf); 811 entry |= MMIO_CMD_SIZE_512; 812 813 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET, 814 &entry, sizeof(entry)); 815 816 amd_iommu_reset_cmd_buffer(iommu); 817 } 818 819 /* 820 * This function disables the command buffer 821 */ 822 static void iommu_disable_command_buffer(struct amd_iommu *iommu) 823 { 824 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); 825 } 826 827 static void __init free_command_buffer(struct amd_iommu *iommu) 828 { 829 iommu_free_pages(iommu->cmd_buf, get_order(CMD_BUFFER_SIZE)); 830 } 831 832 void *__init iommu_alloc_4k_pages(struct amd_iommu *iommu, gfp_t gfp, 833 size_t size) 834 { 835 int order = get_order(size); 836 void *buf = iommu_alloc_pages(gfp, order); 837 838 if (buf && 839 check_feature(FEATURE_SNP) && 840 set_memory_4k((unsigned long)buf, (1 << order))) { 841 iommu_free_pages(buf, order); 842 buf = NULL; 843 } 844 845 return buf; 846 } 847 848 /* allocates the memory where the IOMMU will log its events to */ 849 static int __init alloc_event_buffer(struct amd_iommu *iommu) 850 { 851 iommu->evt_buf = iommu_alloc_4k_pages(iommu, GFP_KERNEL, 852 EVT_BUFFER_SIZE); 853 854 return iommu->evt_buf ? 0 : -ENOMEM; 855 } 856 857 static void iommu_enable_event_buffer(struct amd_iommu *iommu) 858 { 859 u64 entry; 860 861 BUG_ON(iommu->evt_buf == NULL); 862 863 entry = iommu_virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK; 864 865 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET, 866 &entry, sizeof(entry)); 867 868 /* set head and tail to zero manually */ 869 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); 870 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); 871 872 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN); 873 } 874 875 /* 876 * This function disables the event log buffer 877 */ 878 static void iommu_disable_event_buffer(struct amd_iommu *iommu) 879 { 880 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN); 881 } 882 883 static void __init free_event_buffer(struct amd_iommu *iommu) 884 { 885 iommu_free_pages(iommu->evt_buf, get_order(EVT_BUFFER_SIZE)); 886 } 887 888 static void free_ga_log(struct amd_iommu *iommu) 889 { 890 #ifdef CONFIG_IRQ_REMAP 891 iommu_free_pages(iommu->ga_log, get_order(GA_LOG_SIZE)); 892 iommu_free_pages(iommu->ga_log_tail, get_order(8)); 893 #endif 894 } 895 896 #ifdef CONFIG_IRQ_REMAP 897 static int iommu_ga_log_enable(struct amd_iommu *iommu) 898 { 899 u32 status, i; 900 u64 entry; 901 902 if (!iommu->ga_log) 903 return -EINVAL; 904 905 entry = iommu_virt_to_phys(iommu->ga_log) | GA_LOG_SIZE_512; 906 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_BASE_OFFSET, 907 &entry, sizeof(entry)); 908 entry = (iommu_virt_to_phys(iommu->ga_log_tail) & 909 (BIT_ULL(52)-1)) & ~7ULL; 910 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_TAIL_OFFSET, 911 &entry, sizeof(entry)); 912 writel(0x00, iommu->mmio_base + MMIO_GA_HEAD_OFFSET); 913 writel(0x00, iommu->mmio_base + MMIO_GA_TAIL_OFFSET); 914 915 916 iommu_feature_enable(iommu, CONTROL_GAINT_EN); 917 iommu_feature_enable(iommu, CONTROL_GALOG_EN); 918 919 for (i = 0; i < MMIO_STATUS_TIMEOUT; ++i) { 920 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); 921 if (status & (MMIO_STATUS_GALOG_RUN_MASK)) 922 break; 923 udelay(10); 924 } 925 926 if (WARN_ON(i >= MMIO_STATUS_TIMEOUT)) 927 return -EINVAL; 928 929 return 0; 930 } 931 932 static int iommu_init_ga_log(struct amd_iommu *iommu) 933 { 934 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) 935 return 0; 936 937 iommu->ga_log = iommu_alloc_pages(GFP_KERNEL, get_order(GA_LOG_SIZE)); 938 if (!iommu->ga_log) 939 goto err_out; 940 941 iommu->ga_log_tail = iommu_alloc_pages(GFP_KERNEL, get_order(8)); 942 if (!iommu->ga_log_tail) 943 goto err_out; 944 945 return 0; 946 err_out: 947 free_ga_log(iommu); 948 return -EINVAL; 949 } 950 #endif /* CONFIG_IRQ_REMAP */ 951 952 static int __init alloc_cwwb_sem(struct amd_iommu *iommu) 953 { 954 iommu->cmd_sem = iommu_alloc_4k_pages(iommu, GFP_KERNEL, 1); 955 956 return iommu->cmd_sem ? 0 : -ENOMEM; 957 } 958 959 static void __init free_cwwb_sem(struct amd_iommu *iommu) 960 { 961 if (iommu->cmd_sem) 962 iommu_free_page((void *)iommu->cmd_sem); 963 } 964 965 static void iommu_enable_xt(struct amd_iommu *iommu) 966 { 967 #ifdef CONFIG_IRQ_REMAP 968 /* 969 * XT mode (32-bit APIC destination ID) requires 970 * GA mode (128-bit IRTE support) as a prerequisite. 971 */ 972 if (AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir) && 973 amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE) 974 iommu_feature_enable(iommu, CONTROL_XT_EN); 975 #endif /* CONFIG_IRQ_REMAP */ 976 } 977 978 static void iommu_enable_gt(struct amd_iommu *iommu) 979 { 980 if (!check_feature(FEATURE_GT)) 981 return; 982 983 iommu_feature_enable(iommu, CONTROL_GT_EN); 984 } 985 986 /* sets a specific bit in the device table entry. */ 987 static void __set_dev_entry_bit(struct dev_table_entry *dev_table, 988 u16 devid, u8 bit) 989 { 990 int i = (bit >> 6) & 0x03; 991 int _bit = bit & 0x3f; 992 993 dev_table[devid].data[i] |= (1UL << _bit); 994 } 995 996 static void set_dev_entry_bit(struct amd_iommu *iommu, u16 devid, u8 bit) 997 { 998 struct dev_table_entry *dev_table = get_dev_table(iommu); 999 1000 return __set_dev_entry_bit(dev_table, devid, bit); 1001 } 1002 1003 static int __get_dev_entry_bit(struct dev_table_entry *dev_table, 1004 u16 devid, u8 bit) 1005 { 1006 int i = (bit >> 6) & 0x03; 1007 int _bit = bit & 0x3f; 1008 1009 return (dev_table[devid].data[i] & (1UL << _bit)) >> _bit; 1010 } 1011 1012 static int get_dev_entry_bit(struct amd_iommu *iommu, u16 devid, u8 bit) 1013 { 1014 struct dev_table_entry *dev_table = get_dev_table(iommu); 1015 1016 return __get_dev_entry_bit(dev_table, devid, bit); 1017 } 1018 1019 static bool __copy_device_table(struct amd_iommu *iommu) 1020 { 1021 u64 int_ctl, int_tab_len, entry = 0; 1022 struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg; 1023 struct dev_table_entry *old_devtb = NULL; 1024 u32 lo, hi, devid, old_devtb_size; 1025 phys_addr_t old_devtb_phys; 1026 u16 dom_id, dte_v, irq_v; 1027 u64 tmp; 1028 1029 /* Each IOMMU use separate device table with the same size */ 1030 lo = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET); 1031 hi = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET + 4); 1032 entry = (((u64) hi) << 32) + lo; 1033 1034 old_devtb_size = ((entry & ~PAGE_MASK) + 1) << 12; 1035 if (old_devtb_size != pci_seg->dev_table_size) { 1036 pr_err("The device table size of IOMMU:%d is not expected!\n", 1037 iommu->index); 1038 return false; 1039 } 1040 1041 /* 1042 * When SME is enabled in the first kernel, the entry includes the 1043 * memory encryption mask(sme_me_mask), we must remove the memory 1044 * encryption mask to obtain the true physical address in kdump kernel. 1045 */ 1046 old_devtb_phys = __sme_clr(entry) & PAGE_MASK; 1047 1048 if (old_devtb_phys >= 0x100000000ULL) { 1049 pr_err("The address of old device table is above 4G, not trustworthy!\n"); 1050 return false; 1051 } 1052 old_devtb = (cc_platform_has(CC_ATTR_HOST_MEM_ENCRYPT) && is_kdump_kernel()) 1053 ? (__force void *)ioremap_encrypted(old_devtb_phys, 1054 pci_seg->dev_table_size) 1055 : memremap(old_devtb_phys, pci_seg->dev_table_size, MEMREMAP_WB); 1056 1057 if (!old_devtb) 1058 return false; 1059 1060 pci_seg->old_dev_tbl_cpy = iommu_alloc_pages(GFP_KERNEL | GFP_DMA32, 1061 get_order(pci_seg->dev_table_size)); 1062 if (pci_seg->old_dev_tbl_cpy == NULL) { 1063 pr_err("Failed to allocate memory for copying old device table!\n"); 1064 memunmap(old_devtb); 1065 return false; 1066 } 1067 1068 for (devid = 0; devid <= pci_seg->last_bdf; ++devid) { 1069 pci_seg->old_dev_tbl_cpy[devid] = old_devtb[devid]; 1070 dom_id = old_devtb[devid].data[1] & DEV_DOMID_MASK; 1071 dte_v = old_devtb[devid].data[0] & DTE_FLAG_V; 1072 1073 if (dte_v && dom_id) { 1074 pci_seg->old_dev_tbl_cpy[devid].data[0] = old_devtb[devid].data[0]; 1075 pci_seg->old_dev_tbl_cpy[devid].data[1] = old_devtb[devid].data[1]; 1076 /* Reserve the Domain IDs used by previous kernel */ 1077 if (ida_alloc_range(&pdom_ids, dom_id, dom_id, GFP_ATOMIC) != dom_id) { 1078 pr_err("Failed to reserve domain ID 0x%x\n", dom_id); 1079 memunmap(old_devtb); 1080 return false; 1081 } 1082 /* If gcr3 table existed, mask it out */ 1083 if (old_devtb[devid].data[0] & DTE_FLAG_GV) { 1084 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B; 1085 tmp |= DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C; 1086 pci_seg->old_dev_tbl_cpy[devid].data[1] &= ~tmp; 1087 tmp = DTE_GCR3_VAL_A(~0ULL) << DTE_GCR3_SHIFT_A; 1088 tmp |= DTE_FLAG_GV; 1089 pci_seg->old_dev_tbl_cpy[devid].data[0] &= ~tmp; 1090 } 1091 } 1092 1093 irq_v = old_devtb[devid].data[2] & DTE_IRQ_REMAP_ENABLE; 1094 int_ctl = old_devtb[devid].data[2] & DTE_IRQ_REMAP_INTCTL_MASK; 1095 int_tab_len = old_devtb[devid].data[2] & DTE_INTTABLEN_MASK; 1096 if (irq_v && (int_ctl || int_tab_len)) { 1097 if ((int_ctl != DTE_IRQ_REMAP_INTCTL) || 1098 (int_tab_len != DTE_INTTABLEN)) { 1099 pr_err("Wrong old irq remapping flag: %#x\n", devid); 1100 memunmap(old_devtb); 1101 return false; 1102 } 1103 1104 pci_seg->old_dev_tbl_cpy[devid].data[2] = old_devtb[devid].data[2]; 1105 } 1106 } 1107 memunmap(old_devtb); 1108 1109 return true; 1110 } 1111 1112 static bool copy_device_table(void) 1113 { 1114 struct amd_iommu *iommu; 1115 struct amd_iommu_pci_seg *pci_seg; 1116 1117 if (!amd_iommu_pre_enabled) 1118 return false; 1119 1120 pr_warn("Translation is already enabled - trying to copy translation structures\n"); 1121 1122 /* 1123 * All IOMMUs within PCI segment shares common device table. 1124 * Hence copy device table only once per PCI segment. 1125 */ 1126 for_each_pci_segment(pci_seg) { 1127 for_each_iommu(iommu) { 1128 if (pci_seg->id != iommu->pci_seg->id) 1129 continue; 1130 if (!__copy_device_table(iommu)) 1131 return false; 1132 break; 1133 } 1134 } 1135 1136 return true; 1137 } 1138 1139 void amd_iommu_apply_erratum_63(struct amd_iommu *iommu, u16 devid) 1140 { 1141 int sysmgt; 1142 1143 sysmgt = get_dev_entry_bit(iommu, devid, DEV_ENTRY_SYSMGT1) | 1144 (get_dev_entry_bit(iommu, devid, DEV_ENTRY_SYSMGT2) << 1); 1145 1146 if (sysmgt == 0x01) 1147 set_dev_entry_bit(iommu, devid, DEV_ENTRY_IW); 1148 } 1149 1150 /* 1151 * This function takes the device specific flags read from the ACPI 1152 * table and sets up the device table entry with that information 1153 */ 1154 static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu, 1155 u16 devid, u32 flags, u32 ext_flags) 1156 { 1157 if (flags & ACPI_DEVFLAG_INITPASS) 1158 set_dev_entry_bit(iommu, devid, DEV_ENTRY_INIT_PASS); 1159 if (flags & ACPI_DEVFLAG_EXTINT) 1160 set_dev_entry_bit(iommu, devid, DEV_ENTRY_EINT_PASS); 1161 if (flags & ACPI_DEVFLAG_NMI) 1162 set_dev_entry_bit(iommu, devid, DEV_ENTRY_NMI_PASS); 1163 if (flags & ACPI_DEVFLAG_SYSMGT1) 1164 set_dev_entry_bit(iommu, devid, DEV_ENTRY_SYSMGT1); 1165 if (flags & ACPI_DEVFLAG_SYSMGT2) 1166 set_dev_entry_bit(iommu, devid, DEV_ENTRY_SYSMGT2); 1167 if (flags & ACPI_DEVFLAG_LINT0) 1168 set_dev_entry_bit(iommu, devid, DEV_ENTRY_LINT0_PASS); 1169 if (flags & ACPI_DEVFLAG_LINT1) 1170 set_dev_entry_bit(iommu, devid, DEV_ENTRY_LINT1_PASS); 1171 1172 amd_iommu_apply_erratum_63(iommu, devid); 1173 1174 amd_iommu_set_rlookup_table(iommu, devid); 1175 } 1176 1177 int __init add_special_device(u8 type, u8 id, u32 *devid, bool cmd_line) 1178 { 1179 struct devid_map *entry; 1180 struct list_head *list; 1181 1182 if (type == IVHD_SPECIAL_IOAPIC) 1183 list = &ioapic_map; 1184 else if (type == IVHD_SPECIAL_HPET) 1185 list = &hpet_map; 1186 else 1187 return -EINVAL; 1188 1189 list_for_each_entry(entry, list, list) { 1190 if (!(entry->id == id && entry->cmd_line)) 1191 continue; 1192 1193 pr_info("Command-line override present for %s id %d - ignoring\n", 1194 type == IVHD_SPECIAL_IOAPIC ? "IOAPIC" : "HPET", id); 1195 1196 *devid = entry->devid; 1197 1198 return 0; 1199 } 1200 1201 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 1202 if (!entry) 1203 return -ENOMEM; 1204 1205 entry->id = id; 1206 entry->devid = *devid; 1207 entry->cmd_line = cmd_line; 1208 1209 list_add_tail(&entry->list, list); 1210 1211 return 0; 1212 } 1213 1214 static int __init add_acpi_hid_device(u8 *hid, u8 *uid, u32 *devid, 1215 bool cmd_line) 1216 { 1217 struct acpihid_map_entry *entry; 1218 struct list_head *list = &acpihid_map; 1219 1220 list_for_each_entry(entry, list, list) { 1221 if (strcmp(entry->hid, hid) || 1222 (*uid && *entry->uid && strcmp(entry->uid, uid)) || 1223 !entry->cmd_line) 1224 continue; 1225 1226 pr_info("Command-line override for hid:%s uid:%s\n", 1227 hid, uid); 1228 *devid = entry->devid; 1229 return 0; 1230 } 1231 1232 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 1233 if (!entry) 1234 return -ENOMEM; 1235 1236 memcpy(entry->uid, uid, strlen(uid)); 1237 memcpy(entry->hid, hid, strlen(hid)); 1238 entry->devid = *devid; 1239 entry->cmd_line = cmd_line; 1240 entry->root_devid = (entry->devid & (~0x7)); 1241 1242 pr_info("%s, add hid:%s, uid:%s, rdevid:%d\n", 1243 entry->cmd_line ? "cmd" : "ivrs", 1244 entry->hid, entry->uid, entry->root_devid); 1245 1246 list_add_tail(&entry->list, list); 1247 return 0; 1248 } 1249 1250 static int __init add_early_maps(void) 1251 { 1252 int i, ret; 1253 1254 for (i = 0; i < early_ioapic_map_size; ++i) { 1255 ret = add_special_device(IVHD_SPECIAL_IOAPIC, 1256 early_ioapic_map[i].id, 1257 &early_ioapic_map[i].devid, 1258 early_ioapic_map[i].cmd_line); 1259 if (ret) 1260 return ret; 1261 } 1262 1263 for (i = 0; i < early_hpet_map_size; ++i) { 1264 ret = add_special_device(IVHD_SPECIAL_HPET, 1265 early_hpet_map[i].id, 1266 &early_hpet_map[i].devid, 1267 early_hpet_map[i].cmd_line); 1268 if (ret) 1269 return ret; 1270 } 1271 1272 for (i = 0; i < early_acpihid_map_size; ++i) { 1273 ret = add_acpi_hid_device(early_acpihid_map[i].hid, 1274 early_acpihid_map[i].uid, 1275 &early_acpihid_map[i].devid, 1276 early_acpihid_map[i].cmd_line); 1277 if (ret) 1278 return ret; 1279 } 1280 1281 return 0; 1282 } 1283 1284 /* 1285 * Takes a pointer to an AMD IOMMU entry in the ACPI table and 1286 * initializes the hardware and our data structures with it. 1287 */ 1288 static int __init init_iommu_from_acpi(struct amd_iommu *iommu, 1289 struct ivhd_header *h) 1290 { 1291 u8 *p = (u8 *)h; 1292 u8 *end = p, flags = 0; 1293 u16 devid = 0, devid_start = 0, devid_to = 0, seg_id; 1294 u32 dev_i, ext_flags = 0; 1295 bool alias = false; 1296 struct ivhd_entry *e; 1297 struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg; 1298 u32 ivhd_size; 1299 int ret; 1300 1301 1302 ret = add_early_maps(); 1303 if (ret) 1304 return ret; 1305 1306 amd_iommu_apply_ivrs_quirks(); 1307 1308 /* 1309 * First save the recommended feature enable bits from ACPI 1310 */ 1311 iommu->acpi_flags = h->flags; 1312 1313 /* 1314 * Done. Now parse the device entries 1315 */ 1316 ivhd_size = get_ivhd_header_size(h); 1317 if (!ivhd_size) { 1318 pr_err("Unsupported IVHD type %#x\n", h->type); 1319 return -EINVAL; 1320 } 1321 1322 p += ivhd_size; 1323 1324 end += h->length; 1325 1326 1327 while (p < end) { 1328 e = (struct ivhd_entry *)p; 1329 seg_id = pci_seg->id; 1330 1331 switch (e->type) { 1332 case IVHD_DEV_ALL: 1333 1334 DUMP_printk(" DEV_ALL\t\t\tflags: %02x\n", e->flags); 1335 1336 for (dev_i = 0; dev_i <= pci_seg->last_bdf; ++dev_i) 1337 set_dev_entry_from_acpi(iommu, dev_i, e->flags, 0); 1338 break; 1339 case IVHD_DEV_SELECT: 1340 1341 DUMP_printk(" DEV_SELECT\t\t\t devid: %04x:%02x:%02x.%x " 1342 "flags: %02x\n", 1343 seg_id, PCI_BUS_NUM(e->devid), 1344 PCI_SLOT(e->devid), 1345 PCI_FUNC(e->devid), 1346 e->flags); 1347 1348 devid = e->devid; 1349 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); 1350 break; 1351 case IVHD_DEV_SELECT_RANGE_START: 1352 1353 DUMP_printk(" DEV_SELECT_RANGE_START\t " 1354 "devid: %04x:%02x:%02x.%x flags: %02x\n", 1355 seg_id, PCI_BUS_NUM(e->devid), 1356 PCI_SLOT(e->devid), 1357 PCI_FUNC(e->devid), 1358 e->flags); 1359 1360 devid_start = e->devid; 1361 flags = e->flags; 1362 ext_flags = 0; 1363 alias = false; 1364 break; 1365 case IVHD_DEV_ALIAS: 1366 1367 DUMP_printk(" DEV_ALIAS\t\t\t devid: %04x:%02x:%02x.%x " 1368 "flags: %02x devid_to: %02x:%02x.%x\n", 1369 seg_id, PCI_BUS_NUM(e->devid), 1370 PCI_SLOT(e->devid), 1371 PCI_FUNC(e->devid), 1372 e->flags, 1373 PCI_BUS_NUM(e->ext >> 8), 1374 PCI_SLOT(e->ext >> 8), 1375 PCI_FUNC(e->ext >> 8)); 1376 1377 devid = e->devid; 1378 devid_to = e->ext >> 8; 1379 set_dev_entry_from_acpi(iommu, devid , e->flags, 0); 1380 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0); 1381 pci_seg->alias_table[devid] = devid_to; 1382 break; 1383 case IVHD_DEV_ALIAS_RANGE: 1384 1385 DUMP_printk(" DEV_ALIAS_RANGE\t\t " 1386 "devid: %04x:%02x:%02x.%x flags: %02x " 1387 "devid_to: %04x:%02x:%02x.%x\n", 1388 seg_id, PCI_BUS_NUM(e->devid), 1389 PCI_SLOT(e->devid), 1390 PCI_FUNC(e->devid), 1391 e->flags, 1392 seg_id, PCI_BUS_NUM(e->ext >> 8), 1393 PCI_SLOT(e->ext >> 8), 1394 PCI_FUNC(e->ext >> 8)); 1395 1396 devid_start = e->devid; 1397 flags = e->flags; 1398 devid_to = e->ext >> 8; 1399 ext_flags = 0; 1400 alias = true; 1401 break; 1402 case IVHD_DEV_EXT_SELECT: 1403 1404 DUMP_printk(" DEV_EXT_SELECT\t\t devid: %04x:%02x:%02x.%x " 1405 "flags: %02x ext: %08x\n", 1406 seg_id, PCI_BUS_NUM(e->devid), 1407 PCI_SLOT(e->devid), 1408 PCI_FUNC(e->devid), 1409 e->flags, e->ext); 1410 1411 devid = e->devid; 1412 set_dev_entry_from_acpi(iommu, devid, e->flags, 1413 e->ext); 1414 break; 1415 case IVHD_DEV_EXT_SELECT_RANGE: 1416 1417 DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: " 1418 "%04x:%02x:%02x.%x flags: %02x ext: %08x\n", 1419 seg_id, PCI_BUS_NUM(e->devid), 1420 PCI_SLOT(e->devid), 1421 PCI_FUNC(e->devid), 1422 e->flags, e->ext); 1423 1424 devid_start = e->devid; 1425 flags = e->flags; 1426 ext_flags = e->ext; 1427 alias = false; 1428 break; 1429 case IVHD_DEV_RANGE_END: 1430 1431 DUMP_printk(" DEV_RANGE_END\t\t devid: %04x:%02x:%02x.%x\n", 1432 seg_id, PCI_BUS_NUM(e->devid), 1433 PCI_SLOT(e->devid), 1434 PCI_FUNC(e->devid)); 1435 1436 devid = e->devid; 1437 for (dev_i = devid_start; dev_i <= devid; ++dev_i) { 1438 if (alias) { 1439 pci_seg->alias_table[dev_i] = devid_to; 1440 set_dev_entry_from_acpi(iommu, 1441 devid_to, flags, ext_flags); 1442 } 1443 set_dev_entry_from_acpi(iommu, dev_i, 1444 flags, ext_flags); 1445 } 1446 break; 1447 case IVHD_DEV_SPECIAL: { 1448 u8 handle, type; 1449 const char *var; 1450 u32 devid; 1451 int ret; 1452 1453 handle = e->ext & 0xff; 1454 devid = PCI_SEG_DEVID_TO_SBDF(seg_id, (e->ext >> 8)); 1455 type = (e->ext >> 24) & 0xff; 1456 1457 if (type == IVHD_SPECIAL_IOAPIC) 1458 var = "IOAPIC"; 1459 else if (type == IVHD_SPECIAL_HPET) 1460 var = "HPET"; 1461 else 1462 var = "UNKNOWN"; 1463 1464 DUMP_printk(" DEV_SPECIAL(%s[%d])\t\tdevid: %04x:%02x:%02x.%x\n", 1465 var, (int)handle, 1466 seg_id, PCI_BUS_NUM(devid), 1467 PCI_SLOT(devid), 1468 PCI_FUNC(devid)); 1469 1470 ret = add_special_device(type, handle, &devid, false); 1471 if (ret) 1472 return ret; 1473 1474 /* 1475 * add_special_device might update the devid in case a 1476 * command-line override is present. So call 1477 * set_dev_entry_from_acpi after add_special_device. 1478 */ 1479 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); 1480 1481 break; 1482 } 1483 case IVHD_DEV_ACPI_HID: { 1484 u32 devid; 1485 u8 hid[ACPIHID_HID_LEN]; 1486 u8 uid[ACPIHID_UID_LEN]; 1487 int ret; 1488 1489 if (h->type != 0x40) { 1490 pr_err(FW_BUG "Invalid IVHD device type %#x\n", 1491 e->type); 1492 break; 1493 } 1494 1495 BUILD_BUG_ON(sizeof(e->ext_hid) != ACPIHID_HID_LEN - 1); 1496 memcpy(hid, &e->ext_hid, ACPIHID_HID_LEN - 1); 1497 hid[ACPIHID_HID_LEN - 1] = '\0'; 1498 1499 if (!(*hid)) { 1500 pr_err(FW_BUG "Invalid HID.\n"); 1501 break; 1502 } 1503 1504 uid[0] = '\0'; 1505 switch (e->uidf) { 1506 case UID_NOT_PRESENT: 1507 1508 if (e->uidl != 0) 1509 pr_warn(FW_BUG "Invalid UID length.\n"); 1510 1511 break; 1512 case UID_IS_INTEGER: 1513 1514 sprintf(uid, "%d", e->uid); 1515 1516 break; 1517 case UID_IS_CHARACTER: 1518 1519 memcpy(uid, &e->uid, e->uidl); 1520 uid[e->uidl] = '\0'; 1521 1522 break; 1523 default: 1524 break; 1525 } 1526 1527 devid = PCI_SEG_DEVID_TO_SBDF(seg_id, e->devid); 1528 DUMP_printk(" DEV_ACPI_HID(%s[%s])\t\tdevid: %04x:%02x:%02x.%x\n", 1529 hid, uid, seg_id, 1530 PCI_BUS_NUM(devid), 1531 PCI_SLOT(devid), 1532 PCI_FUNC(devid)); 1533 1534 flags = e->flags; 1535 1536 ret = add_acpi_hid_device(hid, uid, &devid, false); 1537 if (ret) 1538 return ret; 1539 1540 /* 1541 * add_special_device might update the devid in case a 1542 * command-line override is present. So call 1543 * set_dev_entry_from_acpi after add_special_device. 1544 */ 1545 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); 1546 1547 break; 1548 } 1549 default: 1550 break; 1551 } 1552 1553 p += ivhd_entry_length(p); 1554 } 1555 1556 return 0; 1557 } 1558 1559 /* Allocate PCI segment data structure */ 1560 static struct amd_iommu_pci_seg *__init alloc_pci_segment(u16 id, 1561 struct acpi_table_header *ivrs_base) 1562 { 1563 struct amd_iommu_pci_seg *pci_seg; 1564 int last_bdf; 1565 1566 /* 1567 * First parse ACPI tables to find the largest Bus/Dev/Func we need to 1568 * handle in this PCI segment. Upon this information the shared data 1569 * structures for the PCI segments in the system will be allocated. 1570 */ 1571 last_bdf = find_last_devid_acpi(ivrs_base, id); 1572 if (last_bdf < 0) 1573 return NULL; 1574 1575 pci_seg = kzalloc(sizeof(struct amd_iommu_pci_seg), GFP_KERNEL); 1576 if (pci_seg == NULL) 1577 return NULL; 1578 1579 pci_seg->last_bdf = last_bdf; 1580 DUMP_printk("PCI segment : 0x%0x, last bdf : 0x%04x\n", id, last_bdf); 1581 pci_seg->dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE, last_bdf); 1582 pci_seg->alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE, last_bdf); 1583 pci_seg->rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE, last_bdf); 1584 1585 pci_seg->id = id; 1586 init_llist_head(&pci_seg->dev_data_list); 1587 INIT_LIST_HEAD(&pci_seg->unity_map); 1588 list_add_tail(&pci_seg->list, &amd_iommu_pci_seg_list); 1589 1590 if (alloc_dev_table(pci_seg)) 1591 return NULL; 1592 if (alloc_alias_table(pci_seg)) 1593 return NULL; 1594 if (alloc_rlookup_table(pci_seg)) 1595 return NULL; 1596 1597 return pci_seg; 1598 } 1599 1600 static struct amd_iommu_pci_seg *__init get_pci_segment(u16 id, 1601 struct acpi_table_header *ivrs_base) 1602 { 1603 struct amd_iommu_pci_seg *pci_seg; 1604 1605 for_each_pci_segment(pci_seg) { 1606 if (pci_seg->id == id) 1607 return pci_seg; 1608 } 1609 1610 return alloc_pci_segment(id, ivrs_base); 1611 } 1612 1613 static void __init free_pci_segments(void) 1614 { 1615 struct amd_iommu_pci_seg *pci_seg, *next; 1616 1617 for_each_pci_segment_safe(pci_seg, next) { 1618 list_del(&pci_seg->list); 1619 free_irq_lookup_table(pci_seg); 1620 free_rlookup_table(pci_seg); 1621 free_alias_table(pci_seg); 1622 free_dev_table(pci_seg); 1623 kfree(pci_seg); 1624 } 1625 } 1626 1627 static void __init free_sysfs(struct amd_iommu *iommu) 1628 { 1629 if (iommu->iommu.dev) { 1630 iommu_device_unregister(&iommu->iommu); 1631 iommu_device_sysfs_remove(&iommu->iommu); 1632 } 1633 } 1634 1635 static void __init free_iommu_one(struct amd_iommu *iommu) 1636 { 1637 free_sysfs(iommu); 1638 free_cwwb_sem(iommu); 1639 free_command_buffer(iommu); 1640 free_event_buffer(iommu); 1641 amd_iommu_free_ppr_log(iommu); 1642 free_ga_log(iommu); 1643 iommu_unmap_mmio_space(iommu); 1644 amd_iommu_iopf_uninit(iommu); 1645 } 1646 1647 static void __init free_iommu_all(void) 1648 { 1649 struct amd_iommu *iommu, *next; 1650 1651 for_each_iommu_safe(iommu, next) { 1652 list_del(&iommu->list); 1653 free_iommu_one(iommu); 1654 kfree(iommu); 1655 } 1656 } 1657 1658 /* 1659 * Family15h Model 10h-1fh erratum 746 (IOMMU Logging May Stall Translations) 1660 * Workaround: 1661 * BIOS should disable L2B micellaneous clock gating by setting 1662 * L2_L2B_CK_GATE_CONTROL[CKGateL2BMiscDisable](D0F2xF4_x90[2]) = 1b 1663 */ 1664 static void amd_iommu_erratum_746_workaround(struct amd_iommu *iommu) 1665 { 1666 u32 value; 1667 1668 if ((boot_cpu_data.x86 != 0x15) || 1669 (boot_cpu_data.x86_model < 0x10) || 1670 (boot_cpu_data.x86_model > 0x1f)) 1671 return; 1672 1673 pci_write_config_dword(iommu->dev, 0xf0, 0x90); 1674 pci_read_config_dword(iommu->dev, 0xf4, &value); 1675 1676 if (value & BIT(2)) 1677 return; 1678 1679 /* Select NB indirect register 0x90 and enable writing */ 1680 pci_write_config_dword(iommu->dev, 0xf0, 0x90 | (1 << 8)); 1681 1682 pci_write_config_dword(iommu->dev, 0xf4, value | 0x4); 1683 pci_info(iommu->dev, "Applying erratum 746 workaround\n"); 1684 1685 /* Clear the enable writing bit */ 1686 pci_write_config_dword(iommu->dev, 0xf0, 0x90); 1687 } 1688 1689 /* 1690 * Family15h Model 30h-3fh (IOMMU Mishandles ATS Write Permission) 1691 * Workaround: 1692 * BIOS should enable ATS write permission check by setting 1693 * L2_DEBUG_3[AtsIgnoreIWDis](D0F2xF4_x47[0]) = 1b 1694 */ 1695 static void amd_iommu_ats_write_check_workaround(struct amd_iommu *iommu) 1696 { 1697 u32 value; 1698 1699 if ((boot_cpu_data.x86 != 0x15) || 1700 (boot_cpu_data.x86_model < 0x30) || 1701 (boot_cpu_data.x86_model > 0x3f)) 1702 return; 1703 1704 /* Test L2_DEBUG_3[AtsIgnoreIWDis] == 1 */ 1705 value = iommu_read_l2(iommu, 0x47); 1706 1707 if (value & BIT(0)) 1708 return; 1709 1710 /* Set L2_DEBUG_3[AtsIgnoreIWDis] = 1 */ 1711 iommu_write_l2(iommu, 0x47, value | BIT(0)); 1712 1713 pci_info(iommu->dev, "Applying ATS write check workaround\n"); 1714 } 1715 1716 /* 1717 * This function glues the initialization function for one IOMMU 1718 * together and also allocates the command buffer and programs the 1719 * hardware. It does NOT enable the IOMMU. This is done afterwards. 1720 */ 1721 static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h, 1722 struct acpi_table_header *ivrs_base) 1723 { 1724 struct amd_iommu_pci_seg *pci_seg; 1725 1726 pci_seg = get_pci_segment(h->pci_seg, ivrs_base); 1727 if (pci_seg == NULL) 1728 return -ENOMEM; 1729 iommu->pci_seg = pci_seg; 1730 1731 raw_spin_lock_init(&iommu->lock); 1732 atomic64_set(&iommu->cmd_sem_val, 0); 1733 1734 /* Add IOMMU to internal data structures */ 1735 list_add_tail(&iommu->list, &amd_iommu_list); 1736 iommu->index = amd_iommus_present++; 1737 1738 if (unlikely(iommu->index >= MAX_IOMMUS)) { 1739 WARN(1, "System has more IOMMUs than supported by this driver\n"); 1740 return -ENOSYS; 1741 } 1742 1743 /* 1744 * Copy data from ACPI table entry to the iommu struct 1745 */ 1746 iommu->devid = h->devid; 1747 iommu->cap_ptr = h->cap_ptr; 1748 iommu->mmio_phys = h->mmio_phys; 1749 1750 switch (h->type) { 1751 case 0x10: 1752 /* Check if IVHD EFR contains proper max banks/counters */ 1753 if ((h->efr_attr != 0) && 1754 ((h->efr_attr & (0xF << 13)) != 0) && 1755 ((h->efr_attr & (0x3F << 17)) != 0)) 1756 iommu->mmio_phys_end = MMIO_REG_END_OFFSET; 1757 else 1758 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET; 1759 1760 /* 1761 * Note: GA (128-bit IRTE) mode requires cmpxchg16b supports. 1762 * GAM also requires GA mode. Therefore, we need to 1763 * check cmpxchg16b support before enabling it. 1764 */ 1765 if (!boot_cpu_has(X86_FEATURE_CX16) || 1766 ((h->efr_attr & (0x1 << IOMMU_FEAT_GASUP_SHIFT)) == 0)) 1767 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY; 1768 break; 1769 case 0x11: 1770 case 0x40: 1771 if (h->efr_reg & (1 << 9)) 1772 iommu->mmio_phys_end = MMIO_REG_END_OFFSET; 1773 else 1774 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET; 1775 1776 /* 1777 * Note: GA (128-bit IRTE) mode requires cmpxchg16b supports. 1778 * XT, GAM also requires GA mode. Therefore, we need to 1779 * check cmpxchg16b support before enabling them. 1780 */ 1781 if (!boot_cpu_has(X86_FEATURE_CX16) || 1782 ((h->efr_reg & (0x1 << IOMMU_EFR_GASUP_SHIFT)) == 0)) { 1783 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY; 1784 break; 1785 } 1786 1787 if (h->efr_reg & BIT(IOMMU_EFR_XTSUP_SHIFT)) 1788 amd_iommu_xt_mode = IRQ_REMAP_X2APIC_MODE; 1789 1790 early_iommu_features_init(iommu, h); 1791 1792 break; 1793 default: 1794 return -EINVAL; 1795 } 1796 1797 iommu->mmio_base = iommu_map_mmio_space(iommu->mmio_phys, 1798 iommu->mmio_phys_end); 1799 if (!iommu->mmio_base) 1800 return -ENOMEM; 1801 1802 return init_iommu_from_acpi(iommu, h); 1803 } 1804 1805 static int __init init_iommu_one_late(struct amd_iommu *iommu) 1806 { 1807 int ret; 1808 1809 if (alloc_cwwb_sem(iommu)) 1810 return -ENOMEM; 1811 1812 if (alloc_command_buffer(iommu)) 1813 return -ENOMEM; 1814 1815 if (alloc_event_buffer(iommu)) 1816 return -ENOMEM; 1817 1818 iommu->int_enabled = false; 1819 1820 init_translation_status(iommu); 1821 if (translation_pre_enabled(iommu) && !is_kdump_kernel()) { 1822 iommu_disable(iommu); 1823 clear_translation_pre_enabled(iommu); 1824 pr_warn("Translation was enabled for IOMMU:%d but we are not in kdump mode\n", 1825 iommu->index); 1826 } 1827 if (amd_iommu_pre_enabled) 1828 amd_iommu_pre_enabled = translation_pre_enabled(iommu); 1829 1830 if (amd_iommu_irq_remap) { 1831 ret = amd_iommu_create_irq_domain(iommu); 1832 if (ret) 1833 return ret; 1834 } 1835 1836 /* 1837 * Make sure IOMMU is not considered to translate itself. The IVRS 1838 * table tells us so, but this is a lie! 1839 */ 1840 iommu->pci_seg->rlookup_table[iommu->devid] = NULL; 1841 1842 return 0; 1843 } 1844 1845 /** 1846 * get_highest_supported_ivhd_type - Look up the appropriate IVHD type 1847 * @ivrs: Pointer to the IVRS header 1848 * 1849 * This function search through all IVDB of the maximum supported IVHD 1850 */ 1851 static u8 get_highest_supported_ivhd_type(struct acpi_table_header *ivrs) 1852 { 1853 u8 *base = (u8 *)ivrs; 1854 struct ivhd_header *ivhd = (struct ivhd_header *) 1855 (base + IVRS_HEADER_LENGTH); 1856 u8 last_type = ivhd->type; 1857 u16 devid = ivhd->devid; 1858 1859 while (((u8 *)ivhd - base < ivrs->length) && 1860 (ivhd->type <= ACPI_IVHD_TYPE_MAX_SUPPORTED)) { 1861 u8 *p = (u8 *) ivhd; 1862 1863 if (ivhd->devid == devid) 1864 last_type = ivhd->type; 1865 ivhd = (struct ivhd_header *)(p + ivhd->length); 1866 } 1867 1868 return last_type; 1869 } 1870 1871 /* 1872 * Iterates over all IOMMU entries in the ACPI table, allocates the 1873 * IOMMU structure and initializes it with init_iommu_one() 1874 */ 1875 static int __init init_iommu_all(struct acpi_table_header *table) 1876 { 1877 u8 *p = (u8 *)table, *end = (u8 *)table; 1878 struct ivhd_header *h; 1879 struct amd_iommu *iommu; 1880 int ret; 1881 1882 end += table->length; 1883 p += IVRS_HEADER_LENGTH; 1884 1885 /* Phase 1: Process all IVHD blocks */ 1886 while (p < end) { 1887 h = (struct ivhd_header *)p; 1888 if (*p == amd_iommu_target_ivhd_type) { 1889 1890 DUMP_printk("device: %04x:%02x:%02x.%01x cap: %04x " 1891 "flags: %01x info %04x\n", 1892 h->pci_seg, PCI_BUS_NUM(h->devid), 1893 PCI_SLOT(h->devid), PCI_FUNC(h->devid), 1894 h->cap_ptr, h->flags, h->info); 1895 DUMP_printk(" mmio-addr: %016llx\n", 1896 h->mmio_phys); 1897 1898 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL); 1899 if (iommu == NULL) 1900 return -ENOMEM; 1901 1902 ret = init_iommu_one(iommu, h, table); 1903 if (ret) 1904 return ret; 1905 } 1906 p += h->length; 1907 1908 } 1909 WARN_ON(p != end); 1910 1911 /* Phase 2 : Early feature support check */ 1912 get_global_efr(); 1913 1914 /* Phase 3 : Enabling IOMMU features */ 1915 for_each_iommu(iommu) { 1916 ret = init_iommu_one_late(iommu); 1917 if (ret) 1918 return ret; 1919 } 1920 1921 return 0; 1922 } 1923 1924 static void init_iommu_perf_ctr(struct amd_iommu *iommu) 1925 { 1926 u64 val; 1927 struct pci_dev *pdev = iommu->dev; 1928 1929 if (!check_feature(FEATURE_PC)) 1930 return; 1931 1932 amd_iommu_pc_present = true; 1933 1934 pci_info(pdev, "IOMMU performance counters supported\n"); 1935 1936 val = readl(iommu->mmio_base + MMIO_CNTR_CONF_OFFSET); 1937 iommu->max_banks = (u8) ((val >> 12) & 0x3f); 1938 iommu->max_counters = (u8) ((val >> 7) & 0xf); 1939 1940 return; 1941 } 1942 1943 static ssize_t amd_iommu_show_cap(struct device *dev, 1944 struct device_attribute *attr, 1945 char *buf) 1946 { 1947 struct amd_iommu *iommu = dev_to_amd_iommu(dev); 1948 return sysfs_emit(buf, "%x\n", iommu->cap); 1949 } 1950 static DEVICE_ATTR(cap, S_IRUGO, amd_iommu_show_cap, NULL); 1951 1952 static ssize_t amd_iommu_show_features(struct device *dev, 1953 struct device_attribute *attr, 1954 char *buf) 1955 { 1956 return sysfs_emit(buf, "%llx:%llx\n", amd_iommu_efr, amd_iommu_efr2); 1957 } 1958 static DEVICE_ATTR(features, S_IRUGO, amd_iommu_show_features, NULL); 1959 1960 static struct attribute *amd_iommu_attrs[] = { 1961 &dev_attr_cap.attr, 1962 &dev_attr_features.attr, 1963 NULL, 1964 }; 1965 1966 static struct attribute_group amd_iommu_group = { 1967 .name = "amd-iommu", 1968 .attrs = amd_iommu_attrs, 1969 }; 1970 1971 static const struct attribute_group *amd_iommu_groups[] = { 1972 &amd_iommu_group, 1973 NULL, 1974 }; 1975 1976 /* 1977 * Note: IVHD 0x11 and 0x40 also contains exact copy 1978 * of the IOMMU Extended Feature Register [MMIO Offset 0030h]. 1979 * Default to EFR in IVHD since it is available sooner (i.e. before PCI init). 1980 */ 1981 static void __init late_iommu_features_init(struct amd_iommu *iommu) 1982 { 1983 u64 features, features2; 1984 1985 if (!(iommu->cap & (1 << IOMMU_CAP_EFR))) 1986 return; 1987 1988 /* read extended feature bits */ 1989 features = readq(iommu->mmio_base + MMIO_EXT_FEATURES); 1990 features2 = readq(iommu->mmio_base + MMIO_EXT_FEATURES2); 1991 1992 if (!amd_iommu_efr) { 1993 amd_iommu_efr = features; 1994 amd_iommu_efr2 = features2; 1995 return; 1996 } 1997 1998 /* 1999 * Sanity check and warn if EFR values from 2000 * IVHD and MMIO conflict. 2001 */ 2002 if (features != amd_iommu_efr || 2003 features2 != amd_iommu_efr2) { 2004 pr_warn(FW_WARN 2005 "EFR mismatch. Use IVHD EFR (%#llx : %#llx), EFR2 (%#llx : %#llx).\n", 2006 features, amd_iommu_efr, 2007 features2, amd_iommu_efr2); 2008 } 2009 } 2010 2011 static int __init iommu_init_pci(struct amd_iommu *iommu) 2012 { 2013 int cap_ptr = iommu->cap_ptr; 2014 int ret; 2015 2016 iommu->dev = pci_get_domain_bus_and_slot(iommu->pci_seg->id, 2017 PCI_BUS_NUM(iommu->devid), 2018 iommu->devid & 0xff); 2019 if (!iommu->dev) 2020 return -ENODEV; 2021 2022 /* Prevent binding other PCI device drivers to IOMMU devices */ 2023 iommu->dev->match_driver = false; 2024 2025 /* ACPI _PRT won't have an IRQ for IOMMU */ 2026 iommu->dev->irq_managed = 1; 2027 2028 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET, 2029 &iommu->cap); 2030 2031 if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB))) 2032 amd_iommu_iotlb_sup = false; 2033 2034 late_iommu_features_init(iommu); 2035 2036 if (check_feature(FEATURE_GT)) { 2037 int glxval; 2038 u64 pasmax; 2039 2040 pasmax = FIELD_GET(FEATURE_PASMAX, amd_iommu_efr); 2041 iommu->iommu.max_pasids = (1 << (pasmax + 1)) - 1; 2042 2043 BUG_ON(iommu->iommu.max_pasids & ~PASID_MASK); 2044 2045 glxval = FIELD_GET(FEATURE_GLX, amd_iommu_efr); 2046 2047 if (amd_iommu_max_glx_val == -1) 2048 amd_iommu_max_glx_val = glxval; 2049 else 2050 amd_iommu_max_glx_val = min(amd_iommu_max_glx_val, glxval); 2051 2052 iommu_enable_gt(iommu); 2053 } 2054 2055 if (check_feature(FEATURE_PPR) && amd_iommu_alloc_ppr_log(iommu)) 2056 return -ENOMEM; 2057 2058 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE)) { 2059 pr_info("Using strict mode due to virtualization\n"); 2060 iommu_set_dma_strict(); 2061 amd_iommu_np_cache = true; 2062 } 2063 2064 init_iommu_perf_ctr(iommu); 2065 2066 if (is_rd890_iommu(iommu->dev)) { 2067 int i, j; 2068 2069 iommu->root_pdev = 2070 pci_get_domain_bus_and_slot(iommu->pci_seg->id, 2071 iommu->dev->bus->number, 2072 PCI_DEVFN(0, 0)); 2073 2074 /* 2075 * Some rd890 systems may not be fully reconfigured by the 2076 * BIOS, so it's necessary for us to store this information so 2077 * it can be reprogrammed on resume 2078 */ 2079 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4, 2080 &iommu->stored_addr_lo); 2081 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8, 2082 &iommu->stored_addr_hi); 2083 2084 /* Low bit locks writes to configuration space */ 2085 iommu->stored_addr_lo &= ~1; 2086 2087 for (i = 0; i < 6; i++) 2088 for (j = 0; j < 0x12; j++) 2089 iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j); 2090 2091 for (i = 0; i < 0x83; i++) 2092 iommu->stored_l2[i] = iommu_read_l2(iommu, i); 2093 } 2094 2095 amd_iommu_erratum_746_workaround(iommu); 2096 amd_iommu_ats_write_check_workaround(iommu); 2097 2098 ret = iommu_device_sysfs_add(&iommu->iommu, &iommu->dev->dev, 2099 amd_iommu_groups, "ivhd%d", iommu->index); 2100 if (ret) 2101 return ret; 2102 2103 /* 2104 * Allocate per IOMMU IOPF queue here so that in attach device path, 2105 * PRI capable device can be added to IOPF queue 2106 */ 2107 if (amd_iommu_gt_ppr_supported()) { 2108 ret = amd_iommu_iopf_init(iommu); 2109 if (ret) 2110 return ret; 2111 } 2112 2113 iommu_device_register(&iommu->iommu, &amd_iommu_ops, NULL); 2114 2115 return pci_enable_device(iommu->dev); 2116 } 2117 2118 static void print_iommu_info(void) 2119 { 2120 int i; 2121 static const char * const feat_str[] = { 2122 "PreF", "PPR", "X2APIC", "NX", "GT", "[5]", 2123 "IA", "GA", "HE", "PC" 2124 }; 2125 2126 if (amd_iommu_efr) { 2127 pr_info("Extended features (%#llx, %#llx):", amd_iommu_efr, amd_iommu_efr2); 2128 2129 for (i = 0; i < ARRAY_SIZE(feat_str); ++i) { 2130 if (check_feature(1ULL << i)) 2131 pr_cont(" %s", feat_str[i]); 2132 } 2133 2134 if (check_feature(FEATURE_GAM_VAPIC)) 2135 pr_cont(" GA_vAPIC"); 2136 2137 if (check_feature(FEATURE_SNP)) 2138 pr_cont(" SNP"); 2139 2140 pr_cont("\n"); 2141 } 2142 2143 if (irq_remapping_enabled) { 2144 pr_info("Interrupt remapping enabled\n"); 2145 if (amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE) 2146 pr_info("X2APIC enabled\n"); 2147 } 2148 if (amd_iommu_pgtable == AMD_IOMMU_V2) { 2149 pr_info("V2 page table enabled (Paging mode : %d level)\n", 2150 amd_iommu_gpt_level); 2151 } 2152 } 2153 2154 static int __init amd_iommu_init_pci(void) 2155 { 2156 struct amd_iommu *iommu; 2157 struct amd_iommu_pci_seg *pci_seg; 2158 int ret; 2159 2160 /* Init global identity domain before registering IOMMU */ 2161 amd_iommu_init_identity_domain(); 2162 2163 for_each_iommu(iommu) { 2164 ret = iommu_init_pci(iommu); 2165 if (ret) { 2166 pr_err("IOMMU%d: Failed to initialize IOMMU Hardware (error=%d)!\n", 2167 iommu->index, ret); 2168 goto out; 2169 } 2170 /* Need to setup range after PCI init */ 2171 iommu_set_cwwb_range(iommu); 2172 } 2173 2174 /* 2175 * Order is important here to make sure any unity map requirements are 2176 * fulfilled. The unity mappings are created and written to the device 2177 * table during the iommu_init_pci() call. 2178 * 2179 * After that we call init_device_table_dma() to make sure any 2180 * uninitialized DTE will block DMA, and in the end we flush the caches 2181 * of all IOMMUs to make sure the changes to the device table are 2182 * active. 2183 */ 2184 for_each_pci_segment(pci_seg) 2185 init_device_table_dma(pci_seg); 2186 2187 for_each_iommu(iommu) 2188 amd_iommu_flush_all_caches(iommu); 2189 2190 print_iommu_info(); 2191 2192 out: 2193 return ret; 2194 } 2195 2196 /**************************************************************************** 2197 * 2198 * The following functions initialize the MSI interrupts for all IOMMUs 2199 * in the system. It's a bit challenging because there could be multiple 2200 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per 2201 * pci_dev. 2202 * 2203 ****************************************************************************/ 2204 2205 static int iommu_setup_msi(struct amd_iommu *iommu) 2206 { 2207 int r; 2208 2209 r = pci_enable_msi(iommu->dev); 2210 if (r) 2211 return r; 2212 2213 r = request_threaded_irq(iommu->dev->irq, 2214 amd_iommu_int_handler, 2215 amd_iommu_int_thread, 2216 0, "AMD-Vi", 2217 iommu); 2218 2219 if (r) { 2220 pci_disable_msi(iommu->dev); 2221 return r; 2222 } 2223 2224 return 0; 2225 } 2226 2227 union intcapxt { 2228 u64 capxt; 2229 struct { 2230 u64 reserved_0 : 2, 2231 dest_mode_logical : 1, 2232 reserved_1 : 5, 2233 destid_0_23 : 24, 2234 vector : 8, 2235 reserved_2 : 16, 2236 destid_24_31 : 8; 2237 }; 2238 } __attribute__ ((packed)); 2239 2240 2241 static struct irq_chip intcapxt_controller; 2242 2243 static int intcapxt_irqdomain_activate(struct irq_domain *domain, 2244 struct irq_data *irqd, bool reserve) 2245 { 2246 return 0; 2247 } 2248 2249 static void intcapxt_irqdomain_deactivate(struct irq_domain *domain, 2250 struct irq_data *irqd) 2251 { 2252 } 2253 2254 2255 static int intcapxt_irqdomain_alloc(struct irq_domain *domain, unsigned int virq, 2256 unsigned int nr_irqs, void *arg) 2257 { 2258 struct irq_alloc_info *info = arg; 2259 int i, ret; 2260 2261 if (!info || info->type != X86_IRQ_ALLOC_TYPE_AMDVI) 2262 return -EINVAL; 2263 2264 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg); 2265 if (ret < 0) 2266 return ret; 2267 2268 for (i = virq; i < virq + nr_irqs; i++) { 2269 struct irq_data *irqd = irq_domain_get_irq_data(domain, i); 2270 2271 irqd->chip = &intcapxt_controller; 2272 irqd->hwirq = info->hwirq; 2273 irqd->chip_data = info->data; 2274 __irq_set_handler(i, handle_edge_irq, 0, "edge"); 2275 } 2276 2277 return ret; 2278 } 2279 2280 static void intcapxt_irqdomain_free(struct irq_domain *domain, unsigned int virq, 2281 unsigned int nr_irqs) 2282 { 2283 irq_domain_free_irqs_top(domain, virq, nr_irqs); 2284 } 2285 2286 2287 static void intcapxt_unmask_irq(struct irq_data *irqd) 2288 { 2289 struct amd_iommu *iommu = irqd->chip_data; 2290 struct irq_cfg *cfg = irqd_cfg(irqd); 2291 union intcapxt xt; 2292 2293 xt.capxt = 0ULL; 2294 xt.dest_mode_logical = apic->dest_mode_logical; 2295 xt.vector = cfg->vector; 2296 xt.destid_0_23 = cfg->dest_apicid & GENMASK(23, 0); 2297 xt.destid_24_31 = cfg->dest_apicid >> 24; 2298 2299 writeq(xt.capxt, iommu->mmio_base + irqd->hwirq); 2300 } 2301 2302 static void intcapxt_mask_irq(struct irq_data *irqd) 2303 { 2304 struct amd_iommu *iommu = irqd->chip_data; 2305 2306 writeq(0, iommu->mmio_base + irqd->hwirq); 2307 } 2308 2309 2310 static int intcapxt_set_affinity(struct irq_data *irqd, 2311 const struct cpumask *mask, bool force) 2312 { 2313 struct irq_data *parent = irqd->parent_data; 2314 int ret; 2315 2316 ret = parent->chip->irq_set_affinity(parent, mask, force); 2317 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE) 2318 return ret; 2319 return 0; 2320 } 2321 2322 static int intcapxt_set_wake(struct irq_data *irqd, unsigned int on) 2323 { 2324 return on ? -EOPNOTSUPP : 0; 2325 } 2326 2327 static struct irq_chip intcapxt_controller = { 2328 .name = "IOMMU-MSI", 2329 .irq_unmask = intcapxt_unmask_irq, 2330 .irq_mask = intcapxt_mask_irq, 2331 .irq_ack = irq_chip_ack_parent, 2332 .irq_retrigger = irq_chip_retrigger_hierarchy, 2333 .irq_set_affinity = intcapxt_set_affinity, 2334 .irq_set_wake = intcapxt_set_wake, 2335 .flags = IRQCHIP_MASK_ON_SUSPEND, 2336 }; 2337 2338 static const struct irq_domain_ops intcapxt_domain_ops = { 2339 .alloc = intcapxt_irqdomain_alloc, 2340 .free = intcapxt_irqdomain_free, 2341 .activate = intcapxt_irqdomain_activate, 2342 .deactivate = intcapxt_irqdomain_deactivate, 2343 }; 2344 2345 2346 static struct irq_domain *iommu_irqdomain; 2347 2348 static struct irq_domain *iommu_get_irqdomain(void) 2349 { 2350 struct fwnode_handle *fn; 2351 2352 /* No need for locking here (yet) as the init is single-threaded */ 2353 if (iommu_irqdomain) 2354 return iommu_irqdomain; 2355 2356 fn = irq_domain_alloc_named_fwnode("AMD-Vi-MSI"); 2357 if (!fn) 2358 return NULL; 2359 2360 iommu_irqdomain = irq_domain_create_hierarchy(x86_vector_domain, 0, 0, 2361 fn, &intcapxt_domain_ops, 2362 NULL); 2363 if (!iommu_irqdomain) 2364 irq_domain_free_fwnode(fn); 2365 2366 return iommu_irqdomain; 2367 } 2368 2369 static int __iommu_setup_intcapxt(struct amd_iommu *iommu, const char *devname, 2370 int hwirq, irq_handler_t thread_fn) 2371 { 2372 struct irq_domain *domain; 2373 struct irq_alloc_info info; 2374 int irq, ret; 2375 int node = dev_to_node(&iommu->dev->dev); 2376 2377 domain = iommu_get_irqdomain(); 2378 if (!domain) 2379 return -ENXIO; 2380 2381 init_irq_alloc_info(&info, NULL); 2382 info.type = X86_IRQ_ALLOC_TYPE_AMDVI; 2383 info.data = iommu; 2384 info.hwirq = hwirq; 2385 2386 irq = irq_domain_alloc_irqs(domain, 1, node, &info); 2387 if (irq < 0) { 2388 irq_domain_remove(domain); 2389 return irq; 2390 } 2391 2392 ret = request_threaded_irq(irq, amd_iommu_int_handler, 2393 thread_fn, 0, devname, iommu); 2394 if (ret) { 2395 irq_domain_free_irqs(irq, 1); 2396 irq_domain_remove(domain); 2397 return ret; 2398 } 2399 2400 return 0; 2401 } 2402 2403 static int iommu_setup_intcapxt(struct amd_iommu *iommu) 2404 { 2405 int ret; 2406 2407 snprintf(iommu->evt_irq_name, sizeof(iommu->evt_irq_name), 2408 "AMD-Vi%d-Evt", iommu->index); 2409 ret = __iommu_setup_intcapxt(iommu, iommu->evt_irq_name, 2410 MMIO_INTCAPXT_EVT_OFFSET, 2411 amd_iommu_int_thread_evtlog); 2412 if (ret) 2413 return ret; 2414 2415 snprintf(iommu->ppr_irq_name, sizeof(iommu->ppr_irq_name), 2416 "AMD-Vi%d-PPR", iommu->index); 2417 ret = __iommu_setup_intcapxt(iommu, iommu->ppr_irq_name, 2418 MMIO_INTCAPXT_PPR_OFFSET, 2419 amd_iommu_int_thread_pprlog); 2420 if (ret) 2421 return ret; 2422 2423 #ifdef CONFIG_IRQ_REMAP 2424 snprintf(iommu->ga_irq_name, sizeof(iommu->ga_irq_name), 2425 "AMD-Vi%d-GA", iommu->index); 2426 ret = __iommu_setup_intcapxt(iommu, iommu->ga_irq_name, 2427 MMIO_INTCAPXT_GALOG_OFFSET, 2428 amd_iommu_int_thread_galog); 2429 #endif 2430 2431 return ret; 2432 } 2433 2434 static int iommu_init_irq(struct amd_iommu *iommu) 2435 { 2436 int ret; 2437 2438 if (iommu->int_enabled) 2439 goto enable_faults; 2440 2441 if (amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE) 2442 ret = iommu_setup_intcapxt(iommu); 2443 else if (iommu->dev->msi_cap) 2444 ret = iommu_setup_msi(iommu); 2445 else 2446 ret = -ENODEV; 2447 2448 if (ret) 2449 return ret; 2450 2451 iommu->int_enabled = true; 2452 enable_faults: 2453 2454 if (amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE) 2455 iommu_feature_enable(iommu, CONTROL_INTCAPXT_EN); 2456 2457 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN); 2458 2459 return 0; 2460 } 2461 2462 /**************************************************************************** 2463 * 2464 * The next functions belong to the third pass of parsing the ACPI 2465 * table. In this last pass the memory mapping requirements are 2466 * gathered (like exclusion and unity mapping ranges). 2467 * 2468 ****************************************************************************/ 2469 2470 static void __init free_unity_maps(void) 2471 { 2472 struct unity_map_entry *entry, *next; 2473 struct amd_iommu_pci_seg *p, *pci_seg; 2474 2475 for_each_pci_segment_safe(pci_seg, p) { 2476 list_for_each_entry_safe(entry, next, &pci_seg->unity_map, list) { 2477 list_del(&entry->list); 2478 kfree(entry); 2479 } 2480 } 2481 } 2482 2483 /* called for unity map ACPI definition */ 2484 static int __init init_unity_map_range(struct ivmd_header *m, 2485 struct acpi_table_header *ivrs_base) 2486 { 2487 struct unity_map_entry *e = NULL; 2488 struct amd_iommu_pci_seg *pci_seg; 2489 char *s; 2490 2491 pci_seg = get_pci_segment(m->pci_seg, ivrs_base); 2492 if (pci_seg == NULL) 2493 return -ENOMEM; 2494 2495 e = kzalloc(sizeof(*e), GFP_KERNEL); 2496 if (e == NULL) 2497 return -ENOMEM; 2498 2499 switch (m->type) { 2500 default: 2501 kfree(e); 2502 return 0; 2503 case ACPI_IVMD_TYPE: 2504 s = "IVMD_TYPEi\t\t\t"; 2505 e->devid_start = e->devid_end = m->devid; 2506 break; 2507 case ACPI_IVMD_TYPE_ALL: 2508 s = "IVMD_TYPE_ALL\t\t"; 2509 e->devid_start = 0; 2510 e->devid_end = pci_seg->last_bdf; 2511 break; 2512 case ACPI_IVMD_TYPE_RANGE: 2513 s = "IVMD_TYPE_RANGE\t\t"; 2514 e->devid_start = m->devid; 2515 e->devid_end = m->aux; 2516 break; 2517 } 2518 e->address_start = PAGE_ALIGN(m->range_start); 2519 e->address_end = e->address_start + PAGE_ALIGN(m->range_length); 2520 e->prot = m->flags >> 1; 2521 2522 /* 2523 * Treat per-device exclusion ranges as r/w unity-mapped regions 2524 * since some buggy BIOSes might lead to the overwritten exclusion 2525 * range (exclusion_start and exclusion_length members). This 2526 * happens when there are multiple exclusion ranges (IVMD entries) 2527 * defined in ACPI table. 2528 */ 2529 if (m->flags & IVMD_FLAG_EXCL_RANGE) 2530 e->prot = (IVMD_FLAG_IW | IVMD_FLAG_IR) >> 1; 2531 2532 DUMP_printk("%s devid_start: %04x:%02x:%02x.%x devid_end: " 2533 "%04x:%02x:%02x.%x range_start: %016llx range_end: %016llx" 2534 " flags: %x\n", s, m->pci_seg, 2535 PCI_BUS_NUM(e->devid_start), PCI_SLOT(e->devid_start), 2536 PCI_FUNC(e->devid_start), m->pci_seg, 2537 PCI_BUS_NUM(e->devid_end), 2538 PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end), 2539 e->address_start, e->address_end, m->flags); 2540 2541 list_add_tail(&e->list, &pci_seg->unity_map); 2542 2543 return 0; 2544 } 2545 2546 /* iterates over all memory definitions we find in the ACPI table */ 2547 static int __init init_memory_definitions(struct acpi_table_header *table) 2548 { 2549 u8 *p = (u8 *)table, *end = (u8 *)table; 2550 struct ivmd_header *m; 2551 2552 end += table->length; 2553 p += IVRS_HEADER_LENGTH; 2554 2555 while (p < end) { 2556 m = (struct ivmd_header *)p; 2557 if (m->flags & (IVMD_FLAG_UNITY_MAP | IVMD_FLAG_EXCL_RANGE)) 2558 init_unity_map_range(m, table); 2559 2560 p += m->length; 2561 } 2562 2563 return 0; 2564 } 2565 2566 /* 2567 * Init the device table to not allow DMA access for devices 2568 */ 2569 static void init_device_table_dma(struct amd_iommu_pci_seg *pci_seg) 2570 { 2571 u32 devid; 2572 struct dev_table_entry *dev_table = pci_seg->dev_table; 2573 2574 if (dev_table == NULL) 2575 return; 2576 2577 for (devid = 0; devid <= pci_seg->last_bdf; ++devid) { 2578 __set_dev_entry_bit(dev_table, devid, DEV_ENTRY_VALID); 2579 if (!amd_iommu_snp_en) 2580 __set_dev_entry_bit(dev_table, devid, DEV_ENTRY_TRANSLATION); 2581 } 2582 } 2583 2584 static void __init uninit_device_table_dma(struct amd_iommu_pci_seg *pci_seg) 2585 { 2586 u32 devid; 2587 struct dev_table_entry *dev_table = pci_seg->dev_table; 2588 2589 if (dev_table == NULL) 2590 return; 2591 2592 for (devid = 0; devid <= pci_seg->last_bdf; ++devid) { 2593 dev_table[devid].data[0] = 0ULL; 2594 dev_table[devid].data[1] = 0ULL; 2595 } 2596 } 2597 2598 static void init_device_table(void) 2599 { 2600 struct amd_iommu_pci_seg *pci_seg; 2601 u32 devid; 2602 2603 if (!amd_iommu_irq_remap) 2604 return; 2605 2606 for_each_pci_segment(pci_seg) { 2607 for (devid = 0; devid <= pci_seg->last_bdf; ++devid) 2608 __set_dev_entry_bit(pci_seg->dev_table, 2609 devid, DEV_ENTRY_IRQ_TBL_EN); 2610 } 2611 } 2612 2613 static void iommu_init_flags(struct amd_iommu *iommu) 2614 { 2615 iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ? 2616 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) : 2617 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN); 2618 2619 iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ? 2620 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) : 2621 iommu_feature_disable(iommu, CONTROL_PASSPW_EN); 2622 2623 iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ? 2624 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) : 2625 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN); 2626 2627 iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ? 2628 iommu_feature_enable(iommu, CONTROL_ISOC_EN) : 2629 iommu_feature_disable(iommu, CONTROL_ISOC_EN); 2630 2631 /* 2632 * make IOMMU memory accesses cache coherent 2633 */ 2634 iommu_feature_enable(iommu, CONTROL_COHERENT_EN); 2635 2636 /* Set IOTLB invalidation timeout to 1s */ 2637 iommu_set_inv_tlb_timeout(iommu, CTRL_INV_TO_1S); 2638 } 2639 2640 static void iommu_apply_resume_quirks(struct amd_iommu *iommu) 2641 { 2642 int i, j; 2643 u32 ioc_feature_control; 2644 struct pci_dev *pdev = iommu->root_pdev; 2645 2646 /* RD890 BIOSes may not have completely reconfigured the iommu */ 2647 if (!is_rd890_iommu(iommu->dev) || !pdev) 2648 return; 2649 2650 /* 2651 * First, we need to ensure that the iommu is enabled. This is 2652 * controlled by a register in the northbridge 2653 */ 2654 2655 /* Select Northbridge indirect register 0x75 and enable writing */ 2656 pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7)); 2657 pci_read_config_dword(pdev, 0x64, &ioc_feature_control); 2658 2659 /* Enable the iommu */ 2660 if (!(ioc_feature_control & 0x1)) 2661 pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1); 2662 2663 /* Restore the iommu BAR */ 2664 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4, 2665 iommu->stored_addr_lo); 2666 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8, 2667 iommu->stored_addr_hi); 2668 2669 /* Restore the l1 indirect regs for each of the 6 l1s */ 2670 for (i = 0; i < 6; i++) 2671 for (j = 0; j < 0x12; j++) 2672 iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]); 2673 2674 /* Restore the l2 indirect regs */ 2675 for (i = 0; i < 0x83; i++) 2676 iommu_write_l2(iommu, i, iommu->stored_l2[i]); 2677 2678 /* Lock PCI setup registers */ 2679 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4, 2680 iommu->stored_addr_lo | 1); 2681 } 2682 2683 static void iommu_enable_ga(struct amd_iommu *iommu) 2684 { 2685 #ifdef CONFIG_IRQ_REMAP 2686 switch (amd_iommu_guest_ir) { 2687 case AMD_IOMMU_GUEST_IR_VAPIC: 2688 case AMD_IOMMU_GUEST_IR_LEGACY_GA: 2689 iommu_feature_enable(iommu, CONTROL_GA_EN); 2690 iommu->irte_ops = &irte_128_ops; 2691 break; 2692 default: 2693 iommu->irte_ops = &irte_32_ops; 2694 break; 2695 } 2696 #endif 2697 } 2698 2699 static void iommu_disable_irtcachedis(struct amd_iommu *iommu) 2700 { 2701 iommu_feature_disable(iommu, CONTROL_IRTCACHEDIS); 2702 } 2703 2704 static void iommu_enable_irtcachedis(struct amd_iommu *iommu) 2705 { 2706 u64 ctrl; 2707 2708 if (!amd_iommu_irtcachedis) 2709 return; 2710 2711 /* 2712 * Note: 2713 * The support for IRTCacheDis feature is dertermined by 2714 * checking if the bit is writable. 2715 */ 2716 iommu_feature_enable(iommu, CONTROL_IRTCACHEDIS); 2717 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); 2718 ctrl &= (1ULL << CONTROL_IRTCACHEDIS); 2719 if (ctrl) 2720 iommu->irtcachedis_enabled = true; 2721 pr_info("iommu%d (%#06x) : IRT cache is %s\n", 2722 iommu->index, iommu->devid, 2723 iommu->irtcachedis_enabled ? "disabled" : "enabled"); 2724 } 2725 2726 static void early_enable_iommu(struct amd_iommu *iommu) 2727 { 2728 iommu_disable(iommu); 2729 iommu_init_flags(iommu); 2730 iommu_set_device_table(iommu); 2731 iommu_enable_command_buffer(iommu); 2732 iommu_enable_event_buffer(iommu); 2733 iommu_set_exclusion_range(iommu); 2734 iommu_enable_gt(iommu); 2735 iommu_enable_ga(iommu); 2736 iommu_enable_xt(iommu); 2737 iommu_enable_irtcachedis(iommu); 2738 iommu_enable(iommu); 2739 amd_iommu_flush_all_caches(iommu); 2740 } 2741 2742 /* 2743 * This function finally enables all IOMMUs found in the system after 2744 * they have been initialized. 2745 * 2746 * Or if in kdump kernel and IOMMUs are all pre-enabled, try to copy 2747 * the old content of device table entries. Not this case or copy failed, 2748 * just continue as normal kernel does. 2749 */ 2750 static void early_enable_iommus(void) 2751 { 2752 struct amd_iommu *iommu; 2753 struct amd_iommu_pci_seg *pci_seg; 2754 2755 if (!copy_device_table()) { 2756 /* 2757 * If come here because of failure in copying device table from old 2758 * kernel with all IOMMUs enabled, print error message and try to 2759 * free allocated old_dev_tbl_cpy. 2760 */ 2761 if (amd_iommu_pre_enabled) 2762 pr_err("Failed to copy DEV table from previous kernel.\n"); 2763 2764 for_each_pci_segment(pci_seg) { 2765 if (pci_seg->old_dev_tbl_cpy != NULL) { 2766 iommu_free_pages(pci_seg->old_dev_tbl_cpy, 2767 get_order(pci_seg->dev_table_size)); 2768 pci_seg->old_dev_tbl_cpy = NULL; 2769 } 2770 } 2771 2772 for_each_iommu(iommu) { 2773 clear_translation_pre_enabled(iommu); 2774 early_enable_iommu(iommu); 2775 } 2776 } else { 2777 pr_info("Copied DEV table from previous kernel.\n"); 2778 2779 for_each_pci_segment(pci_seg) { 2780 iommu_free_pages(pci_seg->dev_table, 2781 get_order(pci_seg->dev_table_size)); 2782 pci_seg->dev_table = pci_seg->old_dev_tbl_cpy; 2783 } 2784 2785 for_each_iommu(iommu) { 2786 iommu_disable_command_buffer(iommu); 2787 iommu_disable_event_buffer(iommu); 2788 iommu_disable_irtcachedis(iommu); 2789 iommu_enable_command_buffer(iommu); 2790 iommu_enable_event_buffer(iommu); 2791 iommu_enable_ga(iommu); 2792 iommu_enable_xt(iommu); 2793 iommu_enable_irtcachedis(iommu); 2794 iommu_set_device_table(iommu); 2795 amd_iommu_flush_all_caches(iommu); 2796 } 2797 } 2798 } 2799 2800 static void enable_iommus_ppr(void) 2801 { 2802 struct amd_iommu *iommu; 2803 2804 if (!amd_iommu_gt_ppr_supported()) 2805 return; 2806 2807 for_each_iommu(iommu) 2808 amd_iommu_enable_ppr_log(iommu); 2809 } 2810 2811 static void enable_iommus_vapic(void) 2812 { 2813 #ifdef CONFIG_IRQ_REMAP 2814 u32 status, i; 2815 struct amd_iommu *iommu; 2816 2817 for_each_iommu(iommu) { 2818 /* 2819 * Disable GALog if already running. It could have been enabled 2820 * in the previous boot before kdump. 2821 */ 2822 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); 2823 if (!(status & MMIO_STATUS_GALOG_RUN_MASK)) 2824 continue; 2825 2826 iommu_feature_disable(iommu, CONTROL_GALOG_EN); 2827 iommu_feature_disable(iommu, CONTROL_GAINT_EN); 2828 2829 /* 2830 * Need to set and poll check the GALOGRun bit to zero before 2831 * we can set/ modify GA Log registers safely. 2832 */ 2833 for (i = 0; i < MMIO_STATUS_TIMEOUT; ++i) { 2834 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); 2835 if (!(status & MMIO_STATUS_GALOG_RUN_MASK)) 2836 break; 2837 udelay(10); 2838 } 2839 2840 if (WARN_ON(i >= MMIO_STATUS_TIMEOUT)) 2841 return; 2842 } 2843 2844 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) && 2845 !check_feature(FEATURE_GAM_VAPIC)) { 2846 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY_GA; 2847 return; 2848 } 2849 2850 if (amd_iommu_snp_en && 2851 !FEATURE_SNPAVICSUP_GAM(amd_iommu_efr2)) { 2852 pr_warn("Force to disable Virtual APIC due to SNP\n"); 2853 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY_GA; 2854 return; 2855 } 2856 2857 /* Enabling GAM and SNPAVIC support */ 2858 for_each_iommu(iommu) { 2859 if (iommu_init_ga_log(iommu) || 2860 iommu_ga_log_enable(iommu)) 2861 return; 2862 2863 iommu_feature_enable(iommu, CONTROL_GAM_EN); 2864 if (amd_iommu_snp_en) 2865 iommu_feature_enable(iommu, CONTROL_SNPAVIC_EN); 2866 } 2867 2868 amd_iommu_irq_ops.capability |= (1 << IRQ_POSTING_CAP); 2869 pr_info("Virtual APIC enabled\n"); 2870 #endif 2871 } 2872 2873 static void disable_iommus(void) 2874 { 2875 struct amd_iommu *iommu; 2876 2877 for_each_iommu(iommu) 2878 iommu_disable(iommu); 2879 2880 #ifdef CONFIG_IRQ_REMAP 2881 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) 2882 amd_iommu_irq_ops.capability &= ~(1 << IRQ_POSTING_CAP); 2883 #endif 2884 } 2885 2886 /* 2887 * Suspend/Resume support 2888 * disable suspend until real resume implemented 2889 */ 2890 2891 static void amd_iommu_resume(void) 2892 { 2893 struct amd_iommu *iommu; 2894 2895 for_each_iommu(iommu) 2896 iommu_apply_resume_quirks(iommu); 2897 2898 /* re-load the hardware */ 2899 for_each_iommu(iommu) 2900 early_enable_iommu(iommu); 2901 2902 amd_iommu_enable_interrupts(); 2903 } 2904 2905 static int amd_iommu_suspend(void) 2906 { 2907 /* disable IOMMUs to go out of the way for BIOS */ 2908 disable_iommus(); 2909 2910 return 0; 2911 } 2912 2913 static struct syscore_ops amd_iommu_syscore_ops = { 2914 .suspend = amd_iommu_suspend, 2915 .resume = amd_iommu_resume, 2916 }; 2917 2918 static void __init free_iommu_resources(void) 2919 { 2920 kmem_cache_destroy(amd_iommu_irq_cache); 2921 amd_iommu_irq_cache = NULL; 2922 2923 free_iommu_all(); 2924 free_pci_segments(); 2925 } 2926 2927 /* SB IOAPIC is always on this device in AMD systems */ 2928 #define IOAPIC_SB_DEVID ((0x00 << 8) | PCI_DEVFN(0x14, 0)) 2929 2930 static bool __init check_ioapic_information(void) 2931 { 2932 const char *fw_bug = FW_BUG; 2933 bool ret, has_sb_ioapic; 2934 int idx; 2935 2936 has_sb_ioapic = false; 2937 ret = false; 2938 2939 /* 2940 * If we have map overrides on the kernel command line the 2941 * messages in this function might not describe firmware bugs 2942 * anymore - so be careful 2943 */ 2944 if (cmdline_maps) 2945 fw_bug = ""; 2946 2947 for (idx = 0; idx < nr_ioapics; idx++) { 2948 int devid, id = mpc_ioapic_id(idx); 2949 2950 devid = get_ioapic_devid(id); 2951 if (devid < 0) { 2952 pr_err("%s: IOAPIC[%d] not in IVRS table\n", 2953 fw_bug, id); 2954 ret = false; 2955 } else if (devid == IOAPIC_SB_DEVID) { 2956 has_sb_ioapic = true; 2957 ret = true; 2958 } 2959 } 2960 2961 if (!has_sb_ioapic) { 2962 /* 2963 * We expect the SB IOAPIC to be listed in the IVRS 2964 * table. The system timer is connected to the SB IOAPIC 2965 * and if we don't have it in the list the system will 2966 * panic at boot time. This situation usually happens 2967 * when the BIOS is buggy and provides us the wrong 2968 * device id for the IOAPIC in the system. 2969 */ 2970 pr_err("%s: No southbridge IOAPIC found\n", fw_bug); 2971 } 2972 2973 if (!ret) 2974 pr_err("Disabling interrupt remapping\n"); 2975 2976 return ret; 2977 } 2978 2979 static void __init free_dma_resources(void) 2980 { 2981 ida_destroy(&pdom_ids); 2982 2983 free_unity_maps(); 2984 } 2985 2986 static void __init ivinfo_init(void *ivrs) 2987 { 2988 amd_iommu_ivinfo = *((u32 *)(ivrs + IOMMU_IVINFO_OFFSET)); 2989 } 2990 2991 /* 2992 * This is the hardware init function for AMD IOMMU in the system. 2993 * This function is called either from amd_iommu_init or from the interrupt 2994 * remapping setup code. 2995 * 2996 * This function basically parses the ACPI table for AMD IOMMU (IVRS) 2997 * four times: 2998 * 2999 * 1 pass) Discover the most comprehensive IVHD type to use. 3000 * 3001 * 2 pass) Find the highest PCI device id the driver has to handle. 3002 * Upon this information the size of the data structures is 3003 * determined that needs to be allocated. 3004 * 3005 * 3 pass) Initialize the data structures just allocated with the 3006 * information in the ACPI table about available AMD IOMMUs 3007 * in the system. It also maps the PCI devices in the 3008 * system to specific IOMMUs 3009 * 3010 * 4 pass) After the basic data structures are allocated and 3011 * initialized we update them with information about memory 3012 * remapping requirements parsed out of the ACPI table in 3013 * this last pass. 3014 * 3015 * After everything is set up the IOMMUs are enabled and the necessary 3016 * hotplug and suspend notifiers are registered. 3017 */ 3018 static int __init early_amd_iommu_init(void) 3019 { 3020 struct acpi_table_header *ivrs_base; 3021 int remap_cache_sz, ret; 3022 acpi_status status; 3023 3024 if (!amd_iommu_detected) 3025 return -ENODEV; 3026 3027 status = acpi_get_table("IVRS", 0, &ivrs_base); 3028 if (status == AE_NOT_FOUND) 3029 return -ENODEV; 3030 else if (ACPI_FAILURE(status)) { 3031 const char *err = acpi_format_exception(status); 3032 pr_err("IVRS table error: %s\n", err); 3033 return -EINVAL; 3034 } 3035 3036 /* 3037 * Validate checksum here so we don't need to do it when 3038 * we actually parse the table 3039 */ 3040 ret = check_ivrs_checksum(ivrs_base); 3041 if (ret) 3042 goto out; 3043 3044 ivinfo_init(ivrs_base); 3045 3046 amd_iommu_target_ivhd_type = get_highest_supported_ivhd_type(ivrs_base); 3047 DUMP_printk("Using IVHD type %#x\n", amd_iommu_target_ivhd_type); 3048 3049 /* 3050 * now the data structures are allocated and basically initialized 3051 * start the real acpi table scan 3052 */ 3053 ret = init_iommu_all(ivrs_base); 3054 if (ret) 3055 goto out; 3056 3057 /* 5 level guest page table */ 3058 if (cpu_feature_enabled(X86_FEATURE_LA57) && 3059 FIELD_GET(FEATURE_GATS, amd_iommu_efr) == GUEST_PGTABLE_5_LEVEL) 3060 amd_iommu_gpt_level = PAGE_MODE_5_LEVEL; 3061 3062 if (amd_iommu_pgtable == AMD_IOMMU_V2) { 3063 if (!amd_iommu_v2_pgtbl_supported()) { 3064 pr_warn("Cannot enable v2 page table for DMA-API. Fallback to v1.\n"); 3065 amd_iommu_pgtable = AMD_IOMMU_V1; 3066 } 3067 } 3068 3069 /* Disable any previously enabled IOMMUs */ 3070 if (!is_kdump_kernel() || amd_iommu_disabled) 3071 disable_iommus(); 3072 3073 if (amd_iommu_irq_remap) 3074 amd_iommu_irq_remap = check_ioapic_information(); 3075 3076 if (amd_iommu_irq_remap) { 3077 struct amd_iommu_pci_seg *pci_seg; 3078 /* 3079 * Interrupt remapping enabled, create kmem_cache for the 3080 * remapping tables. 3081 */ 3082 ret = -ENOMEM; 3083 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir)) 3084 remap_cache_sz = MAX_IRQS_PER_TABLE * sizeof(u32); 3085 else 3086 remap_cache_sz = MAX_IRQS_PER_TABLE * (sizeof(u64) * 2); 3087 amd_iommu_irq_cache = kmem_cache_create("irq_remap_cache", 3088 remap_cache_sz, 3089 DTE_INTTAB_ALIGNMENT, 3090 0, NULL); 3091 if (!amd_iommu_irq_cache) 3092 goto out; 3093 3094 for_each_pci_segment(pci_seg) { 3095 if (alloc_irq_lookup_table(pci_seg)) 3096 goto out; 3097 } 3098 } 3099 3100 ret = init_memory_definitions(ivrs_base); 3101 if (ret) 3102 goto out; 3103 3104 /* init the device table */ 3105 init_device_table(); 3106 3107 out: 3108 /* Don't leak any ACPI memory */ 3109 acpi_put_table(ivrs_base); 3110 3111 return ret; 3112 } 3113 3114 static int amd_iommu_enable_interrupts(void) 3115 { 3116 struct amd_iommu *iommu; 3117 int ret = 0; 3118 3119 for_each_iommu(iommu) { 3120 ret = iommu_init_irq(iommu); 3121 if (ret) 3122 goto out; 3123 } 3124 3125 /* 3126 * Interrupt handler is ready to process interrupts. Enable 3127 * PPR and GA log interrupt for all IOMMUs. 3128 */ 3129 enable_iommus_vapic(); 3130 enable_iommus_ppr(); 3131 3132 out: 3133 return ret; 3134 } 3135 3136 static bool __init detect_ivrs(void) 3137 { 3138 struct acpi_table_header *ivrs_base; 3139 acpi_status status; 3140 int i; 3141 3142 status = acpi_get_table("IVRS", 0, &ivrs_base); 3143 if (status == AE_NOT_FOUND) 3144 return false; 3145 else if (ACPI_FAILURE(status)) { 3146 const char *err = acpi_format_exception(status); 3147 pr_err("IVRS table error: %s\n", err); 3148 return false; 3149 } 3150 3151 acpi_put_table(ivrs_base); 3152 3153 if (amd_iommu_force_enable) 3154 goto out; 3155 3156 /* Don't use IOMMU if there is Stoney Ridge graphics */ 3157 for (i = 0; i < 32; i++) { 3158 u32 pci_id; 3159 3160 pci_id = read_pci_config(0, i, 0, 0); 3161 if ((pci_id & 0xffff) == 0x1002 && (pci_id >> 16) == 0x98e4) { 3162 pr_info("Disable IOMMU on Stoney Ridge\n"); 3163 return false; 3164 } 3165 } 3166 3167 out: 3168 /* Make sure ACS will be enabled during PCI probe */ 3169 pci_request_acs(); 3170 3171 return true; 3172 } 3173 3174 static void iommu_snp_enable(void) 3175 { 3176 #ifdef CONFIG_KVM_AMD_SEV 3177 if (!cc_platform_has(CC_ATTR_HOST_SEV_SNP)) 3178 return; 3179 /* 3180 * The SNP support requires that IOMMU must be enabled, and is 3181 * configured with V1 page table (DTE[Mode] = 0 is not supported). 3182 */ 3183 if (no_iommu || iommu_default_passthrough()) { 3184 pr_warn("SNP: IOMMU disabled or configured in passthrough mode, SNP cannot be supported.\n"); 3185 goto disable_snp; 3186 } 3187 3188 if (amd_iommu_pgtable != AMD_IOMMU_V1) { 3189 pr_warn("SNP: IOMMU is configured with V2 page table mode, SNP cannot be supported.\n"); 3190 goto disable_snp; 3191 } 3192 3193 amd_iommu_snp_en = check_feature(FEATURE_SNP); 3194 if (!amd_iommu_snp_en) { 3195 pr_warn("SNP: IOMMU SNP feature not enabled, SNP cannot be supported.\n"); 3196 goto disable_snp; 3197 } 3198 3199 pr_info("IOMMU SNP support enabled.\n"); 3200 return; 3201 3202 disable_snp: 3203 cc_platform_clear(CC_ATTR_HOST_SEV_SNP); 3204 #endif 3205 } 3206 3207 /**************************************************************************** 3208 * 3209 * AMD IOMMU Initialization State Machine 3210 * 3211 ****************************************************************************/ 3212 3213 static int __init state_next(void) 3214 { 3215 int ret = 0; 3216 3217 switch (init_state) { 3218 case IOMMU_START_STATE: 3219 if (!detect_ivrs()) { 3220 init_state = IOMMU_NOT_FOUND; 3221 ret = -ENODEV; 3222 } else { 3223 init_state = IOMMU_IVRS_DETECTED; 3224 } 3225 break; 3226 case IOMMU_IVRS_DETECTED: 3227 if (amd_iommu_disabled) { 3228 init_state = IOMMU_CMDLINE_DISABLED; 3229 ret = -EINVAL; 3230 } else { 3231 ret = early_amd_iommu_init(); 3232 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_ACPI_FINISHED; 3233 } 3234 break; 3235 case IOMMU_ACPI_FINISHED: 3236 early_enable_iommus(); 3237 x86_platform.iommu_shutdown = disable_iommus; 3238 init_state = IOMMU_ENABLED; 3239 break; 3240 case IOMMU_ENABLED: 3241 register_syscore_ops(&amd_iommu_syscore_ops); 3242 iommu_snp_enable(); 3243 ret = amd_iommu_init_pci(); 3244 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_PCI_INIT; 3245 break; 3246 case IOMMU_PCI_INIT: 3247 ret = amd_iommu_enable_interrupts(); 3248 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_INTERRUPTS_EN; 3249 break; 3250 case IOMMU_INTERRUPTS_EN: 3251 init_state = IOMMU_INITIALIZED; 3252 break; 3253 case IOMMU_INITIALIZED: 3254 /* Nothing to do */ 3255 break; 3256 case IOMMU_NOT_FOUND: 3257 case IOMMU_INIT_ERROR: 3258 case IOMMU_CMDLINE_DISABLED: 3259 /* Error states => do nothing */ 3260 ret = -EINVAL; 3261 break; 3262 default: 3263 /* Unknown state */ 3264 BUG(); 3265 } 3266 3267 if (ret) { 3268 free_dma_resources(); 3269 if (!irq_remapping_enabled) { 3270 disable_iommus(); 3271 free_iommu_resources(); 3272 } else { 3273 struct amd_iommu *iommu; 3274 struct amd_iommu_pci_seg *pci_seg; 3275 3276 for_each_pci_segment(pci_seg) 3277 uninit_device_table_dma(pci_seg); 3278 3279 for_each_iommu(iommu) 3280 amd_iommu_flush_all_caches(iommu); 3281 } 3282 } 3283 return ret; 3284 } 3285 3286 static int __init iommu_go_to_state(enum iommu_init_state state) 3287 { 3288 int ret = -EINVAL; 3289 3290 while (init_state != state) { 3291 if (init_state == IOMMU_NOT_FOUND || 3292 init_state == IOMMU_INIT_ERROR || 3293 init_state == IOMMU_CMDLINE_DISABLED) 3294 break; 3295 ret = state_next(); 3296 } 3297 3298 return ret; 3299 } 3300 3301 #ifdef CONFIG_IRQ_REMAP 3302 int __init amd_iommu_prepare(void) 3303 { 3304 int ret; 3305 3306 amd_iommu_irq_remap = true; 3307 3308 ret = iommu_go_to_state(IOMMU_ACPI_FINISHED); 3309 if (ret) { 3310 amd_iommu_irq_remap = false; 3311 return ret; 3312 } 3313 3314 return amd_iommu_irq_remap ? 0 : -ENODEV; 3315 } 3316 3317 int __init amd_iommu_enable(void) 3318 { 3319 int ret; 3320 3321 ret = iommu_go_to_state(IOMMU_ENABLED); 3322 if (ret) 3323 return ret; 3324 3325 irq_remapping_enabled = 1; 3326 return amd_iommu_xt_mode; 3327 } 3328 3329 void amd_iommu_disable(void) 3330 { 3331 amd_iommu_suspend(); 3332 } 3333 3334 int amd_iommu_reenable(int mode) 3335 { 3336 amd_iommu_resume(); 3337 3338 return 0; 3339 } 3340 3341 int amd_iommu_enable_faulting(unsigned int cpu) 3342 { 3343 /* We enable MSI later when PCI is initialized */ 3344 return 0; 3345 } 3346 #endif 3347 3348 /* 3349 * This is the core init function for AMD IOMMU hardware in the system. 3350 * This function is called from the generic x86 DMA layer initialization 3351 * code. 3352 */ 3353 static int __init amd_iommu_init(void) 3354 { 3355 struct amd_iommu *iommu; 3356 int ret; 3357 3358 ret = iommu_go_to_state(IOMMU_INITIALIZED); 3359 #ifdef CONFIG_GART_IOMMU 3360 if (ret && list_empty(&amd_iommu_list)) { 3361 /* 3362 * We failed to initialize the AMD IOMMU - try fallback 3363 * to GART if possible. 3364 */ 3365 gart_iommu_init(); 3366 } 3367 #endif 3368 3369 for_each_iommu(iommu) 3370 amd_iommu_debugfs_setup(iommu); 3371 3372 return ret; 3373 } 3374 3375 static bool amd_iommu_sme_check(void) 3376 { 3377 if (!cc_platform_has(CC_ATTR_HOST_MEM_ENCRYPT) || 3378 (boot_cpu_data.x86 != 0x17)) 3379 return true; 3380 3381 /* For Fam17h, a specific level of support is required */ 3382 if (boot_cpu_data.microcode >= 0x08001205) 3383 return true; 3384 3385 if ((boot_cpu_data.microcode >= 0x08001126) && 3386 (boot_cpu_data.microcode <= 0x080011ff)) 3387 return true; 3388 3389 pr_notice("IOMMU not currently supported when SME is active\n"); 3390 3391 return false; 3392 } 3393 3394 /**************************************************************************** 3395 * 3396 * Early detect code. This code runs at IOMMU detection time in the DMA 3397 * layer. It just looks if there is an IVRS ACPI table to detect AMD 3398 * IOMMUs 3399 * 3400 ****************************************************************************/ 3401 int __init amd_iommu_detect(void) 3402 { 3403 int ret; 3404 3405 if (no_iommu || (iommu_detected && !gart_iommu_aperture)) 3406 return -ENODEV; 3407 3408 if (!amd_iommu_sme_check()) 3409 return -ENODEV; 3410 3411 ret = iommu_go_to_state(IOMMU_IVRS_DETECTED); 3412 if (ret) 3413 return ret; 3414 3415 amd_iommu_detected = true; 3416 iommu_detected = 1; 3417 x86_init.iommu.iommu_init = amd_iommu_init; 3418 3419 return 1; 3420 } 3421 3422 /**************************************************************************** 3423 * 3424 * Parsing functions for the AMD IOMMU specific kernel command line 3425 * options. 3426 * 3427 ****************************************************************************/ 3428 3429 static int __init parse_amd_iommu_dump(char *str) 3430 { 3431 amd_iommu_dump = true; 3432 3433 return 1; 3434 } 3435 3436 static int __init parse_amd_iommu_intr(char *str) 3437 { 3438 for (; *str; ++str) { 3439 if (strncmp(str, "legacy", 6) == 0) { 3440 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY_GA; 3441 break; 3442 } 3443 if (strncmp(str, "vapic", 5) == 0) { 3444 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC; 3445 break; 3446 } 3447 } 3448 return 1; 3449 } 3450 3451 static int __init parse_amd_iommu_options(char *str) 3452 { 3453 if (!str) 3454 return -EINVAL; 3455 3456 while (*str) { 3457 if (strncmp(str, "fullflush", 9) == 0) { 3458 pr_warn("amd_iommu=fullflush deprecated; use iommu.strict=1 instead\n"); 3459 iommu_set_dma_strict(); 3460 } else if (strncmp(str, "force_enable", 12) == 0) { 3461 amd_iommu_force_enable = true; 3462 } else if (strncmp(str, "off", 3) == 0) { 3463 amd_iommu_disabled = true; 3464 } else if (strncmp(str, "force_isolation", 15) == 0) { 3465 amd_iommu_force_isolation = true; 3466 } else if (strncmp(str, "pgtbl_v1", 8) == 0) { 3467 amd_iommu_pgtable = AMD_IOMMU_V1; 3468 } else if (strncmp(str, "pgtbl_v2", 8) == 0) { 3469 amd_iommu_pgtable = AMD_IOMMU_V2; 3470 } else if (strncmp(str, "irtcachedis", 11) == 0) { 3471 amd_iommu_irtcachedis = true; 3472 } else if (strncmp(str, "nohugepages", 11) == 0) { 3473 pr_info("Restricting V1 page-sizes to 4KiB"); 3474 amd_iommu_pgsize_bitmap = AMD_IOMMU_PGSIZES_4K; 3475 } else if (strncmp(str, "v2_pgsizes_only", 15) == 0) { 3476 pr_info("Restricting V1 page-sizes to 4KiB/2MiB/1GiB"); 3477 amd_iommu_pgsize_bitmap = AMD_IOMMU_PGSIZES_V2; 3478 } else { 3479 pr_notice("Unknown option - '%s'\n", str); 3480 } 3481 3482 str += strcspn(str, ","); 3483 while (*str == ',') 3484 str++; 3485 } 3486 3487 return 1; 3488 } 3489 3490 static int __init parse_ivrs_ioapic(char *str) 3491 { 3492 u32 seg = 0, bus, dev, fn; 3493 int id, i; 3494 u32 devid; 3495 3496 if (sscanf(str, "=%d@%x:%x.%x", &id, &bus, &dev, &fn) == 4 || 3497 sscanf(str, "=%d@%x:%x:%x.%x", &id, &seg, &bus, &dev, &fn) == 5) 3498 goto found; 3499 3500 if (sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn) == 4 || 3501 sscanf(str, "[%d]=%x:%x:%x.%x", &id, &seg, &bus, &dev, &fn) == 5) { 3502 pr_warn("ivrs_ioapic%s option format deprecated; use ivrs_ioapic=%d@%04x:%02x:%02x.%d instead\n", 3503 str, id, seg, bus, dev, fn); 3504 goto found; 3505 } 3506 3507 pr_err("Invalid command line: ivrs_ioapic%s\n", str); 3508 return 1; 3509 3510 found: 3511 if (early_ioapic_map_size == EARLY_MAP_SIZE) { 3512 pr_err("Early IOAPIC map overflow - ignoring ivrs_ioapic%s\n", 3513 str); 3514 return 1; 3515 } 3516 3517 devid = IVRS_GET_SBDF_ID(seg, bus, dev, fn); 3518 3519 cmdline_maps = true; 3520 i = early_ioapic_map_size++; 3521 early_ioapic_map[i].id = id; 3522 early_ioapic_map[i].devid = devid; 3523 early_ioapic_map[i].cmd_line = true; 3524 3525 return 1; 3526 } 3527 3528 static int __init parse_ivrs_hpet(char *str) 3529 { 3530 u32 seg = 0, bus, dev, fn; 3531 int id, i; 3532 u32 devid; 3533 3534 if (sscanf(str, "=%d@%x:%x.%x", &id, &bus, &dev, &fn) == 4 || 3535 sscanf(str, "=%d@%x:%x:%x.%x", &id, &seg, &bus, &dev, &fn) == 5) 3536 goto found; 3537 3538 if (sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn) == 4 || 3539 sscanf(str, "[%d]=%x:%x:%x.%x", &id, &seg, &bus, &dev, &fn) == 5) { 3540 pr_warn("ivrs_hpet%s option format deprecated; use ivrs_hpet=%d@%04x:%02x:%02x.%d instead\n", 3541 str, id, seg, bus, dev, fn); 3542 goto found; 3543 } 3544 3545 pr_err("Invalid command line: ivrs_hpet%s\n", str); 3546 return 1; 3547 3548 found: 3549 if (early_hpet_map_size == EARLY_MAP_SIZE) { 3550 pr_err("Early HPET map overflow - ignoring ivrs_hpet%s\n", 3551 str); 3552 return 1; 3553 } 3554 3555 devid = IVRS_GET_SBDF_ID(seg, bus, dev, fn); 3556 3557 cmdline_maps = true; 3558 i = early_hpet_map_size++; 3559 early_hpet_map[i].id = id; 3560 early_hpet_map[i].devid = devid; 3561 early_hpet_map[i].cmd_line = true; 3562 3563 return 1; 3564 } 3565 3566 #define ACPIID_LEN (ACPIHID_UID_LEN + ACPIHID_HID_LEN) 3567 3568 static int __init parse_ivrs_acpihid(char *str) 3569 { 3570 u32 seg = 0, bus, dev, fn; 3571 char *hid, *uid, *p, *addr; 3572 char acpiid[ACPIID_LEN] = {0}; 3573 int i; 3574 3575 addr = strchr(str, '@'); 3576 if (!addr) { 3577 addr = strchr(str, '='); 3578 if (!addr) 3579 goto not_found; 3580 3581 ++addr; 3582 3583 if (strlen(addr) > ACPIID_LEN) 3584 goto not_found; 3585 3586 if (sscanf(str, "[%x:%x.%x]=%s", &bus, &dev, &fn, acpiid) == 4 || 3587 sscanf(str, "[%x:%x:%x.%x]=%s", &seg, &bus, &dev, &fn, acpiid) == 5) { 3588 pr_warn("ivrs_acpihid%s option format deprecated; use ivrs_acpihid=%s@%04x:%02x:%02x.%d instead\n", 3589 str, acpiid, seg, bus, dev, fn); 3590 goto found; 3591 } 3592 goto not_found; 3593 } 3594 3595 /* We have the '@', make it the terminator to get just the acpiid */ 3596 *addr++ = 0; 3597 3598 if (strlen(str) > ACPIID_LEN + 1) 3599 goto not_found; 3600 3601 if (sscanf(str, "=%s", acpiid) != 1) 3602 goto not_found; 3603 3604 if (sscanf(addr, "%x:%x.%x", &bus, &dev, &fn) == 3 || 3605 sscanf(addr, "%x:%x:%x.%x", &seg, &bus, &dev, &fn) == 4) 3606 goto found; 3607 3608 not_found: 3609 pr_err("Invalid command line: ivrs_acpihid%s\n", str); 3610 return 1; 3611 3612 found: 3613 p = acpiid; 3614 hid = strsep(&p, ":"); 3615 uid = p; 3616 3617 if (!hid || !(*hid) || !uid) { 3618 pr_err("Invalid command line: hid or uid\n"); 3619 return 1; 3620 } 3621 3622 /* 3623 * Ignore leading zeroes after ':', so e.g., AMDI0095:00 3624 * will match AMDI0095:0 in the second strcmp in acpi_dev_hid_uid_match 3625 */ 3626 while (*uid == '0' && *(uid + 1)) 3627 uid++; 3628 3629 i = early_acpihid_map_size++; 3630 memcpy(early_acpihid_map[i].hid, hid, strlen(hid)); 3631 memcpy(early_acpihid_map[i].uid, uid, strlen(uid)); 3632 early_acpihid_map[i].devid = IVRS_GET_SBDF_ID(seg, bus, dev, fn); 3633 early_acpihid_map[i].cmd_line = true; 3634 3635 return 1; 3636 } 3637 3638 __setup("amd_iommu_dump", parse_amd_iommu_dump); 3639 __setup("amd_iommu=", parse_amd_iommu_options); 3640 __setup("amd_iommu_intr=", parse_amd_iommu_intr); 3641 __setup("ivrs_ioapic", parse_ivrs_ioapic); 3642 __setup("ivrs_hpet", parse_ivrs_hpet); 3643 __setup("ivrs_acpihid", parse_ivrs_acpihid); 3644 3645 bool amd_iommu_pasid_supported(void) 3646 { 3647 /* CPU page table size should match IOMMU guest page table size */ 3648 if (cpu_feature_enabled(X86_FEATURE_LA57) && 3649 amd_iommu_gpt_level != PAGE_MODE_5_LEVEL) 3650 return false; 3651 3652 /* 3653 * Since DTE[Mode]=0 is prohibited on SNP-enabled system 3654 * (i.e. EFR[SNPSup]=1), IOMMUv2 page table cannot be used without 3655 * setting up IOMMUv1 page table. 3656 */ 3657 return amd_iommu_gt_ppr_supported() && !amd_iommu_snp_en; 3658 } 3659 3660 struct amd_iommu *get_amd_iommu(unsigned int idx) 3661 { 3662 unsigned int i = 0; 3663 struct amd_iommu *iommu; 3664 3665 for_each_iommu(iommu) 3666 if (i++ == idx) 3667 return iommu; 3668 return NULL; 3669 } 3670 3671 /**************************************************************************** 3672 * 3673 * IOMMU EFR Performance Counter support functionality. This code allows 3674 * access to the IOMMU PC functionality. 3675 * 3676 ****************************************************************************/ 3677 3678 u8 amd_iommu_pc_get_max_banks(unsigned int idx) 3679 { 3680 struct amd_iommu *iommu = get_amd_iommu(idx); 3681 3682 if (iommu) 3683 return iommu->max_banks; 3684 3685 return 0; 3686 } 3687 3688 bool amd_iommu_pc_supported(void) 3689 { 3690 return amd_iommu_pc_present; 3691 } 3692 3693 u8 amd_iommu_pc_get_max_counters(unsigned int idx) 3694 { 3695 struct amd_iommu *iommu = get_amd_iommu(idx); 3696 3697 if (iommu) 3698 return iommu->max_counters; 3699 3700 return 0; 3701 } 3702 3703 static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, 3704 u8 fxn, u64 *value, bool is_write) 3705 { 3706 u32 offset; 3707 u32 max_offset_lim; 3708 3709 /* Make sure the IOMMU PC resource is available */ 3710 if (!amd_iommu_pc_present) 3711 return -ENODEV; 3712 3713 /* Check for valid iommu and pc register indexing */ 3714 if (WARN_ON(!iommu || (fxn > 0x28) || (fxn & 7))) 3715 return -ENODEV; 3716 3717 offset = (u32)(((0x40 | bank) << 12) | (cntr << 8) | fxn); 3718 3719 /* Limit the offset to the hw defined mmio region aperture */ 3720 max_offset_lim = (u32)(((0x40 | iommu->max_banks) << 12) | 3721 (iommu->max_counters << 8) | 0x28); 3722 if ((offset < MMIO_CNTR_REG_OFFSET) || 3723 (offset > max_offset_lim)) 3724 return -EINVAL; 3725 3726 if (is_write) { 3727 u64 val = *value & GENMASK_ULL(47, 0); 3728 3729 writel((u32)val, iommu->mmio_base + offset); 3730 writel((val >> 32), iommu->mmio_base + offset + 4); 3731 } else { 3732 *value = readl(iommu->mmio_base + offset + 4); 3733 *value <<= 32; 3734 *value |= readl(iommu->mmio_base + offset); 3735 *value &= GENMASK_ULL(47, 0); 3736 } 3737 3738 return 0; 3739 } 3740 3741 int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value) 3742 { 3743 if (!iommu) 3744 return -EINVAL; 3745 3746 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, false); 3747 } 3748 3749 int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value) 3750 { 3751 if (!iommu) 3752 return -EINVAL; 3753 3754 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, true); 3755 } 3756 3757 #ifdef CONFIG_KVM_AMD_SEV 3758 static int iommu_page_make_shared(void *page) 3759 { 3760 unsigned long paddr, pfn; 3761 3762 paddr = iommu_virt_to_phys(page); 3763 /* Cbit maybe set in the paddr */ 3764 pfn = __sme_clr(paddr) >> PAGE_SHIFT; 3765 3766 if (!(pfn % PTRS_PER_PMD)) { 3767 int ret, level; 3768 bool assigned; 3769 3770 ret = snp_lookup_rmpentry(pfn, &assigned, &level); 3771 if (ret) { 3772 pr_warn("IOMMU PFN %lx RMP lookup failed, ret %d\n", pfn, ret); 3773 return ret; 3774 } 3775 3776 if (!assigned) { 3777 pr_warn("IOMMU PFN %lx not assigned in RMP table\n", pfn); 3778 return -EINVAL; 3779 } 3780 3781 if (level > PG_LEVEL_4K) { 3782 ret = psmash(pfn); 3783 if (!ret) 3784 goto done; 3785 3786 pr_warn("PSMASH failed for IOMMU PFN %lx huge RMP entry, ret: %d, level: %d\n", 3787 pfn, ret, level); 3788 return ret; 3789 } 3790 } 3791 3792 done: 3793 return rmp_make_shared(pfn, PG_LEVEL_4K); 3794 } 3795 3796 static int iommu_make_shared(void *va, size_t size) 3797 { 3798 void *page; 3799 int ret; 3800 3801 if (!va) 3802 return 0; 3803 3804 for (page = va; page < (va + size); page += PAGE_SIZE) { 3805 ret = iommu_page_make_shared(page); 3806 if (ret) 3807 return ret; 3808 } 3809 3810 return 0; 3811 } 3812 3813 int amd_iommu_snp_disable(void) 3814 { 3815 struct amd_iommu *iommu; 3816 int ret; 3817 3818 if (!amd_iommu_snp_en) 3819 return 0; 3820 3821 for_each_iommu(iommu) { 3822 ret = iommu_make_shared(iommu->evt_buf, EVT_BUFFER_SIZE); 3823 if (ret) 3824 return ret; 3825 3826 ret = iommu_make_shared(iommu->ppr_log, PPR_LOG_SIZE); 3827 if (ret) 3828 return ret; 3829 3830 ret = iommu_make_shared((void *)iommu->cmd_sem, PAGE_SIZE); 3831 if (ret) 3832 return ret; 3833 } 3834 3835 return 0; 3836 } 3837 EXPORT_SYMBOL_GPL(amd_iommu_snp_disable); 3838 #endif 3839