1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. 4 * Author: Joerg Roedel <jroedel@suse.de> 5 * Leo Duran <leo.duran@amd.com> 6 */ 7 8 #define pr_fmt(fmt) "AMD-Vi: " fmt 9 #define dev_fmt(fmt) pr_fmt(fmt) 10 11 #include <linux/pci.h> 12 #include <linux/acpi.h> 13 #include <linux/list.h> 14 #include <linux/bitmap.h> 15 #include <linux/syscore_ops.h> 16 #include <linux/interrupt.h> 17 #include <linux/msi.h> 18 #include <linux/irq.h> 19 #include <linux/amd-iommu.h> 20 #include <linux/export.h> 21 #include <linux/kmemleak.h> 22 #include <linux/cc_platform.h> 23 #include <linux/iopoll.h> 24 #include <asm/pci-direct.h> 25 #include <asm/iommu.h> 26 #include <asm/apic.h> 27 #include <asm/gart.h> 28 #include <asm/x86_init.h> 29 #include <asm/io_apic.h> 30 #include <asm/irq_remapping.h> 31 #include <asm/set_memory.h> 32 #include <asm/sev.h> 33 34 #include <linux/crash_dump.h> 35 36 #include "amd_iommu.h" 37 #include "../irq_remapping.h" 38 #include "../iommu-pages.h" 39 40 /* 41 * definitions for the ACPI scanning code 42 */ 43 #define IVRS_HEADER_LENGTH 48 44 45 #define ACPI_IVHD_TYPE_MAX_SUPPORTED 0x40 46 #define ACPI_IVMD_TYPE_ALL 0x20 47 #define ACPI_IVMD_TYPE 0x21 48 #define ACPI_IVMD_TYPE_RANGE 0x22 49 50 #define IVHD_DEV_ALL 0x01 51 #define IVHD_DEV_SELECT 0x02 52 #define IVHD_DEV_SELECT_RANGE_START 0x03 53 #define IVHD_DEV_RANGE_END 0x04 54 #define IVHD_DEV_ALIAS 0x42 55 #define IVHD_DEV_ALIAS_RANGE 0x43 56 #define IVHD_DEV_EXT_SELECT 0x46 57 #define IVHD_DEV_EXT_SELECT_RANGE 0x47 58 #define IVHD_DEV_SPECIAL 0x48 59 #define IVHD_DEV_ACPI_HID 0xf0 60 61 #define UID_NOT_PRESENT 0 62 #define UID_IS_INTEGER 1 63 #define UID_IS_CHARACTER 2 64 65 #define IVHD_SPECIAL_IOAPIC 1 66 #define IVHD_SPECIAL_HPET 2 67 68 #define IVHD_FLAG_HT_TUN_EN_MASK 0x01 69 #define IVHD_FLAG_PASSPW_EN_MASK 0x02 70 #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04 71 #define IVHD_FLAG_ISOC_EN_MASK 0x08 72 73 #define IVMD_FLAG_EXCL_RANGE 0x08 74 #define IVMD_FLAG_IW 0x04 75 #define IVMD_FLAG_IR 0x02 76 #define IVMD_FLAG_UNITY_MAP 0x01 77 78 #define ACPI_DEVFLAG_INITPASS 0x01 79 #define ACPI_DEVFLAG_EXTINT 0x02 80 #define ACPI_DEVFLAG_NMI 0x04 81 #define ACPI_DEVFLAG_SYSMGT1 0x10 82 #define ACPI_DEVFLAG_SYSMGT2 0x20 83 #define ACPI_DEVFLAG_LINT0 0x40 84 #define ACPI_DEVFLAG_LINT1 0x80 85 #define ACPI_DEVFLAG_ATSDIS 0x10000000 86 87 #define IVRS_GET_SBDF_ID(seg, bus, dev, fn) (((seg & 0xffff) << 16) | ((bus & 0xff) << 8) \ 88 | ((dev & 0x1f) << 3) | (fn & 0x7)) 89 90 /* 91 * ACPI table definitions 92 * 93 * These data structures are laid over the table to parse the important values 94 * out of it. 95 */ 96 97 /* 98 * structure describing one IOMMU in the ACPI table. Typically followed by one 99 * or more ivhd_entrys. 100 */ 101 struct ivhd_header { 102 u8 type; 103 u8 flags; 104 u16 length; 105 u16 devid; 106 u16 cap_ptr; 107 u64 mmio_phys; 108 u16 pci_seg; 109 u16 info; 110 u32 efr_attr; 111 112 /* Following only valid on IVHD type 11h and 40h */ 113 u64 efr_reg; /* Exact copy of MMIO_EXT_FEATURES */ 114 u64 efr_reg2; 115 } __attribute__((packed)); 116 117 /* 118 * A device entry describing which devices a specific IOMMU translates and 119 * which requestor ids they use. 120 */ 121 struct ivhd_entry { 122 u8 type; 123 u16 devid; 124 u8 flags; 125 struct_group(ext_hid, 126 u32 ext; 127 u32 hidh; 128 ); 129 u64 cid; 130 u8 uidf; 131 u8 uidl; 132 u8 uid; 133 } __attribute__((packed)); 134 135 int amd_iommu_evtlog_size = EVTLOG_SIZE_DEF; 136 int amd_iommu_pprlog_size = PPRLOG_SIZE_DEF; 137 138 /* 139 * An AMD IOMMU memory definition structure. It defines things like exclusion 140 * ranges for devices and regions that should be unity mapped. 141 */ 142 struct ivmd_header { 143 u8 type; 144 u8 flags; 145 u16 length; 146 u16 devid; 147 u16 aux; 148 u16 pci_seg; 149 u8 resv[6]; 150 u64 range_start; 151 u64 range_length; 152 } __attribute__((packed)); 153 154 bool amd_iommu_dump; 155 bool amd_iommu_irq_remap __read_mostly; 156 157 enum protection_domain_mode amd_iommu_pgtable = PD_MODE_V1; 158 /* Virtual address size */ 159 u8 amd_iommu_hpt_vasize; 160 /* Guest page table level */ 161 int amd_iommu_gpt_level = PAGE_MODE_4_LEVEL; 162 163 int amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC; 164 static int amd_iommu_xt_mode = IRQ_REMAP_XAPIC_MODE; 165 166 static bool amd_iommu_detected; 167 static bool amd_iommu_disabled __initdata; 168 static bool amd_iommu_force_enable __initdata; 169 static bool amd_iommu_irtcachedis; 170 static int amd_iommu_target_ivhd_type; 171 172 /* Global EFR and EFR2 registers */ 173 u64 amd_iommu_efr; 174 u64 amd_iommu_efr2; 175 176 /* Host (v1) page table is not supported*/ 177 bool amd_iommu_hatdis; 178 179 /* SNP is enabled on the system? */ 180 bool amd_iommu_snp_en; 181 EXPORT_SYMBOL(amd_iommu_snp_en); 182 183 /* SNP page mode 0 support */ 184 bool amd_iommu_snp_mode0_sup; 185 186 LIST_HEAD(amd_iommu_pci_seg_list); /* list of all PCI segments */ 187 LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the system */ 188 LIST_HEAD(amd_ivhd_dev_flags_list); /* list of all IVHD device entry settings */ 189 190 /* Number of IOMMUs present in the system */ 191 static int amd_iommus_present; 192 193 /* IOMMUs have a non-present cache? */ 194 bool amd_iommu_np_cache __read_mostly; 195 bool amd_iommu_iotlb_sup __read_mostly = true; 196 197 static bool amd_iommu_pc_present __read_mostly; 198 bool amdr_ivrs_remap_support __read_mostly; 199 200 bool amd_iommu_force_isolation __read_mostly; 201 202 unsigned long amd_iommu_pgsize_bitmap __ro_after_init = AMD_IOMMU_PGSIZES; 203 204 enum iommu_init_state { 205 IOMMU_START_STATE, 206 IOMMU_IVRS_DETECTED, 207 IOMMU_ACPI_FINISHED, 208 IOMMU_ENABLED, 209 IOMMU_PCI_INIT, 210 IOMMU_INTERRUPTS_EN, 211 IOMMU_INITIALIZED, 212 IOMMU_NOT_FOUND, 213 IOMMU_INIT_ERROR, 214 IOMMU_CMDLINE_DISABLED, 215 }; 216 217 /* Early ioapic and hpet maps from kernel command line */ 218 #define EARLY_MAP_SIZE 4 219 static struct devid_map __initdata early_ioapic_map[EARLY_MAP_SIZE]; 220 static struct devid_map __initdata early_hpet_map[EARLY_MAP_SIZE]; 221 static struct acpihid_map_entry __initdata early_acpihid_map[EARLY_MAP_SIZE]; 222 223 static int __initdata early_ioapic_map_size; 224 static int __initdata early_hpet_map_size; 225 static int __initdata early_acpihid_map_size; 226 227 static bool __initdata cmdline_maps; 228 229 static enum iommu_init_state init_state = IOMMU_START_STATE; 230 231 static int amd_iommu_enable_interrupts(void); 232 static void init_device_table_dma(struct amd_iommu_pci_seg *pci_seg); 233 234 static bool amd_iommu_pre_enabled = true; 235 236 static u32 amd_iommu_ivinfo __initdata; 237 238 bool translation_pre_enabled(struct amd_iommu *iommu) 239 { 240 return (iommu->flags & AMD_IOMMU_FLAG_TRANS_PRE_ENABLED); 241 } 242 243 static void clear_translation_pre_enabled(struct amd_iommu *iommu) 244 { 245 iommu->flags &= ~AMD_IOMMU_FLAG_TRANS_PRE_ENABLED; 246 } 247 248 static void init_translation_status(struct amd_iommu *iommu) 249 { 250 u64 ctrl; 251 252 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); 253 if (ctrl & (1<<CONTROL_IOMMU_EN)) 254 iommu->flags |= AMD_IOMMU_FLAG_TRANS_PRE_ENABLED; 255 } 256 257 int amd_iommu_get_num_iommus(void) 258 { 259 return amd_iommus_present; 260 } 261 262 bool amd_iommu_ht_range_ignore(void) 263 { 264 return check_feature2(FEATURE_HT_RANGE_IGNORE); 265 } 266 267 /* 268 * Iterate through all the IOMMUs to get common EFR 269 * masks among all IOMMUs and warn if found inconsistency. 270 */ 271 static __init void get_global_efr(void) 272 { 273 struct amd_iommu *iommu; 274 275 for_each_iommu(iommu) { 276 u64 tmp = iommu->features; 277 u64 tmp2 = iommu->features2; 278 279 if (list_is_first(&iommu->list, &amd_iommu_list)) { 280 amd_iommu_efr = tmp; 281 amd_iommu_efr2 = tmp2; 282 continue; 283 } 284 285 if (amd_iommu_efr == tmp && 286 amd_iommu_efr2 == tmp2) 287 continue; 288 289 pr_err(FW_BUG 290 "Found inconsistent EFR/EFR2 %#llx,%#llx (global %#llx,%#llx) on iommu%d (%04x:%02x:%02x.%01x).\n", 291 tmp, tmp2, amd_iommu_efr, amd_iommu_efr2, 292 iommu->index, iommu->pci_seg->id, 293 PCI_BUS_NUM(iommu->devid), PCI_SLOT(iommu->devid), 294 PCI_FUNC(iommu->devid)); 295 296 amd_iommu_efr &= tmp; 297 amd_iommu_efr2 &= tmp2; 298 } 299 300 pr_info("Using global IVHD EFR:%#llx, EFR2:%#llx\n", amd_iommu_efr, amd_iommu_efr2); 301 } 302 303 /* 304 * For IVHD type 0x11/0x40, EFR is also available via IVHD. 305 * Default to IVHD EFR since it is available sooner 306 * (i.e. before PCI init). 307 */ 308 static void __init early_iommu_features_init(struct amd_iommu *iommu, 309 struct ivhd_header *h) 310 { 311 if (amd_iommu_ivinfo & IOMMU_IVINFO_EFRSUP) { 312 iommu->features = h->efr_reg; 313 iommu->features2 = h->efr_reg2; 314 } 315 if (amd_iommu_ivinfo & IOMMU_IVINFO_DMA_REMAP) 316 amdr_ivrs_remap_support = true; 317 } 318 319 /* Access to l1 and l2 indexed register spaces */ 320 321 static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address) 322 { 323 u32 val; 324 325 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16)); 326 pci_read_config_dword(iommu->dev, 0xfc, &val); 327 return val; 328 } 329 330 static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val) 331 { 332 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31)); 333 pci_write_config_dword(iommu->dev, 0xfc, val); 334 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16)); 335 } 336 337 static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address) 338 { 339 u32 val; 340 341 pci_write_config_dword(iommu->dev, 0xf0, address); 342 pci_read_config_dword(iommu->dev, 0xf4, &val); 343 return val; 344 } 345 346 static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val) 347 { 348 pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8)); 349 pci_write_config_dword(iommu->dev, 0xf4, val); 350 } 351 352 /**************************************************************************** 353 * 354 * AMD IOMMU MMIO register space handling functions 355 * 356 * These functions are used to program the IOMMU device registers in 357 * MMIO space required for that driver. 358 * 359 ****************************************************************************/ 360 361 static void iommu_set_cwwb_range(struct amd_iommu *iommu) 362 { 363 u64 start = iommu_virt_to_phys((void *)iommu->cmd_sem); 364 u64 entry = start & PM_ADDR_MASK; 365 366 if (!check_feature(FEATURE_SNP)) 367 return; 368 369 /* Note: 370 * Re-purpose Exclusion base/limit registers for Completion wait 371 * write-back base/limit. 372 */ 373 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, 374 &entry, sizeof(entry)); 375 376 /* Note: 377 * Default to 4 Kbytes, which can be specified by setting base 378 * address equal to the limit address. 379 */ 380 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, 381 &entry, sizeof(entry)); 382 } 383 384 /* Programs the physical address of the device table into the IOMMU hardware */ 385 static void iommu_set_device_table(struct amd_iommu *iommu) 386 { 387 u64 entry; 388 u32 dev_table_size = iommu->pci_seg->dev_table_size; 389 void *dev_table = (void *)get_dev_table(iommu); 390 391 BUG_ON(iommu->mmio_base == NULL); 392 393 if (is_kdump_kernel()) 394 return; 395 396 entry = iommu_virt_to_phys(dev_table); 397 entry |= (dev_table_size >> 12) - 1; 398 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET, 399 &entry, sizeof(entry)); 400 } 401 402 static void iommu_feature_set(struct amd_iommu *iommu, u64 val, u64 mask, u8 shift) 403 { 404 u64 ctrl; 405 406 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); 407 mask <<= shift; 408 ctrl &= ~mask; 409 ctrl |= (val << shift) & mask; 410 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); 411 } 412 413 /* Generic functions to enable/disable certain features of the IOMMU. */ 414 void iommu_feature_enable(struct amd_iommu *iommu, u8 bit) 415 { 416 iommu_feature_set(iommu, 1ULL, 1ULL, bit); 417 } 418 419 static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit) 420 { 421 iommu_feature_set(iommu, 0ULL, 1ULL, bit); 422 } 423 424 /* Function to enable the hardware */ 425 static void iommu_enable(struct amd_iommu *iommu) 426 { 427 iommu_feature_enable(iommu, CONTROL_IOMMU_EN); 428 } 429 430 static void iommu_disable(struct amd_iommu *iommu) 431 { 432 if (!iommu->mmio_base) 433 return; 434 435 /* Disable command buffer */ 436 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); 437 438 /* Disable event logging and event interrupts */ 439 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN); 440 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN); 441 442 /* Disable IOMMU GA_LOG */ 443 iommu_feature_disable(iommu, CONTROL_GALOG_EN); 444 iommu_feature_disable(iommu, CONTROL_GAINT_EN); 445 446 /* Disable IOMMU PPR logging */ 447 iommu_feature_disable(iommu, CONTROL_PPRLOG_EN); 448 iommu_feature_disable(iommu, CONTROL_PPRINT_EN); 449 450 /* Disable IOMMU hardware itself */ 451 iommu_feature_disable(iommu, CONTROL_IOMMU_EN); 452 453 /* Clear IRTE cache disabling bit */ 454 iommu_feature_disable(iommu, CONTROL_IRTCACHEDIS); 455 } 456 457 /* 458 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in 459 * the system has one. 460 */ 461 static u8 __iomem * __init iommu_map_mmio_space(u64 address, u64 end) 462 { 463 if (!request_mem_region(address, end, "amd_iommu")) { 464 pr_err("Can not reserve memory region %llx-%llx for mmio\n", 465 address, end); 466 pr_err("This is a BIOS bug. Please contact your hardware vendor\n"); 467 return NULL; 468 } 469 470 return (u8 __iomem *)ioremap(address, end); 471 } 472 473 static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu) 474 { 475 if (iommu->mmio_base) 476 iounmap(iommu->mmio_base); 477 release_mem_region(iommu->mmio_phys, iommu->mmio_phys_end); 478 } 479 480 static inline u32 get_ivhd_header_size(struct ivhd_header *h) 481 { 482 u32 size = 0; 483 484 switch (h->type) { 485 case 0x10: 486 size = 24; 487 break; 488 case 0x11: 489 case 0x40: 490 size = 40; 491 break; 492 } 493 return size; 494 } 495 496 /**************************************************************************** 497 * 498 * The functions below belong to the first pass of AMD IOMMU ACPI table 499 * parsing. In this pass we try to find out the highest device id this 500 * code has to handle. Upon this information the size of the shared data 501 * structures is determined later. 502 * 503 ****************************************************************************/ 504 505 /* 506 * This function calculates the length of a given IVHD entry 507 */ 508 static inline int ivhd_entry_length(u8 *ivhd) 509 { 510 u32 type = ((struct ivhd_entry *)ivhd)->type; 511 512 if (type < 0x80) { 513 return 0x04 << (*ivhd >> 6); 514 } else if (type == IVHD_DEV_ACPI_HID) { 515 /* For ACPI_HID, offset 21 is uid len */ 516 return *((u8 *)ivhd + 21) + 22; 517 } 518 return 0; 519 } 520 521 /* 522 * After reading the highest device id from the IOMMU PCI capability header 523 * this function looks if there is a higher device id defined in the ACPI table 524 */ 525 static int __init find_last_devid_from_ivhd(struct ivhd_header *h) 526 { 527 u8 *p = (void *)h, *end = (void *)h; 528 struct ivhd_entry *dev; 529 int last_devid = -EINVAL; 530 531 u32 ivhd_size = get_ivhd_header_size(h); 532 533 if (!ivhd_size) { 534 pr_err("Unsupported IVHD type %#x\n", h->type); 535 return -EINVAL; 536 } 537 538 p += ivhd_size; 539 end += h->length; 540 541 while (p < end) { 542 dev = (struct ivhd_entry *)p; 543 switch (dev->type) { 544 case IVHD_DEV_ALL: 545 /* Use maximum BDF value for DEV_ALL */ 546 return 0xffff; 547 case IVHD_DEV_SELECT: 548 case IVHD_DEV_RANGE_END: 549 case IVHD_DEV_ALIAS: 550 case IVHD_DEV_EXT_SELECT: 551 /* all the above subfield types refer to device ids */ 552 if (dev->devid > last_devid) 553 last_devid = dev->devid; 554 break; 555 default: 556 break; 557 } 558 p += ivhd_entry_length(p); 559 } 560 561 WARN_ON(p != end); 562 563 return last_devid; 564 } 565 566 static int __init check_ivrs_checksum(struct acpi_table_header *table) 567 { 568 int i; 569 u8 checksum = 0, *p = (u8 *)table; 570 571 for (i = 0; i < table->length; ++i) 572 checksum += p[i]; 573 if (checksum != 0) { 574 /* ACPI table corrupt */ 575 pr_err(FW_BUG "IVRS invalid checksum\n"); 576 return -ENODEV; 577 } 578 579 return 0; 580 } 581 582 /* 583 * Iterate over all IVHD entries in the ACPI table and find the highest device 584 * id which we need to handle. This is the first of three functions which parse 585 * the ACPI table. So we check the checksum here. 586 */ 587 static int __init find_last_devid_acpi(struct acpi_table_header *table, u16 pci_seg) 588 { 589 u8 *p = (u8 *)table, *end = (u8 *)table; 590 struct ivhd_header *h; 591 int last_devid, last_bdf = 0; 592 593 p += IVRS_HEADER_LENGTH; 594 595 end += table->length; 596 while (p < end) { 597 h = (struct ivhd_header *)p; 598 if (h->pci_seg == pci_seg && 599 h->type == amd_iommu_target_ivhd_type) { 600 last_devid = find_last_devid_from_ivhd(h); 601 602 if (last_devid < 0) 603 return -EINVAL; 604 if (last_devid > last_bdf) 605 last_bdf = last_devid; 606 } 607 p += h->length; 608 } 609 WARN_ON(p != end); 610 611 return last_bdf; 612 } 613 614 /**************************************************************************** 615 * 616 * The following functions belong to the code path which parses the ACPI table 617 * the second time. In this ACPI parsing iteration we allocate IOMMU specific 618 * data structures, initialize the per PCI segment device/alias/rlookup table 619 * and also basically initialize the hardware. 620 * 621 ****************************************************************************/ 622 623 /* Allocate per PCI segment device table */ 624 static inline int __init alloc_dev_table(struct amd_iommu_pci_seg *pci_seg) 625 { 626 pci_seg->dev_table = iommu_alloc_pages_sz(GFP_KERNEL | GFP_DMA32, 627 pci_seg->dev_table_size); 628 if (!pci_seg->dev_table) 629 return -ENOMEM; 630 631 return 0; 632 } 633 634 static inline void free_dev_table(struct amd_iommu_pci_seg *pci_seg) 635 { 636 if (is_kdump_kernel()) 637 memunmap((void *)pci_seg->dev_table); 638 else 639 iommu_free_pages(pci_seg->dev_table); 640 pci_seg->dev_table = NULL; 641 } 642 643 /* Allocate per PCI segment IOMMU rlookup table. */ 644 static inline int __init alloc_rlookup_table(struct amd_iommu_pci_seg *pci_seg) 645 { 646 pci_seg->rlookup_table = kvzalloc_objs(*pci_seg->rlookup_table, 647 pci_seg->last_bdf + 1); 648 if (pci_seg->rlookup_table == NULL) 649 return -ENOMEM; 650 651 return 0; 652 } 653 654 static inline void free_rlookup_table(struct amd_iommu_pci_seg *pci_seg) 655 { 656 kvfree(pci_seg->rlookup_table); 657 pci_seg->rlookup_table = NULL; 658 } 659 660 static inline int __init alloc_irq_lookup_table(struct amd_iommu_pci_seg *pci_seg) 661 { 662 pci_seg->irq_lookup_table = kvzalloc_objs(*pci_seg->irq_lookup_table, 663 pci_seg->last_bdf + 1); 664 if (pci_seg->irq_lookup_table == NULL) 665 return -ENOMEM; 666 667 return 0; 668 } 669 670 static inline void free_irq_lookup_table(struct amd_iommu_pci_seg *pci_seg) 671 { 672 kvfree(pci_seg->irq_lookup_table); 673 pci_seg->irq_lookup_table = NULL; 674 } 675 676 static int __init alloc_alias_table(struct amd_iommu_pci_seg *pci_seg) 677 { 678 int i; 679 680 pci_seg->alias_table = kvmalloc_objs(*pci_seg->alias_table, 681 pci_seg->last_bdf + 1); 682 if (!pci_seg->alias_table) 683 return -ENOMEM; 684 685 /* 686 * let all alias entries point to itself 687 */ 688 for (i = 0; i <= pci_seg->last_bdf; ++i) 689 pci_seg->alias_table[i] = i; 690 691 return 0; 692 } 693 694 static void __init free_alias_table(struct amd_iommu_pci_seg *pci_seg) 695 { 696 kvfree(pci_seg->alias_table); 697 pci_seg->alias_table = NULL; 698 } 699 700 static inline void *iommu_memremap(unsigned long paddr, size_t size) 701 { 702 phys_addr_t phys; 703 704 if (!paddr) 705 return NULL; 706 707 /* 708 * Obtain true physical address in kdump kernel when SME is enabled. 709 * Currently, previous kernel with SME enabled and kdump kernel 710 * with SME support disabled is not supported. 711 */ 712 phys = __sme_clr(paddr); 713 714 if (cc_platform_has(CC_ATTR_HOST_MEM_ENCRYPT)) 715 return (__force void *)ioremap_encrypted(phys, size); 716 else 717 return memremap(phys, size, MEMREMAP_WB); 718 } 719 720 /* 721 * Allocates the command buffer. This buffer is per AMD IOMMU. We can 722 * write commands to that buffer later and the IOMMU will execute them 723 * asynchronously 724 */ 725 static int __init alloc_command_buffer(struct amd_iommu *iommu) 726 { 727 iommu->cmd_buf = iommu_alloc_pages_sz(GFP_KERNEL, CMD_BUFFER_SIZE); 728 729 return iommu->cmd_buf ? 0 : -ENOMEM; 730 } 731 732 /* 733 * Interrupt handler has processed all pending events and adjusted head 734 * and tail pointer. Reset overflow mask and restart logging again. 735 */ 736 void amd_iommu_restart_log(struct amd_iommu *iommu, const char *evt_type, 737 u8 cntrl_intr, u8 cntrl_log, 738 u32 status_run_mask, u32 status_overflow_mask) 739 { 740 u32 status; 741 742 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); 743 if (status & status_run_mask) 744 return; 745 746 pr_info_ratelimited("IOMMU %s log restarting\n", evt_type); 747 748 iommu_feature_disable(iommu, cntrl_log); 749 iommu_feature_disable(iommu, cntrl_intr); 750 751 writel(status_overflow_mask, iommu->mmio_base + MMIO_STATUS_OFFSET); 752 753 iommu_feature_enable(iommu, cntrl_intr); 754 iommu_feature_enable(iommu, cntrl_log); 755 } 756 757 /* 758 * This function restarts event logging in case the IOMMU experienced 759 * an event log buffer overflow. 760 */ 761 void amd_iommu_restart_event_logging(struct amd_iommu *iommu) 762 { 763 amd_iommu_restart_log(iommu, "Event", CONTROL_EVT_INT_EN, 764 CONTROL_EVT_LOG_EN, MMIO_STATUS_EVT_RUN_MASK, 765 MMIO_STATUS_EVT_OVERFLOW_MASK); 766 } 767 768 /* 769 * This function restarts event logging in case the IOMMU experienced 770 * GA log overflow. 771 */ 772 void amd_iommu_restart_ga_log(struct amd_iommu *iommu) 773 { 774 amd_iommu_restart_log(iommu, "GA", CONTROL_GAINT_EN, 775 CONTROL_GALOG_EN, MMIO_STATUS_GALOG_RUN_MASK, 776 MMIO_STATUS_GALOG_OVERFLOW_MASK); 777 } 778 779 /* 780 * This function resets the command buffer if the IOMMU stopped fetching 781 * commands from it. 782 */ 783 static void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu) 784 { 785 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); 786 787 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); 788 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); 789 iommu->cmd_buf_head = 0; 790 iommu->cmd_buf_tail = 0; 791 792 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN); 793 } 794 795 /* 796 * This function writes the command buffer address to the hardware and 797 * enables it. 798 */ 799 static void iommu_enable_command_buffer(struct amd_iommu *iommu) 800 { 801 u64 entry; 802 803 BUG_ON(iommu->cmd_buf == NULL); 804 805 if (!is_kdump_kernel()) { 806 /* 807 * Command buffer is re-used for kdump kernel and setting 808 * of MMIO register is not required. 809 */ 810 entry = iommu_virt_to_phys(iommu->cmd_buf); 811 entry |= MMIO_CMD_SIZE_512; 812 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET, 813 &entry, sizeof(entry)); 814 } 815 816 amd_iommu_reset_cmd_buffer(iommu); 817 } 818 819 /* 820 * This function disables the command buffer 821 */ 822 static void iommu_disable_command_buffer(struct amd_iommu *iommu) 823 { 824 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); 825 } 826 827 static void __init free_command_buffer(struct amd_iommu *iommu) 828 { 829 iommu_free_pages(iommu->cmd_buf); 830 } 831 832 void *__init iommu_alloc_4k_pages(struct amd_iommu *iommu, gfp_t gfp, 833 size_t size) 834 { 835 int nid = iommu->dev ? dev_to_node(&iommu->dev->dev) : NUMA_NO_NODE; 836 void *buf; 837 838 size = PAGE_ALIGN(size); 839 buf = iommu_alloc_pages_node_sz(nid, gfp, size); 840 if (!buf) 841 return NULL; 842 if (check_feature(FEATURE_SNP) && 843 set_memory_4k((unsigned long)buf, size / PAGE_SIZE)) { 844 iommu_free_pages(buf); 845 return NULL; 846 } 847 848 return buf; 849 } 850 851 /* allocates the memory where the IOMMU will log its events to */ 852 static int __init alloc_event_buffer(void) 853 { 854 struct amd_iommu *iommu; 855 856 for_each_iommu(iommu) { 857 iommu->evt_buf = iommu_alloc_4k_pages(iommu, GFP_KERNEL, 858 amd_iommu_evtlog_size); 859 if (!iommu->evt_buf) 860 return -ENOMEM; 861 } 862 863 return 0; 864 } 865 866 static void iommu_enable_event_buffer(void) 867 { 868 struct amd_iommu *iommu; 869 u64 entry; 870 871 for_each_iommu(iommu) { 872 BUG_ON(iommu->evt_buf == NULL); 873 874 if (!is_kdump_kernel()) { 875 /* 876 * Event buffer is re-used for kdump kernel and setting 877 * of MMIO register is not required. 878 */ 879 entry = iommu_virt_to_phys(iommu->evt_buf); 880 entry |= (amd_iommu_evtlog_size == EVTLOG_SIZE_DEF) ? 881 EVTLOG_LEN_MASK_DEF : EVTLOG_LEN_MASK_MAX; 882 883 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET, 884 &entry, sizeof(entry)); 885 } 886 887 /* set head and tail to zero manually */ 888 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); 889 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); 890 891 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN); 892 } 893 } 894 895 /* 896 * This function disables the event log buffer 897 */ 898 static void iommu_disable_event_buffer(struct amd_iommu *iommu) 899 { 900 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN); 901 } 902 903 static void __init free_event_buffer(struct amd_iommu *iommu) 904 { 905 iommu_free_pages(iommu->evt_buf); 906 } 907 908 static void free_ga_log(struct amd_iommu *iommu) 909 { 910 #ifdef CONFIG_IRQ_REMAP 911 iommu_free_pages(iommu->ga_log); 912 iommu_free_pages(iommu->ga_log_tail); 913 #endif 914 } 915 916 #ifdef CONFIG_IRQ_REMAP 917 static int iommu_ga_log_enable(struct amd_iommu *iommu) 918 { 919 u32 status, i; 920 u64 entry; 921 922 if (!iommu->ga_log) 923 return -EINVAL; 924 925 entry = iommu_virt_to_phys(iommu->ga_log) | GA_LOG_SIZE_512; 926 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_BASE_OFFSET, 927 &entry, sizeof(entry)); 928 entry = (iommu_virt_to_phys(iommu->ga_log_tail) & 929 (BIT_ULL(52)-1)) & ~7ULL; 930 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_TAIL_OFFSET, 931 &entry, sizeof(entry)); 932 writel(0x00, iommu->mmio_base + MMIO_GA_HEAD_OFFSET); 933 writel(0x00, iommu->mmio_base + MMIO_GA_TAIL_OFFSET); 934 935 936 iommu_feature_enable(iommu, CONTROL_GAINT_EN); 937 iommu_feature_enable(iommu, CONTROL_GALOG_EN); 938 939 for (i = 0; i < MMIO_STATUS_TIMEOUT; ++i) { 940 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); 941 if (status & (MMIO_STATUS_GALOG_RUN_MASK)) 942 break; 943 udelay(10); 944 } 945 946 if (WARN_ON(i >= MMIO_STATUS_TIMEOUT)) 947 return -EINVAL; 948 949 return 0; 950 } 951 952 static int iommu_init_ga_log(struct amd_iommu *iommu) 953 { 954 int nid = iommu->dev ? dev_to_node(&iommu->dev->dev) : NUMA_NO_NODE; 955 956 if (WARN_ON_ONCE(!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))) 957 return -EINVAL; 958 959 iommu->ga_log = iommu_alloc_pages_node_sz(nid, GFP_KERNEL, GA_LOG_SIZE); 960 if (!iommu->ga_log) 961 goto err_out; 962 963 iommu->ga_log_tail = iommu_alloc_pages_node_sz(nid, GFP_KERNEL, 8); 964 if (!iommu->ga_log_tail) 965 goto err_out; 966 967 return 0; 968 err_out: 969 free_ga_log(iommu); 970 return -EINVAL; 971 } 972 #endif /* CONFIG_IRQ_REMAP */ 973 974 static int __init alloc_cwwb_sem(struct amd_iommu *iommu) 975 { 976 iommu->cmd_sem = iommu_alloc_4k_pages(iommu, GFP_KERNEL, 1); 977 if (!iommu->cmd_sem) 978 return -ENOMEM; 979 iommu->cmd_sem_paddr = iommu_virt_to_phys((void *)iommu->cmd_sem); 980 return 0; 981 } 982 983 static int __init remap_event_buffer(void) 984 { 985 struct amd_iommu *iommu; 986 u64 paddr; 987 988 pr_info_once("Re-using event buffer from the previous kernel\n"); 989 for_each_iommu(iommu) { 990 paddr = readq(iommu->mmio_base + MMIO_EVT_BUF_OFFSET) & PM_ADDR_MASK; 991 iommu->evt_buf = iommu_memremap(paddr, amd_iommu_evtlog_size); 992 if (!iommu->evt_buf) 993 return -ENOMEM; 994 } 995 996 return 0; 997 } 998 999 static int __init remap_command_buffer(struct amd_iommu *iommu) 1000 { 1001 u64 paddr; 1002 1003 pr_info_once("Re-using command buffer from the previous kernel\n"); 1004 paddr = readq(iommu->mmio_base + MMIO_CMD_BUF_OFFSET) & PM_ADDR_MASK; 1005 iommu->cmd_buf = iommu_memremap(paddr, CMD_BUFFER_SIZE); 1006 1007 return iommu->cmd_buf ? 0 : -ENOMEM; 1008 } 1009 1010 static int __init remap_or_alloc_cwwb_sem(struct amd_iommu *iommu) 1011 { 1012 u64 paddr; 1013 1014 if (check_feature(FEATURE_SNP)) { 1015 /* 1016 * When SNP is enabled, the exclusion base register is used for the 1017 * completion wait buffer (CWB) address. Read and re-use it. 1018 */ 1019 pr_info_once("Re-using CWB buffers from the previous kernel\n"); 1020 paddr = readq(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET) & PM_ADDR_MASK; 1021 iommu->cmd_sem = iommu_memremap(paddr, PAGE_SIZE); 1022 if (!iommu->cmd_sem) 1023 return -ENOMEM; 1024 iommu->cmd_sem_paddr = paddr; 1025 } else { 1026 return alloc_cwwb_sem(iommu); 1027 } 1028 1029 return 0; 1030 } 1031 1032 static int __init alloc_iommu_buffers(struct amd_iommu *iommu) 1033 { 1034 int ret; 1035 1036 /* 1037 * Reuse/Remap the previous kernel's allocated completion wait 1038 * command and event buffers for kdump boot. 1039 */ 1040 if (is_kdump_kernel()) { 1041 ret = remap_or_alloc_cwwb_sem(iommu); 1042 if (ret) 1043 return ret; 1044 1045 ret = remap_command_buffer(iommu); 1046 if (ret) 1047 return ret; 1048 } else { 1049 ret = alloc_cwwb_sem(iommu); 1050 if (ret) 1051 return ret; 1052 1053 ret = alloc_command_buffer(iommu); 1054 if (ret) 1055 return ret; 1056 } 1057 1058 return 0; 1059 } 1060 1061 static void __init free_cwwb_sem(struct amd_iommu *iommu) 1062 { 1063 if (iommu->cmd_sem) 1064 iommu_free_pages((void *)iommu->cmd_sem); 1065 } 1066 static void __init unmap_cwwb_sem(struct amd_iommu *iommu) 1067 { 1068 if (iommu->cmd_sem) { 1069 if (check_feature(FEATURE_SNP)) 1070 memunmap((void *)iommu->cmd_sem); 1071 else 1072 iommu_free_pages((void *)iommu->cmd_sem); 1073 } 1074 } 1075 1076 static void __init unmap_command_buffer(struct amd_iommu *iommu) 1077 { 1078 memunmap((void *)iommu->cmd_buf); 1079 } 1080 1081 static void __init unmap_event_buffer(struct amd_iommu *iommu) 1082 { 1083 memunmap(iommu->evt_buf); 1084 } 1085 1086 static void __init free_iommu_buffers(struct amd_iommu *iommu) 1087 { 1088 if (is_kdump_kernel()) { 1089 unmap_cwwb_sem(iommu); 1090 unmap_command_buffer(iommu); 1091 unmap_event_buffer(iommu); 1092 } else { 1093 free_cwwb_sem(iommu); 1094 free_command_buffer(iommu); 1095 free_event_buffer(iommu); 1096 } 1097 } 1098 1099 static void iommu_enable_xt(struct amd_iommu *iommu) 1100 { 1101 #ifdef CONFIG_IRQ_REMAP 1102 /* 1103 * XT mode (32-bit APIC destination ID) requires 1104 * GA mode (128-bit IRTE support) as a prerequisite. 1105 */ 1106 if (AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir) && 1107 amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE) 1108 iommu_feature_enable(iommu, CONTROL_XT_EN); 1109 #endif /* CONFIG_IRQ_REMAP */ 1110 } 1111 1112 static void iommu_enable_gt(struct amd_iommu *iommu) 1113 { 1114 if (!check_feature(FEATURE_GT)) 1115 return; 1116 1117 iommu_feature_enable(iommu, CONTROL_GT_EN); 1118 1119 /* 1120 * This feature needs to be enabled prior to a call 1121 * to iommu_snp_enable(). Since this function is called 1122 * in early_enable_iommu(), it is safe to enable here. 1123 */ 1124 if (check_feature2(FEATURE_GCR3TRPMODE)) 1125 iommu_feature_enable(iommu, CONTROL_GCR3TRPMODE); 1126 } 1127 1128 /* sets a specific bit in the device table entry. */ 1129 static void set_dte_bit(struct dev_table_entry *dte, u8 bit) 1130 { 1131 int i = (bit >> 6) & 0x03; 1132 int _bit = bit & 0x3f; 1133 1134 dte->data[i] |= (1UL << _bit); 1135 } 1136 1137 static bool __reuse_device_table(struct amd_iommu *iommu) 1138 { 1139 struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg; 1140 struct dev_table_entry *old_dev_tbl_entry; 1141 u32 lo, hi, old_devtb_size, devid; 1142 phys_addr_t old_devtb_phys; 1143 u16 dom_id; 1144 bool dte_v; 1145 u64 entry; 1146 1147 /* Each IOMMU use separate device table with the same size */ 1148 lo = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET); 1149 hi = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET + 4); 1150 entry = (((u64) hi) << 32) + lo; 1151 1152 old_devtb_size = ((entry & ~PAGE_MASK) + 1) << 12; 1153 if (old_devtb_size != pci_seg->dev_table_size) { 1154 pr_err("The device table size of IOMMU:%d is not expected!\n", 1155 iommu->index); 1156 return false; 1157 } 1158 1159 /* 1160 * When SME is enabled in the first kernel, the entry includes the 1161 * memory encryption mask(sme_me_mask), we must remove the memory 1162 * encryption mask to obtain the true physical address in kdump kernel. 1163 */ 1164 old_devtb_phys = __sme_clr(entry) & PAGE_MASK; 1165 1166 if (old_devtb_phys >= 0x100000000ULL) { 1167 pr_err("The address of old device table is above 4G, not trustworthy!\n"); 1168 return false; 1169 } 1170 1171 /* 1172 * Re-use the previous kernel's device table for kdump. 1173 */ 1174 pci_seg->old_dev_tbl_cpy = iommu_memremap(old_devtb_phys, pci_seg->dev_table_size); 1175 if (pci_seg->old_dev_tbl_cpy == NULL) { 1176 pr_err("Failed to remap memory for reusing old device table!\n"); 1177 return false; 1178 } 1179 1180 for (devid = 0; devid <= pci_seg->last_bdf; devid++) { 1181 old_dev_tbl_entry = &pci_seg->old_dev_tbl_cpy[devid]; 1182 dte_v = FIELD_GET(DTE_FLAG_V, old_dev_tbl_entry->data[0]); 1183 dom_id = FIELD_GET(DTE_DOMID_MASK, old_dev_tbl_entry->data[1]); 1184 1185 if (!dte_v || !dom_id) 1186 continue; 1187 /* 1188 * ID reservation can fail with -ENOSPC when there 1189 * are multiple devices present in the same domain, 1190 * hence check only for -ENOMEM. 1191 */ 1192 if (amd_iommu_pdom_id_reserve(dom_id, GFP_KERNEL) == -ENOMEM) 1193 return false; 1194 } 1195 1196 return true; 1197 } 1198 1199 static bool reuse_device_table(void) 1200 { 1201 struct amd_iommu *iommu; 1202 struct amd_iommu_pci_seg *pci_seg; 1203 1204 if (!amd_iommu_pre_enabled) 1205 return false; 1206 1207 pr_warn("Translation is already enabled - trying to reuse translation structures\n"); 1208 1209 /* 1210 * All IOMMUs within PCI segment shares common device table. 1211 * Hence reuse device table only once per PCI segment. 1212 */ 1213 for_each_pci_segment(pci_seg) { 1214 for_each_iommu(iommu) { 1215 if (pci_seg->id != iommu->pci_seg->id) 1216 continue; 1217 if (!__reuse_device_table(iommu)) 1218 return false; 1219 break; 1220 } 1221 } 1222 1223 return true; 1224 } 1225 1226 struct dev_table_entry *amd_iommu_get_ivhd_dte_flags(u16 segid, u16 devid) 1227 { 1228 struct ivhd_dte_flags *e; 1229 unsigned int best_len = UINT_MAX; 1230 struct dev_table_entry *dte = NULL; 1231 1232 for_each_ivhd_dte_flags(e) { 1233 /* 1234 * Need to go through the whole list to find the smallest range, 1235 * which contains the devid. 1236 */ 1237 if ((e->segid == segid) && 1238 (e->devid_first <= devid) && (devid <= e->devid_last)) { 1239 unsigned int len = e->devid_last - e->devid_first; 1240 1241 if (len < best_len) { 1242 dte = &(e->dte); 1243 best_len = len; 1244 } 1245 } 1246 } 1247 return dte; 1248 } 1249 1250 static bool search_ivhd_dte_flags(u16 segid, u16 first, u16 last) 1251 { 1252 struct ivhd_dte_flags *e; 1253 1254 for_each_ivhd_dte_flags(e) { 1255 if ((e->segid == segid) && 1256 (e->devid_first == first) && 1257 (e->devid_last == last)) 1258 return true; 1259 } 1260 return false; 1261 } 1262 1263 /* 1264 * This function takes the device specific flags read from the ACPI 1265 * table and sets up the device table entry with that information 1266 */ 1267 static void __init 1268 set_dev_entry_from_acpi_range(struct amd_iommu *iommu, u16 first, u16 last, 1269 u32 flags, u32 ext_flags) 1270 { 1271 int i; 1272 struct dev_table_entry dte = {}; 1273 1274 /* Parse IVHD DTE setting flags and store information */ 1275 if (flags) { 1276 struct ivhd_dte_flags *d; 1277 1278 if (search_ivhd_dte_flags(iommu->pci_seg->id, first, last)) 1279 return; 1280 1281 d = kzalloc_obj(struct ivhd_dte_flags); 1282 if (!d) 1283 return; 1284 1285 pr_debug("%s: devid range %#x:%#x\n", __func__, first, last); 1286 1287 if (flags & ACPI_DEVFLAG_INITPASS) 1288 set_dte_bit(&dte, DEV_ENTRY_INIT_PASS); 1289 if (flags & ACPI_DEVFLAG_EXTINT) 1290 set_dte_bit(&dte, DEV_ENTRY_EINT_PASS); 1291 if (flags & ACPI_DEVFLAG_NMI) 1292 set_dte_bit(&dte, DEV_ENTRY_NMI_PASS); 1293 if (flags & ACPI_DEVFLAG_SYSMGT1) 1294 set_dte_bit(&dte, DEV_ENTRY_SYSMGT1); 1295 if (flags & ACPI_DEVFLAG_SYSMGT2) 1296 set_dte_bit(&dte, DEV_ENTRY_SYSMGT2); 1297 if (flags & ACPI_DEVFLAG_LINT0) 1298 set_dte_bit(&dte, DEV_ENTRY_LINT0_PASS); 1299 if (flags & ACPI_DEVFLAG_LINT1) 1300 set_dte_bit(&dte, DEV_ENTRY_LINT1_PASS); 1301 1302 /* Apply erratum 63, which needs info in initial_dte */ 1303 if (FIELD_GET(DTE_DATA1_SYSMGT_MASK, dte.data[1]) == 0x1) 1304 dte.data[0] |= DTE_FLAG_IW; 1305 1306 memcpy(&d->dte, &dte, sizeof(dte)); 1307 d->segid = iommu->pci_seg->id; 1308 d->devid_first = first; 1309 d->devid_last = last; 1310 list_add_tail(&d->list, &amd_ivhd_dev_flags_list); 1311 } 1312 1313 for (i = first; i <= last; i++) { 1314 if (flags) { 1315 struct dev_table_entry *dev_table = get_dev_table(iommu); 1316 1317 memcpy(&dev_table[i], &dte, sizeof(dte)); 1318 } 1319 amd_iommu_set_rlookup_table(iommu, i); 1320 } 1321 } 1322 1323 static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu, 1324 u16 devid, u32 flags, u32 ext_flags) 1325 { 1326 set_dev_entry_from_acpi_range(iommu, devid, devid, flags, ext_flags); 1327 } 1328 1329 int __init add_special_device(u8 type, u8 id, u32 *devid, bool cmd_line) 1330 { 1331 struct devid_map *entry; 1332 struct list_head *list; 1333 1334 if (type == IVHD_SPECIAL_IOAPIC) 1335 list = &ioapic_map; 1336 else if (type == IVHD_SPECIAL_HPET) 1337 list = &hpet_map; 1338 else 1339 return -EINVAL; 1340 1341 list_for_each_entry(entry, list, list) { 1342 if (!(entry->id == id && entry->cmd_line)) 1343 continue; 1344 1345 pr_info("Command-line override present for %s id %d - ignoring\n", 1346 type == IVHD_SPECIAL_IOAPIC ? "IOAPIC" : "HPET", id); 1347 1348 *devid = entry->devid; 1349 1350 return 0; 1351 } 1352 1353 entry = kzalloc_obj(*entry); 1354 if (!entry) 1355 return -ENOMEM; 1356 1357 entry->id = id; 1358 entry->devid = *devid; 1359 entry->cmd_line = cmd_line; 1360 1361 list_add_tail(&entry->list, list); 1362 1363 return 0; 1364 } 1365 1366 static int __init add_acpi_hid_device(u8 *hid, u8 *uid, u32 *devid, 1367 bool cmd_line) 1368 { 1369 struct acpihid_map_entry *entry; 1370 struct list_head *list = &acpihid_map; 1371 1372 list_for_each_entry(entry, list, list) { 1373 if (strcmp(entry->hid, hid) || 1374 (*uid && *entry->uid && strcmp(entry->uid, uid)) || 1375 !entry->cmd_line) 1376 continue; 1377 1378 pr_info("Command-line override for hid:%s uid:%s\n", 1379 hid, uid); 1380 *devid = entry->devid; 1381 return 0; 1382 } 1383 1384 entry = kzalloc_obj(*entry); 1385 if (!entry) 1386 return -ENOMEM; 1387 1388 memcpy(entry->uid, uid, strlen(uid)); 1389 memcpy(entry->hid, hid, strlen(hid)); 1390 entry->devid = *devid; 1391 entry->cmd_line = cmd_line; 1392 entry->root_devid = (entry->devid & (~0x7)); 1393 1394 pr_info("%s, add hid:%s, uid:%s, rdevid:%#x\n", 1395 entry->cmd_line ? "cmd" : "ivrs", 1396 entry->hid, entry->uid, entry->root_devid); 1397 1398 list_add_tail(&entry->list, list); 1399 return 0; 1400 } 1401 1402 static int __init add_early_maps(void) 1403 { 1404 int i, ret; 1405 1406 for (i = 0; i < early_ioapic_map_size; ++i) { 1407 ret = add_special_device(IVHD_SPECIAL_IOAPIC, 1408 early_ioapic_map[i].id, 1409 &early_ioapic_map[i].devid, 1410 early_ioapic_map[i].cmd_line); 1411 if (ret) 1412 return ret; 1413 } 1414 1415 for (i = 0; i < early_hpet_map_size; ++i) { 1416 ret = add_special_device(IVHD_SPECIAL_HPET, 1417 early_hpet_map[i].id, 1418 &early_hpet_map[i].devid, 1419 early_hpet_map[i].cmd_line); 1420 if (ret) 1421 return ret; 1422 } 1423 1424 for (i = 0; i < early_acpihid_map_size; ++i) { 1425 ret = add_acpi_hid_device(early_acpihid_map[i].hid, 1426 early_acpihid_map[i].uid, 1427 &early_acpihid_map[i].devid, 1428 early_acpihid_map[i].cmd_line); 1429 if (ret) 1430 return ret; 1431 } 1432 1433 return 0; 1434 } 1435 1436 /* 1437 * Takes a pointer to an AMD IOMMU entry in the ACPI table and 1438 * initializes the hardware and our data structures with it. 1439 */ 1440 static int __init init_iommu_from_acpi(struct amd_iommu *iommu, 1441 struct ivhd_header *h) 1442 { 1443 u8 *p = (u8 *)h; 1444 u8 *end = p, flags = 0; 1445 u16 devid = 0, devid_start = 0, devid_to = 0, seg_id; 1446 u32 dev_i, ext_flags = 0; 1447 bool alias = false; 1448 struct ivhd_entry *e; 1449 struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg; 1450 u32 ivhd_size; 1451 int ret; 1452 1453 1454 ret = add_early_maps(); 1455 if (ret) 1456 return ret; 1457 1458 amd_iommu_apply_ivrs_quirks(); 1459 1460 /* 1461 * First save the recommended feature enable bits from ACPI 1462 */ 1463 iommu->acpi_flags = h->flags; 1464 1465 /* 1466 * Done. Now parse the device entries 1467 */ 1468 ivhd_size = get_ivhd_header_size(h); 1469 if (!ivhd_size) { 1470 pr_err("Unsupported IVHD type %#x\n", h->type); 1471 return -EINVAL; 1472 } 1473 1474 p += ivhd_size; 1475 1476 end += h->length; 1477 1478 1479 while (p < end) { 1480 e = (struct ivhd_entry *)p; 1481 seg_id = pci_seg->id; 1482 1483 switch (e->type) { 1484 case IVHD_DEV_ALL: 1485 1486 DUMP_printk(" DEV_ALL\t\t\tsetting: %#02x\n", e->flags); 1487 set_dev_entry_from_acpi_range(iommu, 0, pci_seg->last_bdf, e->flags, 0); 1488 break; 1489 case IVHD_DEV_SELECT: 1490 1491 DUMP_printk(" DEV_SELECT\t\t\tdevid: %04x:%02x:%02x.%x flags: %#02x\n", 1492 seg_id, PCI_BUS_NUM(e->devid), 1493 PCI_SLOT(e->devid), 1494 PCI_FUNC(e->devid), 1495 e->flags); 1496 1497 devid = e->devid; 1498 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); 1499 break; 1500 case IVHD_DEV_SELECT_RANGE_START: 1501 1502 DUMP_printk(" DEV_SELECT_RANGE_START\tdevid: %04x:%02x:%02x.%x flags: %#02x\n", 1503 seg_id, PCI_BUS_NUM(e->devid), 1504 PCI_SLOT(e->devid), 1505 PCI_FUNC(e->devid), 1506 e->flags); 1507 1508 devid_start = e->devid; 1509 flags = e->flags; 1510 ext_flags = 0; 1511 alias = false; 1512 break; 1513 case IVHD_DEV_ALIAS: 1514 1515 DUMP_printk(" DEV_ALIAS\t\t\tdevid: %04x:%02x:%02x.%x flags: %#02x devid_to: %02x:%02x.%x\n", 1516 seg_id, PCI_BUS_NUM(e->devid), 1517 PCI_SLOT(e->devid), 1518 PCI_FUNC(e->devid), 1519 e->flags, 1520 PCI_BUS_NUM(e->ext >> 8), 1521 PCI_SLOT(e->ext >> 8), 1522 PCI_FUNC(e->ext >> 8)); 1523 1524 devid = e->devid; 1525 devid_to = e->ext >> 8; 1526 set_dev_entry_from_acpi(iommu, devid , e->flags, 0); 1527 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0); 1528 pci_seg->alias_table[devid] = devid_to; 1529 break; 1530 case IVHD_DEV_ALIAS_RANGE: 1531 1532 DUMP_printk(" DEV_ALIAS_RANGE\t\tdevid: %04x:%02x:%02x.%x flags: %#02x devid_to: %04x:%02x:%02x.%x\n", 1533 seg_id, PCI_BUS_NUM(e->devid), 1534 PCI_SLOT(e->devid), 1535 PCI_FUNC(e->devid), 1536 e->flags, 1537 seg_id, PCI_BUS_NUM(e->ext >> 8), 1538 PCI_SLOT(e->ext >> 8), 1539 PCI_FUNC(e->ext >> 8)); 1540 1541 devid_start = e->devid; 1542 flags = e->flags; 1543 devid_to = e->ext >> 8; 1544 ext_flags = 0; 1545 alias = true; 1546 break; 1547 case IVHD_DEV_EXT_SELECT: 1548 1549 DUMP_printk(" DEV_EXT_SELECT\t\tdevid: %04x:%02x:%02x.%x flags: %#02x ext: %08x\n", 1550 seg_id, PCI_BUS_NUM(e->devid), 1551 PCI_SLOT(e->devid), 1552 PCI_FUNC(e->devid), 1553 e->flags, e->ext); 1554 1555 devid = e->devid; 1556 set_dev_entry_from_acpi(iommu, devid, e->flags, 1557 e->ext); 1558 break; 1559 case IVHD_DEV_EXT_SELECT_RANGE: 1560 1561 DUMP_printk(" DEV_EXT_SELECT_RANGE\tdevid: %04x:%02x:%02x.%x flags: %#02x ext: %08x\n", 1562 seg_id, PCI_BUS_NUM(e->devid), 1563 PCI_SLOT(e->devid), 1564 PCI_FUNC(e->devid), 1565 e->flags, e->ext); 1566 1567 devid_start = e->devid; 1568 flags = e->flags; 1569 ext_flags = e->ext; 1570 alias = false; 1571 break; 1572 case IVHD_DEV_RANGE_END: 1573 1574 DUMP_printk(" DEV_RANGE_END\t\tdevid: %04x:%02x:%02x.%x\n", 1575 seg_id, PCI_BUS_NUM(e->devid), 1576 PCI_SLOT(e->devid), 1577 PCI_FUNC(e->devid)); 1578 1579 devid = e->devid; 1580 if (alias) { 1581 for (dev_i = devid_start; dev_i <= devid; ++dev_i) 1582 pci_seg->alias_table[dev_i] = devid_to; 1583 set_dev_entry_from_acpi(iommu, devid_to, flags, ext_flags); 1584 } 1585 set_dev_entry_from_acpi_range(iommu, devid_start, devid, flags, ext_flags); 1586 break; 1587 case IVHD_DEV_SPECIAL: { 1588 u8 handle, type; 1589 const char *var; 1590 u32 devid; 1591 int ret; 1592 1593 handle = e->ext & 0xff; 1594 devid = PCI_SEG_DEVID_TO_SBDF(seg_id, (e->ext >> 8)); 1595 type = (e->ext >> 24) & 0xff; 1596 1597 if (type == IVHD_SPECIAL_IOAPIC) 1598 var = "IOAPIC"; 1599 else if (type == IVHD_SPECIAL_HPET) 1600 var = "HPET"; 1601 else 1602 var = "UNKNOWN"; 1603 1604 DUMP_printk(" DEV_SPECIAL(%s[%d])\t\tdevid: %04x:%02x:%02x.%x, flags: %#02x\n", 1605 var, (int)handle, 1606 seg_id, PCI_BUS_NUM(devid), 1607 PCI_SLOT(devid), 1608 PCI_FUNC(devid), 1609 e->flags); 1610 1611 ret = add_special_device(type, handle, &devid, false); 1612 if (ret) 1613 return ret; 1614 1615 /* 1616 * add_special_device might update the devid in case a 1617 * command-line override is present. So call 1618 * set_dev_entry_from_acpi after add_special_device. 1619 */ 1620 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); 1621 1622 break; 1623 } 1624 case IVHD_DEV_ACPI_HID: { 1625 u32 devid; 1626 u8 hid[ACPIHID_HID_LEN]; 1627 u8 uid[ACPIHID_UID_LEN]; 1628 int ret; 1629 1630 if (h->type != 0x40) { 1631 pr_err(FW_BUG "Invalid IVHD device type %#x\n", 1632 e->type); 1633 break; 1634 } 1635 1636 BUILD_BUG_ON(sizeof(e->ext_hid) != ACPIHID_HID_LEN - 1); 1637 memcpy(hid, &e->ext_hid, ACPIHID_HID_LEN - 1); 1638 hid[ACPIHID_HID_LEN - 1] = '\0'; 1639 1640 if (!(*hid)) { 1641 pr_err(FW_BUG "Invalid HID.\n"); 1642 break; 1643 } 1644 1645 uid[0] = '\0'; 1646 switch (e->uidf) { 1647 case UID_NOT_PRESENT: 1648 1649 if (e->uidl != 0) 1650 pr_warn(FW_BUG "Invalid UID length.\n"); 1651 1652 break; 1653 case UID_IS_INTEGER: 1654 1655 sprintf(uid, "%d", e->uid); 1656 1657 break; 1658 case UID_IS_CHARACTER: 1659 1660 memcpy(uid, &e->uid, e->uidl); 1661 uid[e->uidl] = '\0'; 1662 1663 break; 1664 default: 1665 break; 1666 } 1667 1668 devid = PCI_SEG_DEVID_TO_SBDF(seg_id, e->devid); 1669 DUMP_printk(" DEV_ACPI_HID(%s[%s])\t\tdevid: %04x:%02x:%02x.%x, flags: %#02x\n", 1670 hid, uid, seg_id, 1671 PCI_BUS_NUM(devid), 1672 PCI_SLOT(devid), 1673 PCI_FUNC(devid), 1674 e->flags); 1675 1676 flags = e->flags; 1677 1678 ret = add_acpi_hid_device(hid, uid, &devid, false); 1679 if (ret) 1680 return ret; 1681 1682 /* 1683 * add_special_device might update the devid in case a 1684 * command-line override is present. So call 1685 * set_dev_entry_from_acpi after add_special_device. 1686 */ 1687 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); 1688 1689 break; 1690 } 1691 default: 1692 break; 1693 } 1694 1695 p += ivhd_entry_length(p); 1696 } 1697 1698 return 0; 1699 } 1700 1701 /* Allocate PCI segment data structure */ 1702 static struct amd_iommu_pci_seg *__init alloc_pci_segment(u16 id, 1703 struct acpi_table_header *ivrs_base) 1704 { 1705 struct amd_iommu_pci_seg *pci_seg; 1706 int last_bdf; 1707 1708 /* 1709 * First parse ACPI tables to find the largest Bus/Dev/Func we need to 1710 * handle in this PCI segment. Upon this information the shared data 1711 * structures for the PCI segments in the system will be allocated. 1712 */ 1713 last_bdf = find_last_devid_acpi(ivrs_base, id); 1714 if (last_bdf < 0) 1715 return NULL; 1716 1717 pci_seg = kzalloc_obj(struct amd_iommu_pci_seg); 1718 if (pci_seg == NULL) 1719 return NULL; 1720 1721 pci_seg->last_bdf = last_bdf; 1722 DUMP_printk("PCI segment : 0x%0x, last bdf : 0x%04x\n", id, last_bdf); 1723 pci_seg->dev_table_size = 1724 max(roundup_pow_of_two((last_bdf + 1) * DEV_TABLE_ENTRY_SIZE), 1725 SZ_4K); 1726 1727 pci_seg->id = id; 1728 init_llist_head(&pci_seg->dev_data_list); 1729 INIT_LIST_HEAD(&pci_seg->unity_map); 1730 list_add_tail(&pci_seg->list, &amd_iommu_pci_seg_list); 1731 1732 if (alloc_dev_table(pci_seg)) 1733 goto err_free_pci_seg; 1734 if (alloc_alias_table(pci_seg)) 1735 goto err_free_dev_table; 1736 if (alloc_rlookup_table(pci_seg)) 1737 goto err_free_alias_table; 1738 1739 return pci_seg; 1740 1741 err_free_alias_table: 1742 free_alias_table(pci_seg); 1743 err_free_dev_table: 1744 free_dev_table(pci_seg); 1745 err_free_pci_seg: 1746 list_del(&pci_seg->list); 1747 kfree(pci_seg); 1748 return NULL; 1749 } 1750 1751 static struct amd_iommu_pci_seg *__init get_pci_segment(u16 id, 1752 struct acpi_table_header *ivrs_base) 1753 { 1754 struct amd_iommu_pci_seg *pci_seg; 1755 1756 for_each_pci_segment(pci_seg) { 1757 if (pci_seg->id == id) 1758 return pci_seg; 1759 } 1760 1761 return alloc_pci_segment(id, ivrs_base); 1762 } 1763 1764 static void __init free_pci_segments(void) 1765 { 1766 struct amd_iommu_pci_seg *pci_seg, *next; 1767 1768 for_each_pci_segment_safe(pci_seg, next) { 1769 list_del(&pci_seg->list); 1770 free_irq_lookup_table(pci_seg); 1771 free_rlookup_table(pci_seg); 1772 free_alias_table(pci_seg); 1773 free_dev_table(pci_seg); 1774 kfree(pci_seg); 1775 } 1776 } 1777 1778 static void __init free_sysfs(struct amd_iommu *iommu) 1779 { 1780 if (iommu->iommu.dev) { 1781 iommu_device_unregister(&iommu->iommu); 1782 iommu_device_sysfs_remove(&iommu->iommu); 1783 } 1784 } 1785 1786 static void __init free_iommu_one(struct amd_iommu *iommu) 1787 { 1788 free_sysfs(iommu); 1789 free_iommu_buffers(iommu); 1790 amd_iommu_free_ppr_log(iommu); 1791 free_ga_log(iommu); 1792 iommu_unmap_mmio_space(iommu); 1793 amd_iommu_iopf_uninit(iommu); 1794 } 1795 1796 static void __init free_iommu_all(void) 1797 { 1798 struct amd_iommu *iommu, *next; 1799 1800 for_each_iommu_safe(iommu, next) { 1801 list_del(&iommu->list); 1802 free_iommu_one(iommu); 1803 kfree(iommu); 1804 } 1805 } 1806 1807 /* 1808 * Family15h Model 10h-1fh erratum 746 (IOMMU Logging May Stall Translations) 1809 * Workaround: 1810 * BIOS should disable L2B micellaneous clock gating by setting 1811 * L2_L2B_CK_GATE_CONTROL[CKGateL2BMiscDisable](D0F2xF4_x90[2]) = 1b 1812 */ 1813 static void amd_iommu_erratum_746_workaround(struct amd_iommu *iommu) 1814 { 1815 u32 value; 1816 1817 if ((boot_cpu_data.x86 != 0x15) || 1818 (boot_cpu_data.x86_model < 0x10) || 1819 (boot_cpu_data.x86_model > 0x1f)) 1820 return; 1821 1822 pci_write_config_dword(iommu->dev, 0xf0, 0x90); 1823 pci_read_config_dword(iommu->dev, 0xf4, &value); 1824 1825 if (value & BIT(2)) 1826 return; 1827 1828 /* Select NB indirect register 0x90 and enable writing */ 1829 pci_write_config_dword(iommu->dev, 0xf0, 0x90 | (1 << 8)); 1830 1831 pci_write_config_dword(iommu->dev, 0xf4, value | 0x4); 1832 pci_info(iommu->dev, "Applying erratum 746 workaround\n"); 1833 1834 /* Clear the enable writing bit */ 1835 pci_write_config_dword(iommu->dev, 0xf0, 0x90); 1836 } 1837 1838 /* 1839 * Family15h Model 30h-3fh (IOMMU Mishandles ATS Write Permission) 1840 * Workaround: 1841 * BIOS should enable ATS write permission check by setting 1842 * L2_DEBUG_3[AtsIgnoreIWDis](D0F2xF4_x47[0]) = 1b 1843 */ 1844 static void amd_iommu_ats_write_check_workaround(struct amd_iommu *iommu) 1845 { 1846 u32 value; 1847 1848 if ((boot_cpu_data.x86 != 0x15) || 1849 (boot_cpu_data.x86_model < 0x30) || 1850 (boot_cpu_data.x86_model > 0x3f)) 1851 return; 1852 1853 /* Test L2_DEBUG_3[AtsIgnoreIWDis] == 1 */ 1854 value = iommu_read_l2(iommu, 0x47); 1855 1856 if (value & BIT(0)) 1857 return; 1858 1859 /* Set L2_DEBUG_3[AtsIgnoreIWDis] = 1 */ 1860 iommu_write_l2(iommu, 0x47, value | BIT(0)); 1861 1862 pci_info(iommu->dev, "Applying ATS write check workaround\n"); 1863 } 1864 1865 /* 1866 * This function glues the initialization function for one IOMMU 1867 * together and also allocates the command buffer and programs the 1868 * hardware. It does NOT enable the IOMMU. This is done afterwards. 1869 */ 1870 static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h, 1871 struct acpi_table_header *ivrs_base) 1872 { 1873 struct amd_iommu_pci_seg *pci_seg; 1874 1875 pci_seg = get_pci_segment(h->pci_seg, ivrs_base); 1876 if (pci_seg == NULL) 1877 return -ENOMEM; 1878 iommu->pci_seg = pci_seg; 1879 1880 raw_spin_lock_init(&iommu->lock); 1881 iommu->cmd_sem_val = 0; 1882 1883 /* Add IOMMU to internal data structures */ 1884 list_add_tail(&iommu->list, &amd_iommu_list); 1885 iommu->index = amd_iommus_present++; 1886 1887 if (unlikely(iommu->index >= MAX_IOMMUS)) { 1888 WARN(1, "System has more IOMMUs than supported by this driver\n"); 1889 return -ENOSYS; 1890 } 1891 1892 /* 1893 * Copy data from ACPI table entry to the iommu struct 1894 */ 1895 iommu->devid = h->devid; 1896 iommu->cap_ptr = h->cap_ptr; 1897 iommu->mmio_phys = h->mmio_phys; 1898 1899 switch (h->type) { 1900 case 0x10: 1901 /* Check if IVHD EFR contains proper max banks/counters */ 1902 if ((h->efr_attr != 0) && 1903 ((h->efr_attr & (0xF << 13)) != 0) && 1904 ((h->efr_attr & (0x3F << 17)) != 0)) 1905 iommu->mmio_phys_end = MMIO_REG_END_OFFSET; 1906 else 1907 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET; 1908 1909 /* GAM requires GA mode. */ 1910 if ((h->efr_attr & (0x1 << IOMMU_FEAT_GASUP_SHIFT)) == 0) 1911 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY; 1912 break; 1913 case 0x11: 1914 case 0x40: 1915 if (h->efr_reg & (1 << 9)) 1916 iommu->mmio_phys_end = MMIO_REG_END_OFFSET; 1917 else 1918 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET; 1919 1920 /* XT and GAM require GA mode. */ 1921 if ((h->efr_reg & (0x1 << IOMMU_EFR_GASUP_SHIFT)) == 0) { 1922 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY; 1923 } else { 1924 if (h->efr_reg & BIT(IOMMU_EFR_XTSUP_SHIFT)) 1925 amd_iommu_xt_mode = IRQ_REMAP_X2APIC_MODE; 1926 } 1927 1928 if (h->efr_attr & BIT(IOMMU_IVHD_ATTR_HATDIS_SHIFT)) { 1929 pr_warn_once("Host Address Translation is not supported.\n"); 1930 amd_iommu_hatdis = true; 1931 } 1932 1933 early_iommu_features_init(iommu, h); 1934 1935 break; 1936 default: 1937 return -EINVAL; 1938 } 1939 1940 iommu->mmio_base = iommu_map_mmio_space(iommu->mmio_phys, 1941 iommu->mmio_phys_end); 1942 if (!iommu->mmio_base) 1943 return -ENOMEM; 1944 1945 return init_iommu_from_acpi(iommu, h); 1946 } 1947 1948 static int __init init_iommu_one_late(struct amd_iommu *iommu) 1949 { 1950 int ret; 1951 1952 ret = alloc_iommu_buffers(iommu); 1953 if (ret) 1954 return ret; 1955 1956 iommu->int_enabled = false; 1957 1958 init_translation_status(iommu); 1959 if (translation_pre_enabled(iommu) && !is_kdump_kernel()) { 1960 iommu_disable(iommu); 1961 clear_translation_pre_enabled(iommu); 1962 pr_warn("Translation was enabled for IOMMU:%d but we are not in kdump mode\n", 1963 iommu->index); 1964 } 1965 if (amd_iommu_pre_enabled) 1966 amd_iommu_pre_enabled = translation_pre_enabled(iommu); 1967 1968 if (amd_iommu_irq_remap) { 1969 ret = amd_iommu_create_irq_domain(iommu); 1970 if (ret) 1971 return ret; 1972 } 1973 1974 /* 1975 * Make sure IOMMU is not considered to translate itself. The IVRS 1976 * table tells us so, but this is a lie! 1977 */ 1978 iommu->pci_seg->rlookup_table[iommu->devid] = NULL; 1979 1980 return 0; 1981 } 1982 1983 /** 1984 * get_highest_supported_ivhd_type - Look up the appropriate IVHD type 1985 * @ivrs: Pointer to the IVRS header 1986 * 1987 * This function search through all IVDB of the maximum supported IVHD 1988 */ 1989 static u8 get_highest_supported_ivhd_type(struct acpi_table_header *ivrs) 1990 { 1991 u8 *base = (u8 *)ivrs; 1992 struct ivhd_header *ivhd = (struct ivhd_header *) 1993 (base + IVRS_HEADER_LENGTH); 1994 u8 last_type = ivhd->type; 1995 u16 devid = ivhd->devid; 1996 1997 while (((u8 *)ivhd - base < ivrs->length) && 1998 (ivhd->type <= ACPI_IVHD_TYPE_MAX_SUPPORTED)) { 1999 u8 *p = (u8 *) ivhd; 2000 2001 if (ivhd->devid == devid) 2002 last_type = ivhd->type; 2003 ivhd = (struct ivhd_header *)(p + ivhd->length); 2004 } 2005 2006 return last_type; 2007 } 2008 2009 /* 2010 * Iterates over all IOMMU entries in the ACPI table, allocates the 2011 * IOMMU structure and initializes it with init_iommu_one() 2012 */ 2013 static int __init init_iommu_all(struct acpi_table_header *table) 2014 { 2015 u8 *p = (u8 *)table, *end = (u8 *)table; 2016 struct ivhd_header *h; 2017 struct amd_iommu *iommu; 2018 int ret; 2019 2020 end += table->length; 2021 p += IVRS_HEADER_LENGTH; 2022 2023 /* Phase 1: Process all IVHD blocks */ 2024 while (p < end) { 2025 h = (struct ivhd_header *)p; 2026 if (*p == amd_iommu_target_ivhd_type) { 2027 2028 DUMP_printk("device: %04x:%02x:%02x.%01x cap: %04x " 2029 "flags: %01x info %04x\n", 2030 h->pci_seg, PCI_BUS_NUM(h->devid), 2031 PCI_SLOT(h->devid), PCI_FUNC(h->devid), 2032 h->cap_ptr, h->flags, h->info); 2033 DUMP_printk(" mmio-addr: %016llx\n", 2034 h->mmio_phys); 2035 2036 iommu = kzalloc_obj(struct amd_iommu); 2037 if (iommu == NULL) 2038 return -ENOMEM; 2039 2040 ret = init_iommu_one(iommu, h, table); 2041 if (ret) 2042 return ret; 2043 } 2044 p += h->length; 2045 2046 } 2047 WARN_ON(p != end); 2048 2049 /* Phase 2 : Early feature support check */ 2050 get_global_efr(); 2051 2052 /* Phase 3 : Enabling IOMMU features */ 2053 for_each_iommu(iommu) { 2054 ret = init_iommu_one_late(iommu); 2055 if (ret) 2056 return ret; 2057 } 2058 2059 return 0; 2060 } 2061 2062 static void init_iommu_perf_ctr(struct amd_iommu *iommu) 2063 { 2064 u64 val; 2065 struct pci_dev *pdev = iommu->dev; 2066 2067 if (!check_feature(FEATURE_PC)) 2068 return; 2069 2070 amd_iommu_pc_present = true; 2071 2072 pci_info(pdev, "IOMMU performance counters supported\n"); 2073 2074 val = readl(iommu->mmio_base + MMIO_CNTR_CONF_OFFSET); 2075 iommu->max_banks = (u8) ((val >> 12) & 0x3f); 2076 iommu->max_counters = (u8) ((val >> 7) & 0xf); 2077 2078 return; 2079 } 2080 2081 static ssize_t amd_iommu_show_cap(struct device *dev, 2082 struct device_attribute *attr, 2083 char *buf) 2084 { 2085 struct amd_iommu *iommu = dev_to_amd_iommu(dev); 2086 return sysfs_emit(buf, "%x\n", iommu->cap); 2087 } 2088 static DEVICE_ATTR(cap, S_IRUGO, amd_iommu_show_cap, NULL); 2089 2090 static ssize_t amd_iommu_show_features(struct device *dev, 2091 struct device_attribute *attr, 2092 char *buf) 2093 { 2094 return sysfs_emit(buf, "%llx:%llx\n", amd_iommu_efr, amd_iommu_efr2); 2095 } 2096 static DEVICE_ATTR(features, S_IRUGO, amd_iommu_show_features, NULL); 2097 2098 static struct attribute *amd_iommu_attrs[] = { 2099 &dev_attr_cap.attr, 2100 &dev_attr_features.attr, 2101 NULL, 2102 }; 2103 2104 static struct attribute_group amd_iommu_group = { 2105 .name = "amd-iommu", 2106 .attrs = amd_iommu_attrs, 2107 }; 2108 2109 static const struct attribute_group *amd_iommu_groups[] = { 2110 &amd_iommu_group, 2111 NULL, 2112 }; 2113 2114 /* 2115 * Note: IVHD 0x11 and 0x40 also contains exact copy 2116 * of the IOMMU Extended Feature Register [MMIO Offset 0030h]. 2117 * Default to EFR in IVHD since it is available sooner (i.e. before PCI init). 2118 */ 2119 static void __init late_iommu_features_init(struct amd_iommu *iommu) 2120 { 2121 u64 features, features2; 2122 2123 if (!(iommu->cap & (1 << IOMMU_CAP_EFR))) 2124 return; 2125 2126 /* read extended feature bits */ 2127 features = readq(iommu->mmio_base + MMIO_EXT_FEATURES); 2128 features2 = readq(iommu->mmio_base + MMIO_EXT_FEATURES2); 2129 2130 if (!amd_iommu_efr) { 2131 amd_iommu_efr = features; 2132 amd_iommu_efr2 = features2; 2133 return; 2134 } 2135 2136 /* 2137 * Sanity check and warn if EFR values from 2138 * IVHD and MMIO conflict. 2139 */ 2140 if (features != amd_iommu_efr || 2141 features2 != amd_iommu_efr2) { 2142 pr_warn(FW_WARN 2143 "EFR mismatch. Use IVHD EFR (%#llx : %#llx), EFR2 (%#llx : %#llx).\n", 2144 features, amd_iommu_efr, 2145 features2, amd_iommu_efr2); 2146 } 2147 } 2148 2149 static int __init iommu_init_pci(struct amd_iommu *iommu) 2150 { 2151 int cap_ptr = iommu->cap_ptr; 2152 int ret; 2153 2154 iommu->dev = pci_get_domain_bus_and_slot(iommu->pci_seg->id, 2155 PCI_BUS_NUM(iommu->devid), 2156 iommu->devid & 0xff); 2157 if (!iommu->dev) 2158 return -ENODEV; 2159 2160 /* ACPI _PRT won't have an IRQ for IOMMU */ 2161 iommu->dev->irq_managed = 1; 2162 2163 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET, 2164 &iommu->cap); 2165 2166 if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB))) 2167 amd_iommu_iotlb_sup = false; 2168 2169 late_iommu_features_init(iommu); 2170 2171 if (check_feature(FEATURE_GT)) { 2172 int glxval; 2173 u64 pasmax; 2174 2175 pasmax = FIELD_GET(FEATURE_PASMAX, amd_iommu_efr); 2176 iommu->iommu.max_pasids = (1 << (pasmax + 1)) - 1; 2177 2178 BUG_ON(iommu->iommu.max_pasids & ~PASID_MASK); 2179 2180 glxval = FIELD_GET(FEATURE_GLX, amd_iommu_efr); 2181 2182 if (amd_iommu_max_glx_val == -1) 2183 amd_iommu_max_glx_val = glxval; 2184 else 2185 amd_iommu_max_glx_val = min(amd_iommu_max_glx_val, glxval); 2186 2187 iommu_enable_gt(iommu); 2188 } 2189 2190 if (check_feature(FEATURE_PPR) && amd_iommu_alloc_ppr_log(iommu)) 2191 return -ENOMEM; 2192 2193 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE)) { 2194 pr_info("Using strict mode due to virtualization\n"); 2195 iommu_set_dma_strict(); 2196 amd_iommu_np_cache = true; 2197 } 2198 2199 init_iommu_perf_ctr(iommu); 2200 2201 if (is_rd890_iommu(iommu->dev)) { 2202 int i, j; 2203 2204 iommu->root_pdev = 2205 pci_get_domain_bus_and_slot(iommu->pci_seg->id, 2206 iommu->dev->bus->number, 2207 PCI_DEVFN(0, 0)); 2208 2209 /* 2210 * Some rd890 systems may not be fully reconfigured by the 2211 * BIOS, so it's necessary for us to store this information so 2212 * it can be reprogrammed on resume 2213 */ 2214 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4, 2215 &iommu->stored_addr_lo); 2216 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8, 2217 &iommu->stored_addr_hi); 2218 2219 /* Low bit locks writes to configuration space */ 2220 iommu->stored_addr_lo &= ~1; 2221 2222 for (i = 0; i < 6; i++) 2223 for (j = 0; j < 0x12; j++) 2224 iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j); 2225 2226 for (i = 0; i < 0x83; i++) 2227 iommu->stored_l2[i] = iommu_read_l2(iommu, i); 2228 } 2229 2230 amd_iommu_erratum_746_workaround(iommu); 2231 amd_iommu_ats_write_check_workaround(iommu); 2232 2233 ret = iommu_device_sysfs_add(&iommu->iommu, &iommu->dev->dev, 2234 amd_iommu_groups, "ivhd%d", iommu->index); 2235 if (ret) 2236 return ret; 2237 2238 /* 2239 * Allocate per IOMMU IOPF queue here so that in attach device path, 2240 * PRI capable device can be added to IOPF queue 2241 */ 2242 if (amd_iommu_gt_ppr_supported()) { 2243 ret = amd_iommu_iopf_init(iommu); 2244 if (ret) 2245 return ret; 2246 } 2247 2248 ret = iommu_device_register(&iommu->iommu, &amd_iommu_ops, NULL); 2249 if (ret || amd_iommu_pgtable == PD_MODE_NONE) { 2250 /* 2251 * Remove sysfs if DMA translation is not supported by the 2252 * IOMMU. Do not return an error to enable IRQ remapping 2253 * in state_next(), DTE[V, TV] must eventually be set to 0. 2254 */ 2255 iommu_device_sysfs_remove(&iommu->iommu); 2256 } 2257 2258 return pci_enable_device(iommu->dev); 2259 } 2260 2261 static void print_iommu_info(void) 2262 { 2263 int i; 2264 static const char * const feat_str[] = { 2265 "PreF", "PPR", "X2APIC", "NX", "GT", "[5]", 2266 "IA", "GA", "HE", "PC" 2267 }; 2268 2269 if (amd_iommu_efr) { 2270 pr_info("Extended features (%#llx, %#llx):", amd_iommu_efr, amd_iommu_efr2); 2271 2272 for (i = 0; i < ARRAY_SIZE(feat_str); ++i) { 2273 if (check_feature(1ULL << i)) 2274 pr_cont(" %s", feat_str[i]); 2275 } 2276 2277 if (check_feature(FEATURE_GAM_VAPIC)) 2278 pr_cont(" GA_vAPIC"); 2279 2280 if (check_feature(FEATURE_SNP)) 2281 pr_cont(" SNP"); 2282 2283 if (check_feature2(FEATURE_SEVSNPIO_SUP)) 2284 pr_cont(" SEV-TIO"); 2285 2286 pr_cont("\n"); 2287 } 2288 2289 if (irq_remapping_enabled) { 2290 pr_info("Interrupt remapping enabled\n"); 2291 if (amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE) 2292 pr_info("X2APIC enabled\n"); 2293 } 2294 if (amd_iommu_pgtable == PD_MODE_V2) { 2295 pr_info("V2 page table enabled (Paging mode : %d level)\n", 2296 amd_iommu_gpt_level); 2297 } 2298 } 2299 2300 static int __init amd_iommu_init_pci(void) 2301 { 2302 struct amd_iommu *iommu; 2303 struct amd_iommu_pci_seg *pci_seg; 2304 int ret; 2305 2306 /* Init global identity domain before registering IOMMU */ 2307 amd_iommu_init_identity_domain(); 2308 2309 for_each_iommu(iommu) { 2310 ret = iommu_init_pci(iommu); 2311 if (ret) { 2312 pr_err("IOMMU%d: Failed to initialize IOMMU Hardware (error=%d)!\n", 2313 iommu->index, ret); 2314 goto out; 2315 } 2316 /* Need to setup range after PCI init */ 2317 iommu_set_cwwb_range(iommu); 2318 } 2319 2320 /* 2321 * Order is important here to make sure any unity map requirements are 2322 * fulfilled. The unity mappings are created and written to the device 2323 * table during the iommu_init_pci() call. 2324 * 2325 * After that we call init_device_table_dma() to make sure any 2326 * uninitialized DTE will block DMA, and in the end we flush the caches 2327 * of all IOMMUs to make sure the changes to the device table are 2328 * active. 2329 */ 2330 for_each_pci_segment(pci_seg) 2331 init_device_table_dma(pci_seg); 2332 2333 for_each_iommu(iommu) 2334 amd_iommu_flush_all_caches(iommu); 2335 2336 print_iommu_info(); 2337 2338 out: 2339 return ret; 2340 } 2341 2342 /**************************************************************************** 2343 * 2344 * The following functions initialize the MSI interrupts for all IOMMUs 2345 * in the system. It's a bit challenging because there could be multiple 2346 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per 2347 * pci_dev. 2348 * 2349 ****************************************************************************/ 2350 2351 static int iommu_setup_msi(struct amd_iommu *iommu) 2352 { 2353 int r; 2354 2355 r = pci_enable_msi(iommu->dev); 2356 if (r) 2357 return r; 2358 2359 r = request_threaded_irq(iommu->dev->irq, NULL, amd_iommu_int_thread, 2360 IRQF_ONESHOT, "AMD-Vi", iommu); 2361 if (r) { 2362 pci_disable_msi(iommu->dev); 2363 return r; 2364 } 2365 2366 return 0; 2367 } 2368 2369 union intcapxt { 2370 u64 capxt; 2371 struct { 2372 u64 reserved_0 : 2, 2373 dest_mode_logical : 1, 2374 reserved_1 : 5, 2375 destid_0_23 : 24, 2376 vector : 8, 2377 reserved_2 : 16, 2378 destid_24_31 : 8; 2379 }; 2380 } __attribute__ ((packed)); 2381 2382 2383 static struct irq_chip intcapxt_controller; 2384 2385 static int intcapxt_irqdomain_activate(struct irq_domain *domain, 2386 struct irq_data *irqd, bool reserve) 2387 { 2388 return 0; 2389 } 2390 2391 static void intcapxt_irqdomain_deactivate(struct irq_domain *domain, 2392 struct irq_data *irqd) 2393 { 2394 } 2395 2396 2397 static int intcapxt_irqdomain_alloc(struct irq_domain *domain, unsigned int virq, 2398 unsigned int nr_irqs, void *arg) 2399 { 2400 struct irq_alloc_info *info = arg; 2401 int i, ret; 2402 2403 if (!info || info->type != X86_IRQ_ALLOC_TYPE_AMDVI) 2404 return -EINVAL; 2405 2406 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg); 2407 if (ret < 0) 2408 return ret; 2409 2410 for (i = virq; i < virq + nr_irqs; i++) { 2411 struct irq_data *irqd = irq_domain_get_irq_data(domain, i); 2412 2413 irqd->chip = &intcapxt_controller; 2414 irqd->hwirq = info->hwirq; 2415 irqd->chip_data = info->data; 2416 __irq_set_handler(i, handle_edge_irq, 0, "edge"); 2417 } 2418 2419 return ret; 2420 } 2421 2422 static void intcapxt_irqdomain_free(struct irq_domain *domain, unsigned int virq, 2423 unsigned int nr_irqs) 2424 { 2425 irq_domain_free_irqs_top(domain, virq, nr_irqs); 2426 } 2427 2428 2429 static void intcapxt_unmask_irq(struct irq_data *irqd) 2430 { 2431 struct amd_iommu *iommu = irqd->chip_data; 2432 struct irq_cfg *cfg = irqd_cfg(irqd); 2433 union intcapxt xt; 2434 2435 xt.capxt = 0ULL; 2436 xt.dest_mode_logical = apic->dest_mode_logical; 2437 xt.vector = cfg->vector; 2438 xt.destid_0_23 = cfg->dest_apicid & GENMASK(23, 0); 2439 xt.destid_24_31 = cfg->dest_apicid >> 24; 2440 2441 writeq(xt.capxt, iommu->mmio_base + irqd->hwirq); 2442 } 2443 2444 static void intcapxt_mask_irq(struct irq_data *irqd) 2445 { 2446 struct amd_iommu *iommu = irqd->chip_data; 2447 2448 writeq(0, iommu->mmio_base + irqd->hwirq); 2449 } 2450 2451 2452 static int intcapxt_set_affinity(struct irq_data *irqd, 2453 const struct cpumask *mask, bool force) 2454 { 2455 struct irq_data *parent = irqd->parent_data; 2456 int ret; 2457 2458 ret = parent->chip->irq_set_affinity(parent, mask, force); 2459 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE) 2460 return ret; 2461 return 0; 2462 } 2463 2464 static int intcapxt_set_wake(struct irq_data *irqd, unsigned int on) 2465 { 2466 return on ? -EOPNOTSUPP : 0; 2467 } 2468 2469 static struct irq_chip intcapxt_controller = { 2470 .name = "IOMMU-MSI", 2471 .irq_unmask = intcapxt_unmask_irq, 2472 .irq_mask = intcapxt_mask_irq, 2473 .irq_ack = irq_chip_ack_parent, 2474 .irq_retrigger = irq_chip_retrigger_hierarchy, 2475 .irq_set_affinity = intcapxt_set_affinity, 2476 .irq_set_wake = intcapxt_set_wake, 2477 .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_MOVE_DEFERRED, 2478 }; 2479 2480 static const struct irq_domain_ops intcapxt_domain_ops = { 2481 .alloc = intcapxt_irqdomain_alloc, 2482 .free = intcapxt_irqdomain_free, 2483 .activate = intcapxt_irqdomain_activate, 2484 .deactivate = intcapxt_irqdomain_deactivate, 2485 }; 2486 2487 2488 static struct irq_domain *iommu_irqdomain; 2489 2490 static struct irq_domain *iommu_get_irqdomain(void) 2491 { 2492 struct fwnode_handle *fn; 2493 2494 /* No need for locking here (yet) as the init is single-threaded */ 2495 if (iommu_irqdomain) 2496 return iommu_irqdomain; 2497 2498 fn = irq_domain_alloc_named_fwnode("AMD-Vi-MSI"); 2499 if (!fn) 2500 return NULL; 2501 2502 iommu_irqdomain = irq_domain_create_hierarchy(x86_vector_domain, 0, 0, 2503 fn, &intcapxt_domain_ops, 2504 NULL); 2505 if (!iommu_irqdomain) 2506 irq_domain_free_fwnode(fn); 2507 2508 return iommu_irqdomain; 2509 } 2510 2511 static int __iommu_setup_intcapxt(struct amd_iommu *iommu, const char *devname, 2512 int hwirq, irq_handler_t thread_fn) 2513 { 2514 struct irq_domain *domain; 2515 struct irq_alloc_info info; 2516 int irq, ret; 2517 int node = dev_to_node(&iommu->dev->dev); 2518 2519 domain = iommu_get_irqdomain(); 2520 if (!domain) 2521 return -ENXIO; 2522 2523 init_irq_alloc_info(&info, NULL); 2524 info.type = X86_IRQ_ALLOC_TYPE_AMDVI; 2525 info.data = iommu; 2526 info.hwirq = hwirq; 2527 2528 irq = irq_domain_alloc_irqs(domain, 1, node, &info); 2529 if (irq < 0) { 2530 irq_domain_remove(domain); 2531 return irq; 2532 } 2533 2534 ret = request_threaded_irq(irq, NULL, thread_fn, IRQF_ONESHOT, devname, 2535 iommu); 2536 if (ret) { 2537 irq_domain_free_irqs(irq, 1); 2538 irq_domain_remove(domain); 2539 return ret; 2540 } 2541 2542 return 0; 2543 } 2544 2545 static int iommu_setup_intcapxt(struct amd_iommu *iommu) 2546 { 2547 int ret; 2548 2549 snprintf(iommu->evt_irq_name, sizeof(iommu->evt_irq_name), 2550 "AMD-Vi%d-Evt", iommu->index); 2551 ret = __iommu_setup_intcapxt(iommu, iommu->evt_irq_name, 2552 MMIO_INTCAPXT_EVT_OFFSET, 2553 amd_iommu_int_thread_evtlog); 2554 if (ret) 2555 return ret; 2556 2557 snprintf(iommu->ppr_irq_name, sizeof(iommu->ppr_irq_name), 2558 "AMD-Vi%d-PPR", iommu->index); 2559 ret = __iommu_setup_intcapxt(iommu, iommu->ppr_irq_name, 2560 MMIO_INTCAPXT_PPR_OFFSET, 2561 amd_iommu_int_thread_pprlog); 2562 if (ret) 2563 return ret; 2564 2565 #ifdef CONFIG_IRQ_REMAP 2566 snprintf(iommu->ga_irq_name, sizeof(iommu->ga_irq_name), 2567 "AMD-Vi%d-GA", iommu->index); 2568 ret = __iommu_setup_intcapxt(iommu, iommu->ga_irq_name, 2569 MMIO_INTCAPXT_GALOG_OFFSET, 2570 amd_iommu_int_thread_galog); 2571 #endif 2572 2573 return ret; 2574 } 2575 2576 static int iommu_init_irq(struct amd_iommu *iommu) 2577 { 2578 int ret; 2579 2580 if (iommu->int_enabled) 2581 goto enable_faults; 2582 2583 if (amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE) 2584 ret = iommu_setup_intcapxt(iommu); 2585 else if (iommu->dev->msi_cap) 2586 ret = iommu_setup_msi(iommu); 2587 else 2588 ret = -ENODEV; 2589 2590 if (ret) 2591 return ret; 2592 2593 iommu->int_enabled = true; 2594 enable_faults: 2595 2596 if (amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE) 2597 iommu_feature_enable(iommu, CONTROL_INTCAPXT_EN); 2598 2599 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN); 2600 2601 return 0; 2602 } 2603 2604 /**************************************************************************** 2605 * 2606 * The next functions belong to the third pass of parsing the ACPI 2607 * table. In this last pass the memory mapping requirements are 2608 * gathered (like exclusion and unity mapping ranges). 2609 * 2610 ****************************************************************************/ 2611 2612 static void __init free_unity_maps(void) 2613 { 2614 struct unity_map_entry *entry, *next; 2615 struct amd_iommu_pci_seg *p, *pci_seg; 2616 2617 for_each_pci_segment_safe(pci_seg, p) { 2618 list_for_each_entry_safe(entry, next, &pci_seg->unity_map, list) { 2619 list_del(&entry->list); 2620 kfree(entry); 2621 } 2622 } 2623 } 2624 2625 /* called for unity map ACPI definition */ 2626 static int __init init_unity_map_range(struct ivmd_header *m, 2627 struct acpi_table_header *ivrs_base) 2628 { 2629 struct unity_map_entry *e = NULL; 2630 struct amd_iommu_pci_seg *pci_seg; 2631 char *s; 2632 2633 pci_seg = get_pci_segment(m->pci_seg, ivrs_base); 2634 if (pci_seg == NULL) 2635 return -ENOMEM; 2636 2637 e = kzalloc_obj(*e); 2638 if (e == NULL) 2639 return -ENOMEM; 2640 2641 switch (m->type) { 2642 default: 2643 kfree(e); 2644 return 0; 2645 case ACPI_IVMD_TYPE: 2646 s = "IVMD_TYPEi\t\t\t"; 2647 e->devid_start = e->devid_end = m->devid; 2648 break; 2649 case ACPI_IVMD_TYPE_ALL: 2650 s = "IVMD_TYPE_ALL\t\t"; 2651 e->devid_start = 0; 2652 e->devid_end = pci_seg->last_bdf; 2653 break; 2654 case ACPI_IVMD_TYPE_RANGE: 2655 s = "IVMD_TYPE_RANGE\t\t"; 2656 e->devid_start = m->devid; 2657 e->devid_end = m->aux; 2658 break; 2659 } 2660 e->address_start = PAGE_ALIGN(m->range_start); 2661 e->address_end = e->address_start + PAGE_ALIGN(m->range_length); 2662 e->prot = m->flags >> 1; 2663 2664 /* 2665 * Treat per-device exclusion ranges as r/w unity-mapped regions 2666 * since some buggy BIOSes might lead to the overwritten exclusion 2667 * range (exclusion_start and exclusion_length members). This 2668 * happens when there are multiple exclusion ranges (IVMD entries) 2669 * defined in ACPI table. 2670 */ 2671 if (m->flags & IVMD_FLAG_EXCL_RANGE) 2672 e->prot = (IVMD_FLAG_IW | IVMD_FLAG_IR) >> 1; 2673 2674 DUMP_printk("%s devid_start: %04x:%02x:%02x.%x devid_end: " 2675 "%04x:%02x:%02x.%x range_start: %016llx range_end: %016llx" 2676 " flags: %x\n", s, m->pci_seg, 2677 PCI_BUS_NUM(e->devid_start), PCI_SLOT(e->devid_start), 2678 PCI_FUNC(e->devid_start), m->pci_seg, 2679 PCI_BUS_NUM(e->devid_end), 2680 PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end), 2681 e->address_start, e->address_end, m->flags); 2682 2683 list_add_tail(&e->list, &pci_seg->unity_map); 2684 2685 return 0; 2686 } 2687 2688 /* iterates over all memory definitions we find in the ACPI table */ 2689 static int __init init_memory_definitions(struct acpi_table_header *table) 2690 { 2691 u8 *p = (u8 *)table, *end = (u8 *)table; 2692 struct ivmd_header *m; 2693 2694 end += table->length; 2695 p += IVRS_HEADER_LENGTH; 2696 2697 while (p < end) { 2698 m = (struct ivmd_header *)p; 2699 if (m->flags & (IVMD_FLAG_UNITY_MAP | IVMD_FLAG_EXCL_RANGE)) 2700 init_unity_map_range(m, table); 2701 2702 p += m->length; 2703 } 2704 2705 return 0; 2706 } 2707 2708 /* 2709 * Init the device table to not allow DMA access for devices 2710 */ 2711 static void init_device_table_dma(struct amd_iommu_pci_seg *pci_seg) 2712 { 2713 u32 devid; 2714 struct dev_table_entry *dev_table = pci_seg->dev_table; 2715 2716 if (!dev_table || amd_iommu_pgtable == PD_MODE_NONE) 2717 return; 2718 2719 for (devid = 0; devid <= pci_seg->last_bdf; ++devid) { 2720 set_dte_bit(&dev_table[devid], DEV_ENTRY_VALID); 2721 if (!amd_iommu_snp_en) 2722 set_dte_bit(&dev_table[devid], DEV_ENTRY_TRANSLATION); 2723 } 2724 } 2725 2726 static void __init uninit_device_table_dma(struct amd_iommu_pci_seg *pci_seg) 2727 { 2728 u32 devid; 2729 struct dev_table_entry *dev_table = pci_seg->dev_table; 2730 2731 if (dev_table == NULL) 2732 return; 2733 2734 for (devid = 0; devid <= pci_seg->last_bdf; ++devid) { 2735 dev_table[devid].data[0] = 0ULL; 2736 dev_table[devid].data[1] = 0ULL; 2737 } 2738 } 2739 2740 static void init_device_table(void) 2741 { 2742 struct amd_iommu_pci_seg *pci_seg; 2743 u32 devid; 2744 2745 if (!amd_iommu_irq_remap) 2746 return; 2747 2748 for_each_pci_segment(pci_seg) { 2749 for (devid = 0; devid <= pci_seg->last_bdf; ++devid) 2750 set_dte_bit(&pci_seg->dev_table[devid], DEV_ENTRY_IRQ_TBL_EN); 2751 } 2752 } 2753 2754 static void iommu_init_flags(struct amd_iommu *iommu) 2755 { 2756 iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ? 2757 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) : 2758 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN); 2759 2760 iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ? 2761 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) : 2762 iommu_feature_disable(iommu, CONTROL_PASSPW_EN); 2763 2764 iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ? 2765 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) : 2766 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN); 2767 2768 iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ? 2769 iommu_feature_enable(iommu, CONTROL_ISOC_EN) : 2770 iommu_feature_disable(iommu, CONTROL_ISOC_EN); 2771 2772 /* 2773 * make IOMMU memory accesses cache coherent 2774 */ 2775 iommu_feature_enable(iommu, CONTROL_COHERENT_EN); 2776 2777 /* Set IOTLB invalidation timeout to 1s */ 2778 iommu_feature_set(iommu, CTRL_INV_TO_1S, CTRL_INV_TO_MASK, CONTROL_INV_TIMEOUT); 2779 2780 /* Enable Enhanced Peripheral Page Request Handling */ 2781 if (check_feature(FEATURE_EPHSUP)) 2782 iommu_feature_enable(iommu, CONTROL_EPH_EN); 2783 } 2784 2785 static void iommu_apply_resume_quirks(struct amd_iommu *iommu) 2786 { 2787 int i, j; 2788 u32 ioc_feature_control; 2789 struct pci_dev *pdev = iommu->root_pdev; 2790 2791 /* RD890 BIOSes may not have completely reconfigured the iommu */ 2792 if (!is_rd890_iommu(iommu->dev) || !pdev) 2793 return; 2794 2795 /* 2796 * First, we need to ensure that the iommu is enabled. This is 2797 * controlled by a register in the northbridge 2798 */ 2799 2800 /* Select Northbridge indirect register 0x75 and enable writing */ 2801 pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7)); 2802 pci_read_config_dword(pdev, 0x64, &ioc_feature_control); 2803 2804 /* Enable the iommu */ 2805 if (!(ioc_feature_control & 0x1)) 2806 pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1); 2807 2808 /* Restore the iommu BAR */ 2809 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4, 2810 iommu->stored_addr_lo); 2811 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8, 2812 iommu->stored_addr_hi); 2813 2814 /* Restore the l1 indirect regs for each of the 6 l1s */ 2815 for (i = 0; i < 6; i++) 2816 for (j = 0; j < 0x12; j++) 2817 iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]); 2818 2819 /* Restore the l2 indirect regs */ 2820 for (i = 0; i < 0x83; i++) 2821 iommu_write_l2(iommu, i, iommu->stored_l2[i]); 2822 2823 /* Lock PCI setup registers */ 2824 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4, 2825 iommu->stored_addr_lo | 1); 2826 } 2827 2828 static void iommu_enable_ga(struct amd_iommu *iommu) 2829 { 2830 #ifdef CONFIG_IRQ_REMAP 2831 switch (amd_iommu_guest_ir) { 2832 case AMD_IOMMU_GUEST_IR_VAPIC: 2833 case AMD_IOMMU_GUEST_IR_LEGACY_GA: 2834 iommu_feature_enable(iommu, CONTROL_GA_EN); 2835 iommu->irte_ops = &irte_128_ops; 2836 break; 2837 default: 2838 iommu->irte_ops = &irte_32_ops; 2839 break; 2840 } 2841 #endif 2842 } 2843 2844 static void iommu_disable_irtcachedis(struct amd_iommu *iommu) 2845 { 2846 iommu_feature_disable(iommu, CONTROL_IRTCACHEDIS); 2847 } 2848 2849 static void iommu_enable_irtcachedis(struct amd_iommu *iommu) 2850 { 2851 u64 ctrl; 2852 2853 if (!amd_iommu_irtcachedis) 2854 return; 2855 2856 /* 2857 * Note: 2858 * The support for IRTCacheDis feature is dertermined by 2859 * checking if the bit is writable. 2860 */ 2861 iommu_feature_enable(iommu, CONTROL_IRTCACHEDIS); 2862 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); 2863 ctrl &= (1ULL << CONTROL_IRTCACHEDIS); 2864 if (ctrl) 2865 iommu->irtcachedis_enabled = true; 2866 pr_info("iommu%d (%#06x) : IRT cache is %s\n", 2867 iommu->index, iommu->devid, 2868 iommu->irtcachedis_enabled ? "disabled" : "enabled"); 2869 } 2870 2871 static void iommu_enable_2k_int(struct amd_iommu *iommu) 2872 { 2873 if (!FEATURE_NUM_INT_REMAP_SUP_2K(amd_iommu_efr2)) 2874 return; 2875 2876 iommu_feature_set(iommu, 2877 CONTROL_NUM_INT_REMAP_MODE_2K, 2878 CONTROL_NUM_INT_REMAP_MODE_MASK, 2879 CONTROL_NUM_INT_REMAP_MODE); 2880 } 2881 2882 static void early_enable_iommu(struct amd_iommu *iommu) 2883 { 2884 iommu_disable(iommu); 2885 iommu_init_flags(iommu); 2886 iommu_set_device_table(iommu); 2887 iommu_enable_command_buffer(iommu); 2888 iommu_enable_gt(iommu); 2889 iommu_enable_ga(iommu); 2890 iommu_enable_xt(iommu); 2891 iommu_enable_irtcachedis(iommu); 2892 iommu_enable_2k_int(iommu); 2893 iommu_enable(iommu); 2894 amd_iommu_flush_all_caches(iommu); 2895 } 2896 2897 /* 2898 * This function finally enables all IOMMUs found in the system after 2899 * they have been initialized. 2900 * 2901 * Or if in kdump kernel and IOMMUs are all pre-enabled, try to reuse 2902 * the old content of device table entries. Not this case or reuse failed, 2903 * just continue as normal kernel does. 2904 */ 2905 static void early_enable_iommus(void) 2906 { 2907 struct amd_iommu *iommu; 2908 struct amd_iommu_pci_seg *pci_seg; 2909 2910 if (!reuse_device_table()) { 2911 /* 2912 * If come here because of failure in reusing device table from old 2913 * kernel with all IOMMUs enabled, print error message and try to 2914 * free allocated old_dev_tbl_cpy. 2915 */ 2916 if (amd_iommu_pre_enabled) { 2917 pr_err("Failed to reuse DEV table from previous kernel.\n"); 2918 /* 2919 * Bail out early if unable to remap/reuse DEV table from 2920 * previous kernel if SNP enabled as IOMMU commands will 2921 * time out without DEV table and cause kdump boot panic. 2922 */ 2923 BUG_ON(check_feature(FEATURE_SNP)); 2924 } 2925 2926 for_each_pci_segment(pci_seg) { 2927 if (pci_seg->old_dev_tbl_cpy != NULL) { 2928 memunmap((void *)pci_seg->old_dev_tbl_cpy); 2929 pci_seg->old_dev_tbl_cpy = NULL; 2930 } 2931 } 2932 2933 for_each_iommu(iommu) { 2934 clear_translation_pre_enabled(iommu); 2935 early_enable_iommu(iommu); 2936 } 2937 } else { 2938 pr_info("Reused DEV table from previous kernel.\n"); 2939 2940 for_each_pci_segment(pci_seg) { 2941 iommu_free_pages(pci_seg->dev_table); 2942 pci_seg->dev_table = pci_seg->old_dev_tbl_cpy; 2943 } 2944 2945 for_each_iommu(iommu) { 2946 iommu_disable_command_buffer(iommu); 2947 iommu_disable_event_buffer(iommu); 2948 iommu_disable_irtcachedis(iommu); 2949 iommu_enable_command_buffer(iommu); 2950 iommu_enable_ga(iommu); 2951 iommu_enable_xt(iommu); 2952 iommu_enable_irtcachedis(iommu); 2953 iommu_enable_2k_int(iommu); 2954 iommu_set_device_table(iommu); 2955 amd_iommu_flush_all_caches(iommu); 2956 } 2957 } 2958 } 2959 2960 static void enable_iommus_ppr(void) 2961 { 2962 struct amd_iommu *iommu; 2963 2964 if (!amd_iommu_gt_ppr_supported()) 2965 return; 2966 2967 for_each_iommu(iommu) 2968 amd_iommu_enable_ppr_log(iommu); 2969 } 2970 2971 static void enable_iommus_vapic(void) 2972 { 2973 #ifdef CONFIG_IRQ_REMAP 2974 u32 status, i; 2975 struct amd_iommu *iommu; 2976 2977 for_each_iommu(iommu) { 2978 /* 2979 * Disable GALog if already running. It could have been enabled 2980 * in the previous boot before kdump. 2981 */ 2982 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); 2983 if (!(status & MMIO_STATUS_GALOG_RUN_MASK)) 2984 continue; 2985 2986 iommu_feature_disable(iommu, CONTROL_GALOG_EN); 2987 iommu_feature_disable(iommu, CONTROL_GAINT_EN); 2988 2989 /* 2990 * Need to set and poll check the GALOGRun bit to zero before 2991 * we can set/ modify GA Log registers safely. 2992 */ 2993 for (i = 0; i < MMIO_STATUS_TIMEOUT; ++i) { 2994 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); 2995 if (!(status & MMIO_STATUS_GALOG_RUN_MASK)) 2996 break; 2997 udelay(10); 2998 } 2999 3000 if (WARN_ON(i >= MMIO_STATUS_TIMEOUT)) 3001 return; 3002 } 3003 3004 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) 3005 return; 3006 3007 if (!check_feature(FEATURE_GAM_VAPIC)) { 3008 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY_GA; 3009 return; 3010 } 3011 3012 if (amd_iommu_snp_en && 3013 !FEATURE_SNPAVICSUP_GAM(amd_iommu_efr2)) { 3014 pr_warn("Force to disable Virtual APIC due to SNP\n"); 3015 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY_GA; 3016 return; 3017 } 3018 3019 /* Enabling GAM and SNPAVIC support */ 3020 for_each_iommu(iommu) { 3021 if (iommu_init_ga_log(iommu) || 3022 iommu_ga_log_enable(iommu)) 3023 return; 3024 3025 iommu_feature_enable(iommu, CONTROL_GAM_EN); 3026 if (amd_iommu_snp_en) 3027 iommu_feature_enable(iommu, CONTROL_SNPAVIC_EN); 3028 } 3029 3030 amd_iommu_irq_ops.capability |= (1 << IRQ_POSTING_CAP); 3031 pr_info("Virtual APIC enabled\n"); 3032 #endif 3033 } 3034 3035 static void disable_iommus(void) 3036 { 3037 struct amd_iommu *iommu; 3038 3039 for_each_iommu(iommu) 3040 iommu_disable(iommu); 3041 3042 #ifdef CONFIG_IRQ_REMAP 3043 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) 3044 amd_iommu_irq_ops.capability &= ~(1 << IRQ_POSTING_CAP); 3045 #endif 3046 } 3047 3048 /* 3049 * Suspend/Resume support 3050 * disable suspend until real resume implemented 3051 */ 3052 3053 static void amd_iommu_resume(void *data) 3054 { 3055 struct amd_iommu *iommu; 3056 3057 for_each_iommu(iommu) 3058 iommu_apply_resume_quirks(iommu); 3059 3060 /* re-load the hardware */ 3061 for_each_iommu(iommu) 3062 early_enable_iommu(iommu); 3063 3064 iommu_enable_event_buffer(); 3065 amd_iommu_enable_interrupts(); 3066 } 3067 3068 static int amd_iommu_suspend(void *data) 3069 { 3070 /* disable IOMMUs to go out of the way for BIOS */ 3071 disable_iommus(); 3072 3073 return 0; 3074 } 3075 3076 static const struct syscore_ops amd_iommu_syscore_ops = { 3077 .suspend = amd_iommu_suspend, 3078 .resume = amd_iommu_resume, 3079 }; 3080 3081 static struct syscore amd_iommu_syscore = { 3082 .ops = &amd_iommu_syscore_ops, 3083 }; 3084 3085 static void __init free_iommu_resources(void) 3086 { 3087 free_iommu_all(); 3088 free_pci_segments(); 3089 } 3090 3091 static bool __init check_sb_ioapic(int devid) 3092 { 3093 u8 bus = PCI_BUS_NUM(devid); 3094 u8 devfn = devid & 0xff; 3095 u16 val; 3096 3097 val = read_pci_config_16(bus, PCI_SLOT(devfn), PCI_FUNC(devfn), 3098 PCI_CLASS_DEVICE); 3099 3100 /* 3101 * The SB IOAPIC is integrated into the FCH (Southbridge), which is 3102 * exposed as an SMBus or ISA bridge in PCI config space. 3103 */ 3104 return val == PCI_CLASS_SERIAL_SMBUS || val == PCI_CLASS_BRIDGE_ISA; 3105 } 3106 3107 /* 3108 * The Southbridge IOAPIC is assigned a GSI Base of 0 (handling interrupts 3109 * 0 through 23). 3110 */ 3111 static int __init get_sb_ioapic_id(void) 3112 { 3113 int idx = mp_find_ioapic(0); 3114 3115 if (idx < 0) 3116 return -ENODEV; 3117 3118 return mpc_ioapic_id(idx); 3119 } 3120 3121 static bool __init check_ioapic_information(void) 3122 { 3123 const char *fw_bug = FW_BUG; 3124 bool ret, has_sb_ioapic; 3125 int idx, sb_apicid; 3126 3127 has_sb_ioapic = false; 3128 ret = true; 3129 3130 /* 3131 * If we have map overrides on the kernel command line the 3132 * messages in this function might not describe firmware bugs 3133 * anymore - so be careful 3134 */ 3135 if (cmdline_maps) 3136 fw_bug = ""; 3137 3138 sb_apicid = get_sb_ioapic_id(); 3139 if (sb_apicid < 0) { 3140 /* 3141 * Lack of SB IOAPIC registration is not a firmware bug, 3142 * e.g. kernel booted with noapic or noacpi. 3143 */ 3144 fw_bug = ""; 3145 goto out; 3146 } 3147 3148 for (idx = 0; idx < nr_ioapics; idx++) { 3149 int devid, id = mpc_ioapic_id(idx); 3150 3151 devid = get_ioapic_devid(id); 3152 if (devid < 0) { 3153 pr_err("%s: IOAPIC[%d] not in IVRS table\n", 3154 fw_bug, id); 3155 ret = false; 3156 } else if (id == sb_apicid && check_sb_ioapic(devid)) { 3157 has_sb_ioapic = true; 3158 } 3159 } 3160 out: 3161 if (!has_sb_ioapic) { 3162 /* 3163 * We expect the SB IOAPIC to be listed in the IVRS 3164 * table. The system timer is connected to the SB IOAPIC 3165 * and if we don't have it in the list the system will 3166 * panic at boot time. This situation usually happens 3167 * when the BIOS is buggy and provides us the wrong 3168 * device id for the IOAPIC in the system. 3169 */ 3170 pr_err("%s: No southbridge IOAPIC found\n", fw_bug); 3171 ret = false; 3172 } 3173 3174 if (!ret) 3175 pr_err("Disabling interrupt remapping\n"); 3176 3177 return ret; 3178 } 3179 3180 static void __init free_dma_resources(void) 3181 { 3182 amd_iommu_pdom_id_destroy(); 3183 free_unity_maps(); 3184 } 3185 3186 static void __init ivinfo_init(void *ivrs) 3187 { 3188 amd_iommu_ivinfo = *((u32 *)(ivrs + IOMMU_IVINFO_OFFSET)); 3189 } 3190 3191 /* 3192 * This is the hardware init function for AMD IOMMU in the system. 3193 * This function is called either from amd_iommu_init or from the interrupt 3194 * remapping setup code. 3195 * 3196 * This function basically parses the ACPI table for AMD IOMMU (IVRS) 3197 * four times: 3198 * 3199 * 1 pass) Discover the most comprehensive IVHD type to use. 3200 * 3201 * 2 pass) Find the highest PCI device id the driver has to handle. 3202 * Upon this information the size of the data structures is 3203 * determined that needs to be allocated. 3204 * 3205 * 3 pass) Initialize the data structures just allocated with the 3206 * information in the ACPI table about available AMD IOMMUs 3207 * in the system. It also maps the PCI devices in the 3208 * system to specific IOMMUs 3209 * 3210 * 4 pass) After the basic data structures are allocated and 3211 * initialized we update them with information about memory 3212 * remapping requirements parsed out of the ACPI table in 3213 * this last pass. 3214 * 3215 * After everything is set up the IOMMUs are enabled and the necessary 3216 * hotplug and suspend notifiers are registered. 3217 */ 3218 static int __init early_amd_iommu_init(void) 3219 { 3220 struct acpi_table_header *ivrs_base; 3221 int ret; 3222 acpi_status status; 3223 u8 efr_hats, max_vasize; 3224 3225 if (!amd_iommu_detected) 3226 return -ENODEV; 3227 3228 status = acpi_get_table("IVRS", 0, &ivrs_base); 3229 if (status == AE_NOT_FOUND) 3230 return -ENODEV; 3231 else if (ACPI_FAILURE(status)) { 3232 const char *err = acpi_format_exception(status); 3233 pr_err("IVRS table error: %s\n", err); 3234 return -EINVAL; 3235 } 3236 3237 if (!boot_cpu_has(X86_FEATURE_CX16)) { 3238 pr_err("Failed to initialize. The CMPXCHG16B feature is required.\n"); 3239 ret = -EINVAL; 3240 goto out; 3241 } 3242 3243 /* 3244 * Validate checksum here so we don't need to do it when 3245 * we actually parse the table 3246 */ 3247 ret = check_ivrs_checksum(ivrs_base); 3248 if (ret) 3249 goto out; 3250 3251 ivinfo_init(ivrs_base); 3252 3253 max_vasize = FIELD_GET(IOMMU_IVINFO_VASIZE, amd_iommu_ivinfo); 3254 if (!max_vasize) 3255 max_vasize = 64; 3256 3257 amd_iommu_target_ivhd_type = get_highest_supported_ivhd_type(ivrs_base); 3258 DUMP_printk("Using IVHD type %#x\n", amd_iommu_target_ivhd_type); 3259 3260 /* 3261 * now the data structures are allocated and basically initialized 3262 * start the real acpi table scan 3263 */ 3264 ret = init_iommu_all(ivrs_base); 3265 if (ret) 3266 goto out; 3267 3268 /* 5 level guest page table */ 3269 if (cpu_feature_enabled(X86_FEATURE_LA57) && 3270 FIELD_GET(FEATURE_GATS, amd_iommu_efr) == GUEST_PGTABLE_5_LEVEL) 3271 amd_iommu_gpt_level = PAGE_MODE_5_LEVEL; 3272 3273 efr_hats = FIELD_GET(FEATURE_HATS, amd_iommu_efr); 3274 if (efr_hats != 0x3) { 3275 /* 3276 * efr[HATS] bits specify the maximum host translation level 3277 * supported, with LEVEL 4 being initial max level. 3278 */ 3279 amd_iommu_hpt_vasize = min_t(unsigned int, max_vasize, 3280 (efr_hats + PAGE_MODE_4_LEVEL - 1) * 9 + 21); 3281 } else { 3282 pr_warn_once(FW_BUG "Disable host address translation due to invalid translation level (%#x).\n", 3283 efr_hats); 3284 amd_iommu_hatdis = true; 3285 } 3286 3287 if (amd_iommu_pgtable == PD_MODE_V2) { 3288 if (!amd_iommu_v2_pgtbl_supported()) { 3289 pr_warn("Cannot enable v2 page table for DMA-API. Fallback to v1.\n"); 3290 amd_iommu_pgtable = PD_MODE_V1; 3291 } 3292 } 3293 3294 if (amd_iommu_hatdis) { 3295 /* 3296 * Host (v1) page table is not available. Attempt to use 3297 * Guest (v2) page table. 3298 */ 3299 if (amd_iommu_v2_pgtbl_supported()) 3300 amd_iommu_pgtable = PD_MODE_V2; 3301 else 3302 amd_iommu_pgtable = PD_MODE_NONE; 3303 } 3304 3305 /* Disable any previously enabled IOMMUs */ 3306 if (!is_kdump_kernel() || amd_iommu_disabled) 3307 disable_iommus(); 3308 3309 if (amd_iommu_irq_remap) 3310 amd_iommu_irq_remap = check_ioapic_information(); 3311 3312 if (amd_iommu_irq_remap) { 3313 struct amd_iommu_pci_seg *pci_seg; 3314 ret = -ENOMEM; 3315 for_each_pci_segment(pci_seg) { 3316 if (alloc_irq_lookup_table(pci_seg)) 3317 goto out; 3318 } 3319 } 3320 3321 ret = init_memory_definitions(ivrs_base); 3322 if (ret) 3323 goto out; 3324 3325 /* init the device table */ 3326 init_device_table(); 3327 3328 out: 3329 /* Don't leak any ACPI memory */ 3330 acpi_put_table(ivrs_base); 3331 3332 return ret; 3333 } 3334 3335 static int amd_iommu_enable_interrupts(void) 3336 { 3337 struct amd_iommu *iommu; 3338 int ret = 0; 3339 3340 for_each_iommu(iommu) { 3341 ret = iommu_init_irq(iommu); 3342 if (ret) 3343 goto out; 3344 } 3345 3346 /* 3347 * Interrupt handler is ready to process interrupts. Enable 3348 * PPR and GA log interrupt for all IOMMUs. 3349 */ 3350 enable_iommus_vapic(); 3351 enable_iommus_ppr(); 3352 3353 out: 3354 return ret; 3355 } 3356 3357 static bool __init detect_ivrs(void) 3358 { 3359 struct acpi_table_header *ivrs_base; 3360 acpi_status status; 3361 int i; 3362 3363 status = acpi_get_table("IVRS", 0, &ivrs_base); 3364 if (status == AE_NOT_FOUND) 3365 return false; 3366 else if (ACPI_FAILURE(status)) { 3367 const char *err = acpi_format_exception(status); 3368 pr_err("IVRS table error: %s\n", err); 3369 return false; 3370 } 3371 3372 acpi_put_table(ivrs_base); 3373 3374 if (amd_iommu_force_enable) 3375 goto out; 3376 3377 /* Don't use IOMMU if there is Stoney Ridge graphics */ 3378 for (i = 0; i < 32; i++) { 3379 u32 pci_id; 3380 3381 pci_id = read_pci_config(0, i, 0, 0); 3382 if ((pci_id & 0xffff) == 0x1002 && (pci_id >> 16) == 0x98e4) { 3383 pr_info("Disable IOMMU on Stoney Ridge\n"); 3384 return false; 3385 } 3386 } 3387 3388 out: 3389 /* Make sure ACS will be enabled during PCI probe */ 3390 pci_request_acs(); 3391 3392 return true; 3393 } 3394 3395 static __init void iommu_snp_enable(void) 3396 { 3397 #ifdef CONFIG_KVM_AMD_SEV 3398 if (!cc_platform_has(CC_ATTR_HOST_SEV_SNP)) 3399 return; 3400 3401 /* SNP support required IOMMU to be ON */ 3402 if (no_iommu) { 3403 pr_warn("SNP: IOMMU disabled, SNP cannot be supported.\n"); 3404 goto disable_snp; 3405 } 3406 3407 amd_iommu_snp_mode0_sup = check_feature2(FEATURE_SNP_PAGE_MODE0_SUP); 3408 /* 3409 * If SNP page mode 0 is not enabled, then SNP support requires that IOMMU 3410 * must be configured with V1 page table (DTE[Mode] != 0). 3411 */ 3412 if (!amd_iommu_snp_mode0_sup) { 3413 if (iommu_default_passthrough()) { 3414 pr_warn("SNP: IOMMU configured in passthrough mode, SNP cannot be supported.\n"); 3415 goto disable_snp; 3416 } 3417 3418 if (amd_iommu_pgtable != PD_MODE_V1) { 3419 pr_warn("SNP: IOMMU is configured with V2 page table mode, SNP cannot be supported.\n"); 3420 goto disable_snp; 3421 } 3422 } 3423 3424 amd_iommu_snp_en = check_feature(FEATURE_SNP); 3425 if (!amd_iommu_snp_en) { 3426 pr_warn("SNP: IOMMU SNP feature not enabled, SNP cannot be supported.\n"); 3427 goto disable_snp; 3428 } 3429 3430 /* 3431 * Enable host SNP support once SNP support is checked on IOMMU. 3432 */ 3433 if (snp_rmptable_init()) { 3434 pr_warn("SNP: RMP initialization failed, SNP cannot be supported.\n"); 3435 goto disable_snp; 3436 } 3437 3438 pr_info("IOMMU SNP support enabled.\n"); 3439 return; 3440 3441 disable_snp: 3442 cc_platform_clear(CC_ATTR_HOST_SEV_SNP); 3443 #endif 3444 } 3445 3446 static void amd_iommu_apply_erratum_snp(void) 3447 { 3448 #ifdef CONFIG_KVM_AMD_SEV 3449 if (!amd_iommu_snp_en) 3450 return; 3451 3452 /* Errata fix for Family 0x19 */ 3453 if (boot_cpu_data.x86 != 0x19) 3454 return; 3455 3456 /* Set event log buffer size to max */ 3457 amd_iommu_evtlog_size = EVTLOG_SIZE_MAX; 3458 pr_info("Applying erratum: Increase Event log size to 0x%x\n", 3459 amd_iommu_evtlog_size); 3460 3461 /* 3462 * Set PPR log buffer size to max. 3463 * (Family 0x19, model < 0x10 doesn't support PPR when SNP is enabled). 3464 */ 3465 if (boot_cpu_data.x86_model >= 0x10) { 3466 amd_iommu_pprlog_size = PPRLOG_SIZE_MAX; 3467 pr_info("Applying erratum: Increase PPR log size to 0x%x\n", 3468 amd_iommu_pprlog_size); 3469 } 3470 #endif 3471 } 3472 3473 /**************************************************************************** 3474 * 3475 * AMD IOMMU Initialization State Machine 3476 * 3477 ****************************************************************************/ 3478 3479 static int __init state_next(void) 3480 { 3481 int ret = 0; 3482 3483 switch (init_state) { 3484 case IOMMU_START_STATE: 3485 if (!detect_ivrs()) { 3486 init_state = IOMMU_NOT_FOUND; 3487 ret = -ENODEV; 3488 } else { 3489 init_state = IOMMU_IVRS_DETECTED; 3490 } 3491 break; 3492 case IOMMU_IVRS_DETECTED: 3493 if (amd_iommu_disabled) { 3494 init_state = IOMMU_CMDLINE_DISABLED; 3495 ret = -EINVAL; 3496 } else { 3497 ret = early_amd_iommu_init(); 3498 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_ACPI_FINISHED; 3499 } 3500 break; 3501 case IOMMU_ACPI_FINISHED: 3502 early_enable_iommus(); 3503 x86_platform.iommu_shutdown = disable_iommus; 3504 init_state = IOMMU_ENABLED; 3505 break; 3506 case IOMMU_ENABLED: 3507 register_syscore(&amd_iommu_syscore); 3508 iommu_snp_enable(); 3509 3510 amd_iommu_apply_erratum_snp(); 3511 3512 /* Allocate/enable event log buffer */ 3513 if (is_kdump_kernel()) 3514 ret = remap_event_buffer(); 3515 else 3516 ret = alloc_event_buffer(); 3517 3518 if (ret) { 3519 init_state = IOMMU_INIT_ERROR; 3520 break; 3521 } 3522 iommu_enable_event_buffer(); 3523 3524 ret = amd_iommu_init_pci(); 3525 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_PCI_INIT; 3526 break; 3527 case IOMMU_PCI_INIT: 3528 ret = amd_iommu_enable_interrupts(); 3529 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_INTERRUPTS_EN; 3530 break; 3531 case IOMMU_INTERRUPTS_EN: 3532 init_state = IOMMU_INITIALIZED; 3533 break; 3534 case IOMMU_INITIALIZED: 3535 /* Nothing to do */ 3536 break; 3537 case IOMMU_NOT_FOUND: 3538 case IOMMU_INIT_ERROR: 3539 case IOMMU_CMDLINE_DISABLED: 3540 /* Error states => do nothing */ 3541 ret = -EINVAL; 3542 break; 3543 default: 3544 /* Unknown state */ 3545 BUG(); 3546 } 3547 3548 if (ret) { 3549 free_dma_resources(); 3550 if (!irq_remapping_enabled) { 3551 disable_iommus(); 3552 free_iommu_resources(); 3553 } else { 3554 struct amd_iommu *iommu; 3555 struct amd_iommu_pci_seg *pci_seg; 3556 3557 for_each_pci_segment(pci_seg) 3558 uninit_device_table_dma(pci_seg); 3559 3560 for_each_iommu(iommu) 3561 amd_iommu_flush_all_caches(iommu); 3562 } 3563 } 3564 return ret; 3565 } 3566 3567 static int __init iommu_go_to_state(enum iommu_init_state state) 3568 { 3569 int ret = -EINVAL; 3570 3571 while (init_state != state) { 3572 if (init_state == IOMMU_NOT_FOUND || 3573 init_state == IOMMU_INIT_ERROR || 3574 init_state == IOMMU_CMDLINE_DISABLED) 3575 break; 3576 ret = state_next(); 3577 } 3578 3579 /* 3580 * SNP platform initilazation requires IOMMUs to be fully configured. 3581 * If the SNP support on IOMMUs has NOT been checked, simply mark SNP 3582 * as unsupported. If the SNP support on IOMMUs has been checked and 3583 * host SNP support enabled but RMP enforcement has not been enabled 3584 * in IOMMUs, then the system is in a half-baked state, but can limp 3585 * along as all memory should be Hypervisor-Owned in the RMP. WARN, 3586 * but leave SNP as "supported" to avoid confusing the kernel. 3587 */ 3588 if (ret && cc_platform_has(CC_ATTR_HOST_SEV_SNP) && 3589 !WARN_ON_ONCE(amd_iommu_snp_en)) 3590 cc_platform_clear(CC_ATTR_HOST_SEV_SNP); 3591 3592 return ret; 3593 } 3594 3595 #ifdef CONFIG_IRQ_REMAP 3596 int __init amd_iommu_prepare(void) 3597 { 3598 int ret; 3599 3600 amd_iommu_irq_remap = true; 3601 3602 ret = iommu_go_to_state(IOMMU_ACPI_FINISHED); 3603 if (ret) { 3604 amd_iommu_irq_remap = false; 3605 return ret; 3606 } 3607 3608 return amd_iommu_irq_remap ? 0 : -ENODEV; 3609 } 3610 3611 int __init amd_iommu_enable(void) 3612 { 3613 int ret; 3614 3615 ret = iommu_go_to_state(IOMMU_ENABLED); 3616 if (ret) 3617 return ret; 3618 3619 irq_remapping_enabled = 1; 3620 return amd_iommu_xt_mode; 3621 } 3622 3623 void amd_iommu_disable(void) 3624 { 3625 amd_iommu_suspend(NULL); 3626 } 3627 3628 int amd_iommu_reenable(int mode) 3629 { 3630 amd_iommu_resume(NULL); 3631 3632 return 0; 3633 } 3634 3635 int amd_iommu_enable_faulting(unsigned int cpu) 3636 { 3637 /* We enable MSI later when PCI is initialized */ 3638 return 0; 3639 } 3640 #endif 3641 3642 /* 3643 * This is the core init function for AMD IOMMU hardware in the system. 3644 * This function is called from the generic x86 DMA layer initialization 3645 * code. 3646 */ 3647 static int __init amd_iommu_init(void) 3648 { 3649 int ret; 3650 3651 ret = iommu_go_to_state(IOMMU_INITIALIZED); 3652 #ifdef CONFIG_GART_IOMMU 3653 if (ret && list_empty(&amd_iommu_list)) { 3654 /* 3655 * We failed to initialize the AMD IOMMU - try fallback 3656 * to GART if possible. 3657 */ 3658 gart_iommu_init(); 3659 } 3660 #endif 3661 3662 if (!ret) 3663 amd_iommu_debugfs_setup(); 3664 3665 return ret; 3666 } 3667 3668 static bool amd_iommu_sme_check(void) 3669 { 3670 if (!cc_platform_has(CC_ATTR_HOST_MEM_ENCRYPT) || 3671 (boot_cpu_data.x86 != 0x17)) 3672 return true; 3673 3674 /* For Fam17h, a specific level of support is required */ 3675 if (boot_cpu_data.microcode >= 0x08001205) 3676 return true; 3677 3678 if ((boot_cpu_data.microcode >= 0x08001126) && 3679 (boot_cpu_data.microcode <= 0x080011ff)) 3680 return true; 3681 3682 pr_notice("IOMMU not currently supported when SME is active\n"); 3683 3684 return false; 3685 } 3686 3687 /**************************************************************************** 3688 * 3689 * Early detect code. This code runs at IOMMU detection time in the DMA 3690 * layer. It just looks if there is an IVRS ACPI table to detect AMD 3691 * IOMMUs 3692 * 3693 ****************************************************************************/ 3694 void __init amd_iommu_detect(void) 3695 { 3696 int ret; 3697 3698 if (no_iommu || (iommu_detected && !gart_iommu_aperture)) 3699 goto disable_snp; 3700 3701 if (!amd_iommu_sme_check()) 3702 goto disable_snp; 3703 3704 ret = iommu_go_to_state(IOMMU_IVRS_DETECTED); 3705 if (ret) 3706 goto disable_snp; 3707 3708 amd_iommu_detected = true; 3709 iommu_detected = 1; 3710 x86_init.iommu.iommu_init = amd_iommu_init; 3711 return; 3712 3713 disable_snp: 3714 if (cc_platform_has(CC_ATTR_HOST_SEV_SNP)) 3715 cc_platform_clear(CC_ATTR_HOST_SEV_SNP); 3716 } 3717 3718 /**************************************************************************** 3719 * 3720 * Parsing functions for the AMD IOMMU specific kernel command line 3721 * options. 3722 * 3723 ****************************************************************************/ 3724 3725 static int __init parse_amd_iommu_dump(char *str) 3726 { 3727 amd_iommu_dump = true; 3728 3729 return 1; 3730 } 3731 3732 static int __init parse_amd_iommu_intr(char *str) 3733 { 3734 for (; *str; ++str) { 3735 if (strncmp(str, "legacy", 6) == 0) { 3736 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY_GA; 3737 break; 3738 } 3739 if (strncmp(str, "vapic", 5) == 0) { 3740 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC; 3741 break; 3742 } 3743 } 3744 return 1; 3745 } 3746 3747 static int __init parse_amd_iommu_options(char *str) 3748 { 3749 if (!str) 3750 return -EINVAL; 3751 3752 while (*str) { 3753 if (strncmp(str, "fullflush", 9) == 0) { 3754 pr_warn("amd_iommu=fullflush deprecated; use iommu.strict=1 instead\n"); 3755 iommu_set_dma_strict(); 3756 } else if (strncmp(str, "force_enable", 12) == 0) { 3757 amd_iommu_force_enable = true; 3758 } else if (strncmp(str, "off", 3) == 0) { 3759 amd_iommu_disabled = true; 3760 } else if (strncmp(str, "force_isolation", 15) == 0) { 3761 amd_iommu_force_isolation = true; 3762 } else if (strncmp(str, "pgtbl_v1", 8) == 0) { 3763 amd_iommu_pgtable = PD_MODE_V1; 3764 } else if (strncmp(str, "pgtbl_v2", 8) == 0) { 3765 amd_iommu_pgtable = PD_MODE_V2; 3766 } else if (strncmp(str, "irtcachedis", 11) == 0) { 3767 amd_iommu_irtcachedis = true; 3768 } else if (strncmp(str, "nohugepages", 11) == 0) { 3769 pr_info("Restricting V1 page-sizes to 4KiB"); 3770 amd_iommu_pgsize_bitmap = AMD_IOMMU_PGSIZES_4K; 3771 } else if (strncmp(str, "v2_pgsizes_only", 15) == 0) { 3772 pr_info("Restricting V1 page-sizes to 4KiB/2MiB/1GiB"); 3773 amd_iommu_pgsize_bitmap = AMD_IOMMU_PGSIZES_V2; 3774 } else { 3775 pr_notice("Unknown option - '%s'\n", str); 3776 } 3777 3778 str += strcspn(str, ","); 3779 while (*str == ',') 3780 str++; 3781 } 3782 3783 return 1; 3784 } 3785 3786 static int __init parse_ivrs_ioapic(char *str) 3787 { 3788 u32 seg = 0, bus, dev, fn; 3789 int id, i; 3790 u32 devid; 3791 3792 if (sscanf(str, "=%d@%x:%x.%x", &id, &bus, &dev, &fn) == 4 || 3793 sscanf(str, "=%d@%x:%x:%x.%x", &id, &seg, &bus, &dev, &fn) == 5) 3794 goto found; 3795 3796 if (sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn) == 4 || 3797 sscanf(str, "[%d]=%x:%x:%x.%x", &id, &seg, &bus, &dev, &fn) == 5) { 3798 pr_warn("ivrs_ioapic%s option format deprecated; use ivrs_ioapic=%d@%04x:%02x:%02x.%d instead\n", 3799 str, id, seg, bus, dev, fn); 3800 goto found; 3801 } 3802 3803 pr_err("Invalid command line: ivrs_ioapic%s\n", str); 3804 return 1; 3805 3806 found: 3807 if (early_ioapic_map_size == EARLY_MAP_SIZE) { 3808 pr_err("Early IOAPIC map overflow - ignoring ivrs_ioapic%s\n", 3809 str); 3810 return 1; 3811 } 3812 3813 devid = IVRS_GET_SBDF_ID(seg, bus, dev, fn); 3814 3815 cmdline_maps = true; 3816 i = early_ioapic_map_size++; 3817 early_ioapic_map[i].id = id; 3818 early_ioapic_map[i].devid = devid; 3819 early_ioapic_map[i].cmd_line = true; 3820 3821 return 1; 3822 } 3823 3824 static int __init parse_ivrs_hpet(char *str) 3825 { 3826 u32 seg = 0, bus, dev, fn; 3827 int id, i; 3828 u32 devid; 3829 3830 if (sscanf(str, "=%d@%x:%x.%x", &id, &bus, &dev, &fn) == 4 || 3831 sscanf(str, "=%d@%x:%x:%x.%x", &id, &seg, &bus, &dev, &fn) == 5) 3832 goto found; 3833 3834 if (sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn) == 4 || 3835 sscanf(str, "[%d]=%x:%x:%x.%x", &id, &seg, &bus, &dev, &fn) == 5) { 3836 pr_warn("ivrs_hpet%s option format deprecated; use ivrs_hpet=%d@%04x:%02x:%02x.%d instead\n", 3837 str, id, seg, bus, dev, fn); 3838 goto found; 3839 } 3840 3841 pr_err("Invalid command line: ivrs_hpet%s\n", str); 3842 return 1; 3843 3844 found: 3845 if (early_hpet_map_size == EARLY_MAP_SIZE) { 3846 pr_err("Early HPET map overflow - ignoring ivrs_hpet%s\n", 3847 str); 3848 return 1; 3849 } 3850 3851 devid = IVRS_GET_SBDF_ID(seg, bus, dev, fn); 3852 3853 cmdline_maps = true; 3854 i = early_hpet_map_size++; 3855 early_hpet_map[i].id = id; 3856 early_hpet_map[i].devid = devid; 3857 early_hpet_map[i].cmd_line = true; 3858 3859 return 1; 3860 } 3861 3862 #define ACPIID_LEN (ACPIHID_UID_LEN + ACPIHID_HID_LEN) 3863 3864 static int __init parse_ivrs_acpihid(char *str) 3865 { 3866 u32 seg = 0, bus, dev, fn; 3867 char *hid, *uid, *p, *addr; 3868 char acpiid[ACPIID_LEN + 1] = { }; /* size with NULL terminator */ 3869 int i; 3870 3871 addr = strchr(str, '@'); 3872 if (!addr) { 3873 addr = strchr(str, '='); 3874 if (!addr) 3875 goto not_found; 3876 3877 ++addr; 3878 3879 if (strlen(addr) > ACPIID_LEN) 3880 goto not_found; 3881 3882 if (sscanf(str, "[%x:%x.%x]=%s", &bus, &dev, &fn, acpiid) == 4 || 3883 sscanf(str, "[%x:%x:%x.%x]=%s", &seg, &bus, &dev, &fn, acpiid) == 5) { 3884 pr_warn("ivrs_acpihid%s option format deprecated; use ivrs_acpihid=%s@%04x:%02x:%02x.%d instead\n", 3885 str, acpiid, seg, bus, dev, fn); 3886 goto found; 3887 } 3888 goto not_found; 3889 } 3890 3891 /* We have the '@', make it the terminator to get just the acpiid */ 3892 *addr++ = 0; 3893 3894 if (strlen(str) > ACPIID_LEN) 3895 goto not_found; 3896 3897 if (sscanf(str, "=%s", acpiid) != 1) 3898 goto not_found; 3899 3900 if (sscanf(addr, "%x:%x.%x", &bus, &dev, &fn) == 3 || 3901 sscanf(addr, "%x:%x:%x.%x", &seg, &bus, &dev, &fn) == 4) 3902 goto found; 3903 3904 not_found: 3905 pr_err("Invalid command line: ivrs_acpihid%s\n", str); 3906 return 1; 3907 3908 found: 3909 if (early_acpihid_map_size == EARLY_MAP_SIZE) { 3910 pr_err("Early ACPI HID map overflow - ignoring ivrs_acpihid%s\n", 3911 str); 3912 return 1; 3913 } 3914 3915 p = acpiid; 3916 hid = strsep(&p, ":"); 3917 uid = p; 3918 3919 if (!hid || !(*hid) || !uid) { 3920 pr_err("Invalid command line: hid or uid\n"); 3921 return 1; 3922 } 3923 3924 /* 3925 * Ignore leading zeroes after ':', so e.g., AMDI0095:00 3926 * will match AMDI0095:0 in the second strcmp in acpi_dev_hid_uid_match 3927 */ 3928 while (*uid == '0' && *(uid + 1)) 3929 uid++; 3930 3931 if (strlen(hid) >= ACPIHID_HID_LEN) { 3932 pr_err("Invalid command line: hid is too long\n"); 3933 return 1; 3934 } else if (strlen(uid) >= ACPIHID_UID_LEN) { 3935 pr_err("Invalid command line: uid is too long\n"); 3936 return 1; 3937 } 3938 3939 i = early_acpihid_map_size++; 3940 memcpy(early_acpihid_map[i].hid, hid, strlen(hid)); 3941 memcpy(early_acpihid_map[i].uid, uid, strlen(uid)); 3942 early_acpihid_map[i].devid = IVRS_GET_SBDF_ID(seg, bus, dev, fn); 3943 early_acpihid_map[i].cmd_line = true; 3944 3945 return 1; 3946 } 3947 3948 __setup("amd_iommu_dump", parse_amd_iommu_dump); 3949 __setup("amd_iommu=", parse_amd_iommu_options); 3950 __setup("amd_iommu_intr=", parse_amd_iommu_intr); 3951 __setup("ivrs_ioapic", parse_ivrs_ioapic); 3952 __setup("ivrs_hpet", parse_ivrs_hpet); 3953 __setup("ivrs_acpihid", parse_ivrs_acpihid); 3954 3955 bool amd_iommu_pasid_supported(void) 3956 { 3957 /* CPU page table size should match IOMMU guest page table size */ 3958 if (cpu_feature_enabled(X86_FEATURE_LA57) && 3959 amd_iommu_gpt_level != PAGE_MODE_5_LEVEL) 3960 return false; 3961 3962 if (!amd_iommu_gt_ppr_supported()) 3963 return false; 3964 3965 /* 3966 * If SNP page mode 0 is not supported, then DTE[Mode]=0 is prohibited 3967 * on SNP-enabled system (i.e. EFR[SNPSup]=1). IOMMUv2 page table 3968 * cannot be used without setting up IOMMUv1 page table. 3969 */ 3970 return (!amd_iommu_snp_en) || (amd_iommu_snp_en && amd_iommu_snp_mode0_sup); 3971 } 3972 3973 struct amd_iommu *get_amd_iommu(unsigned int idx) 3974 { 3975 unsigned int i = 0; 3976 struct amd_iommu *iommu; 3977 3978 for_each_iommu(iommu) 3979 if (i++ == idx) 3980 return iommu; 3981 return NULL; 3982 } 3983 3984 /**************************************************************************** 3985 * 3986 * IOMMU EFR Performance Counter support functionality. This code allows 3987 * access to the IOMMU PC functionality. 3988 * 3989 ****************************************************************************/ 3990 3991 u8 amd_iommu_pc_get_max_banks(unsigned int idx) 3992 { 3993 struct amd_iommu *iommu = get_amd_iommu(idx); 3994 3995 if (iommu) 3996 return iommu->max_banks; 3997 3998 return 0; 3999 } 4000 4001 bool amd_iommu_pc_supported(void) 4002 { 4003 return amd_iommu_pc_present; 4004 } 4005 4006 u8 amd_iommu_pc_get_max_counters(unsigned int idx) 4007 { 4008 struct amd_iommu *iommu = get_amd_iommu(idx); 4009 4010 if (iommu) 4011 return iommu->max_counters; 4012 4013 return 0; 4014 } 4015 4016 static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, 4017 u8 fxn, u64 *value, bool is_write) 4018 { 4019 u32 offset; 4020 u32 max_offset_lim; 4021 4022 /* Make sure the IOMMU PC resource is available */ 4023 if (!amd_iommu_pc_present) 4024 return -ENODEV; 4025 4026 /* Check for valid iommu and pc register indexing */ 4027 if (WARN_ON(!iommu || (fxn > 0x28) || (fxn & 7))) 4028 return -ENODEV; 4029 4030 offset = (u32)(((0x40 | bank) << 12) | (cntr << 8) | fxn); 4031 4032 /* Limit the offset to the hw defined mmio region aperture */ 4033 max_offset_lim = (u32)(((0x40 | iommu->max_banks) << 12) | 4034 (iommu->max_counters << 8) | 0x28); 4035 if ((offset < MMIO_CNTR_REG_OFFSET) || 4036 (offset > max_offset_lim)) 4037 return -EINVAL; 4038 4039 if (is_write) { 4040 u64 val = *value & GENMASK_ULL(47, 0); 4041 4042 writel((u32)val, iommu->mmio_base + offset); 4043 writel((val >> 32), iommu->mmio_base + offset + 4); 4044 } else { 4045 *value = readl(iommu->mmio_base + offset + 4); 4046 *value <<= 32; 4047 *value |= readl(iommu->mmio_base + offset); 4048 *value &= GENMASK_ULL(47, 0); 4049 } 4050 4051 return 0; 4052 } 4053 4054 int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value) 4055 { 4056 if (!iommu) 4057 return -EINVAL; 4058 4059 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, false); 4060 } 4061 4062 int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value) 4063 { 4064 if (!iommu) 4065 return -EINVAL; 4066 4067 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, true); 4068 } 4069 4070 #ifdef CONFIG_KVM_AMD_SEV 4071 static int iommu_page_make_shared(void *page) 4072 { 4073 unsigned long paddr, pfn; 4074 4075 paddr = iommu_virt_to_phys(page); 4076 /* Cbit maybe set in the paddr */ 4077 pfn = __sme_clr(paddr) >> PAGE_SHIFT; 4078 4079 if (!(pfn % PTRS_PER_PMD)) { 4080 int ret, level; 4081 bool assigned; 4082 4083 ret = snp_lookup_rmpentry(pfn, &assigned, &level); 4084 if (ret) { 4085 pr_warn("IOMMU PFN %lx RMP lookup failed, ret %d\n", pfn, ret); 4086 return ret; 4087 } 4088 4089 if (!assigned) { 4090 pr_warn("IOMMU PFN %lx not assigned in RMP table\n", pfn); 4091 return -EINVAL; 4092 } 4093 4094 if (level > PG_LEVEL_4K) { 4095 ret = psmash(pfn); 4096 if (!ret) 4097 goto done; 4098 4099 pr_warn("PSMASH failed for IOMMU PFN %lx huge RMP entry, ret: %d, level: %d\n", 4100 pfn, ret, level); 4101 return ret; 4102 } 4103 } 4104 4105 done: 4106 return rmp_make_shared(pfn, PG_LEVEL_4K); 4107 } 4108 4109 static int iommu_make_shared(void *va, size_t size) 4110 { 4111 void *page; 4112 int ret; 4113 4114 if (!va) 4115 return 0; 4116 4117 for (page = va; page < (va + size); page += PAGE_SIZE) { 4118 ret = iommu_page_make_shared(page); 4119 if (ret) 4120 return ret; 4121 } 4122 4123 return 0; 4124 } 4125 4126 int amd_iommu_snp_disable(void) 4127 { 4128 struct amd_iommu *iommu; 4129 int ret; 4130 4131 if (!amd_iommu_snp_en) 4132 return 0; 4133 4134 for_each_iommu(iommu) { 4135 ret = iommu_make_shared(iommu->evt_buf, amd_iommu_evtlog_size); 4136 if (ret) 4137 return ret; 4138 4139 ret = iommu_make_shared(iommu->ppr_log, amd_iommu_pprlog_size); 4140 if (ret) 4141 return ret; 4142 4143 ret = iommu_make_shared((void *)iommu->cmd_sem, PAGE_SIZE); 4144 if (ret) 4145 return ret; 4146 } 4147 4148 return 0; 4149 } 4150 EXPORT_SYMBOL_GPL(amd_iommu_snp_disable); 4151 4152 bool amd_iommu_sev_tio_supported(void) 4153 { 4154 return check_feature2(FEATURE_SEVSNPIO_SUP); 4155 } 4156 EXPORT_SYMBOL_GPL(amd_iommu_sev_tio_supported); 4157 #endif 4158