1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. 4 * Author: Joerg Roedel <jroedel@suse.de> 5 * Leo Duran <leo.duran@amd.com> 6 */ 7 8 #define pr_fmt(fmt) "AMD-Vi: " fmt 9 #define dev_fmt(fmt) pr_fmt(fmt) 10 11 #include <linux/pci.h> 12 #include <linux/acpi.h> 13 #include <linux/list.h> 14 #include <linux/bitmap.h> 15 #include <linux/syscore_ops.h> 16 #include <linux/interrupt.h> 17 #include <linux/msi.h> 18 #include <linux/irq.h> 19 #include <linux/amd-iommu.h> 20 #include <linux/export.h> 21 #include <linux/kmemleak.h> 22 #include <linux/cc_platform.h> 23 #include <linux/iopoll.h> 24 #include <asm/pci-direct.h> 25 #include <asm/iommu.h> 26 #include <asm/apic.h> 27 #include <asm/gart.h> 28 #include <asm/x86_init.h> 29 #include <asm/io_apic.h> 30 #include <asm/irq_remapping.h> 31 #include <asm/set_memory.h> 32 #include <asm/sev.h> 33 34 #include <linux/crash_dump.h> 35 36 #include "amd_iommu.h" 37 #include "../irq_remapping.h" 38 #include "../iommu-pages.h" 39 40 /* 41 * definitions for the ACPI scanning code 42 */ 43 #define IVRS_HEADER_LENGTH 48 44 45 #define ACPI_IVHD_TYPE_MAX_SUPPORTED 0x40 46 #define ACPI_IVMD_TYPE_ALL 0x20 47 #define ACPI_IVMD_TYPE 0x21 48 #define ACPI_IVMD_TYPE_RANGE 0x22 49 50 #define IVHD_DEV_ALL 0x01 51 #define IVHD_DEV_SELECT 0x02 52 #define IVHD_DEV_SELECT_RANGE_START 0x03 53 #define IVHD_DEV_RANGE_END 0x04 54 #define IVHD_DEV_ALIAS 0x42 55 #define IVHD_DEV_ALIAS_RANGE 0x43 56 #define IVHD_DEV_EXT_SELECT 0x46 57 #define IVHD_DEV_EXT_SELECT_RANGE 0x47 58 #define IVHD_DEV_SPECIAL 0x48 59 #define IVHD_DEV_ACPI_HID 0xf0 60 61 #define UID_NOT_PRESENT 0 62 #define UID_IS_INTEGER 1 63 #define UID_IS_CHARACTER 2 64 65 #define IVHD_SPECIAL_IOAPIC 1 66 #define IVHD_SPECIAL_HPET 2 67 68 #define IVHD_FLAG_HT_TUN_EN_MASK 0x01 69 #define IVHD_FLAG_PASSPW_EN_MASK 0x02 70 #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04 71 #define IVHD_FLAG_ISOC_EN_MASK 0x08 72 73 #define IVMD_FLAG_EXCL_RANGE 0x08 74 #define IVMD_FLAG_IW 0x04 75 #define IVMD_FLAG_IR 0x02 76 #define IVMD_FLAG_UNITY_MAP 0x01 77 78 #define ACPI_DEVFLAG_INITPASS 0x01 79 #define ACPI_DEVFLAG_EXTINT 0x02 80 #define ACPI_DEVFLAG_NMI 0x04 81 #define ACPI_DEVFLAG_SYSMGT1 0x10 82 #define ACPI_DEVFLAG_SYSMGT2 0x20 83 #define ACPI_DEVFLAG_LINT0 0x40 84 #define ACPI_DEVFLAG_LINT1 0x80 85 #define ACPI_DEVFLAG_ATSDIS 0x10000000 86 87 #define IVRS_GET_SBDF_ID(seg, bus, dev, fn) (((seg & 0xffff) << 16) | ((bus & 0xff) << 8) \ 88 | ((dev & 0x1f) << 3) | (fn & 0x7)) 89 90 /* 91 * ACPI table definitions 92 * 93 * These data structures are laid over the table to parse the important values 94 * out of it. 95 */ 96 97 /* 98 * structure describing one IOMMU in the ACPI table. Typically followed by one 99 * or more ivhd_entrys. 100 */ 101 struct ivhd_header { 102 u8 type; 103 u8 flags; 104 u16 length; 105 u16 devid; 106 u16 cap_ptr; 107 u64 mmio_phys; 108 u16 pci_seg; 109 u16 info; 110 u32 efr_attr; 111 112 /* Following only valid on IVHD type 11h and 40h */ 113 u64 efr_reg; /* Exact copy of MMIO_EXT_FEATURES */ 114 u64 efr_reg2; 115 } __attribute__((packed)); 116 117 /* 118 * A device entry describing which devices a specific IOMMU translates and 119 * which requestor ids they use. 120 */ 121 struct ivhd_entry { 122 u8 type; 123 u16 devid; 124 u8 flags; 125 struct_group(ext_hid, 126 u32 ext; 127 u32 hidh; 128 ); 129 u64 cid; 130 u8 uidf; 131 u8 uidl; 132 u8 uid; 133 } __attribute__((packed)); 134 135 /* 136 * An AMD IOMMU memory definition structure. It defines things like exclusion 137 * ranges for devices and regions that should be unity mapped. 138 */ 139 struct ivmd_header { 140 u8 type; 141 u8 flags; 142 u16 length; 143 u16 devid; 144 u16 aux; 145 u16 pci_seg; 146 u8 resv[6]; 147 u64 range_start; 148 u64 range_length; 149 } __attribute__((packed)); 150 151 bool amd_iommu_dump; 152 bool amd_iommu_irq_remap __read_mostly; 153 154 enum protection_domain_mode amd_iommu_pgtable = PD_MODE_V1; 155 /* Host page table level */ 156 u8 amd_iommu_hpt_level; 157 /* Guest page table level */ 158 int amd_iommu_gpt_level = PAGE_MODE_4_LEVEL; 159 160 int amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC; 161 static int amd_iommu_xt_mode = IRQ_REMAP_XAPIC_MODE; 162 163 static bool amd_iommu_detected; 164 static bool amd_iommu_disabled __initdata; 165 static bool amd_iommu_force_enable __initdata; 166 static bool amd_iommu_irtcachedis; 167 static int amd_iommu_target_ivhd_type; 168 169 /* Global EFR and EFR2 registers */ 170 u64 amd_iommu_efr; 171 u64 amd_iommu_efr2; 172 173 /* Host (v1) page table is not supported*/ 174 bool amd_iommu_hatdis; 175 176 /* SNP is enabled on the system? */ 177 bool amd_iommu_snp_en; 178 EXPORT_SYMBOL(amd_iommu_snp_en); 179 180 LIST_HEAD(amd_iommu_pci_seg_list); /* list of all PCI segments */ 181 LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the system */ 182 LIST_HEAD(amd_ivhd_dev_flags_list); /* list of all IVHD device entry settings */ 183 184 /* Number of IOMMUs present in the system */ 185 static int amd_iommus_present; 186 187 /* IOMMUs have a non-present cache? */ 188 bool amd_iommu_np_cache __read_mostly; 189 bool amd_iommu_iotlb_sup __read_mostly = true; 190 191 static bool amd_iommu_pc_present __read_mostly; 192 bool amdr_ivrs_remap_support __read_mostly; 193 194 bool amd_iommu_force_isolation __read_mostly; 195 196 unsigned long amd_iommu_pgsize_bitmap __ro_after_init = AMD_IOMMU_PGSIZES; 197 198 enum iommu_init_state { 199 IOMMU_START_STATE, 200 IOMMU_IVRS_DETECTED, 201 IOMMU_ACPI_FINISHED, 202 IOMMU_ENABLED, 203 IOMMU_PCI_INIT, 204 IOMMU_INTERRUPTS_EN, 205 IOMMU_INITIALIZED, 206 IOMMU_NOT_FOUND, 207 IOMMU_INIT_ERROR, 208 IOMMU_CMDLINE_DISABLED, 209 }; 210 211 /* Early ioapic and hpet maps from kernel command line */ 212 #define EARLY_MAP_SIZE 4 213 static struct devid_map __initdata early_ioapic_map[EARLY_MAP_SIZE]; 214 static struct devid_map __initdata early_hpet_map[EARLY_MAP_SIZE]; 215 static struct acpihid_map_entry __initdata early_acpihid_map[EARLY_MAP_SIZE]; 216 217 static int __initdata early_ioapic_map_size; 218 static int __initdata early_hpet_map_size; 219 static int __initdata early_acpihid_map_size; 220 221 static bool __initdata cmdline_maps; 222 223 static enum iommu_init_state init_state = IOMMU_START_STATE; 224 225 static int amd_iommu_enable_interrupts(void); 226 static void init_device_table_dma(struct amd_iommu_pci_seg *pci_seg); 227 228 static bool amd_iommu_pre_enabled = true; 229 230 static u32 amd_iommu_ivinfo __initdata; 231 232 bool translation_pre_enabled(struct amd_iommu *iommu) 233 { 234 return (iommu->flags & AMD_IOMMU_FLAG_TRANS_PRE_ENABLED); 235 } 236 237 static void clear_translation_pre_enabled(struct amd_iommu *iommu) 238 { 239 iommu->flags &= ~AMD_IOMMU_FLAG_TRANS_PRE_ENABLED; 240 } 241 242 static void init_translation_status(struct amd_iommu *iommu) 243 { 244 u64 ctrl; 245 246 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); 247 if (ctrl & (1<<CONTROL_IOMMU_EN)) 248 iommu->flags |= AMD_IOMMU_FLAG_TRANS_PRE_ENABLED; 249 } 250 251 int amd_iommu_get_num_iommus(void) 252 { 253 return amd_iommus_present; 254 } 255 256 bool amd_iommu_ht_range_ignore(void) 257 { 258 return check_feature2(FEATURE_HT_RANGE_IGNORE); 259 } 260 261 /* 262 * Iterate through all the IOMMUs to get common EFR 263 * masks among all IOMMUs and warn if found inconsistency. 264 */ 265 static __init void get_global_efr(void) 266 { 267 struct amd_iommu *iommu; 268 269 for_each_iommu(iommu) { 270 u64 tmp = iommu->features; 271 u64 tmp2 = iommu->features2; 272 273 if (list_is_first(&iommu->list, &amd_iommu_list)) { 274 amd_iommu_efr = tmp; 275 amd_iommu_efr2 = tmp2; 276 continue; 277 } 278 279 if (amd_iommu_efr == tmp && 280 amd_iommu_efr2 == tmp2) 281 continue; 282 283 pr_err(FW_BUG 284 "Found inconsistent EFR/EFR2 %#llx,%#llx (global %#llx,%#llx) on iommu%d (%04x:%02x:%02x.%01x).\n", 285 tmp, tmp2, amd_iommu_efr, amd_iommu_efr2, 286 iommu->index, iommu->pci_seg->id, 287 PCI_BUS_NUM(iommu->devid), PCI_SLOT(iommu->devid), 288 PCI_FUNC(iommu->devid)); 289 290 amd_iommu_efr &= tmp; 291 amd_iommu_efr2 &= tmp2; 292 } 293 294 pr_info("Using global IVHD EFR:%#llx, EFR2:%#llx\n", amd_iommu_efr, amd_iommu_efr2); 295 } 296 297 /* 298 * For IVHD type 0x11/0x40, EFR is also available via IVHD. 299 * Default to IVHD EFR since it is available sooner 300 * (i.e. before PCI init). 301 */ 302 static void __init early_iommu_features_init(struct amd_iommu *iommu, 303 struct ivhd_header *h) 304 { 305 if (amd_iommu_ivinfo & IOMMU_IVINFO_EFRSUP) { 306 iommu->features = h->efr_reg; 307 iommu->features2 = h->efr_reg2; 308 } 309 if (amd_iommu_ivinfo & IOMMU_IVINFO_DMA_REMAP) 310 amdr_ivrs_remap_support = true; 311 } 312 313 /* Access to l1 and l2 indexed register spaces */ 314 315 static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address) 316 { 317 u32 val; 318 319 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16)); 320 pci_read_config_dword(iommu->dev, 0xfc, &val); 321 return val; 322 } 323 324 static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val) 325 { 326 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31)); 327 pci_write_config_dword(iommu->dev, 0xfc, val); 328 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16)); 329 } 330 331 static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address) 332 { 333 u32 val; 334 335 pci_write_config_dword(iommu->dev, 0xf0, address); 336 pci_read_config_dword(iommu->dev, 0xf4, &val); 337 return val; 338 } 339 340 static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val) 341 { 342 pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8)); 343 pci_write_config_dword(iommu->dev, 0xf4, val); 344 } 345 346 /**************************************************************************** 347 * 348 * AMD IOMMU MMIO register space handling functions 349 * 350 * These functions are used to program the IOMMU device registers in 351 * MMIO space required for that driver. 352 * 353 ****************************************************************************/ 354 355 /* 356 * This function set the exclusion range in the IOMMU. DMA accesses to the 357 * exclusion range are passed through untranslated 358 */ 359 static void iommu_set_exclusion_range(struct amd_iommu *iommu) 360 { 361 u64 start = iommu->exclusion_start & PAGE_MASK; 362 u64 limit = (start + iommu->exclusion_length - 1) & PAGE_MASK; 363 u64 entry; 364 365 if (!iommu->exclusion_start) 366 return; 367 368 entry = start | MMIO_EXCL_ENABLE_MASK; 369 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, 370 &entry, sizeof(entry)); 371 372 entry = limit; 373 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, 374 &entry, sizeof(entry)); 375 } 376 377 static void iommu_set_cwwb_range(struct amd_iommu *iommu) 378 { 379 u64 start = iommu_virt_to_phys((void *)iommu->cmd_sem); 380 u64 entry = start & PM_ADDR_MASK; 381 382 if (!check_feature(FEATURE_SNP)) 383 return; 384 385 /* Note: 386 * Re-purpose Exclusion base/limit registers for Completion wait 387 * write-back base/limit. 388 */ 389 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, 390 &entry, sizeof(entry)); 391 392 /* Note: 393 * Default to 4 Kbytes, which can be specified by setting base 394 * address equal to the limit address. 395 */ 396 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, 397 &entry, sizeof(entry)); 398 } 399 400 /* Programs the physical address of the device table into the IOMMU hardware */ 401 static void iommu_set_device_table(struct amd_iommu *iommu) 402 { 403 u64 entry; 404 u32 dev_table_size = iommu->pci_seg->dev_table_size; 405 void *dev_table = (void *)get_dev_table(iommu); 406 407 BUG_ON(iommu->mmio_base == NULL); 408 409 entry = iommu_virt_to_phys(dev_table); 410 entry |= (dev_table_size >> 12) - 1; 411 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET, 412 &entry, sizeof(entry)); 413 } 414 415 static void iommu_feature_set(struct amd_iommu *iommu, u64 val, u64 mask, u8 shift) 416 { 417 u64 ctrl; 418 419 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); 420 mask <<= shift; 421 ctrl &= ~mask; 422 ctrl |= (val << shift) & mask; 423 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); 424 } 425 426 /* Generic functions to enable/disable certain features of the IOMMU. */ 427 void iommu_feature_enable(struct amd_iommu *iommu, u8 bit) 428 { 429 iommu_feature_set(iommu, 1ULL, 1ULL, bit); 430 } 431 432 static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit) 433 { 434 iommu_feature_set(iommu, 0ULL, 1ULL, bit); 435 } 436 437 /* Function to enable the hardware */ 438 static void iommu_enable(struct amd_iommu *iommu) 439 { 440 iommu_feature_enable(iommu, CONTROL_IOMMU_EN); 441 } 442 443 static void iommu_disable(struct amd_iommu *iommu) 444 { 445 if (!iommu->mmio_base) 446 return; 447 448 /* Disable command buffer */ 449 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); 450 451 /* Disable event logging and event interrupts */ 452 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN); 453 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN); 454 455 /* Disable IOMMU GA_LOG */ 456 iommu_feature_disable(iommu, CONTROL_GALOG_EN); 457 iommu_feature_disable(iommu, CONTROL_GAINT_EN); 458 459 /* Disable IOMMU PPR logging */ 460 iommu_feature_disable(iommu, CONTROL_PPRLOG_EN); 461 iommu_feature_disable(iommu, CONTROL_PPRINT_EN); 462 463 /* Disable IOMMU hardware itself */ 464 iommu_feature_disable(iommu, CONTROL_IOMMU_EN); 465 466 /* Clear IRTE cache disabling bit */ 467 iommu_feature_disable(iommu, CONTROL_IRTCACHEDIS); 468 } 469 470 /* 471 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in 472 * the system has one. 473 */ 474 static u8 __iomem * __init iommu_map_mmio_space(u64 address, u64 end) 475 { 476 if (!request_mem_region(address, end, "amd_iommu")) { 477 pr_err("Can not reserve memory region %llx-%llx for mmio\n", 478 address, end); 479 pr_err("This is a BIOS bug. Please contact your hardware vendor\n"); 480 return NULL; 481 } 482 483 return (u8 __iomem *)ioremap(address, end); 484 } 485 486 static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu) 487 { 488 if (iommu->mmio_base) 489 iounmap(iommu->mmio_base); 490 release_mem_region(iommu->mmio_phys, iommu->mmio_phys_end); 491 } 492 493 static inline u32 get_ivhd_header_size(struct ivhd_header *h) 494 { 495 u32 size = 0; 496 497 switch (h->type) { 498 case 0x10: 499 size = 24; 500 break; 501 case 0x11: 502 case 0x40: 503 size = 40; 504 break; 505 } 506 return size; 507 } 508 509 /**************************************************************************** 510 * 511 * The functions below belong to the first pass of AMD IOMMU ACPI table 512 * parsing. In this pass we try to find out the highest device id this 513 * code has to handle. Upon this information the size of the shared data 514 * structures is determined later. 515 * 516 ****************************************************************************/ 517 518 /* 519 * This function calculates the length of a given IVHD entry 520 */ 521 static inline int ivhd_entry_length(u8 *ivhd) 522 { 523 u32 type = ((struct ivhd_entry *)ivhd)->type; 524 525 if (type < 0x80) { 526 return 0x04 << (*ivhd >> 6); 527 } else if (type == IVHD_DEV_ACPI_HID) { 528 /* For ACPI_HID, offset 21 is uid len */ 529 return *((u8 *)ivhd + 21) + 22; 530 } 531 return 0; 532 } 533 534 /* 535 * After reading the highest device id from the IOMMU PCI capability header 536 * this function looks if there is a higher device id defined in the ACPI table 537 */ 538 static int __init find_last_devid_from_ivhd(struct ivhd_header *h) 539 { 540 u8 *p = (void *)h, *end = (void *)h; 541 struct ivhd_entry *dev; 542 int last_devid = -EINVAL; 543 544 u32 ivhd_size = get_ivhd_header_size(h); 545 546 if (!ivhd_size) { 547 pr_err("Unsupported IVHD type %#x\n", h->type); 548 return -EINVAL; 549 } 550 551 p += ivhd_size; 552 end += h->length; 553 554 while (p < end) { 555 dev = (struct ivhd_entry *)p; 556 switch (dev->type) { 557 case IVHD_DEV_ALL: 558 /* Use maximum BDF value for DEV_ALL */ 559 return 0xffff; 560 case IVHD_DEV_SELECT: 561 case IVHD_DEV_RANGE_END: 562 case IVHD_DEV_ALIAS: 563 case IVHD_DEV_EXT_SELECT: 564 /* all the above subfield types refer to device ids */ 565 if (dev->devid > last_devid) 566 last_devid = dev->devid; 567 break; 568 default: 569 break; 570 } 571 p += ivhd_entry_length(p); 572 } 573 574 WARN_ON(p != end); 575 576 return last_devid; 577 } 578 579 static int __init check_ivrs_checksum(struct acpi_table_header *table) 580 { 581 int i; 582 u8 checksum = 0, *p = (u8 *)table; 583 584 for (i = 0; i < table->length; ++i) 585 checksum += p[i]; 586 if (checksum != 0) { 587 /* ACPI table corrupt */ 588 pr_err(FW_BUG "IVRS invalid checksum\n"); 589 return -ENODEV; 590 } 591 592 return 0; 593 } 594 595 /* 596 * Iterate over all IVHD entries in the ACPI table and find the highest device 597 * id which we need to handle. This is the first of three functions which parse 598 * the ACPI table. So we check the checksum here. 599 */ 600 static int __init find_last_devid_acpi(struct acpi_table_header *table, u16 pci_seg) 601 { 602 u8 *p = (u8 *)table, *end = (u8 *)table; 603 struct ivhd_header *h; 604 int last_devid, last_bdf = 0; 605 606 p += IVRS_HEADER_LENGTH; 607 608 end += table->length; 609 while (p < end) { 610 h = (struct ivhd_header *)p; 611 if (h->pci_seg == pci_seg && 612 h->type == amd_iommu_target_ivhd_type) { 613 last_devid = find_last_devid_from_ivhd(h); 614 615 if (last_devid < 0) 616 return -EINVAL; 617 if (last_devid > last_bdf) 618 last_bdf = last_devid; 619 } 620 p += h->length; 621 } 622 WARN_ON(p != end); 623 624 return last_bdf; 625 } 626 627 /**************************************************************************** 628 * 629 * The following functions belong to the code path which parses the ACPI table 630 * the second time. In this ACPI parsing iteration we allocate IOMMU specific 631 * data structures, initialize the per PCI segment device/alias/rlookup table 632 * and also basically initialize the hardware. 633 * 634 ****************************************************************************/ 635 636 /* Allocate per PCI segment device table */ 637 static inline int __init alloc_dev_table(struct amd_iommu_pci_seg *pci_seg) 638 { 639 pci_seg->dev_table = iommu_alloc_pages_sz(GFP_KERNEL | GFP_DMA32, 640 pci_seg->dev_table_size); 641 if (!pci_seg->dev_table) 642 return -ENOMEM; 643 644 return 0; 645 } 646 647 static inline void free_dev_table(struct amd_iommu_pci_seg *pci_seg) 648 { 649 iommu_free_pages(pci_seg->dev_table); 650 pci_seg->dev_table = NULL; 651 } 652 653 /* Allocate per PCI segment IOMMU rlookup table. */ 654 static inline int __init alloc_rlookup_table(struct amd_iommu_pci_seg *pci_seg) 655 { 656 pci_seg->rlookup_table = kvcalloc(pci_seg->last_bdf + 1, 657 sizeof(*pci_seg->rlookup_table), 658 GFP_KERNEL); 659 if (pci_seg->rlookup_table == NULL) 660 return -ENOMEM; 661 662 return 0; 663 } 664 665 static inline void free_rlookup_table(struct amd_iommu_pci_seg *pci_seg) 666 { 667 kvfree(pci_seg->rlookup_table); 668 pci_seg->rlookup_table = NULL; 669 } 670 671 static inline int __init alloc_irq_lookup_table(struct amd_iommu_pci_seg *pci_seg) 672 { 673 pci_seg->irq_lookup_table = kvcalloc(pci_seg->last_bdf + 1, 674 sizeof(*pci_seg->irq_lookup_table), 675 GFP_KERNEL); 676 if (pci_seg->irq_lookup_table == NULL) 677 return -ENOMEM; 678 679 return 0; 680 } 681 682 static inline void free_irq_lookup_table(struct amd_iommu_pci_seg *pci_seg) 683 { 684 kvfree(pci_seg->irq_lookup_table); 685 pci_seg->irq_lookup_table = NULL; 686 } 687 688 static int __init alloc_alias_table(struct amd_iommu_pci_seg *pci_seg) 689 { 690 int i; 691 692 pci_seg->alias_table = kvmalloc_array(pci_seg->last_bdf + 1, 693 sizeof(*pci_seg->alias_table), 694 GFP_KERNEL); 695 if (!pci_seg->alias_table) 696 return -ENOMEM; 697 698 /* 699 * let all alias entries point to itself 700 */ 701 for (i = 0; i <= pci_seg->last_bdf; ++i) 702 pci_seg->alias_table[i] = i; 703 704 return 0; 705 } 706 707 static void __init free_alias_table(struct amd_iommu_pci_seg *pci_seg) 708 { 709 kvfree(pci_seg->alias_table); 710 pci_seg->alias_table = NULL; 711 } 712 713 /* 714 * Allocates the command buffer. This buffer is per AMD IOMMU. We can 715 * write commands to that buffer later and the IOMMU will execute them 716 * asynchronously 717 */ 718 static int __init alloc_command_buffer(struct amd_iommu *iommu) 719 { 720 iommu->cmd_buf = iommu_alloc_pages_sz(GFP_KERNEL, CMD_BUFFER_SIZE); 721 722 return iommu->cmd_buf ? 0 : -ENOMEM; 723 } 724 725 /* 726 * Interrupt handler has processed all pending events and adjusted head 727 * and tail pointer. Reset overflow mask and restart logging again. 728 */ 729 void amd_iommu_restart_log(struct amd_iommu *iommu, const char *evt_type, 730 u8 cntrl_intr, u8 cntrl_log, 731 u32 status_run_mask, u32 status_overflow_mask) 732 { 733 u32 status; 734 735 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); 736 if (status & status_run_mask) 737 return; 738 739 pr_info_ratelimited("IOMMU %s log restarting\n", evt_type); 740 741 iommu_feature_disable(iommu, cntrl_log); 742 iommu_feature_disable(iommu, cntrl_intr); 743 744 writel(status_overflow_mask, iommu->mmio_base + MMIO_STATUS_OFFSET); 745 746 iommu_feature_enable(iommu, cntrl_intr); 747 iommu_feature_enable(iommu, cntrl_log); 748 } 749 750 /* 751 * This function restarts event logging in case the IOMMU experienced 752 * an event log buffer overflow. 753 */ 754 void amd_iommu_restart_event_logging(struct amd_iommu *iommu) 755 { 756 amd_iommu_restart_log(iommu, "Event", CONTROL_EVT_INT_EN, 757 CONTROL_EVT_LOG_EN, MMIO_STATUS_EVT_RUN_MASK, 758 MMIO_STATUS_EVT_OVERFLOW_MASK); 759 } 760 761 /* 762 * This function restarts event logging in case the IOMMU experienced 763 * GA log overflow. 764 */ 765 void amd_iommu_restart_ga_log(struct amd_iommu *iommu) 766 { 767 amd_iommu_restart_log(iommu, "GA", CONTROL_GAINT_EN, 768 CONTROL_GALOG_EN, MMIO_STATUS_GALOG_RUN_MASK, 769 MMIO_STATUS_GALOG_OVERFLOW_MASK); 770 } 771 772 /* 773 * This function resets the command buffer if the IOMMU stopped fetching 774 * commands from it. 775 */ 776 static void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu) 777 { 778 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); 779 780 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); 781 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); 782 iommu->cmd_buf_head = 0; 783 iommu->cmd_buf_tail = 0; 784 785 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN); 786 } 787 788 /* 789 * This function writes the command buffer address to the hardware and 790 * enables it. 791 */ 792 static void iommu_enable_command_buffer(struct amd_iommu *iommu) 793 { 794 u64 entry; 795 796 BUG_ON(iommu->cmd_buf == NULL); 797 798 entry = iommu_virt_to_phys(iommu->cmd_buf); 799 entry |= MMIO_CMD_SIZE_512; 800 801 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET, 802 &entry, sizeof(entry)); 803 804 amd_iommu_reset_cmd_buffer(iommu); 805 } 806 807 /* 808 * This function disables the command buffer 809 */ 810 static void iommu_disable_command_buffer(struct amd_iommu *iommu) 811 { 812 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); 813 } 814 815 static void __init free_command_buffer(struct amd_iommu *iommu) 816 { 817 iommu_free_pages(iommu->cmd_buf); 818 } 819 820 void *__init iommu_alloc_4k_pages(struct amd_iommu *iommu, gfp_t gfp, 821 size_t size) 822 { 823 void *buf; 824 825 size = PAGE_ALIGN(size); 826 buf = iommu_alloc_pages_sz(gfp, size); 827 if (!buf) 828 return NULL; 829 if (check_feature(FEATURE_SNP) && 830 set_memory_4k((unsigned long)buf, size / PAGE_SIZE)) { 831 iommu_free_pages(buf); 832 return NULL; 833 } 834 835 return buf; 836 } 837 838 /* allocates the memory where the IOMMU will log its events to */ 839 static int __init alloc_event_buffer(struct amd_iommu *iommu) 840 { 841 iommu->evt_buf = iommu_alloc_4k_pages(iommu, GFP_KERNEL, 842 EVT_BUFFER_SIZE); 843 844 return iommu->evt_buf ? 0 : -ENOMEM; 845 } 846 847 static void iommu_enable_event_buffer(struct amd_iommu *iommu) 848 { 849 u64 entry; 850 851 BUG_ON(iommu->evt_buf == NULL); 852 853 entry = iommu_virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK; 854 855 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET, 856 &entry, sizeof(entry)); 857 858 /* set head and tail to zero manually */ 859 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); 860 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); 861 862 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN); 863 } 864 865 /* 866 * This function disables the event log buffer 867 */ 868 static void iommu_disable_event_buffer(struct amd_iommu *iommu) 869 { 870 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN); 871 } 872 873 static void __init free_event_buffer(struct amd_iommu *iommu) 874 { 875 iommu_free_pages(iommu->evt_buf); 876 } 877 878 static void free_ga_log(struct amd_iommu *iommu) 879 { 880 #ifdef CONFIG_IRQ_REMAP 881 iommu_free_pages(iommu->ga_log); 882 iommu_free_pages(iommu->ga_log_tail); 883 #endif 884 } 885 886 #ifdef CONFIG_IRQ_REMAP 887 static int iommu_ga_log_enable(struct amd_iommu *iommu) 888 { 889 u32 status, i; 890 u64 entry; 891 892 if (!iommu->ga_log) 893 return -EINVAL; 894 895 entry = iommu_virt_to_phys(iommu->ga_log) | GA_LOG_SIZE_512; 896 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_BASE_OFFSET, 897 &entry, sizeof(entry)); 898 entry = (iommu_virt_to_phys(iommu->ga_log_tail) & 899 (BIT_ULL(52)-1)) & ~7ULL; 900 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_TAIL_OFFSET, 901 &entry, sizeof(entry)); 902 writel(0x00, iommu->mmio_base + MMIO_GA_HEAD_OFFSET); 903 writel(0x00, iommu->mmio_base + MMIO_GA_TAIL_OFFSET); 904 905 906 iommu_feature_enable(iommu, CONTROL_GAINT_EN); 907 iommu_feature_enable(iommu, CONTROL_GALOG_EN); 908 909 for (i = 0; i < MMIO_STATUS_TIMEOUT; ++i) { 910 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); 911 if (status & (MMIO_STATUS_GALOG_RUN_MASK)) 912 break; 913 udelay(10); 914 } 915 916 if (WARN_ON(i >= MMIO_STATUS_TIMEOUT)) 917 return -EINVAL; 918 919 return 0; 920 } 921 922 static int iommu_init_ga_log(struct amd_iommu *iommu) 923 { 924 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) 925 return 0; 926 927 iommu->ga_log = iommu_alloc_pages_sz(GFP_KERNEL, GA_LOG_SIZE); 928 if (!iommu->ga_log) 929 goto err_out; 930 931 iommu->ga_log_tail = iommu_alloc_pages_sz(GFP_KERNEL, 8); 932 if (!iommu->ga_log_tail) 933 goto err_out; 934 935 return 0; 936 err_out: 937 free_ga_log(iommu); 938 return -EINVAL; 939 } 940 #endif /* CONFIG_IRQ_REMAP */ 941 942 static int __init alloc_cwwb_sem(struct amd_iommu *iommu) 943 { 944 iommu->cmd_sem = iommu_alloc_4k_pages(iommu, GFP_KERNEL, 1); 945 946 return iommu->cmd_sem ? 0 : -ENOMEM; 947 } 948 949 static void __init free_cwwb_sem(struct amd_iommu *iommu) 950 { 951 if (iommu->cmd_sem) 952 iommu_free_pages((void *)iommu->cmd_sem); 953 } 954 955 static void iommu_enable_xt(struct amd_iommu *iommu) 956 { 957 #ifdef CONFIG_IRQ_REMAP 958 /* 959 * XT mode (32-bit APIC destination ID) requires 960 * GA mode (128-bit IRTE support) as a prerequisite. 961 */ 962 if (AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir) && 963 amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE) 964 iommu_feature_enable(iommu, CONTROL_XT_EN); 965 #endif /* CONFIG_IRQ_REMAP */ 966 } 967 968 static void iommu_enable_gt(struct amd_iommu *iommu) 969 { 970 if (!check_feature(FEATURE_GT)) 971 return; 972 973 iommu_feature_enable(iommu, CONTROL_GT_EN); 974 } 975 976 /* sets a specific bit in the device table entry. */ 977 static void set_dte_bit(struct dev_table_entry *dte, u8 bit) 978 { 979 int i = (bit >> 6) & 0x03; 980 int _bit = bit & 0x3f; 981 982 dte->data[i] |= (1UL << _bit); 983 } 984 985 static bool __copy_device_table(struct amd_iommu *iommu) 986 { 987 u64 int_ctl, int_tab_len, entry = 0; 988 struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg; 989 struct dev_table_entry *old_devtb = NULL; 990 u32 lo, hi, devid, old_devtb_size; 991 phys_addr_t old_devtb_phys; 992 u16 dom_id, dte_v, irq_v; 993 u64 tmp; 994 995 /* Each IOMMU use separate device table with the same size */ 996 lo = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET); 997 hi = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET + 4); 998 entry = (((u64) hi) << 32) + lo; 999 1000 old_devtb_size = ((entry & ~PAGE_MASK) + 1) << 12; 1001 if (old_devtb_size != pci_seg->dev_table_size) { 1002 pr_err("The device table size of IOMMU:%d is not expected!\n", 1003 iommu->index); 1004 return false; 1005 } 1006 1007 /* 1008 * When SME is enabled in the first kernel, the entry includes the 1009 * memory encryption mask(sme_me_mask), we must remove the memory 1010 * encryption mask to obtain the true physical address in kdump kernel. 1011 */ 1012 old_devtb_phys = __sme_clr(entry) & PAGE_MASK; 1013 1014 if (old_devtb_phys >= 0x100000000ULL) { 1015 pr_err("The address of old device table is above 4G, not trustworthy!\n"); 1016 return false; 1017 } 1018 old_devtb = (cc_platform_has(CC_ATTR_HOST_MEM_ENCRYPT) && is_kdump_kernel()) 1019 ? (__force void *)ioremap_encrypted(old_devtb_phys, 1020 pci_seg->dev_table_size) 1021 : memremap(old_devtb_phys, pci_seg->dev_table_size, MEMREMAP_WB); 1022 1023 if (!old_devtb) 1024 return false; 1025 1026 pci_seg->old_dev_tbl_cpy = iommu_alloc_pages_sz( 1027 GFP_KERNEL | GFP_DMA32, pci_seg->dev_table_size); 1028 if (pci_seg->old_dev_tbl_cpy == NULL) { 1029 pr_err("Failed to allocate memory for copying old device table!\n"); 1030 memunmap(old_devtb); 1031 return false; 1032 } 1033 1034 for (devid = 0; devid <= pci_seg->last_bdf; ++devid) { 1035 pci_seg->old_dev_tbl_cpy[devid] = old_devtb[devid]; 1036 dom_id = old_devtb[devid].data[1] & DEV_DOMID_MASK; 1037 dte_v = old_devtb[devid].data[0] & DTE_FLAG_V; 1038 1039 if (dte_v && dom_id) { 1040 pci_seg->old_dev_tbl_cpy[devid].data[0] = old_devtb[devid].data[0]; 1041 pci_seg->old_dev_tbl_cpy[devid].data[1] = old_devtb[devid].data[1]; 1042 /* Reserve the Domain IDs used by previous kernel */ 1043 if (ida_alloc_range(&pdom_ids, dom_id, dom_id, GFP_ATOMIC) != dom_id) { 1044 pr_err("Failed to reserve domain ID 0x%x\n", dom_id); 1045 memunmap(old_devtb); 1046 return false; 1047 } 1048 /* If gcr3 table existed, mask it out */ 1049 if (old_devtb[devid].data[0] & DTE_FLAG_GV) { 1050 tmp = (DTE_GCR3_30_15 | DTE_GCR3_51_31); 1051 pci_seg->old_dev_tbl_cpy[devid].data[1] &= ~tmp; 1052 tmp = (DTE_GCR3_14_12 | DTE_FLAG_GV); 1053 pci_seg->old_dev_tbl_cpy[devid].data[0] &= ~tmp; 1054 } 1055 } 1056 1057 irq_v = old_devtb[devid].data[2] & DTE_IRQ_REMAP_ENABLE; 1058 int_ctl = old_devtb[devid].data[2] & DTE_IRQ_REMAP_INTCTL_MASK; 1059 int_tab_len = old_devtb[devid].data[2] & DTE_INTTABLEN_MASK; 1060 if (irq_v && (int_ctl || int_tab_len)) { 1061 if ((int_ctl != DTE_IRQ_REMAP_INTCTL) || 1062 (int_tab_len != DTE_INTTABLEN_512 && 1063 int_tab_len != DTE_INTTABLEN_2K)) { 1064 pr_err("Wrong old irq remapping flag: %#x\n", devid); 1065 memunmap(old_devtb); 1066 return false; 1067 } 1068 1069 pci_seg->old_dev_tbl_cpy[devid].data[2] = old_devtb[devid].data[2]; 1070 } 1071 } 1072 memunmap(old_devtb); 1073 1074 return true; 1075 } 1076 1077 static bool copy_device_table(void) 1078 { 1079 struct amd_iommu *iommu; 1080 struct amd_iommu_pci_seg *pci_seg; 1081 1082 if (!amd_iommu_pre_enabled) 1083 return false; 1084 1085 pr_warn("Translation is already enabled - trying to copy translation structures\n"); 1086 1087 /* 1088 * All IOMMUs within PCI segment shares common device table. 1089 * Hence copy device table only once per PCI segment. 1090 */ 1091 for_each_pci_segment(pci_seg) { 1092 for_each_iommu(iommu) { 1093 if (pci_seg->id != iommu->pci_seg->id) 1094 continue; 1095 if (!__copy_device_table(iommu)) 1096 return false; 1097 break; 1098 } 1099 } 1100 1101 return true; 1102 } 1103 1104 struct dev_table_entry *amd_iommu_get_ivhd_dte_flags(u16 segid, u16 devid) 1105 { 1106 struct ivhd_dte_flags *e; 1107 unsigned int best_len = UINT_MAX; 1108 struct dev_table_entry *dte = NULL; 1109 1110 for_each_ivhd_dte_flags(e) { 1111 /* 1112 * Need to go through the whole list to find the smallest range, 1113 * which contains the devid. 1114 */ 1115 if ((e->segid == segid) && 1116 (e->devid_first <= devid) && (devid <= e->devid_last)) { 1117 unsigned int len = e->devid_last - e->devid_first; 1118 1119 if (len < best_len) { 1120 dte = &(e->dte); 1121 best_len = len; 1122 } 1123 } 1124 } 1125 return dte; 1126 } 1127 1128 static bool search_ivhd_dte_flags(u16 segid, u16 first, u16 last) 1129 { 1130 struct ivhd_dte_flags *e; 1131 1132 for_each_ivhd_dte_flags(e) { 1133 if ((e->segid == segid) && 1134 (e->devid_first == first) && 1135 (e->devid_last == last)) 1136 return true; 1137 } 1138 return false; 1139 } 1140 1141 /* 1142 * This function takes the device specific flags read from the ACPI 1143 * table and sets up the device table entry with that information 1144 */ 1145 static void __init 1146 set_dev_entry_from_acpi_range(struct amd_iommu *iommu, u16 first, u16 last, 1147 u32 flags, u32 ext_flags) 1148 { 1149 int i; 1150 struct dev_table_entry dte = {}; 1151 1152 /* Parse IVHD DTE setting flags and store information */ 1153 if (flags) { 1154 struct ivhd_dte_flags *d; 1155 1156 if (search_ivhd_dte_flags(iommu->pci_seg->id, first, last)) 1157 return; 1158 1159 d = kzalloc(sizeof(struct ivhd_dte_flags), GFP_KERNEL); 1160 if (!d) 1161 return; 1162 1163 pr_debug("%s: devid range %#x:%#x\n", __func__, first, last); 1164 1165 if (flags & ACPI_DEVFLAG_INITPASS) 1166 set_dte_bit(&dte, DEV_ENTRY_INIT_PASS); 1167 if (flags & ACPI_DEVFLAG_EXTINT) 1168 set_dte_bit(&dte, DEV_ENTRY_EINT_PASS); 1169 if (flags & ACPI_DEVFLAG_NMI) 1170 set_dte_bit(&dte, DEV_ENTRY_NMI_PASS); 1171 if (flags & ACPI_DEVFLAG_SYSMGT1) 1172 set_dte_bit(&dte, DEV_ENTRY_SYSMGT1); 1173 if (flags & ACPI_DEVFLAG_SYSMGT2) 1174 set_dte_bit(&dte, DEV_ENTRY_SYSMGT2); 1175 if (flags & ACPI_DEVFLAG_LINT0) 1176 set_dte_bit(&dte, DEV_ENTRY_LINT0_PASS); 1177 if (flags & ACPI_DEVFLAG_LINT1) 1178 set_dte_bit(&dte, DEV_ENTRY_LINT1_PASS); 1179 1180 /* Apply erratum 63, which needs info in initial_dte */ 1181 if (FIELD_GET(DTE_DATA1_SYSMGT_MASK, dte.data[1]) == 0x1) 1182 dte.data[0] |= DTE_FLAG_IW; 1183 1184 memcpy(&d->dte, &dte, sizeof(dte)); 1185 d->segid = iommu->pci_seg->id; 1186 d->devid_first = first; 1187 d->devid_last = last; 1188 list_add_tail(&d->list, &amd_ivhd_dev_flags_list); 1189 } 1190 1191 for (i = first; i <= last; i++) { 1192 if (flags) { 1193 struct dev_table_entry *dev_table = get_dev_table(iommu); 1194 1195 memcpy(&dev_table[i], &dte, sizeof(dte)); 1196 } 1197 amd_iommu_set_rlookup_table(iommu, i); 1198 } 1199 } 1200 1201 static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu, 1202 u16 devid, u32 flags, u32 ext_flags) 1203 { 1204 set_dev_entry_from_acpi_range(iommu, devid, devid, flags, ext_flags); 1205 } 1206 1207 int __init add_special_device(u8 type, u8 id, u32 *devid, bool cmd_line) 1208 { 1209 struct devid_map *entry; 1210 struct list_head *list; 1211 1212 if (type == IVHD_SPECIAL_IOAPIC) 1213 list = &ioapic_map; 1214 else if (type == IVHD_SPECIAL_HPET) 1215 list = &hpet_map; 1216 else 1217 return -EINVAL; 1218 1219 list_for_each_entry(entry, list, list) { 1220 if (!(entry->id == id && entry->cmd_line)) 1221 continue; 1222 1223 pr_info("Command-line override present for %s id %d - ignoring\n", 1224 type == IVHD_SPECIAL_IOAPIC ? "IOAPIC" : "HPET", id); 1225 1226 *devid = entry->devid; 1227 1228 return 0; 1229 } 1230 1231 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 1232 if (!entry) 1233 return -ENOMEM; 1234 1235 entry->id = id; 1236 entry->devid = *devid; 1237 entry->cmd_line = cmd_line; 1238 1239 list_add_tail(&entry->list, list); 1240 1241 return 0; 1242 } 1243 1244 static int __init add_acpi_hid_device(u8 *hid, u8 *uid, u32 *devid, 1245 bool cmd_line) 1246 { 1247 struct acpihid_map_entry *entry; 1248 struct list_head *list = &acpihid_map; 1249 1250 list_for_each_entry(entry, list, list) { 1251 if (strcmp(entry->hid, hid) || 1252 (*uid && *entry->uid && strcmp(entry->uid, uid)) || 1253 !entry->cmd_line) 1254 continue; 1255 1256 pr_info("Command-line override for hid:%s uid:%s\n", 1257 hid, uid); 1258 *devid = entry->devid; 1259 return 0; 1260 } 1261 1262 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 1263 if (!entry) 1264 return -ENOMEM; 1265 1266 memcpy(entry->uid, uid, strlen(uid)); 1267 memcpy(entry->hid, hid, strlen(hid)); 1268 entry->devid = *devid; 1269 entry->cmd_line = cmd_line; 1270 entry->root_devid = (entry->devid & (~0x7)); 1271 1272 pr_info("%s, add hid:%s, uid:%s, rdevid:%#x\n", 1273 entry->cmd_line ? "cmd" : "ivrs", 1274 entry->hid, entry->uid, entry->root_devid); 1275 1276 list_add_tail(&entry->list, list); 1277 return 0; 1278 } 1279 1280 static int __init add_early_maps(void) 1281 { 1282 int i, ret; 1283 1284 for (i = 0; i < early_ioapic_map_size; ++i) { 1285 ret = add_special_device(IVHD_SPECIAL_IOAPIC, 1286 early_ioapic_map[i].id, 1287 &early_ioapic_map[i].devid, 1288 early_ioapic_map[i].cmd_line); 1289 if (ret) 1290 return ret; 1291 } 1292 1293 for (i = 0; i < early_hpet_map_size; ++i) { 1294 ret = add_special_device(IVHD_SPECIAL_HPET, 1295 early_hpet_map[i].id, 1296 &early_hpet_map[i].devid, 1297 early_hpet_map[i].cmd_line); 1298 if (ret) 1299 return ret; 1300 } 1301 1302 for (i = 0; i < early_acpihid_map_size; ++i) { 1303 ret = add_acpi_hid_device(early_acpihid_map[i].hid, 1304 early_acpihid_map[i].uid, 1305 &early_acpihid_map[i].devid, 1306 early_acpihid_map[i].cmd_line); 1307 if (ret) 1308 return ret; 1309 } 1310 1311 return 0; 1312 } 1313 1314 /* 1315 * Takes a pointer to an AMD IOMMU entry in the ACPI table and 1316 * initializes the hardware and our data structures with it. 1317 */ 1318 static int __init init_iommu_from_acpi(struct amd_iommu *iommu, 1319 struct ivhd_header *h) 1320 { 1321 u8 *p = (u8 *)h; 1322 u8 *end = p, flags = 0; 1323 u16 devid = 0, devid_start = 0, devid_to = 0, seg_id; 1324 u32 dev_i, ext_flags = 0; 1325 bool alias = false; 1326 struct ivhd_entry *e; 1327 struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg; 1328 u32 ivhd_size; 1329 int ret; 1330 1331 1332 ret = add_early_maps(); 1333 if (ret) 1334 return ret; 1335 1336 amd_iommu_apply_ivrs_quirks(); 1337 1338 /* 1339 * First save the recommended feature enable bits from ACPI 1340 */ 1341 iommu->acpi_flags = h->flags; 1342 1343 /* 1344 * Done. Now parse the device entries 1345 */ 1346 ivhd_size = get_ivhd_header_size(h); 1347 if (!ivhd_size) { 1348 pr_err("Unsupported IVHD type %#x\n", h->type); 1349 return -EINVAL; 1350 } 1351 1352 p += ivhd_size; 1353 1354 end += h->length; 1355 1356 1357 while (p < end) { 1358 e = (struct ivhd_entry *)p; 1359 seg_id = pci_seg->id; 1360 1361 switch (e->type) { 1362 case IVHD_DEV_ALL: 1363 1364 DUMP_printk(" DEV_ALL\t\t\tsetting: %#02x\n", e->flags); 1365 set_dev_entry_from_acpi_range(iommu, 0, pci_seg->last_bdf, e->flags, 0); 1366 break; 1367 case IVHD_DEV_SELECT: 1368 1369 DUMP_printk(" DEV_SELECT\t\t\tdevid: %04x:%02x:%02x.%x flags: %#02x\n", 1370 seg_id, PCI_BUS_NUM(e->devid), 1371 PCI_SLOT(e->devid), 1372 PCI_FUNC(e->devid), 1373 e->flags); 1374 1375 devid = e->devid; 1376 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); 1377 break; 1378 case IVHD_DEV_SELECT_RANGE_START: 1379 1380 DUMP_printk(" DEV_SELECT_RANGE_START\tdevid: %04x:%02x:%02x.%x flags: %#02x\n", 1381 seg_id, PCI_BUS_NUM(e->devid), 1382 PCI_SLOT(e->devid), 1383 PCI_FUNC(e->devid), 1384 e->flags); 1385 1386 devid_start = e->devid; 1387 flags = e->flags; 1388 ext_flags = 0; 1389 alias = false; 1390 break; 1391 case IVHD_DEV_ALIAS: 1392 1393 DUMP_printk(" DEV_ALIAS\t\t\tdevid: %04x:%02x:%02x.%x flags: %#02x devid_to: %02x:%02x.%x\n", 1394 seg_id, PCI_BUS_NUM(e->devid), 1395 PCI_SLOT(e->devid), 1396 PCI_FUNC(e->devid), 1397 e->flags, 1398 PCI_BUS_NUM(e->ext >> 8), 1399 PCI_SLOT(e->ext >> 8), 1400 PCI_FUNC(e->ext >> 8)); 1401 1402 devid = e->devid; 1403 devid_to = e->ext >> 8; 1404 set_dev_entry_from_acpi(iommu, devid , e->flags, 0); 1405 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0); 1406 pci_seg->alias_table[devid] = devid_to; 1407 break; 1408 case IVHD_DEV_ALIAS_RANGE: 1409 1410 DUMP_printk(" DEV_ALIAS_RANGE\t\tdevid: %04x:%02x:%02x.%x flags: %#02x devid_to: %04x:%02x:%02x.%x\n", 1411 seg_id, PCI_BUS_NUM(e->devid), 1412 PCI_SLOT(e->devid), 1413 PCI_FUNC(e->devid), 1414 e->flags, 1415 seg_id, PCI_BUS_NUM(e->ext >> 8), 1416 PCI_SLOT(e->ext >> 8), 1417 PCI_FUNC(e->ext >> 8)); 1418 1419 devid_start = e->devid; 1420 flags = e->flags; 1421 devid_to = e->ext >> 8; 1422 ext_flags = 0; 1423 alias = true; 1424 break; 1425 case IVHD_DEV_EXT_SELECT: 1426 1427 DUMP_printk(" DEV_EXT_SELECT\t\tdevid: %04x:%02x:%02x.%x flags: %#02x ext: %08x\n", 1428 seg_id, PCI_BUS_NUM(e->devid), 1429 PCI_SLOT(e->devid), 1430 PCI_FUNC(e->devid), 1431 e->flags, e->ext); 1432 1433 devid = e->devid; 1434 set_dev_entry_from_acpi(iommu, devid, e->flags, 1435 e->ext); 1436 break; 1437 case IVHD_DEV_EXT_SELECT_RANGE: 1438 1439 DUMP_printk(" DEV_EXT_SELECT_RANGE\tdevid: %04x:%02x:%02x.%x flags: %#02x ext: %08x\n", 1440 seg_id, PCI_BUS_NUM(e->devid), 1441 PCI_SLOT(e->devid), 1442 PCI_FUNC(e->devid), 1443 e->flags, e->ext); 1444 1445 devid_start = e->devid; 1446 flags = e->flags; 1447 ext_flags = e->ext; 1448 alias = false; 1449 break; 1450 case IVHD_DEV_RANGE_END: 1451 1452 DUMP_printk(" DEV_RANGE_END\t\tdevid: %04x:%02x:%02x.%x\n", 1453 seg_id, PCI_BUS_NUM(e->devid), 1454 PCI_SLOT(e->devid), 1455 PCI_FUNC(e->devid)); 1456 1457 devid = e->devid; 1458 for (dev_i = devid_start; dev_i <= devid; ++dev_i) { 1459 if (alias) 1460 pci_seg->alias_table[dev_i] = devid_to; 1461 } 1462 set_dev_entry_from_acpi_range(iommu, devid_start, devid, flags, ext_flags); 1463 set_dev_entry_from_acpi(iommu, devid_to, flags, ext_flags); 1464 break; 1465 case IVHD_DEV_SPECIAL: { 1466 u8 handle, type; 1467 const char *var; 1468 u32 devid; 1469 int ret; 1470 1471 handle = e->ext & 0xff; 1472 devid = PCI_SEG_DEVID_TO_SBDF(seg_id, (e->ext >> 8)); 1473 type = (e->ext >> 24) & 0xff; 1474 1475 if (type == IVHD_SPECIAL_IOAPIC) 1476 var = "IOAPIC"; 1477 else if (type == IVHD_SPECIAL_HPET) 1478 var = "HPET"; 1479 else 1480 var = "UNKNOWN"; 1481 1482 DUMP_printk(" DEV_SPECIAL(%s[%d])\t\tdevid: %04x:%02x:%02x.%x, flags: %#02x\n", 1483 var, (int)handle, 1484 seg_id, PCI_BUS_NUM(devid), 1485 PCI_SLOT(devid), 1486 PCI_FUNC(devid), 1487 e->flags); 1488 1489 ret = add_special_device(type, handle, &devid, false); 1490 if (ret) 1491 return ret; 1492 1493 /* 1494 * add_special_device might update the devid in case a 1495 * command-line override is present. So call 1496 * set_dev_entry_from_acpi after add_special_device. 1497 */ 1498 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); 1499 1500 break; 1501 } 1502 case IVHD_DEV_ACPI_HID: { 1503 u32 devid; 1504 u8 hid[ACPIHID_HID_LEN]; 1505 u8 uid[ACPIHID_UID_LEN]; 1506 int ret; 1507 1508 if (h->type != 0x40) { 1509 pr_err(FW_BUG "Invalid IVHD device type %#x\n", 1510 e->type); 1511 break; 1512 } 1513 1514 BUILD_BUG_ON(sizeof(e->ext_hid) != ACPIHID_HID_LEN - 1); 1515 memcpy(hid, &e->ext_hid, ACPIHID_HID_LEN - 1); 1516 hid[ACPIHID_HID_LEN - 1] = '\0'; 1517 1518 if (!(*hid)) { 1519 pr_err(FW_BUG "Invalid HID.\n"); 1520 break; 1521 } 1522 1523 uid[0] = '\0'; 1524 switch (e->uidf) { 1525 case UID_NOT_PRESENT: 1526 1527 if (e->uidl != 0) 1528 pr_warn(FW_BUG "Invalid UID length.\n"); 1529 1530 break; 1531 case UID_IS_INTEGER: 1532 1533 sprintf(uid, "%d", e->uid); 1534 1535 break; 1536 case UID_IS_CHARACTER: 1537 1538 memcpy(uid, &e->uid, e->uidl); 1539 uid[e->uidl] = '\0'; 1540 1541 break; 1542 default: 1543 break; 1544 } 1545 1546 devid = PCI_SEG_DEVID_TO_SBDF(seg_id, e->devid); 1547 DUMP_printk(" DEV_ACPI_HID(%s[%s])\t\tdevid: %04x:%02x:%02x.%x, flags: %#02x\n", 1548 hid, uid, seg_id, 1549 PCI_BUS_NUM(devid), 1550 PCI_SLOT(devid), 1551 PCI_FUNC(devid), 1552 e->flags); 1553 1554 flags = e->flags; 1555 1556 ret = add_acpi_hid_device(hid, uid, &devid, false); 1557 if (ret) 1558 return ret; 1559 1560 /* 1561 * add_special_device might update the devid in case a 1562 * command-line override is present. So call 1563 * set_dev_entry_from_acpi after add_special_device. 1564 */ 1565 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); 1566 1567 break; 1568 } 1569 default: 1570 break; 1571 } 1572 1573 p += ivhd_entry_length(p); 1574 } 1575 1576 return 0; 1577 } 1578 1579 /* Allocate PCI segment data structure */ 1580 static struct amd_iommu_pci_seg *__init alloc_pci_segment(u16 id, 1581 struct acpi_table_header *ivrs_base) 1582 { 1583 struct amd_iommu_pci_seg *pci_seg; 1584 int last_bdf; 1585 1586 /* 1587 * First parse ACPI tables to find the largest Bus/Dev/Func we need to 1588 * handle in this PCI segment. Upon this information the shared data 1589 * structures for the PCI segments in the system will be allocated. 1590 */ 1591 last_bdf = find_last_devid_acpi(ivrs_base, id); 1592 if (last_bdf < 0) 1593 return NULL; 1594 1595 pci_seg = kzalloc(sizeof(struct amd_iommu_pci_seg), GFP_KERNEL); 1596 if (pci_seg == NULL) 1597 return NULL; 1598 1599 pci_seg->last_bdf = last_bdf; 1600 DUMP_printk("PCI segment : 0x%0x, last bdf : 0x%04x\n", id, last_bdf); 1601 pci_seg->dev_table_size = 1602 max(roundup_pow_of_two((last_bdf + 1) * DEV_TABLE_ENTRY_SIZE), 1603 SZ_4K); 1604 1605 pci_seg->id = id; 1606 init_llist_head(&pci_seg->dev_data_list); 1607 INIT_LIST_HEAD(&pci_seg->unity_map); 1608 list_add_tail(&pci_seg->list, &amd_iommu_pci_seg_list); 1609 1610 if (alloc_dev_table(pci_seg)) 1611 return NULL; 1612 if (alloc_alias_table(pci_seg)) 1613 return NULL; 1614 if (alloc_rlookup_table(pci_seg)) 1615 return NULL; 1616 1617 return pci_seg; 1618 } 1619 1620 static struct amd_iommu_pci_seg *__init get_pci_segment(u16 id, 1621 struct acpi_table_header *ivrs_base) 1622 { 1623 struct amd_iommu_pci_seg *pci_seg; 1624 1625 for_each_pci_segment(pci_seg) { 1626 if (pci_seg->id == id) 1627 return pci_seg; 1628 } 1629 1630 return alloc_pci_segment(id, ivrs_base); 1631 } 1632 1633 static void __init free_pci_segments(void) 1634 { 1635 struct amd_iommu_pci_seg *pci_seg, *next; 1636 1637 for_each_pci_segment_safe(pci_seg, next) { 1638 list_del(&pci_seg->list); 1639 free_irq_lookup_table(pci_seg); 1640 free_rlookup_table(pci_seg); 1641 free_alias_table(pci_seg); 1642 free_dev_table(pci_seg); 1643 kfree(pci_seg); 1644 } 1645 } 1646 1647 static void __init free_sysfs(struct amd_iommu *iommu) 1648 { 1649 if (iommu->iommu.dev) { 1650 iommu_device_unregister(&iommu->iommu); 1651 iommu_device_sysfs_remove(&iommu->iommu); 1652 } 1653 } 1654 1655 static void __init free_iommu_one(struct amd_iommu *iommu) 1656 { 1657 free_sysfs(iommu); 1658 free_cwwb_sem(iommu); 1659 free_command_buffer(iommu); 1660 free_event_buffer(iommu); 1661 amd_iommu_free_ppr_log(iommu); 1662 free_ga_log(iommu); 1663 iommu_unmap_mmio_space(iommu); 1664 amd_iommu_iopf_uninit(iommu); 1665 } 1666 1667 static void __init free_iommu_all(void) 1668 { 1669 struct amd_iommu *iommu, *next; 1670 1671 for_each_iommu_safe(iommu, next) { 1672 list_del(&iommu->list); 1673 free_iommu_one(iommu); 1674 kfree(iommu); 1675 } 1676 } 1677 1678 /* 1679 * Family15h Model 10h-1fh erratum 746 (IOMMU Logging May Stall Translations) 1680 * Workaround: 1681 * BIOS should disable L2B micellaneous clock gating by setting 1682 * L2_L2B_CK_GATE_CONTROL[CKGateL2BMiscDisable](D0F2xF4_x90[2]) = 1b 1683 */ 1684 static void amd_iommu_erratum_746_workaround(struct amd_iommu *iommu) 1685 { 1686 u32 value; 1687 1688 if ((boot_cpu_data.x86 != 0x15) || 1689 (boot_cpu_data.x86_model < 0x10) || 1690 (boot_cpu_data.x86_model > 0x1f)) 1691 return; 1692 1693 pci_write_config_dword(iommu->dev, 0xf0, 0x90); 1694 pci_read_config_dword(iommu->dev, 0xf4, &value); 1695 1696 if (value & BIT(2)) 1697 return; 1698 1699 /* Select NB indirect register 0x90 and enable writing */ 1700 pci_write_config_dword(iommu->dev, 0xf0, 0x90 | (1 << 8)); 1701 1702 pci_write_config_dword(iommu->dev, 0xf4, value | 0x4); 1703 pci_info(iommu->dev, "Applying erratum 746 workaround\n"); 1704 1705 /* Clear the enable writing bit */ 1706 pci_write_config_dword(iommu->dev, 0xf0, 0x90); 1707 } 1708 1709 /* 1710 * Family15h Model 30h-3fh (IOMMU Mishandles ATS Write Permission) 1711 * Workaround: 1712 * BIOS should enable ATS write permission check by setting 1713 * L2_DEBUG_3[AtsIgnoreIWDis](D0F2xF4_x47[0]) = 1b 1714 */ 1715 static void amd_iommu_ats_write_check_workaround(struct amd_iommu *iommu) 1716 { 1717 u32 value; 1718 1719 if ((boot_cpu_data.x86 != 0x15) || 1720 (boot_cpu_data.x86_model < 0x30) || 1721 (boot_cpu_data.x86_model > 0x3f)) 1722 return; 1723 1724 /* Test L2_DEBUG_3[AtsIgnoreIWDis] == 1 */ 1725 value = iommu_read_l2(iommu, 0x47); 1726 1727 if (value & BIT(0)) 1728 return; 1729 1730 /* Set L2_DEBUG_3[AtsIgnoreIWDis] = 1 */ 1731 iommu_write_l2(iommu, 0x47, value | BIT(0)); 1732 1733 pci_info(iommu->dev, "Applying ATS write check workaround\n"); 1734 } 1735 1736 /* 1737 * This function glues the initialization function for one IOMMU 1738 * together and also allocates the command buffer and programs the 1739 * hardware. It does NOT enable the IOMMU. This is done afterwards. 1740 */ 1741 static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h, 1742 struct acpi_table_header *ivrs_base) 1743 { 1744 struct amd_iommu_pci_seg *pci_seg; 1745 1746 pci_seg = get_pci_segment(h->pci_seg, ivrs_base); 1747 if (pci_seg == NULL) 1748 return -ENOMEM; 1749 iommu->pci_seg = pci_seg; 1750 1751 raw_spin_lock_init(&iommu->lock); 1752 atomic64_set(&iommu->cmd_sem_val, 0); 1753 1754 /* Add IOMMU to internal data structures */ 1755 list_add_tail(&iommu->list, &amd_iommu_list); 1756 iommu->index = amd_iommus_present++; 1757 1758 if (unlikely(iommu->index >= MAX_IOMMUS)) { 1759 WARN(1, "System has more IOMMUs than supported by this driver\n"); 1760 return -ENOSYS; 1761 } 1762 1763 /* 1764 * Copy data from ACPI table entry to the iommu struct 1765 */ 1766 iommu->devid = h->devid; 1767 iommu->cap_ptr = h->cap_ptr; 1768 iommu->mmio_phys = h->mmio_phys; 1769 1770 switch (h->type) { 1771 case 0x10: 1772 /* Check if IVHD EFR contains proper max banks/counters */ 1773 if ((h->efr_attr != 0) && 1774 ((h->efr_attr & (0xF << 13)) != 0) && 1775 ((h->efr_attr & (0x3F << 17)) != 0)) 1776 iommu->mmio_phys_end = MMIO_REG_END_OFFSET; 1777 else 1778 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET; 1779 1780 /* GAM requires GA mode. */ 1781 if ((h->efr_attr & (0x1 << IOMMU_FEAT_GASUP_SHIFT)) == 0) 1782 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY; 1783 break; 1784 case 0x11: 1785 case 0x40: 1786 if (h->efr_reg & (1 << 9)) 1787 iommu->mmio_phys_end = MMIO_REG_END_OFFSET; 1788 else 1789 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET; 1790 1791 /* XT and GAM require GA mode. */ 1792 if ((h->efr_reg & (0x1 << IOMMU_EFR_GASUP_SHIFT)) == 0) { 1793 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY; 1794 break; 1795 } 1796 1797 if (h->efr_reg & BIT(IOMMU_EFR_XTSUP_SHIFT)) 1798 amd_iommu_xt_mode = IRQ_REMAP_X2APIC_MODE; 1799 1800 if (h->efr_attr & BIT(IOMMU_IVHD_ATTR_HATDIS_SHIFT)) { 1801 pr_warn_once("Host Address Translation is not supported.\n"); 1802 amd_iommu_hatdis = true; 1803 } 1804 1805 early_iommu_features_init(iommu, h); 1806 1807 break; 1808 default: 1809 return -EINVAL; 1810 } 1811 1812 iommu->mmio_base = iommu_map_mmio_space(iommu->mmio_phys, 1813 iommu->mmio_phys_end); 1814 if (!iommu->mmio_base) 1815 return -ENOMEM; 1816 1817 return init_iommu_from_acpi(iommu, h); 1818 } 1819 1820 static int __init init_iommu_one_late(struct amd_iommu *iommu) 1821 { 1822 int ret; 1823 1824 if (alloc_cwwb_sem(iommu)) 1825 return -ENOMEM; 1826 1827 if (alloc_command_buffer(iommu)) 1828 return -ENOMEM; 1829 1830 if (alloc_event_buffer(iommu)) 1831 return -ENOMEM; 1832 1833 iommu->int_enabled = false; 1834 1835 init_translation_status(iommu); 1836 if (translation_pre_enabled(iommu) && !is_kdump_kernel()) { 1837 iommu_disable(iommu); 1838 clear_translation_pre_enabled(iommu); 1839 pr_warn("Translation was enabled for IOMMU:%d but we are not in kdump mode\n", 1840 iommu->index); 1841 } 1842 if (amd_iommu_pre_enabled) 1843 amd_iommu_pre_enabled = translation_pre_enabled(iommu); 1844 1845 if (amd_iommu_irq_remap) { 1846 ret = amd_iommu_create_irq_domain(iommu); 1847 if (ret) 1848 return ret; 1849 } 1850 1851 /* 1852 * Make sure IOMMU is not considered to translate itself. The IVRS 1853 * table tells us so, but this is a lie! 1854 */ 1855 iommu->pci_seg->rlookup_table[iommu->devid] = NULL; 1856 1857 return 0; 1858 } 1859 1860 /** 1861 * get_highest_supported_ivhd_type - Look up the appropriate IVHD type 1862 * @ivrs: Pointer to the IVRS header 1863 * 1864 * This function search through all IVDB of the maximum supported IVHD 1865 */ 1866 static u8 get_highest_supported_ivhd_type(struct acpi_table_header *ivrs) 1867 { 1868 u8 *base = (u8 *)ivrs; 1869 struct ivhd_header *ivhd = (struct ivhd_header *) 1870 (base + IVRS_HEADER_LENGTH); 1871 u8 last_type = ivhd->type; 1872 u16 devid = ivhd->devid; 1873 1874 while (((u8 *)ivhd - base < ivrs->length) && 1875 (ivhd->type <= ACPI_IVHD_TYPE_MAX_SUPPORTED)) { 1876 u8 *p = (u8 *) ivhd; 1877 1878 if (ivhd->devid == devid) 1879 last_type = ivhd->type; 1880 ivhd = (struct ivhd_header *)(p + ivhd->length); 1881 } 1882 1883 return last_type; 1884 } 1885 1886 /* 1887 * Iterates over all IOMMU entries in the ACPI table, allocates the 1888 * IOMMU structure and initializes it with init_iommu_one() 1889 */ 1890 static int __init init_iommu_all(struct acpi_table_header *table) 1891 { 1892 u8 *p = (u8 *)table, *end = (u8 *)table; 1893 struct ivhd_header *h; 1894 struct amd_iommu *iommu; 1895 int ret; 1896 1897 end += table->length; 1898 p += IVRS_HEADER_LENGTH; 1899 1900 /* Phase 1: Process all IVHD blocks */ 1901 while (p < end) { 1902 h = (struct ivhd_header *)p; 1903 if (*p == amd_iommu_target_ivhd_type) { 1904 1905 DUMP_printk("device: %04x:%02x:%02x.%01x cap: %04x " 1906 "flags: %01x info %04x\n", 1907 h->pci_seg, PCI_BUS_NUM(h->devid), 1908 PCI_SLOT(h->devid), PCI_FUNC(h->devid), 1909 h->cap_ptr, h->flags, h->info); 1910 DUMP_printk(" mmio-addr: %016llx\n", 1911 h->mmio_phys); 1912 1913 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL); 1914 if (iommu == NULL) 1915 return -ENOMEM; 1916 1917 ret = init_iommu_one(iommu, h, table); 1918 if (ret) 1919 return ret; 1920 } 1921 p += h->length; 1922 1923 } 1924 WARN_ON(p != end); 1925 1926 /* Phase 2 : Early feature support check */ 1927 get_global_efr(); 1928 1929 /* Phase 3 : Enabling IOMMU features */ 1930 for_each_iommu(iommu) { 1931 ret = init_iommu_one_late(iommu); 1932 if (ret) 1933 return ret; 1934 } 1935 1936 return 0; 1937 } 1938 1939 static void init_iommu_perf_ctr(struct amd_iommu *iommu) 1940 { 1941 u64 val; 1942 struct pci_dev *pdev = iommu->dev; 1943 1944 if (!check_feature(FEATURE_PC)) 1945 return; 1946 1947 amd_iommu_pc_present = true; 1948 1949 pci_info(pdev, "IOMMU performance counters supported\n"); 1950 1951 val = readl(iommu->mmio_base + MMIO_CNTR_CONF_OFFSET); 1952 iommu->max_banks = (u8) ((val >> 12) & 0x3f); 1953 iommu->max_counters = (u8) ((val >> 7) & 0xf); 1954 1955 return; 1956 } 1957 1958 static ssize_t amd_iommu_show_cap(struct device *dev, 1959 struct device_attribute *attr, 1960 char *buf) 1961 { 1962 struct amd_iommu *iommu = dev_to_amd_iommu(dev); 1963 return sysfs_emit(buf, "%x\n", iommu->cap); 1964 } 1965 static DEVICE_ATTR(cap, S_IRUGO, amd_iommu_show_cap, NULL); 1966 1967 static ssize_t amd_iommu_show_features(struct device *dev, 1968 struct device_attribute *attr, 1969 char *buf) 1970 { 1971 return sysfs_emit(buf, "%llx:%llx\n", amd_iommu_efr, amd_iommu_efr2); 1972 } 1973 static DEVICE_ATTR(features, S_IRUGO, amd_iommu_show_features, NULL); 1974 1975 static struct attribute *amd_iommu_attrs[] = { 1976 &dev_attr_cap.attr, 1977 &dev_attr_features.attr, 1978 NULL, 1979 }; 1980 1981 static struct attribute_group amd_iommu_group = { 1982 .name = "amd-iommu", 1983 .attrs = amd_iommu_attrs, 1984 }; 1985 1986 static const struct attribute_group *amd_iommu_groups[] = { 1987 &amd_iommu_group, 1988 NULL, 1989 }; 1990 1991 /* 1992 * Note: IVHD 0x11 and 0x40 also contains exact copy 1993 * of the IOMMU Extended Feature Register [MMIO Offset 0030h]. 1994 * Default to EFR in IVHD since it is available sooner (i.e. before PCI init). 1995 */ 1996 static void __init late_iommu_features_init(struct amd_iommu *iommu) 1997 { 1998 u64 features, features2; 1999 2000 if (!(iommu->cap & (1 << IOMMU_CAP_EFR))) 2001 return; 2002 2003 /* read extended feature bits */ 2004 features = readq(iommu->mmio_base + MMIO_EXT_FEATURES); 2005 features2 = readq(iommu->mmio_base + MMIO_EXT_FEATURES2); 2006 2007 if (!amd_iommu_efr) { 2008 amd_iommu_efr = features; 2009 amd_iommu_efr2 = features2; 2010 return; 2011 } 2012 2013 /* 2014 * Sanity check and warn if EFR values from 2015 * IVHD and MMIO conflict. 2016 */ 2017 if (features != amd_iommu_efr || 2018 features2 != amd_iommu_efr2) { 2019 pr_warn(FW_WARN 2020 "EFR mismatch. Use IVHD EFR (%#llx : %#llx), EFR2 (%#llx : %#llx).\n", 2021 features, amd_iommu_efr, 2022 features2, amd_iommu_efr2); 2023 } 2024 } 2025 2026 static int __init iommu_init_pci(struct amd_iommu *iommu) 2027 { 2028 int cap_ptr = iommu->cap_ptr; 2029 int ret; 2030 2031 iommu->dev = pci_get_domain_bus_and_slot(iommu->pci_seg->id, 2032 PCI_BUS_NUM(iommu->devid), 2033 iommu->devid & 0xff); 2034 if (!iommu->dev) 2035 return -ENODEV; 2036 2037 /* ACPI _PRT won't have an IRQ for IOMMU */ 2038 iommu->dev->irq_managed = 1; 2039 2040 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET, 2041 &iommu->cap); 2042 2043 if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB))) 2044 amd_iommu_iotlb_sup = false; 2045 2046 late_iommu_features_init(iommu); 2047 2048 if (check_feature(FEATURE_GT)) { 2049 int glxval; 2050 u64 pasmax; 2051 2052 pasmax = FIELD_GET(FEATURE_PASMAX, amd_iommu_efr); 2053 iommu->iommu.max_pasids = (1 << (pasmax + 1)) - 1; 2054 2055 BUG_ON(iommu->iommu.max_pasids & ~PASID_MASK); 2056 2057 glxval = FIELD_GET(FEATURE_GLX, amd_iommu_efr); 2058 2059 if (amd_iommu_max_glx_val == -1) 2060 amd_iommu_max_glx_val = glxval; 2061 else 2062 amd_iommu_max_glx_val = min(amd_iommu_max_glx_val, glxval); 2063 2064 iommu_enable_gt(iommu); 2065 } 2066 2067 if (check_feature(FEATURE_PPR) && amd_iommu_alloc_ppr_log(iommu)) 2068 return -ENOMEM; 2069 2070 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE)) { 2071 pr_info("Using strict mode due to virtualization\n"); 2072 iommu_set_dma_strict(); 2073 amd_iommu_np_cache = true; 2074 } 2075 2076 init_iommu_perf_ctr(iommu); 2077 2078 if (is_rd890_iommu(iommu->dev)) { 2079 int i, j; 2080 2081 iommu->root_pdev = 2082 pci_get_domain_bus_and_slot(iommu->pci_seg->id, 2083 iommu->dev->bus->number, 2084 PCI_DEVFN(0, 0)); 2085 2086 /* 2087 * Some rd890 systems may not be fully reconfigured by the 2088 * BIOS, so it's necessary for us to store this information so 2089 * it can be reprogrammed on resume 2090 */ 2091 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4, 2092 &iommu->stored_addr_lo); 2093 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8, 2094 &iommu->stored_addr_hi); 2095 2096 /* Low bit locks writes to configuration space */ 2097 iommu->stored_addr_lo &= ~1; 2098 2099 for (i = 0; i < 6; i++) 2100 for (j = 0; j < 0x12; j++) 2101 iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j); 2102 2103 for (i = 0; i < 0x83; i++) 2104 iommu->stored_l2[i] = iommu_read_l2(iommu, i); 2105 } 2106 2107 amd_iommu_erratum_746_workaround(iommu); 2108 amd_iommu_ats_write_check_workaround(iommu); 2109 2110 ret = iommu_device_sysfs_add(&iommu->iommu, &iommu->dev->dev, 2111 amd_iommu_groups, "ivhd%d", iommu->index); 2112 if (ret) 2113 return ret; 2114 2115 /* 2116 * Allocate per IOMMU IOPF queue here so that in attach device path, 2117 * PRI capable device can be added to IOPF queue 2118 */ 2119 if (amd_iommu_gt_ppr_supported()) { 2120 ret = amd_iommu_iopf_init(iommu); 2121 if (ret) 2122 return ret; 2123 } 2124 2125 ret = iommu_device_register(&iommu->iommu, &amd_iommu_ops, NULL); 2126 if (ret || amd_iommu_pgtable == PD_MODE_NONE) { 2127 /* 2128 * Remove sysfs if DMA translation is not supported by the 2129 * IOMMU. Do not return an error to enable IRQ remapping 2130 * in state_next(), DTE[V, TV] must eventually be set to 0. 2131 */ 2132 iommu_device_sysfs_remove(&iommu->iommu); 2133 } 2134 2135 return pci_enable_device(iommu->dev); 2136 } 2137 2138 static void print_iommu_info(void) 2139 { 2140 int i; 2141 static const char * const feat_str[] = { 2142 "PreF", "PPR", "X2APIC", "NX", "GT", "[5]", 2143 "IA", "GA", "HE", "PC" 2144 }; 2145 2146 if (amd_iommu_efr) { 2147 pr_info("Extended features (%#llx, %#llx):", amd_iommu_efr, amd_iommu_efr2); 2148 2149 for (i = 0; i < ARRAY_SIZE(feat_str); ++i) { 2150 if (check_feature(1ULL << i)) 2151 pr_cont(" %s", feat_str[i]); 2152 } 2153 2154 if (check_feature(FEATURE_GAM_VAPIC)) 2155 pr_cont(" GA_vAPIC"); 2156 2157 if (check_feature(FEATURE_SNP)) 2158 pr_cont(" SNP"); 2159 2160 pr_cont("\n"); 2161 } 2162 2163 if (irq_remapping_enabled) { 2164 pr_info("Interrupt remapping enabled\n"); 2165 if (amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE) 2166 pr_info("X2APIC enabled\n"); 2167 } 2168 if (amd_iommu_pgtable == PD_MODE_V2) { 2169 pr_info("V2 page table enabled (Paging mode : %d level)\n", 2170 amd_iommu_gpt_level); 2171 } 2172 } 2173 2174 static int __init amd_iommu_init_pci(void) 2175 { 2176 struct amd_iommu *iommu; 2177 struct amd_iommu_pci_seg *pci_seg; 2178 int ret; 2179 2180 /* Init global identity domain before registering IOMMU */ 2181 amd_iommu_init_identity_domain(); 2182 2183 for_each_iommu(iommu) { 2184 ret = iommu_init_pci(iommu); 2185 if (ret) { 2186 pr_err("IOMMU%d: Failed to initialize IOMMU Hardware (error=%d)!\n", 2187 iommu->index, ret); 2188 goto out; 2189 } 2190 /* Need to setup range after PCI init */ 2191 iommu_set_cwwb_range(iommu); 2192 } 2193 2194 /* 2195 * Order is important here to make sure any unity map requirements are 2196 * fulfilled. The unity mappings are created and written to the device 2197 * table during the iommu_init_pci() call. 2198 * 2199 * After that we call init_device_table_dma() to make sure any 2200 * uninitialized DTE will block DMA, and in the end we flush the caches 2201 * of all IOMMUs to make sure the changes to the device table are 2202 * active. 2203 */ 2204 for_each_pci_segment(pci_seg) 2205 init_device_table_dma(pci_seg); 2206 2207 for_each_iommu(iommu) 2208 amd_iommu_flush_all_caches(iommu); 2209 2210 print_iommu_info(); 2211 2212 out: 2213 return ret; 2214 } 2215 2216 /**************************************************************************** 2217 * 2218 * The following functions initialize the MSI interrupts for all IOMMUs 2219 * in the system. It's a bit challenging because there could be multiple 2220 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per 2221 * pci_dev. 2222 * 2223 ****************************************************************************/ 2224 2225 static int iommu_setup_msi(struct amd_iommu *iommu) 2226 { 2227 int r; 2228 2229 r = pci_enable_msi(iommu->dev); 2230 if (r) 2231 return r; 2232 2233 r = request_threaded_irq(iommu->dev->irq, 2234 amd_iommu_int_handler, 2235 amd_iommu_int_thread, 2236 0, "AMD-Vi", 2237 iommu); 2238 2239 if (r) { 2240 pci_disable_msi(iommu->dev); 2241 return r; 2242 } 2243 2244 return 0; 2245 } 2246 2247 union intcapxt { 2248 u64 capxt; 2249 struct { 2250 u64 reserved_0 : 2, 2251 dest_mode_logical : 1, 2252 reserved_1 : 5, 2253 destid_0_23 : 24, 2254 vector : 8, 2255 reserved_2 : 16, 2256 destid_24_31 : 8; 2257 }; 2258 } __attribute__ ((packed)); 2259 2260 2261 static struct irq_chip intcapxt_controller; 2262 2263 static int intcapxt_irqdomain_activate(struct irq_domain *domain, 2264 struct irq_data *irqd, bool reserve) 2265 { 2266 return 0; 2267 } 2268 2269 static void intcapxt_irqdomain_deactivate(struct irq_domain *domain, 2270 struct irq_data *irqd) 2271 { 2272 } 2273 2274 2275 static int intcapxt_irqdomain_alloc(struct irq_domain *domain, unsigned int virq, 2276 unsigned int nr_irqs, void *arg) 2277 { 2278 struct irq_alloc_info *info = arg; 2279 int i, ret; 2280 2281 if (!info || info->type != X86_IRQ_ALLOC_TYPE_AMDVI) 2282 return -EINVAL; 2283 2284 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg); 2285 if (ret < 0) 2286 return ret; 2287 2288 for (i = virq; i < virq + nr_irqs; i++) { 2289 struct irq_data *irqd = irq_domain_get_irq_data(domain, i); 2290 2291 irqd->chip = &intcapxt_controller; 2292 irqd->hwirq = info->hwirq; 2293 irqd->chip_data = info->data; 2294 __irq_set_handler(i, handle_edge_irq, 0, "edge"); 2295 } 2296 2297 return ret; 2298 } 2299 2300 static void intcapxt_irqdomain_free(struct irq_domain *domain, unsigned int virq, 2301 unsigned int nr_irqs) 2302 { 2303 irq_domain_free_irqs_top(domain, virq, nr_irqs); 2304 } 2305 2306 2307 static void intcapxt_unmask_irq(struct irq_data *irqd) 2308 { 2309 struct amd_iommu *iommu = irqd->chip_data; 2310 struct irq_cfg *cfg = irqd_cfg(irqd); 2311 union intcapxt xt; 2312 2313 xt.capxt = 0ULL; 2314 xt.dest_mode_logical = apic->dest_mode_logical; 2315 xt.vector = cfg->vector; 2316 xt.destid_0_23 = cfg->dest_apicid & GENMASK(23, 0); 2317 xt.destid_24_31 = cfg->dest_apicid >> 24; 2318 2319 writeq(xt.capxt, iommu->mmio_base + irqd->hwirq); 2320 } 2321 2322 static void intcapxt_mask_irq(struct irq_data *irqd) 2323 { 2324 struct amd_iommu *iommu = irqd->chip_data; 2325 2326 writeq(0, iommu->mmio_base + irqd->hwirq); 2327 } 2328 2329 2330 static int intcapxt_set_affinity(struct irq_data *irqd, 2331 const struct cpumask *mask, bool force) 2332 { 2333 struct irq_data *parent = irqd->parent_data; 2334 int ret; 2335 2336 ret = parent->chip->irq_set_affinity(parent, mask, force); 2337 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE) 2338 return ret; 2339 return 0; 2340 } 2341 2342 static int intcapxt_set_wake(struct irq_data *irqd, unsigned int on) 2343 { 2344 return on ? -EOPNOTSUPP : 0; 2345 } 2346 2347 static struct irq_chip intcapxt_controller = { 2348 .name = "IOMMU-MSI", 2349 .irq_unmask = intcapxt_unmask_irq, 2350 .irq_mask = intcapxt_mask_irq, 2351 .irq_ack = irq_chip_ack_parent, 2352 .irq_retrigger = irq_chip_retrigger_hierarchy, 2353 .irq_set_affinity = intcapxt_set_affinity, 2354 .irq_set_wake = intcapxt_set_wake, 2355 .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_MOVE_DEFERRED, 2356 }; 2357 2358 static const struct irq_domain_ops intcapxt_domain_ops = { 2359 .alloc = intcapxt_irqdomain_alloc, 2360 .free = intcapxt_irqdomain_free, 2361 .activate = intcapxt_irqdomain_activate, 2362 .deactivate = intcapxt_irqdomain_deactivate, 2363 }; 2364 2365 2366 static struct irq_domain *iommu_irqdomain; 2367 2368 static struct irq_domain *iommu_get_irqdomain(void) 2369 { 2370 struct fwnode_handle *fn; 2371 2372 /* No need for locking here (yet) as the init is single-threaded */ 2373 if (iommu_irqdomain) 2374 return iommu_irqdomain; 2375 2376 fn = irq_domain_alloc_named_fwnode("AMD-Vi-MSI"); 2377 if (!fn) 2378 return NULL; 2379 2380 iommu_irqdomain = irq_domain_create_hierarchy(x86_vector_domain, 0, 0, 2381 fn, &intcapxt_domain_ops, 2382 NULL); 2383 if (!iommu_irqdomain) 2384 irq_domain_free_fwnode(fn); 2385 2386 return iommu_irqdomain; 2387 } 2388 2389 static int __iommu_setup_intcapxt(struct amd_iommu *iommu, const char *devname, 2390 int hwirq, irq_handler_t thread_fn) 2391 { 2392 struct irq_domain *domain; 2393 struct irq_alloc_info info; 2394 int irq, ret; 2395 int node = dev_to_node(&iommu->dev->dev); 2396 2397 domain = iommu_get_irqdomain(); 2398 if (!domain) 2399 return -ENXIO; 2400 2401 init_irq_alloc_info(&info, NULL); 2402 info.type = X86_IRQ_ALLOC_TYPE_AMDVI; 2403 info.data = iommu; 2404 info.hwirq = hwirq; 2405 2406 irq = irq_domain_alloc_irqs(domain, 1, node, &info); 2407 if (irq < 0) { 2408 irq_domain_remove(domain); 2409 return irq; 2410 } 2411 2412 ret = request_threaded_irq(irq, amd_iommu_int_handler, 2413 thread_fn, 0, devname, iommu); 2414 if (ret) { 2415 irq_domain_free_irqs(irq, 1); 2416 irq_domain_remove(domain); 2417 return ret; 2418 } 2419 2420 return 0; 2421 } 2422 2423 static int iommu_setup_intcapxt(struct amd_iommu *iommu) 2424 { 2425 int ret; 2426 2427 snprintf(iommu->evt_irq_name, sizeof(iommu->evt_irq_name), 2428 "AMD-Vi%d-Evt", iommu->index); 2429 ret = __iommu_setup_intcapxt(iommu, iommu->evt_irq_name, 2430 MMIO_INTCAPXT_EVT_OFFSET, 2431 amd_iommu_int_thread_evtlog); 2432 if (ret) 2433 return ret; 2434 2435 snprintf(iommu->ppr_irq_name, sizeof(iommu->ppr_irq_name), 2436 "AMD-Vi%d-PPR", iommu->index); 2437 ret = __iommu_setup_intcapxt(iommu, iommu->ppr_irq_name, 2438 MMIO_INTCAPXT_PPR_OFFSET, 2439 amd_iommu_int_thread_pprlog); 2440 if (ret) 2441 return ret; 2442 2443 #ifdef CONFIG_IRQ_REMAP 2444 snprintf(iommu->ga_irq_name, sizeof(iommu->ga_irq_name), 2445 "AMD-Vi%d-GA", iommu->index); 2446 ret = __iommu_setup_intcapxt(iommu, iommu->ga_irq_name, 2447 MMIO_INTCAPXT_GALOG_OFFSET, 2448 amd_iommu_int_thread_galog); 2449 #endif 2450 2451 return ret; 2452 } 2453 2454 static int iommu_init_irq(struct amd_iommu *iommu) 2455 { 2456 int ret; 2457 2458 if (iommu->int_enabled) 2459 goto enable_faults; 2460 2461 if (amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE) 2462 ret = iommu_setup_intcapxt(iommu); 2463 else if (iommu->dev->msi_cap) 2464 ret = iommu_setup_msi(iommu); 2465 else 2466 ret = -ENODEV; 2467 2468 if (ret) 2469 return ret; 2470 2471 iommu->int_enabled = true; 2472 enable_faults: 2473 2474 if (amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE) 2475 iommu_feature_enable(iommu, CONTROL_INTCAPXT_EN); 2476 2477 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN); 2478 2479 return 0; 2480 } 2481 2482 /**************************************************************************** 2483 * 2484 * The next functions belong to the third pass of parsing the ACPI 2485 * table. In this last pass the memory mapping requirements are 2486 * gathered (like exclusion and unity mapping ranges). 2487 * 2488 ****************************************************************************/ 2489 2490 static void __init free_unity_maps(void) 2491 { 2492 struct unity_map_entry *entry, *next; 2493 struct amd_iommu_pci_seg *p, *pci_seg; 2494 2495 for_each_pci_segment_safe(pci_seg, p) { 2496 list_for_each_entry_safe(entry, next, &pci_seg->unity_map, list) { 2497 list_del(&entry->list); 2498 kfree(entry); 2499 } 2500 } 2501 } 2502 2503 /* called for unity map ACPI definition */ 2504 static int __init init_unity_map_range(struct ivmd_header *m, 2505 struct acpi_table_header *ivrs_base) 2506 { 2507 struct unity_map_entry *e = NULL; 2508 struct amd_iommu_pci_seg *pci_seg; 2509 char *s; 2510 2511 pci_seg = get_pci_segment(m->pci_seg, ivrs_base); 2512 if (pci_seg == NULL) 2513 return -ENOMEM; 2514 2515 e = kzalloc(sizeof(*e), GFP_KERNEL); 2516 if (e == NULL) 2517 return -ENOMEM; 2518 2519 switch (m->type) { 2520 default: 2521 kfree(e); 2522 return 0; 2523 case ACPI_IVMD_TYPE: 2524 s = "IVMD_TYPEi\t\t\t"; 2525 e->devid_start = e->devid_end = m->devid; 2526 break; 2527 case ACPI_IVMD_TYPE_ALL: 2528 s = "IVMD_TYPE_ALL\t\t"; 2529 e->devid_start = 0; 2530 e->devid_end = pci_seg->last_bdf; 2531 break; 2532 case ACPI_IVMD_TYPE_RANGE: 2533 s = "IVMD_TYPE_RANGE\t\t"; 2534 e->devid_start = m->devid; 2535 e->devid_end = m->aux; 2536 break; 2537 } 2538 e->address_start = PAGE_ALIGN(m->range_start); 2539 e->address_end = e->address_start + PAGE_ALIGN(m->range_length); 2540 e->prot = m->flags >> 1; 2541 2542 /* 2543 * Treat per-device exclusion ranges as r/w unity-mapped regions 2544 * since some buggy BIOSes might lead to the overwritten exclusion 2545 * range (exclusion_start and exclusion_length members). This 2546 * happens when there are multiple exclusion ranges (IVMD entries) 2547 * defined in ACPI table. 2548 */ 2549 if (m->flags & IVMD_FLAG_EXCL_RANGE) 2550 e->prot = (IVMD_FLAG_IW | IVMD_FLAG_IR) >> 1; 2551 2552 DUMP_printk("%s devid_start: %04x:%02x:%02x.%x devid_end: " 2553 "%04x:%02x:%02x.%x range_start: %016llx range_end: %016llx" 2554 " flags: %x\n", s, m->pci_seg, 2555 PCI_BUS_NUM(e->devid_start), PCI_SLOT(e->devid_start), 2556 PCI_FUNC(e->devid_start), m->pci_seg, 2557 PCI_BUS_NUM(e->devid_end), 2558 PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end), 2559 e->address_start, e->address_end, m->flags); 2560 2561 list_add_tail(&e->list, &pci_seg->unity_map); 2562 2563 return 0; 2564 } 2565 2566 /* iterates over all memory definitions we find in the ACPI table */ 2567 static int __init init_memory_definitions(struct acpi_table_header *table) 2568 { 2569 u8 *p = (u8 *)table, *end = (u8 *)table; 2570 struct ivmd_header *m; 2571 2572 end += table->length; 2573 p += IVRS_HEADER_LENGTH; 2574 2575 while (p < end) { 2576 m = (struct ivmd_header *)p; 2577 if (m->flags & (IVMD_FLAG_UNITY_MAP | IVMD_FLAG_EXCL_RANGE)) 2578 init_unity_map_range(m, table); 2579 2580 p += m->length; 2581 } 2582 2583 return 0; 2584 } 2585 2586 /* 2587 * Init the device table to not allow DMA access for devices 2588 */ 2589 static void init_device_table_dma(struct amd_iommu_pci_seg *pci_seg) 2590 { 2591 u32 devid; 2592 struct dev_table_entry *dev_table = pci_seg->dev_table; 2593 2594 if (!dev_table || amd_iommu_pgtable == PD_MODE_NONE) 2595 return; 2596 2597 for (devid = 0; devid <= pci_seg->last_bdf; ++devid) { 2598 set_dte_bit(&dev_table[devid], DEV_ENTRY_VALID); 2599 if (!amd_iommu_snp_en) 2600 set_dte_bit(&dev_table[devid], DEV_ENTRY_TRANSLATION); 2601 } 2602 } 2603 2604 static void __init uninit_device_table_dma(struct amd_iommu_pci_seg *pci_seg) 2605 { 2606 u32 devid; 2607 struct dev_table_entry *dev_table = pci_seg->dev_table; 2608 2609 if (dev_table == NULL) 2610 return; 2611 2612 for (devid = 0; devid <= pci_seg->last_bdf; ++devid) { 2613 dev_table[devid].data[0] = 0ULL; 2614 dev_table[devid].data[1] = 0ULL; 2615 } 2616 } 2617 2618 static void init_device_table(void) 2619 { 2620 struct amd_iommu_pci_seg *pci_seg; 2621 u32 devid; 2622 2623 if (!amd_iommu_irq_remap) 2624 return; 2625 2626 for_each_pci_segment(pci_seg) { 2627 for (devid = 0; devid <= pci_seg->last_bdf; ++devid) 2628 set_dte_bit(&pci_seg->dev_table[devid], DEV_ENTRY_IRQ_TBL_EN); 2629 } 2630 } 2631 2632 static void iommu_init_flags(struct amd_iommu *iommu) 2633 { 2634 iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ? 2635 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) : 2636 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN); 2637 2638 iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ? 2639 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) : 2640 iommu_feature_disable(iommu, CONTROL_PASSPW_EN); 2641 2642 iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ? 2643 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) : 2644 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN); 2645 2646 iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ? 2647 iommu_feature_enable(iommu, CONTROL_ISOC_EN) : 2648 iommu_feature_disable(iommu, CONTROL_ISOC_EN); 2649 2650 /* 2651 * make IOMMU memory accesses cache coherent 2652 */ 2653 iommu_feature_enable(iommu, CONTROL_COHERENT_EN); 2654 2655 /* Set IOTLB invalidation timeout to 1s */ 2656 iommu_feature_set(iommu, CTRL_INV_TO_1S, CTRL_INV_TO_MASK, CONTROL_INV_TIMEOUT); 2657 2658 /* Enable Enhanced Peripheral Page Request Handling */ 2659 if (check_feature(FEATURE_EPHSUP)) 2660 iommu_feature_enable(iommu, CONTROL_EPH_EN); 2661 } 2662 2663 static void iommu_apply_resume_quirks(struct amd_iommu *iommu) 2664 { 2665 int i, j; 2666 u32 ioc_feature_control; 2667 struct pci_dev *pdev = iommu->root_pdev; 2668 2669 /* RD890 BIOSes may not have completely reconfigured the iommu */ 2670 if (!is_rd890_iommu(iommu->dev) || !pdev) 2671 return; 2672 2673 /* 2674 * First, we need to ensure that the iommu is enabled. This is 2675 * controlled by a register in the northbridge 2676 */ 2677 2678 /* Select Northbridge indirect register 0x75 and enable writing */ 2679 pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7)); 2680 pci_read_config_dword(pdev, 0x64, &ioc_feature_control); 2681 2682 /* Enable the iommu */ 2683 if (!(ioc_feature_control & 0x1)) 2684 pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1); 2685 2686 /* Restore the iommu BAR */ 2687 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4, 2688 iommu->stored_addr_lo); 2689 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8, 2690 iommu->stored_addr_hi); 2691 2692 /* Restore the l1 indirect regs for each of the 6 l1s */ 2693 for (i = 0; i < 6; i++) 2694 for (j = 0; j < 0x12; j++) 2695 iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]); 2696 2697 /* Restore the l2 indirect regs */ 2698 for (i = 0; i < 0x83; i++) 2699 iommu_write_l2(iommu, i, iommu->stored_l2[i]); 2700 2701 /* Lock PCI setup registers */ 2702 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4, 2703 iommu->stored_addr_lo | 1); 2704 } 2705 2706 static void iommu_enable_ga(struct amd_iommu *iommu) 2707 { 2708 #ifdef CONFIG_IRQ_REMAP 2709 switch (amd_iommu_guest_ir) { 2710 case AMD_IOMMU_GUEST_IR_VAPIC: 2711 case AMD_IOMMU_GUEST_IR_LEGACY_GA: 2712 iommu_feature_enable(iommu, CONTROL_GA_EN); 2713 iommu->irte_ops = &irte_128_ops; 2714 break; 2715 default: 2716 iommu->irte_ops = &irte_32_ops; 2717 break; 2718 } 2719 #endif 2720 } 2721 2722 static void iommu_disable_irtcachedis(struct amd_iommu *iommu) 2723 { 2724 iommu_feature_disable(iommu, CONTROL_IRTCACHEDIS); 2725 } 2726 2727 static void iommu_enable_irtcachedis(struct amd_iommu *iommu) 2728 { 2729 u64 ctrl; 2730 2731 if (!amd_iommu_irtcachedis) 2732 return; 2733 2734 /* 2735 * Note: 2736 * The support for IRTCacheDis feature is dertermined by 2737 * checking if the bit is writable. 2738 */ 2739 iommu_feature_enable(iommu, CONTROL_IRTCACHEDIS); 2740 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); 2741 ctrl &= (1ULL << CONTROL_IRTCACHEDIS); 2742 if (ctrl) 2743 iommu->irtcachedis_enabled = true; 2744 pr_info("iommu%d (%#06x) : IRT cache is %s\n", 2745 iommu->index, iommu->devid, 2746 iommu->irtcachedis_enabled ? "disabled" : "enabled"); 2747 } 2748 2749 static void iommu_enable_2k_int(struct amd_iommu *iommu) 2750 { 2751 if (!FEATURE_NUM_INT_REMAP_SUP_2K(amd_iommu_efr2)) 2752 return; 2753 2754 iommu_feature_set(iommu, 2755 CONTROL_NUM_INT_REMAP_MODE_2K, 2756 CONTROL_NUM_INT_REMAP_MODE_MASK, 2757 CONTROL_NUM_INT_REMAP_MODE); 2758 } 2759 2760 static void early_enable_iommu(struct amd_iommu *iommu) 2761 { 2762 iommu_disable(iommu); 2763 iommu_init_flags(iommu); 2764 iommu_set_device_table(iommu); 2765 iommu_enable_command_buffer(iommu); 2766 iommu_enable_event_buffer(iommu); 2767 iommu_set_exclusion_range(iommu); 2768 iommu_enable_gt(iommu); 2769 iommu_enable_ga(iommu); 2770 iommu_enable_xt(iommu); 2771 iommu_enable_irtcachedis(iommu); 2772 iommu_enable_2k_int(iommu); 2773 iommu_enable(iommu); 2774 amd_iommu_flush_all_caches(iommu); 2775 } 2776 2777 /* 2778 * This function finally enables all IOMMUs found in the system after 2779 * they have been initialized. 2780 * 2781 * Or if in kdump kernel and IOMMUs are all pre-enabled, try to copy 2782 * the old content of device table entries. Not this case or copy failed, 2783 * just continue as normal kernel does. 2784 */ 2785 static void early_enable_iommus(void) 2786 { 2787 struct amd_iommu *iommu; 2788 struct amd_iommu_pci_seg *pci_seg; 2789 2790 if (!copy_device_table()) { 2791 /* 2792 * If come here because of failure in copying device table from old 2793 * kernel with all IOMMUs enabled, print error message and try to 2794 * free allocated old_dev_tbl_cpy. 2795 */ 2796 if (amd_iommu_pre_enabled) 2797 pr_err("Failed to copy DEV table from previous kernel.\n"); 2798 2799 for_each_pci_segment(pci_seg) { 2800 if (pci_seg->old_dev_tbl_cpy != NULL) { 2801 iommu_free_pages(pci_seg->old_dev_tbl_cpy); 2802 pci_seg->old_dev_tbl_cpy = NULL; 2803 } 2804 } 2805 2806 for_each_iommu(iommu) { 2807 clear_translation_pre_enabled(iommu); 2808 early_enable_iommu(iommu); 2809 } 2810 } else { 2811 pr_info("Copied DEV table from previous kernel.\n"); 2812 2813 for_each_pci_segment(pci_seg) { 2814 iommu_free_pages(pci_seg->dev_table); 2815 pci_seg->dev_table = pci_seg->old_dev_tbl_cpy; 2816 } 2817 2818 for_each_iommu(iommu) { 2819 iommu_disable_command_buffer(iommu); 2820 iommu_disable_event_buffer(iommu); 2821 iommu_disable_irtcachedis(iommu); 2822 iommu_enable_command_buffer(iommu); 2823 iommu_enable_event_buffer(iommu); 2824 iommu_enable_ga(iommu); 2825 iommu_enable_xt(iommu); 2826 iommu_enable_irtcachedis(iommu); 2827 iommu_enable_2k_int(iommu); 2828 iommu_set_device_table(iommu); 2829 amd_iommu_flush_all_caches(iommu); 2830 } 2831 } 2832 } 2833 2834 static void enable_iommus_ppr(void) 2835 { 2836 struct amd_iommu *iommu; 2837 2838 if (!amd_iommu_gt_ppr_supported()) 2839 return; 2840 2841 for_each_iommu(iommu) 2842 amd_iommu_enable_ppr_log(iommu); 2843 } 2844 2845 static void enable_iommus_vapic(void) 2846 { 2847 #ifdef CONFIG_IRQ_REMAP 2848 u32 status, i; 2849 struct amd_iommu *iommu; 2850 2851 for_each_iommu(iommu) { 2852 /* 2853 * Disable GALog if already running. It could have been enabled 2854 * in the previous boot before kdump. 2855 */ 2856 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); 2857 if (!(status & MMIO_STATUS_GALOG_RUN_MASK)) 2858 continue; 2859 2860 iommu_feature_disable(iommu, CONTROL_GALOG_EN); 2861 iommu_feature_disable(iommu, CONTROL_GAINT_EN); 2862 2863 /* 2864 * Need to set and poll check the GALOGRun bit to zero before 2865 * we can set/ modify GA Log registers safely. 2866 */ 2867 for (i = 0; i < MMIO_STATUS_TIMEOUT; ++i) { 2868 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); 2869 if (!(status & MMIO_STATUS_GALOG_RUN_MASK)) 2870 break; 2871 udelay(10); 2872 } 2873 2874 if (WARN_ON(i >= MMIO_STATUS_TIMEOUT)) 2875 return; 2876 } 2877 2878 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) && 2879 !check_feature(FEATURE_GAM_VAPIC)) { 2880 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY_GA; 2881 return; 2882 } 2883 2884 if (amd_iommu_snp_en && 2885 !FEATURE_SNPAVICSUP_GAM(amd_iommu_efr2)) { 2886 pr_warn("Force to disable Virtual APIC due to SNP\n"); 2887 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY_GA; 2888 return; 2889 } 2890 2891 /* Enabling GAM and SNPAVIC support */ 2892 for_each_iommu(iommu) { 2893 if (iommu_init_ga_log(iommu) || 2894 iommu_ga_log_enable(iommu)) 2895 return; 2896 2897 iommu_feature_enable(iommu, CONTROL_GAM_EN); 2898 if (amd_iommu_snp_en) 2899 iommu_feature_enable(iommu, CONTROL_SNPAVIC_EN); 2900 } 2901 2902 amd_iommu_irq_ops.capability |= (1 << IRQ_POSTING_CAP); 2903 pr_info("Virtual APIC enabled\n"); 2904 #endif 2905 } 2906 2907 static void disable_iommus(void) 2908 { 2909 struct amd_iommu *iommu; 2910 2911 for_each_iommu(iommu) 2912 iommu_disable(iommu); 2913 2914 #ifdef CONFIG_IRQ_REMAP 2915 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) 2916 amd_iommu_irq_ops.capability &= ~(1 << IRQ_POSTING_CAP); 2917 #endif 2918 } 2919 2920 /* 2921 * Suspend/Resume support 2922 * disable suspend until real resume implemented 2923 */ 2924 2925 static void amd_iommu_resume(void) 2926 { 2927 struct amd_iommu *iommu; 2928 2929 for_each_iommu(iommu) 2930 iommu_apply_resume_quirks(iommu); 2931 2932 /* re-load the hardware */ 2933 for_each_iommu(iommu) 2934 early_enable_iommu(iommu); 2935 2936 amd_iommu_enable_interrupts(); 2937 } 2938 2939 static int amd_iommu_suspend(void) 2940 { 2941 /* disable IOMMUs to go out of the way for BIOS */ 2942 disable_iommus(); 2943 2944 return 0; 2945 } 2946 2947 static struct syscore_ops amd_iommu_syscore_ops = { 2948 .suspend = amd_iommu_suspend, 2949 .resume = amd_iommu_resume, 2950 }; 2951 2952 static void __init free_iommu_resources(void) 2953 { 2954 free_iommu_all(); 2955 free_pci_segments(); 2956 } 2957 2958 /* SB IOAPIC is always on this device in AMD systems */ 2959 #define IOAPIC_SB_DEVID ((0x00 << 8) | PCI_DEVFN(0x14, 0)) 2960 2961 static bool __init check_ioapic_information(void) 2962 { 2963 const char *fw_bug = FW_BUG; 2964 bool ret, has_sb_ioapic; 2965 int idx; 2966 2967 has_sb_ioapic = false; 2968 ret = false; 2969 2970 /* 2971 * If we have map overrides on the kernel command line the 2972 * messages in this function might not describe firmware bugs 2973 * anymore - so be careful 2974 */ 2975 if (cmdline_maps) 2976 fw_bug = ""; 2977 2978 for (idx = 0; idx < nr_ioapics; idx++) { 2979 int devid, id = mpc_ioapic_id(idx); 2980 2981 devid = get_ioapic_devid(id); 2982 if (devid < 0) { 2983 pr_err("%s: IOAPIC[%d] not in IVRS table\n", 2984 fw_bug, id); 2985 ret = false; 2986 } else if (devid == IOAPIC_SB_DEVID) { 2987 has_sb_ioapic = true; 2988 ret = true; 2989 } 2990 } 2991 2992 if (!has_sb_ioapic) { 2993 /* 2994 * We expect the SB IOAPIC to be listed in the IVRS 2995 * table. The system timer is connected to the SB IOAPIC 2996 * and if we don't have it in the list the system will 2997 * panic at boot time. This situation usually happens 2998 * when the BIOS is buggy and provides us the wrong 2999 * device id for the IOAPIC in the system. 3000 */ 3001 pr_err("%s: No southbridge IOAPIC found\n", fw_bug); 3002 } 3003 3004 if (!ret) 3005 pr_err("Disabling interrupt remapping\n"); 3006 3007 return ret; 3008 } 3009 3010 static void __init free_dma_resources(void) 3011 { 3012 ida_destroy(&pdom_ids); 3013 3014 free_unity_maps(); 3015 } 3016 3017 static void __init ivinfo_init(void *ivrs) 3018 { 3019 amd_iommu_ivinfo = *((u32 *)(ivrs + IOMMU_IVINFO_OFFSET)); 3020 } 3021 3022 /* 3023 * This is the hardware init function for AMD IOMMU in the system. 3024 * This function is called either from amd_iommu_init or from the interrupt 3025 * remapping setup code. 3026 * 3027 * This function basically parses the ACPI table for AMD IOMMU (IVRS) 3028 * four times: 3029 * 3030 * 1 pass) Discover the most comprehensive IVHD type to use. 3031 * 3032 * 2 pass) Find the highest PCI device id the driver has to handle. 3033 * Upon this information the size of the data structures is 3034 * determined that needs to be allocated. 3035 * 3036 * 3 pass) Initialize the data structures just allocated with the 3037 * information in the ACPI table about available AMD IOMMUs 3038 * in the system. It also maps the PCI devices in the 3039 * system to specific IOMMUs 3040 * 3041 * 4 pass) After the basic data structures are allocated and 3042 * initialized we update them with information about memory 3043 * remapping requirements parsed out of the ACPI table in 3044 * this last pass. 3045 * 3046 * After everything is set up the IOMMUs are enabled and the necessary 3047 * hotplug and suspend notifiers are registered. 3048 */ 3049 static int __init early_amd_iommu_init(void) 3050 { 3051 struct acpi_table_header *ivrs_base; 3052 int ret; 3053 acpi_status status; 3054 u8 efr_hats; 3055 3056 if (!amd_iommu_detected) 3057 return -ENODEV; 3058 3059 status = acpi_get_table("IVRS", 0, &ivrs_base); 3060 if (status == AE_NOT_FOUND) 3061 return -ENODEV; 3062 else if (ACPI_FAILURE(status)) { 3063 const char *err = acpi_format_exception(status); 3064 pr_err("IVRS table error: %s\n", err); 3065 return -EINVAL; 3066 } 3067 3068 if (!boot_cpu_has(X86_FEATURE_CX16)) { 3069 pr_err("Failed to initialize. The CMPXCHG16B feature is required.\n"); 3070 return -EINVAL; 3071 } 3072 3073 /* 3074 * Validate checksum here so we don't need to do it when 3075 * we actually parse the table 3076 */ 3077 ret = check_ivrs_checksum(ivrs_base); 3078 if (ret) 3079 goto out; 3080 3081 ivinfo_init(ivrs_base); 3082 3083 amd_iommu_target_ivhd_type = get_highest_supported_ivhd_type(ivrs_base); 3084 DUMP_printk("Using IVHD type %#x\n", amd_iommu_target_ivhd_type); 3085 3086 /* 3087 * now the data structures are allocated and basically initialized 3088 * start the real acpi table scan 3089 */ 3090 ret = init_iommu_all(ivrs_base); 3091 if (ret) 3092 goto out; 3093 3094 /* 5 level guest page table */ 3095 if (cpu_feature_enabled(X86_FEATURE_LA57) && 3096 FIELD_GET(FEATURE_GATS, amd_iommu_efr) == GUEST_PGTABLE_5_LEVEL) 3097 amd_iommu_gpt_level = PAGE_MODE_5_LEVEL; 3098 3099 efr_hats = FIELD_GET(FEATURE_HATS, amd_iommu_efr); 3100 if (efr_hats != 0x3) { 3101 /* 3102 * efr[HATS] bits specify the maximum host translation level 3103 * supported, with LEVEL 4 being initial max level. 3104 */ 3105 amd_iommu_hpt_level = efr_hats + PAGE_MODE_4_LEVEL; 3106 } else { 3107 pr_warn_once(FW_BUG "Disable host address translation due to invalid translation level (%#x).\n", 3108 efr_hats); 3109 amd_iommu_hatdis = true; 3110 } 3111 3112 if (amd_iommu_pgtable == PD_MODE_V2) { 3113 if (!amd_iommu_v2_pgtbl_supported()) { 3114 pr_warn("Cannot enable v2 page table for DMA-API. Fallback to v1.\n"); 3115 amd_iommu_pgtable = PD_MODE_V1; 3116 } 3117 } 3118 3119 if (amd_iommu_hatdis) { 3120 /* 3121 * Host (v1) page table is not available. Attempt to use 3122 * Guest (v2) page table. 3123 */ 3124 if (amd_iommu_v2_pgtbl_supported()) 3125 amd_iommu_pgtable = PD_MODE_V2; 3126 else 3127 amd_iommu_pgtable = PD_MODE_NONE; 3128 } 3129 3130 /* Disable any previously enabled IOMMUs */ 3131 if (!is_kdump_kernel() || amd_iommu_disabled) 3132 disable_iommus(); 3133 3134 if (amd_iommu_irq_remap) 3135 amd_iommu_irq_remap = check_ioapic_information(); 3136 3137 if (amd_iommu_irq_remap) { 3138 struct amd_iommu_pci_seg *pci_seg; 3139 ret = -ENOMEM; 3140 for_each_pci_segment(pci_seg) { 3141 if (alloc_irq_lookup_table(pci_seg)) 3142 goto out; 3143 } 3144 } 3145 3146 ret = init_memory_definitions(ivrs_base); 3147 if (ret) 3148 goto out; 3149 3150 /* init the device table */ 3151 init_device_table(); 3152 3153 out: 3154 /* Don't leak any ACPI memory */ 3155 acpi_put_table(ivrs_base); 3156 3157 return ret; 3158 } 3159 3160 static int amd_iommu_enable_interrupts(void) 3161 { 3162 struct amd_iommu *iommu; 3163 int ret = 0; 3164 3165 for_each_iommu(iommu) { 3166 ret = iommu_init_irq(iommu); 3167 if (ret) 3168 goto out; 3169 } 3170 3171 /* 3172 * Interrupt handler is ready to process interrupts. Enable 3173 * PPR and GA log interrupt for all IOMMUs. 3174 */ 3175 enable_iommus_vapic(); 3176 enable_iommus_ppr(); 3177 3178 out: 3179 return ret; 3180 } 3181 3182 static bool __init detect_ivrs(void) 3183 { 3184 struct acpi_table_header *ivrs_base; 3185 acpi_status status; 3186 int i; 3187 3188 status = acpi_get_table("IVRS", 0, &ivrs_base); 3189 if (status == AE_NOT_FOUND) 3190 return false; 3191 else if (ACPI_FAILURE(status)) { 3192 const char *err = acpi_format_exception(status); 3193 pr_err("IVRS table error: %s\n", err); 3194 return false; 3195 } 3196 3197 acpi_put_table(ivrs_base); 3198 3199 if (amd_iommu_force_enable) 3200 goto out; 3201 3202 /* Don't use IOMMU if there is Stoney Ridge graphics */ 3203 for (i = 0; i < 32; i++) { 3204 u32 pci_id; 3205 3206 pci_id = read_pci_config(0, i, 0, 0); 3207 if ((pci_id & 0xffff) == 0x1002 && (pci_id >> 16) == 0x98e4) { 3208 pr_info("Disable IOMMU on Stoney Ridge\n"); 3209 return false; 3210 } 3211 } 3212 3213 out: 3214 /* Make sure ACS will be enabled during PCI probe */ 3215 pci_request_acs(); 3216 3217 return true; 3218 } 3219 3220 static __init void iommu_snp_enable(void) 3221 { 3222 #ifdef CONFIG_KVM_AMD_SEV 3223 if (!cc_platform_has(CC_ATTR_HOST_SEV_SNP)) 3224 return; 3225 /* 3226 * The SNP support requires that IOMMU must be enabled, and is 3227 * configured with V1 page table (DTE[Mode] = 0 is not supported). 3228 */ 3229 if (no_iommu || iommu_default_passthrough()) { 3230 pr_warn("SNP: IOMMU disabled or configured in passthrough mode, SNP cannot be supported.\n"); 3231 goto disable_snp; 3232 } 3233 3234 if (amd_iommu_pgtable != PD_MODE_V1) { 3235 pr_warn("SNP: IOMMU is configured with V2 page table mode, SNP cannot be supported.\n"); 3236 goto disable_snp; 3237 } 3238 3239 amd_iommu_snp_en = check_feature(FEATURE_SNP); 3240 if (!amd_iommu_snp_en) { 3241 pr_warn("SNP: IOMMU SNP feature not enabled, SNP cannot be supported.\n"); 3242 goto disable_snp; 3243 } 3244 3245 /* 3246 * Enable host SNP support once SNP support is checked on IOMMU. 3247 */ 3248 if (snp_rmptable_init()) { 3249 pr_warn("SNP: RMP initialization failed, SNP cannot be supported.\n"); 3250 goto disable_snp; 3251 } 3252 3253 pr_info("IOMMU SNP support enabled.\n"); 3254 return; 3255 3256 disable_snp: 3257 cc_platform_clear(CC_ATTR_HOST_SEV_SNP); 3258 #endif 3259 } 3260 3261 /**************************************************************************** 3262 * 3263 * AMD IOMMU Initialization State Machine 3264 * 3265 ****************************************************************************/ 3266 3267 static int __init state_next(void) 3268 { 3269 int ret = 0; 3270 3271 switch (init_state) { 3272 case IOMMU_START_STATE: 3273 if (!detect_ivrs()) { 3274 init_state = IOMMU_NOT_FOUND; 3275 ret = -ENODEV; 3276 } else { 3277 init_state = IOMMU_IVRS_DETECTED; 3278 } 3279 break; 3280 case IOMMU_IVRS_DETECTED: 3281 if (amd_iommu_disabled) { 3282 init_state = IOMMU_CMDLINE_DISABLED; 3283 ret = -EINVAL; 3284 } else { 3285 ret = early_amd_iommu_init(); 3286 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_ACPI_FINISHED; 3287 } 3288 break; 3289 case IOMMU_ACPI_FINISHED: 3290 early_enable_iommus(); 3291 x86_platform.iommu_shutdown = disable_iommus; 3292 init_state = IOMMU_ENABLED; 3293 break; 3294 case IOMMU_ENABLED: 3295 register_syscore_ops(&amd_iommu_syscore_ops); 3296 iommu_snp_enable(); 3297 ret = amd_iommu_init_pci(); 3298 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_PCI_INIT; 3299 break; 3300 case IOMMU_PCI_INIT: 3301 ret = amd_iommu_enable_interrupts(); 3302 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_INTERRUPTS_EN; 3303 break; 3304 case IOMMU_INTERRUPTS_EN: 3305 init_state = IOMMU_INITIALIZED; 3306 break; 3307 case IOMMU_INITIALIZED: 3308 /* Nothing to do */ 3309 break; 3310 case IOMMU_NOT_FOUND: 3311 case IOMMU_INIT_ERROR: 3312 case IOMMU_CMDLINE_DISABLED: 3313 /* Error states => do nothing */ 3314 ret = -EINVAL; 3315 break; 3316 default: 3317 /* Unknown state */ 3318 BUG(); 3319 } 3320 3321 if (ret) { 3322 free_dma_resources(); 3323 if (!irq_remapping_enabled) { 3324 disable_iommus(); 3325 free_iommu_resources(); 3326 } else { 3327 struct amd_iommu *iommu; 3328 struct amd_iommu_pci_seg *pci_seg; 3329 3330 for_each_pci_segment(pci_seg) 3331 uninit_device_table_dma(pci_seg); 3332 3333 for_each_iommu(iommu) 3334 amd_iommu_flush_all_caches(iommu); 3335 } 3336 } 3337 return ret; 3338 } 3339 3340 static int __init iommu_go_to_state(enum iommu_init_state state) 3341 { 3342 int ret = -EINVAL; 3343 3344 while (init_state != state) { 3345 if (init_state == IOMMU_NOT_FOUND || 3346 init_state == IOMMU_INIT_ERROR || 3347 init_state == IOMMU_CMDLINE_DISABLED) 3348 break; 3349 ret = state_next(); 3350 } 3351 3352 /* 3353 * SNP platform initilazation requires IOMMUs to be fully configured. 3354 * If the SNP support on IOMMUs has NOT been checked, simply mark SNP 3355 * as unsupported. If the SNP support on IOMMUs has been checked and 3356 * host SNP support enabled but RMP enforcement has not been enabled 3357 * in IOMMUs, then the system is in a half-baked state, but can limp 3358 * along as all memory should be Hypervisor-Owned in the RMP. WARN, 3359 * but leave SNP as "supported" to avoid confusing the kernel. 3360 */ 3361 if (ret && cc_platform_has(CC_ATTR_HOST_SEV_SNP) && 3362 !WARN_ON_ONCE(amd_iommu_snp_en)) 3363 cc_platform_clear(CC_ATTR_HOST_SEV_SNP); 3364 3365 return ret; 3366 } 3367 3368 #ifdef CONFIG_IRQ_REMAP 3369 int __init amd_iommu_prepare(void) 3370 { 3371 int ret; 3372 3373 amd_iommu_irq_remap = true; 3374 3375 ret = iommu_go_to_state(IOMMU_ACPI_FINISHED); 3376 if (ret) { 3377 amd_iommu_irq_remap = false; 3378 return ret; 3379 } 3380 3381 return amd_iommu_irq_remap ? 0 : -ENODEV; 3382 } 3383 3384 int __init amd_iommu_enable(void) 3385 { 3386 int ret; 3387 3388 ret = iommu_go_to_state(IOMMU_ENABLED); 3389 if (ret) 3390 return ret; 3391 3392 irq_remapping_enabled = 1; 3393 return amd_iommu_xt_mode; 3394 } 3395 3396 void amd_iommu_disable(void) 3397 { 3398 amd_iommu_suspend(); 3399 } 3400 3401 int amd_iommu_reenable(int mode) 3402 { 3403 amd_iommu_resume(); 3404 3405 return 0; 3406 } 3407 3408 int amd_iommu_enable_faulting(unsigned int cpu) 3409 { 3410 /* We enable MSI later when PCI is initialized */ 3411 return 0; 3412 } 3413 #endif 3414 3415 /* 3416 * This is the core init function for AMD IOMMU hardware in the system. 3417 * This function is called from the generic x86 DMA layer initialization 3418 * code. 3419 */ 3420 static int __init amd_iommu_init(void) 3421 { 3422 int ret; 3423 3424 ret = iommu_go_to_state(IOMMU_INITIALIZED); 3425 #ifdef CONFIG_GART_IOMMU 3426 if (ret && list_empty(&amd_iommu_list)) { 3427 /* 3428 * We failed to initialize the AMD IOMMU - try fallback 3429 * to GART if possible. 3430 */ 3431 gart_iommu_init(); 3432 } 3433 #endif 3434 3435 if (!ret) 3436 amd_iommu_debugfs_setup(); 3437 3438 return ret; 3439 } 3440 3441 static bool amd_iommu_sme_check(void) 3442 { 3443 if (!cc_platform_has(CC_ATTR_HOST_MEM_ENCRYPT) || 3444 (boot_cpu_data.x86 != 0x17)) 3445 return true; 3446 3447 /* For Fam17h, a specific level of support is required */ 3448 if (boot_cpu_data.microcode >= 0x08001205) 3449 return true; 3450 3451 if ((boot_cpu_data.microcode >= 0x08001126) && 3452 (boot_cpu_data.microcode <= 0x080011ff)) 3453 return true; 3454 3455 pr_notice("IOMMU not currently supported when SME is active\n"); 3456 3457 return false; 3458 } 3459 3460 /**************************************************************************** 3461 * 3462 * Early detect code. This code runs at IOMMU detection time in the DMA 3463 * layer. It just looks if there is an IVRS ACPI table to detect AMD 3464 * IOMMUs 3465 * 3466 ****************************************************************************/ 3467 void __init amd_iommu_detect(void) 3468 { 3469 int ret; 3470 3471 if (no_iommu || (iommu_detected && !gart_iommu_aperture)) 3472 goto disable_snp; 3473 3474 if (!amd_iommu_sme_check()) 3475 goto disable_snp; 3476 3477 ret = iommu_go_to_state(IOMMU_IVRS_DETECTED); 3478 if (ret) 3479 goto disable_snp; 3480 3481 amd_iommu_detected = true; 3482 iommu_detected = 1; 3483 x86_init.iommu.iommu_init = amd_iommu_init; 3484 return; 3485 3486 disable_snp: 3487 if (cc_platform_has(CC_ATTR_HOST_SEV_SNP)) 3488 cc_platform_clear(CC_ATTR_HOST_SEV_SNP); 3489 } 3490 3491 /**************************************************************************** 3492 * 3493 * Parsing functions for the AMD IOMMU specific kernel command line 3494 * options. 3495 * 3496 ****************************************************************************/ 3497 3498 static int __init parse_amd_iommu_dump(char *str) 3499 { 3500 amd_iommu_dump = true; 3501 3502 return 1; 3503 } 3504 3505 static int __init parse_amd_iommu_intr(char *str) 3506 { 3507 for (; *str; ++str) { 3508 if (strncmp(str, "legacy", 6) == 0) { 3509 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY_GA; 3510 break; 3511 } 3512 if (strncmp(str, "vapic", 5) == 0) { 3513 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC; 3514 break; 3515 } 3516 } 3517 return 1; 3518 } 3519 3520 static int __init parse_amd_iommu_options(char *str) 3521 { 3522 if (!str) 3523 return -EINVAL; 3524 3525 while (*str) { 3526 if (strncmp(str, "fullflush", 9) == 0) { 3527 pr_warn("amd_iommu=fullflush deprecated; use iommu.strict=1 instead\n"); 3528 iommu_set_dma_strict(); 3529 } else if (strncmp(str, "force_enable", 12) == 0) { 3530 amd_iommu_force_enable = true; 3531 } else if (strncmp(str, "off", 3) == 0) { 3532 amd_iommu_disabled = true; 3533 } else if (strncmp(str, "force_isolation", 15) == 0) { 3534 amd_iommu_force_isolation = true; 3535 } else if (strncmp(str, "pgtbl_v1", 8) == 0) { 3536 amd_iommu_pgtable = PD_MODE_V1; 3537 } else if (strncmp(str, "pgtbl_v2", 8) == 0) { 3538 amd_iommu_pgtable = PD_MODE_V2; 3539 } else if (strncmp(str, "irtcachedis", 11) == 0) { 3540 amd_iommu_irtcachedis = true; 3541 } else if (strncmp(str, "nohugepages", 11) == 0) { 3542 pr_info("Restricting V1 page-sizes to 4KiB"); 3543 amd_iommu_pgsize_bitmap = AMD_IOMMU_PGSIZES_4K; 3544 } else if (strncmp(str, "v2_pgsizes_only", 15) == 0) { 3545 pr_info("Restricting V1 page-sizes to 4KiB/2MiB/1GiB"); 3546 amd_iommu_pgsize_bitmap = AMD_IOMMU_PGSIZES_V2; 3547 } else { 3548 pr_notice("Unknown option - '%s'\n", str); 3549 } 3550 3551 str += strcspn(str, ","); 3552 while (*str == ',') 3553 str++; 3554 } 3555 3556 return 1; 3557 } 3558 3559 static int __init parse_ivrs_ioapic(char *str) 3560 { 3561 u32 seg = 0, bus, dev, fn; 3562 int id, i; 3563 u32 devid; 3564 3565 if (sscanf(str, "=%d@%x:%x.%x", &id, &bus, &dev, &fn) == 4 || 3566 sscanf(str, "=%d@%x:%x:%x.%x", &id, &seg, &bus, &dev, &fn) == 5) 3567 goto found; 3568 3569 if (sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn) == 4 || 3570 sscanf(str, "[%d]=%x:%x:%x.%x", &id, &seg, &bus, &dev, &fn) == 5) { 3571 pr_warn("ivrs_ioapic%s option format deprecated; use ivrs_ioapic=%d@%04x:%02x:%02x.%d instead\n", 3572 str, id, seg, bus, dev, fn); 3573 goto found; 3574 } 3575 3576 pr_err("Invalid command line: ivrs_ioapic%s\n", str); 3577 return 1; 3578 3579 found: 3580 if (early_ioapic_map_size == EARLY_MAP_SIZE) { 3581 pr_err("Early IOAPIC map overflow - ignoring ivrs_ioapic%s\n", 3582 str); 3583 return 1; 3584 } 3585 3586 devid = IVRS_GET_SBDF_ID(seg, bus, dev, fn); 3587 3588 cmdline_maps = true; 3589 i = early_ioapic_map_size++; 3590 early_ioapic_map[i].id = id; 3591 early_ioapic_map[i].devid = devid; 3592 early_ioapic_map[i].cmd_line = true; 3593 3594 return 1; 3595 } 3596 3597 static int __init parse_ivrs_hpet(char *str) 3598 { 3599 u32 seg = 0, bus, dev, fn; 3600 int id, i; 3601 u32 devid; 3602 3603 if (sscanf(str, "=%d@%x:%x.%x", &id, &bus, &dev, &fn) == 4 || 3604 sscanf(str, "=%d@%x:%x:%x.%x", &id, &seg, &bus, &dev, &fn) == 5) 3605 goto found; 3606 3607 if (sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn) == 4 || 3608 sscanf(str, "[%d]=%x:%x:%x.%x", &id, &seg, &bus, &dev, &fn) == 5) { 3609 pr_warn("ivrs_hpet%s option format deprecated; use ivrs_hpet=%d@%04x:%02x:%02x.%d instead\n", 3610 str, id, seg, bus, dev, fn); 3611 goto found; 3612 } 3613 3614 pr_err("Invalid command line: ivrs_hpet%s\n", str); 3615 return 1; 3616 3617 found: 3618 if (early_hpet_map_size == EARLY_MAP_SIZE) { 3619 pr_err("Early HPET map overflow - ignoring ivrs_hpet%s\n", 3620 str); 3621 return 1; 3622 } 3623 3624 devid = IVRS_GET_SBDF_ID(seg, bus, dev, fn); 3625 3626 cmdline_maps = true; 3627 i = early_hpet_map_size++; 3628 early_hpet_map[i].id = id; 3629 early_hpet_map[i].devid = devid; 3630 early_hpet_map[i].cmd_line = true; 3631 3632 return 1; 3633 } 3634 3635 #define ACPIID_LEN (ACPIHID_UID_LEN + ACPIHID_HID_LEN) 3636 3637 static int __init parse_ivrs_acpihid(char *str) 3638 { 3639 u32 seg = 0, bus, dev, fn; 3640 char *hid, *uid, *p, *addr; 3641 char acpiid[ACPIID_LEN] = {0}; 3642 int i; 3643 3644 addr = strchr(str, '@'); 3645 if (!addr) { 3646 addr = strchr(str, '='); 3647 if (!addr) 3648 goto not_found; 3649 3650 ++addr; 3651 3652 if (strlen(addr) > ACPIID_LEN) 3653 goto not_found; 3654 3655 if (sscanf(str, "[%x:%x.%x]=%s", &bus, &dev, &fn, acpiid) == 4 || 3656 sscanf(str, "[%x:%x:%x.%x]=%s", &seg, &bus, &dev, &fn, acpiid) == 5) { 3657 pr_warn("ivrs_acpihid%s option format deprecated; use ivrs_acpihid=%s@%04x:%02x:%02x.%d instead\n", 3658 str, acpiid, seg, bus, dev, fn); 3659 goto found; 3660 } 3661 goto not_found; 3662 } 3663 3664 /* We have the '@', make it the terminator to get just the acpiid */ 3665 *addr++ = 0; 3666 3667 if (strlen(str) > ACPIID_LEN + 1) 3668 goto not_found; 3669 3670 if (sscanf(str, "=%s", acpiid) != 1) 3671 goto not_found; 3672 3673 if (sscanf(addr, "%x:%x.%x", &bus, &dev, &fn) == 3 || 3674 sscanf(addr, "%x:%x:%x.%x", &seg, &bus, &dev, &fn) == 4) 3675 goto found; 3676 3677 not_found: 3678 pr_err("Invalid command line: ivrs_acpihid%s\n", str); 3679 return 1; 3680 3681 found: 3682 p = acpiid; 3683 hid = strsep(&p, ":"); 3684 uid = p; 3685 3686 if (!hid || !(*hid) || !uid) { 3687 pr_err("Invalid command line: hid or uid\n"); 3688 return 1; 3689 } 3690 3691 /* 3692 * Ignore leading zeroes after ':', so e.g., AMDI0095:00 3693 * will match AMDI0095:0 in the second strcmp in acpi_dev_hid_uid_match 3694 */ 3695 while (*uid == '0' && *(uid + 1)) 3696 uid++; 3697 3698 if (strlen(hid) >= ACPIHID_HID_LEN) { 3699 pr_err("Invalid command line: hid is too long\n"); 3700 return 1; 3701 } else if (strlen(uid) >= ACPIHID_UID_LEN) { 3702 pr_err("Invalid command line: uid is too long\n"); 3703 return 1; 3704 } 3705 3706 i = early_acpihid_map_size++; 3707 memcpy(early_acpihid_map[i].hid, hid, strlen(hid)); 3708 memcpy(early_acpihid_map[i].uid, uid, strlen(uid)); 3709 early_acpihid_map[i].devid = IVRS_GET_SBDF_ID(seg, bus, dev, fn); 3710 early_acpihid_map[i].cmd_line = true; 3711 3712 return 1; 3713 } 3714 3715 __setup("amd_iommu_dump", parse_amd_iommu_dump); 3716 __setup("amd_iommu=", parse_amd_iommu_options); 3717 __setup("amd_iommu_intr=", parse_amd_iommu_intr); 3718 __setup("ivrs_ioapic", parse_ivrs_ioapic); 3719 __setup("ivrs_hpet", parse_ivrs_hpet); 3720 __setup("ivrs_acpihid", parse_ivrs_acpihid); 3721 3722 bool amd_iommu_pasid_supported(void) 3723 { 3724 /* CPU page table size should match IOMMU guest page table size */ 3725 if (cpu_feature_enabled(X86_FEATURE_LA57) && 3726 amd_iommu_gpt_level != PAGE_MODE_5_LEVEL) 3727 return false; 3728 3729 /* 3730 * Since DTE[Mode]=0 is prohibited on SNP-enabled system 3731 * (i.e. EFR[SNPSup]=1), IOMMUv2 page table cannot be used without 3732 * setting up IOMMUv1 page table. 3733 */ 3734 return amd_iommu_gt_ppr_supported() && !amd_iommu_snp_en; 3735 } 3736 3737 struct amd_iommu *get_amd_iommu(unsigned int idx) 3738 { 3739 unsigned int i = 0; 3740 struct amd_iommu *iommu; 3741 3742 for_each_iommu(iommu) 3743 if (i++ == idx) 3744 return iommu; 3745 return NULL; 3746 } 3747 3748 /**************************************************************************** 3749 * 3750 * IOMMU EFR Performance Counter support functionality. This code allows 3751 * access to the IOMMU PC functionality. 3752 * 3753 ****************************************************************************/ 3754 3755 u8 amd_iommu_pc_get_max_banks(unsigned int idx) 3756 { 3757 struct amd_iommu *iommu = get_amd_iommu(idx); 3758 3759 if (iommu) 3760 return iommu->max_banks; 3761 3762 return 0; 3763 } 3764 3765 bool amd_iommu_pc_supported(void) 3766 { 3767 return amd_iommu_pc_present; 3768 } 3769 3770 u8 amd_iommu_pc_get_max_counters(unsigned int idx) 3771 { 3772 struct amd_iommu *iommu = get_amd_iommu(idx); 3773 3774 if (iommu) 3775 return iommu->max_counters; 3776 3777 return 0; 3778 } 3779 3780 static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, 3781 u8 fxn, u64 *value, bool is_write) 3782 { 3783 u32 offset; 3784 u32 max_offset_lim; 3785 3786 /* Make sure the IOMMU PC resource is available */ 3787 if (!amd_iommu_pc_present) 3788 return -ENODEV; 3789 3790 /* Check for valid iommu and pc register indexing */ 3791 if (WARN_ON(!iommu || (fxn > 0x28) || (fxn & 7))) 3792 return -ENODEV; 3793 3794 offset = (u32)(((0x40 | bank) << 12) | (cntr << 8) | fxn); 3795 3796 /* Limit the offset to the hw defined mmio region aperture */ 3797 max_offset_lim = (u32)(((0x40 | iommu->max_banks) << 12) | 3798 (iommu->max_counters << 8) | 0x28); 3799 if ((offset < MMIO_CNTR_REG_OFFSET) || 3800 (offset > max_offset_lim)) 3801 return -EINVAL; 3802 3803 if (is_write) { 3804 u64 val = *value & GENMASK_ULL(47, 0); 3805 3806 writel((u32)val, iommu->mmio_base + offset); 3807 writel((val >> 32), iommu->mmio_base + offset + 4); 3808 } else { 3809 *value = readl(iommu->mmio_base + offset + 4); 3810 *value <<= 32; 3811 *value |= readl(iommu->mmio_base + offset); 3812 *value &= GENMASK_ULL(47, 0); 3813 } 3814 3815 return 0; 3816 } 3817 3818 int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value) 3819 { 3820 if (!iommu) 3821 return -EINVAL; 3822 3823 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, false); 3824 } 3825 3826 int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value) 3827 { 3828 if (!iommu) 3829 return -EINVAL; 3830 3831 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, true); 3832 } 3833 3834 #ifdef CONFIG_KVM_AMD_SEV 3835 static int iommu_page_make_shared(void *page) 3836 { 3837 unsigned long paddr, pfn; 3838 3839 paddr = iommu_virt_to_phys(page); 3840 /* Cbit maybe set in the paddr */ 3841 pfn = __sme_clr(paddr) >> PAGE_SHIFT; 3842 3843 if (!(pfn % PTRS_PER_PMD)) { 3844 int ret, level; 3845 bool assigned; 3846 3847 ret = snp_lookup_rmpentry(pfn, &assigned, &level); 3848 if (ret) { 3849 pr_warn("IOMMU PFN %lx RMP lookup failed, ret %d\n", pfn, ret); 3850 return ret; 3851 } 3852 3853 if (!assigned) { 3854 pr_warn("IOMMU PFN %lx not assigned in RMP table\n", pfn); 3855 return -EINVAL; 3856 } 3857 3858 if (level > PG_LEVEL_4K) { 3859 ret = psmash(pfn); 3860 if (!ret) 3861 goto done; 3862 3863 pr_warn("PSMASH failed for IOMMU PFN %lx huge RMP entry, ret: %d, level: %d\n", 3864 pfn, ret, level); 3865 return ret; 3866 } 3867 } 3868 3869 done: 3870 return rmp_make_shared(pfn, PG_LEVEL_4K); 3871 } 3872 3873 static int iommu_make_shared(void *va, size_t size) 3874 { 3875 void *page; 3876 int ret; 3877 3878 if (!va) 3879 return 0; 3880 3881 for (page = va; page < (va + size); page += PAGE_SIZE) { 3882 ret = iommu_page_make_shared(page); 3883 if (ret) 3884 return ret; 3885 } 3886 3887 return 0; 3888 } 3889 3890 int amd_iommu_snp_disable(void) 3891 { 3892 struct amd_iommu *iommu; 3893 int ret; 3894 3895 if (!amd_iommu_snp_en) 3896 return 0; 3897 3898 for_each_iommu(iommu) { 3899 ret = iommu_make_shared(iommu->evt_buf, EVT_BUFFER_SIZE); 3900 if (ret) 3901 return ret; 3902 3903 ret = iommu_make_shared(iommu->ppr_log, PPR_LOG_SIZE); 3904 if (ret) 3905 return ret; 3906 3907 ret = iommu_make_shared((void *)iommu->cmd_sem, PAGE_SIZE); 3908 if (ret) 3909 return ret; 3910 } 3911 3912 return 0; 3913 } 3914 EXPORT_SYMBOL_GPL(amd_iommu_snp_disable); 3915 #endif 3916