1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. 4 * Author: Joerg Roedel <jroedel@suse.de> 5 * Leo Duran <leo.duran@amd.com> 6 */ 7 8 #define pr_fmt(fmt) "AMD-Vi: " fmt 9 #define dev_fmt(fmt) pr_fmt(fmt) 10 11 #include <linux/pci.h> 12 #include <linux/acpi.h> 13 #include <linux/list.h> 14 #include <linux/bitmap.h> 15 #include <linux/syscore_ops.h> 16 #include <linux/interrupt.h> 17 #include <linux/msi.h> 18 #include <linux/irq.h> 19 #include <linux/amd-iommu.h> 20 #include <linux/export.h> 21 #include <linux/kmemleak.h> 22 #include <linux/cc_platform.h> 23 #include <linux/iopoll.h> 24 #include <asm/pci-direct.h> 25 #include <asm/iommu.h> 26 #include <asm/apic.h> 27 #include <asm/gart.h> 28 #include <asm/x86_init.h> 29 #include <asm/io_apic.h> 30 #include <asm/irq_remapping.h> 31 #include <asm/set_memory.h> 32 #include <asm/sev.h> 33 34 #include <linux/crash_dump.h> 35 36 #include "amd_iommu.h" 37 #include "../irq_remapping.h" 38 #include "../iommu-pages.h" 39 40 /* 41 * definitions for the ACPI scanning code 42 */ 43 #define IVRS_HEADER_LENGTH 48 44 45 #define ACPI_IVHD_TYPE_MAX_SUPPORTED 0x40 46 #define ACPI_IVMD_TYPE_ALL 0x20 47 #define ACPI_IVMD_TYPE 0x21 48 #define ACPI_IVMD_TYPE_RANGE 0x22 49 50 #define IVHD_DEV_ALL 0x01 51 #define IVHD_DEV_SELECT 0x02 52 #define IVHD_DEV_SELECT_RANGE_START 0x03 53 #define IVHD_DEV_RANGE_END 0x04 54 #define IVHD_DEV_ALIAS 0x42 55 #define IVHD_DEV_ALIAS_RANGE 0x43 56 #define IVHD_DEV_EXT_SELECT 0x46 57 #define IVHD_DEV_EXT_SELECT_RANGE 0x47 58 #define IVHD_DEV_SPECIAL 0x48 59 #define IVHD_DEV_ACPI_HID 0xf0 60 61 #define UID_NOT_PRESENT 0 62 #define UID_IS_INTEGER 1 63 #define UID_IS_CHARACTER 2 64 65 #define IVHD_SPECIAL_IOAPIC 1 66 #define IVHD_SPECIAL_HPET 2 67 68 #define IVHD_FLAG_HT_TUN_EN_MASK 0x01 69 #define IVHD_FLAG_PASSPW_EN_MASK 0x02 70 #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04 71 #define IVHD_FLAG_ISOC_EN_MASK 0x08 72 73 #define IVMD_FLAG_EXCL_RANGE 0x08 74 #define IVMD_FLAG_IW 0x04 75 #define IVMD_FLAG_IR 0x02 76 #define IVMD_FLAG_UNITY_MAP 0x01 77 78 #define ACPI_DEVFLAG_INITPASS 0x01 79 #define ACPI_DEVFLAG_EXTINT 0x02 80 #define ACPI_DEVFLAG_NMI 0x04 81 #define ACPI_DEVFLAG_SYSMGT1 0x10 82 #define ACPI_DEVFLAG_SYSMGT2 0x20 83 #define ACPI_DEVFLAG_LINT0 0x40 84 #define ACPI_DEVFLAG_LINT1 0x80 85 #define ACPI_DEVFLAG_ATSDIS 0x10000000 86 87 #define IVRS_GET_SBDF_ID(seg, bus, dev, fn) (((seg & 0xffff) << 16) | ((bus & 0xff) << 8) \ 88 | ((dev & 0x1f) << 3) | (fn & 0x7)) 89 90 /* 91 * ACPI table definitions 92 * 93 * These data structures are laid over the table to parse the important values 94 * out of it. 95 */ 96 97 /* 98 * structure describing one IOMMU in the ACPI table. Typically followed by one 99 * or more ivhd_entrys. 100 */ 101 struct ivhd_header { 102 u8 type; 103 u8 flags; 104 u16 length; 105 u16 devid; 106 u16 cap_ptr; 107 u64 mmio_phys; 108 u16 pci_seg; 109 u16 info; 110 u32 efr_attr; 111 112 /* Following only valid on IVHD type 11h and 40h */ 113 u64 efr_reg; /* Exact copy of MMIO_EXT_FEATURES */ 114 u64 efr_reg2; 115 } __attribute__((packed)); 116 117 /* 118 * A device entry describing which devices a specific IOMMU translates and 119 * which requestor ids they use. 120 */ 121 struct ivhd_entry { 122 u8 type; 123 u16 devid; 124 u8 flags; 125 struct_group(ext_hid, 126 u32 ext; 127 u32 hidh; 128 ); 129 u64 cid; 130 u8 uidf; 131 u8 uidl; 132 u8 uid; 133 } __attribute__((packed)); 134 135 /* 136 * An AMD IOMMU memory definition structure. It defines things like exclusion 137 * ranges for devices and regions that should be unity mapped. 138 */ 139 struct ivmd_header { 140 u8 type; 141 u8 flags; 142 u16 length; 143 u16 devid; 144 u16 aux; 145 u16 pci_seg; 146 u8 resv[6]; 147 u64 range_start; 148 u64 range_length; 149 } __attribute__((packed)); 150 151 bool amd_iommu_dump; 152 bool amd_iommu_irq_remap __read_mostly; 153 154 enum protection_domain_mode amd_iommu_pgtable = PD_MODE_V1; 155 /* Host page table level */ 156 u8 amd_iommu_hpt_level; 157 /* Guest page table level */ 158 int amd_iommu_gpt_level = PAGE_MODE_4_LEVEL; 159 160 int amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC; 161 static int amd_iommu_xt_mode = IRQ_REMAP_XAPIC_MODE; 162 163 static bool amd_iommu_detected; 164 static bool amd_iommu_disabled __initdata; 165 static bool amd_iommu_force_enable __initdata; 166 static bool amd_iommu_irtcachedis; 167 static int amd_iommu_target_ivhd_type; 168 169 /* Global EFR and EFR2 registers */ 170 u64 amd_iommu_efr; 171 u64 amd_iommu_efr2; 172 173 /* Host (v1) page table is not supported*/ 174 bool amd_iommu_hatdis; 175 176 /* SNP is enabled on the system? */ 177 bool amd_iommu_snp_en; 178 EXPORT_SYMBOL(amd_iommu_snp_en); 179 180 LIST_HEAD(amd_iommu_pci_seg_list); /* list of all PCI segments */ 181 LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the system */ 182 LIST_HEAD(amd_ivhd_dev_flags_list); /* list of all IVHD device entry settings */ 183 184 /* Number of IOMMUs present in the system */ 185 static int amd_iommus_present; 186 187 /* IOMMUs have a non-present cache? */ 188 bool amd_iommu_np_cache __read_mostly; 189 bool amd_iommu_iotlb_sup __read_mostly = true; 190 191 static bool amd_iommu_pc_present __read_mostly; 192 bool amdr_ivrs_remap_support __read_mostly; 193 194 bool amd_iommu_force_isolation __read_mostly; 195 196 unsigned long amd_iommu_pgsize_bitmap __ro_after_init = AMD_IOMMU_PGSIZES; 197 198 enum iommu_init_state { 199 IOMMU_START_STATE, 200 IOMMU_IVRS_DETECTED, 201 IOMMU_ACPI_FINISHED, 202 IOMMU_ENABLED, 203 IOMMU_PCI_INIT, 204 IOMMU_INTERRUPTS_EN, 205 IOMMU_INITIALIZED, 206 IOMMU_NOT_FOUND, 207 IOMMU_INIT_ERROR, 208 IOMMU_CMDLINE_DISABLED, 209 }; 210 211 /* Early ioapic and hpet maps from kernel command line */ 212 #define EARLY_MAP_SIZE 4 213 static struct devid_map __initdata early_ioapic_map[EARLY_MAP_SIZE]; 214 static struct devid_map __initdata early_hpet_map[EARLY_MAP_SIZE]; 215 static struct acpihid_map_entry __initdata early_acpihid_map[EARLY_MAP_SIZE]; 216 217 static int __initdata early_ioapic_map_size; 218 static int __initdata early_hpet_map_size; 219 static int __initdata early_acpihid_map_size; 220 221 static bool __initdata cmdline_maps; 222 223 static enum iommu_init_state init_state = IOMMU_START_STATE; 224 225 static int amd_iommu_enable_interrupts(void); 226 static void init_device_table_dma(struct amd_iommu_pci_seg *pci_seg); 227 228 static bool amd_iommu_pre_enabled = true; 229 230 static u32 amd_iommu_ivinfo __initdata; 231 232 bool translation_pre_enabled(struct amd_iommu *iommu) 233 { 234 return (iommu->flags & AMD_IOMMU_FLAG_TRANS_PRE_ENABLED); 235 } 236 237 static void clear_translation_pre_enabled(struct amd_iommu *iommu) 238 { 239 iommu->flags &= ~AMD_IOMMU_FLAG_TRANS_PRE_ENABLED; 240 } 241 242 static void init_translation_status(struct amd_iommu *iommu) 243 { 244 u64 ctrl; 245 246 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); 247 if (ctrl & (1<<CONTROL_IOMMU_EN)) 248 iommu->flags |= AMD_IOMMU_FLAG_TRANS_PRE_ENABLED; 249 } 250 251 int amd_iommu_get_num_iommus(void) 252 { 253 return amd_iommus_present; 254 } 255 256 bool amd_iommu_ht_range_ignore(void) 257 { 258 return check_feature2(FEATURE_HT_RANGE_IGNORE); 259 } 260 261 /* 262 * Iterate through all the IOMMUs to get common EFR 263 * masks among all IOMMUs and warn if found inconsistency. 264 */ 265 static __init void get_global_efr(void) 266 { 267 struct amd_iommu *iommu; 268 269 for_each_iommu(iommu) { 270 u64 tmp = iommu->features; 271 u64 tmp2 = iommu->features2; 272 273 if (list_is_first(&iommu->list, &amd_iommu_list)) { 274 amd_iommu_efr = tmp; 275 amd_iommu_efr2 = tmp2; 276 continue; 277 } 278 279 if (amd_iommu_efr == tmp && 280 amd_iommu_efr2 == tmp2) 281 continue; 282 283 pr_err(FW_BUG 284 "Found inconsistent EFR/EFR2 %#llx,%#llx (global %#llx,%#llx) on iommu%d (%04x:%02x:%02x.%01x).\n", 285 tmp, tmp2, amd_iommu_efr, amd_iommu_efr2, 286 iommu->index, iommu->pci_seg->id, 287 PCI_BUS_NUM(iommu->devid), PCI_SLOT(iommu->devid), 288 PCI_FUNC(iommu->devid)); 289 290 amd_iommu_efr &= tmp; 291 amd_iommu_efr2 &= tmp2; 292 } 293 294 pr_info("Using global IVHD EFR:%#llx, EFR2:%#llx\n", amd_iommu_efr, amd_iommu_efr2); 295 } 296 297 /* 298 * For IVHD type 0x11/0x40, EFR is also available via IVHD. 299 * Default to IVHD EFR since it is available sooner 300 * (i.e. before PCI init). 301 */ 302 static void __init early_iommu_features_init(struct amd_iommu *iommu, 303 struct ivhd_header *h) 304 { 305 if (amd_iommu_ivinfo & IOMMU_IVINFO_EFRSUP) { 306 iommu->features = h->efr_reg; 307 iommu->features2 = h->efr_reg2; 308 } 309 if (amd_iommu_ivinfo & IOMMU_IVINFO_DMA_REMAP) 310 amdr_ivrs_remap_support = true; 311 } 312 313 /* Access to l1 and l2 indexed register spaces */ 314 315 static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address) 316 { 317 u32 val; 318 319 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16)); 320 pci_read_config_dword(iommu->dev, 0xfc, &val); 321 return val; 322 } 323 324 static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val) 325 { 326 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31)); 327 pci_write_config_dword(iommu->dev, 0xfc, val); 328 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16)); 329 } 330 331 static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address) 332 { 333 u32 val; 334 335 pci_write_config_dword(iommu->dev, 0xf0, address); 336 pci_read_config_dword(iommu->dev, 0xf4, &val); 337 return val; 338 } 339 340 static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val) 341 { 342 pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8)); 343 pci_write_config_dword(iommu->dev, 0xf4, val); 344 } 345 346 /**************************************************************************** 347 * 348 * AMD IOMMU MMIO register space handling functions 349 * 350 * These functions are used to program the IOMMU device registers in 351 * MMIO space required for that driver. 352 * 353 ****************************************************************************/ 354 355 /* 356 * This function set the exclusion range in the IOMMU. DMA accesses to the 357 * exclusion range are passed through untranslated 358 */ 359 static void iommu_set_exclusion_range(struct amd_iommu *iommu) 360 { 361 u64 start = iommu->exclusion_start & PAGE_MASK; 362 u64 limit = (start + iommu->exclusion_length - 1) & PAGE_MASK; 363 u64 entry; 364 365 if (!iommu->exclusion_start) 366 return; 367 368 entry = start | MMIO_EXCL_ENABLE_MASK; 369 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, 370 &entry, sizeof(entry)); 371 372 entry = limit; 373 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, 374 &entry, sizeof(entry)); 375 } 376 377 static void iommu_set_cwwb_range(struct amd_iommu *iommu) 378 { 379 u64 start = iommu_virt_to_phys((void *)iommu->cmd_sem); 380 u64 entry = start & PM_ADDR_MASK; 381 382 if (!check_feature(FEATURE_SNP)) 383 return; 384 385 /* Note: 386 * Re-purpose Exclusion base/limit registers for Completion wait 387 * write-back base/limit. 388 */ 389 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, 390 &entry, sizeof(entry)); 391 392 /* Note: 393 * Default to 4 Kbytes, which can be specified by setting base 394 * address equal to the limit address. 395 */ 396 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, 397 &entry, sizeof(entry)); 398 } 399 400 /* Programs the physical address of the device table into the IOMMU hardware */ 401 static void iommu_set_device_table(struct amd_iommu *iommu) 402 { 403 u64 entry; 404 u32 dev_table_size = iommu->pci_seg->dev_table_size; 405 void *dev_table = (void *)get_dev_table(iommu); 406 407 BUG_ON(iommu->mmio_base == NULL); 408 409 if (is_kdump_kernel()) 410 return; 411 412 entry = iommu_virt_to_phys(dev_table); 413 entry |= (dev_table_size >> 12) - 1; 414 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET, 415 &entry, sizeof(entry)); 416 } 417 418 static void iommu_feature_set(struct amd_iommu *iommu, u64 val, u64 mask, u8 shift) 419 { 420 u64 ctrl; 421 422 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); 423 mask <<= shift; 424 ctrl &= ~mask; 425 ctrl |= (val << shift) & mask; 426 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); 427 } 428 429 /* Generic functions to enable/disable certain features of the IOMMU. */ 430 void iommu_feature_enable(struct amd_iommu *iommu, u8 bit) 431 { 432 iommu_feature_set(iommu, 1ULL, 1ULL, bit); 433 } 434 435 static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit) 436 { 437 iommu_feature_set(iommu, 0ULL, 1ULL, bit); 438 } 439 440 /* Function to enable the hardware */ 441 static void iommu_enable(struct amd_iommu *iommu) 442 { 443 iommu_feature_enable(iommu, CONTROL_IOMMU_EN); 444 } 445 446 static void iommu_disable(struct amd_iommu *iommu) 447 { 448 if (!iommu->mmio_base) 449 return; 450 451 /* Disable command buffer */ 452 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); 453 454 /* Disable event logging and event interrupts */ 455 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN); 456 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN); 457 458 /* Disable IOMMU GA_LOG */ 459 iommu_feature_disable(iommu, CONTROL_GALOG_EN); 460 iommu_feature_disable(iommu, CONTROL_GAINT_EN); 461 462 /* Disable IOMMU PPR logging */ 463 iommu_feature_disable(iommu, CONTROL_PPRLOG_EN); 464 iommu_feature_disable(iommu, CONTROL_PPRINT_EN); 465 466 /* Disable IOMMU hardware itself */ 467 iommu_feature_disable(iommu, CONTROL_IOMMU_EN); 468 469 /* Clear IRTE cache disabling bit */ 470 iommu_feature_disable(iommu, CONTROL_IRTCACHEDIS); 471 } 472 473 /* 474 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in 475 * the system has one. 476 */ 477 static u8 __iomem * __init iommu_map_mmio_space(u64 address, u64 end) 478 { 479 if (!request_mem_region(address, end, "amd_iommu")) { 480 pr_err("Can not reserve memory region %llx-%llx for mmio\n", 481 address, end); 482 pr_err("This is a BIOS bug. Please contact your hardware vendor\n"); 483 return NULL; 484 } 485 486 return (u8 __iomem *)ioremap(address, end); 487 } 488 489 static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu) 490 { 491 if (iommu->mmio_base) 492 iounmap(iommu->mmio_base); 493 release_mem_region(iommu->mmio_phys, iommu->mmio_phys_end); 494 } 495 496 static inline u32 get_ivhd_header_size(struct ivhd_header *h) 497 { 498 u32 size = 0; 499 500 switch (h->type) { 501 case 0x10: 502 size = 24; 503 break; 504 case 0x11: 505 case 0x40: 506 size = 40; 507 break; 508 } 509 return size; 510 } 511 512 /**************************************************************************** 513 * 514 * The functions below belong to the first pass of AMD IOMMU ACPI table 515 * parsing. In this pass we try to find out the highest device id this 516 * code has to handle. Upon this information the size of the shared data 517 * structures is determined later. 518 * 519 ****************************************************************************/ 520 521 /* 522 * This function calculates the length of a given IVHD entry 523 */ 524 static inline int ivhd_entry_length(u8 *ivhd) 525 { 526 u32 type = ((struct ivhd_entry *)ivhd)->type; 527 528 if (type < 0x80) { 529 return 0x04 << (*ivhd >> 6); 530 } else if (type == IVHD_DEV_ACPI_HID) { 531 /* For ACPI_HID, offset 21 is uid len */ 532 return *((u8 *)ivhd + 21) + 22; 533 } 534 return 0; 535 } 536 537 /* 538 * After reading the highest device id from the IOMMU PCI capability header 539 * this function looks if there is a higher device id defined in the ACPI table 540 */ 541 static int __init find_last_devid_from_ivhd(struct ivhd_header *h) 542 { 543 u8 *p = (void *)h, *end = (void *)h; 544 struct ivhd_entry *dev; 545 int last_devid = -EINVAL; 546 547 u32 ivhd_size = get_ivhd_header_size(h); 548 549 if (!ivhd_size) { 550 pr_err("Unsupported IVHD type %#x\n", h->type); 551 return -EINVAL; 552 } 553 554 p += ivhd_size; 555 end += h->length; 556 557 while (p < end) { 558 dev = (struct ivhd_entry *)p; 559 switch (dev->type) { 560 case IVHD_DEV_ALL: 561 /* Use maximum BDF value for DEV_ALL */ 562 return 0xffff; 563 case IVHD_DEV_SELECT: 564 case IVHD_DEV_RANGE_END: 565 case IVHD_DEV_ALIAS: 566 case IVHD_DEV_EXT_SELECT: 567 /* all the above subfield types refer to device ids */ 568 if (dev->devid > last_devid) 569 last_devid = dev->devid; 570 break; 571 default: 572 break; 573 } 574 p += ivhd_entry_length(p); 575 } 576 577 WARN_ON(p != end); 578 579 return last_devid; 580 } 581 582 static int __init check_ivrs_checksum(struct acpi_table_header *table) 583 { 584 int i; 585 u8 checksum = 0, *p = (u8 *)table; 586 587 for (i = 0; i < table->length; ++i) 588 checksum += p[i]; 589 if (checksum != 0) { 590 /* ACPI table corrupt */ 591 pr_err(FW_BUG "IVRS invalid checksum\n"); 592 return -ENODEV; 593 } 594 595 return 0; 596 } 597 598 /* 599 * Iterate over all IVHD entries in the ACPI table and find the highest device 600 * id which we need to handle. This is the first of three functions which parse 601 * the ACPI table. So we check the checksum here. 602 */ 603 static int __init find_last_devid_acpi(struct acpi_table_header *table, u16 pci_seg) 604 { 605 u8 *p = (u8 *)table, *end = (u8 *)table; 606 struct ivhd_header *h; 607 int last_devid, last_bdf = 0; 608 609 p += IVRS_HEADER_LENGTH; 610 611 end += table->length; 612 while (p < end) { 613 h = (struct ivhd_header *)p; 614 if (h->pci_seg == pci_seg && 615 h->type == amd_iommu_target_ivhd_type) { 616 last_devid = find_last_devid_from_ivhd(h); 617 618 if (last_devid < 0) 619 return -EINVAL; 620 if (last_devid > last_bdf) 621 last_bdf = last_devid; 622 } 623 p += h->length; 624 } 625 WARN_ON(p != end); 626 627 return last_bdf; 628 } 629 630 /**************************************************************************** 631 * 632 * The following functions belong to the code path which parses the ACPI table 633 * the second time. In this ACPI parsing iteration we allocate IOMMU specific 634 * data structures, initialize the per PCI segment device/alias/rlookup table 635 * and also basically initialize the hardware. 636 * 637 ****************************************************************************/ 638 639 /* Allocate per PCI segment device table */ 640 static inline int __init alloc_dev_table(struct amd_iommu_pci_seg *pci_seg) 641 { 642 pci_seg->dev_table = iommu_alloc_pages_sz(GFP_KERNEL | GFP_DMA32, 643 pci_seg->dev_table_size); 644 if (!pci_seg->dev_table) 645 return -ENOMEM; 646 647 return 0; 648 } 649 650 static inline void free_dev_table(struct amd_iommu_pci_seg *pci_seg) 651 { 652 if (is_kdump_kernel()) 653 memunmap((void *)pci_seg->dev_table); 654 else 655 iommu_free_pages(pci_seg->dev_table); 656 pci_seg->dev_table = NULL; 657 } 658 659 /* Allocate per PCI segment IOMMU rlookup table. */ 660 static inline int __init alloc_rlookup_table(struct amd_iommu_pci_seg *pci_seg) 661 { 662 pci_seg->rlookup_table = kvzalloc_objs(*pci_seg->rlookup_table, 663 pci_seg->last_bdf + 1); 664 if (pci_seg->rlookup_table == NULL) 665 return -ENOMEM; 666 667 return 0; 668 } 669 670 static inline void free_rlookup_table(struct amd_iommu_pci_seg *pci_seg) 671 { 672 kvfree(pci_seg->rlookup_table); 673 pci_seg->rlookup_table = NULL; 674 } 675 676 static inline int __init alloc_irq_lookup_table(struct amd_iommu_pci_seg *pci_seg) 677 { 678 pci_seg->irq_lookup_table = kvzalloc_objs(*pci_seg->irq_lookup_table, 679 pci_seg->last_bdf + 1); 680 if (pci_seg->irq_lookup_table == NULL) 681 return -ENOMEM; 682 683 return 0; 684 } 685 686 static inline void free_irq_lookup_table(struct amd_iommu_pci_seg *pci_seg) 687 { 688 kvfree(pci_seg->irq_lookup_table); 689 pci_seg->irq_lookup_table = NULL; 690 } 691 692 static int __init alloc_alias_table(struct amd_iommu_pci_seg *pci_seg) 693 { 694 int i; 695 696 pci_seg->alias_table = kvmalloc_objs(*pci_seg->alias_table, 697 pci_seg->last_bdf + 1); 698 if (!pci_seg->alias_table) 699 return -ENOMEM; 700 701 /* 702 * let all alias entries point to itself 703 */ 704 for (i = 0; i <= pci_seg->last_bdf; ++i) 705 pci_seg->alias_table[i] = i; 706 707 return 0; 708 } 709 710 static void __init free_alias_table(struct amd_iommu_pci_seg *pci_seg) 711 { 712 kvfree(pci_seg->alias_table); 713 pci_seg->alias_table = NULL; 714 } 715 716 static inline void *iommu_memremap(unsigned long paddr, size_t size) 717 { 718 phys_addr_t phys; 719 720 if (!paddr) 721 return NULL; 722 723 /* 724 * Obtain true physical address in kdump kernel when SME is enabled. 725 * Currently, previous kernel with SME enabled and kdump kernel 726 * with SME support disabled is not supported. 727 */ 728 phys = __sme_clr(paddr); 729 730 if (cc_platform_has(CC_ATTR_HOST_MEM_ENCRYPT)) 731 return (__force void *)ioremap_encrypted(phys, size); 732 else 733 return memremap(phys, size, MEMREMAP_WB); 734 } 735 736 /* 737 * Allocates the command buffer. This buffer is per AMD IOMMU. We can 738 * write commands to that buffer later and the IOMMU will execute them 739 * asynchronously 740 */ 741 static int __init alloc_command_buffer(struct amd_iommu *iommu) 742 { 743 iommu->cmd_buf = iommu_alloc_pages_sz(GFP_KERNEL, CMD_BUFFER_SIZE); 744 745 return iommu->cmd_buf ? 0 : -ENOMEM; 746 } 747 748 /* 749 * Interrupt handler has processed all pending events and adjusted head 750 * and tail pointer. Reset overflow mask and restart logging again. 751 */ 752 void amd_iommu_restart_log(struct amd_iommu *iommu, const char *evt_type, 753 u8 cntrl_intr, u8 cntrl_log, 754 u32 status_run_mask, u32 status_overflow_mask) 755 { 756 u32 status; 757 758 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); 759 if (status & status_run_mask) 760 return; 761 762 pr_info_ratelimited("IOMMU %s log restarting\n", evt_type); 763 764 iommu_feature_disable(iommu, cntrl_log); 765 iommu_feature_disable(iommu, cntrl_intr); 766 767 writel(status_overflow_mask, iommu->mmio_base + MMIO_STATUS_OFFSET); 768 769 iommu_feature_enable(iommu, cntrl_intr); 770 iommu_feature_enable(iommu, cntrl_log); 771 } 772 773 /* 774 * This function restarts event logging in case the IOMMU experienced 775 * an event log buffer overflow. 776 */ 777 void amd_iommu_restart_event_logging(struct amd_iommu *iommu) 778 { 779 amd_iommu_restart_log(iommu, "Event", CONTROL_EVT_INT_EN, 780 CONTROL_EVT_LOG_EN, MMIO_STATUS_EVT_RUN_MASK, 781 MMIO_STATUS_EVT_OVERFLOW_MASK); 782 } 783 784 /* 785 * This function restarts event logging in case the IOMMU experienced 786 * GA log overflow. 787 */ 788 void amd_iommu_restart_ga_log(struct amd_iommu *iommu) 789 { 790 amd_iommu_restart_log(iommu, "GA", CONTROL_GAINT_EN, 791 CONTROL_GALOG_EN, MMIO_STATUS_GALOG_RUN_MASK, 792 MMIO_STATUS_GALOG_OVERFLOW_MASK); 793 } 794 795 /* 796 * This function resets the command buffer if the IOMMU stopped fetching 797 * commands from it. 798 */ 799 static void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu) 800 { 801 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); 802 803 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); 804 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); 805 iommu->cmd_buf_head = 0; 806 iommu->cmd_buf_tail = 0; 807 808 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN); 809 } 810 811 /* 812 * This function writes the command buffer address to the hardware and 813 * enables it. 814 */ 815 static void iommu_enable_command_buffer(struct amd_iommu *iommu) 816 { 817 u64 entry; 818 819 BUG_ON(iommu->cmd_buf == NULL); 820 821 if (!is_kdump_kernel()) { 822 /* 823 * Command buffer is re-used for kdump kernel and setting 824 * of MMIO register is not required. 825 */ 826 entry = iommu_virt_to_phys(iommu->cmd_buf); 827 entry |= MMIO_CMD_SIZE_512; 828 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET, 829 &entry, sizeof(entry)); 830 } 831 832 amd_iommu_reset_cmd_buffer(iommu); 833 } 834 835 /* 836 * This function disables the command buffer 837 */ 838 static void iommu_disable_command_buffer(struct amd_iommu *iommu) 839 { 840 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); 841 } 842 843 static void __init free_command_buffer(struct amd_iommu *iommu) 844 { 845 iommu_free_pages(iommu->cmd_buf); 846 } 847 848 void *__init iommu_alloc_4k_pages(struct amd_iommu *iommu, gfp_t gfp, 849 size_t size) 850 { 851 void *buf; 852 853 size = PAGE_ALIGN(size); 854 buf = iommu_alloc_pages_sz(gfp, size); 855 if (!buf) 856 return NULL; 857 if (check_feature(FEATURE_SNP) && 858 set_memory_4k((unsigned long)buf, size / PAGE_SIZE)) { 859 iommu_free_pages(buf); 860 return NULL; 861 } 862 863 return buf; 864 } 865 866 /* allocates the memory where the IOMMU will log its events to */ 867 static int __init alloc_event_buffer(struct amd_iommu *iommu) 868 { 869 iommu->evt_buf = iommu_alloc_4k_pages(iommu, GFP_KERNEL, 870 EVT_BUFFER_SIZE); 871 872 return iommu->evt_buf ? 0 : -ENOMEM; 873 } 874 875 static void iommu_enable_event_buffer(struct amd_iommu *iommu) 876 { 877 u64 entry; 878 879 BUG_ON(iommu->evt_buf == NULL); 880 881 if (!is_kdump_kernel()) { 882 /* 883 * Event buffer is re-used for kdump kernel and setting 884 * of MMIO register is not required. 885 */ 886 entry = iommu_virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK; 887 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET, 888 &entry, sizeof(entry)); 889 } 890 891 /* set head and tail to zero manually */ 892 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); 893 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); 894 895 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN); 896 } 897 898 /* 899 * This function disables the event log buffer 900 */ 901 static void iommu_disable_event_buffer(struct amd_iommu *iommu) 902 { 903 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN); 904 } 905 906 static void __init free_event_buffer(struct amd_iommu *iommu) 907 { 908 iommu_free_pages(iommu->evt_buf); 909 } 910 911 static void free_ga_log(struct amd_iommu *iommu) 912 { 913 #ifdef CONFIG_IRQ_REMAP 914 iommu_free_pages(iommu->ga_log); 915 iommu_free_pages(iommu->ga_log_tail); 916 #endif 917 } 918 919 #ifdef CONFIG_IRQ_REMAP 920 static int iommu_ga_log_enable(struct amd_iommu *iommu) 921 { 922 u32 status, i; 923 u64 entry; 924 925 if (!iommu->ga_log) 926 return -EINVAL; 927 928 entry = iommu_virt_to_phys(iommu->ga_log) | GA_LOG_SIZE_512; 929 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_BASE_OFFSET, 930 &entry, sizeof(entry)); 931 entry = (iommu_virt_to_phys(iommu->ga_log_tail) & 932 (BIT_ULL(52)-1)) & ~7ULL; 933 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_TAIL_OFFSET, 934 &entry, sizeof(entry)); 935 writel(0x00, iommu->mmio_base + MMIO_GA_HEAD_OFFSET); 936 writel(0x00, iommu->mmio_base + MMIO_GA_TAIL_OFFSET); 937 938 939 iommu_feature_enable(iommu, CONTROL_GAINT_EN); 940 iommu_feature_enable(iommu, CONTROL_GALOG_EN); 941 942 for (i = 0; i < MMIO_STATUS_TIMEOUT; ++i) { 943 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); 944 if (status & (MMIO_STATUS_GALOG_RUN_MASK)) 945 break; 946 udelay(10); 947 } 948 949 if (WARN_ON(i >= MMIO_STATUS_TIMEOUT)) 950 return -EINVAL; 951 952 return 0; 953 } 954 955 static int iommu_init_ga_log(struct amd_iommu *iommu) 956 { 957 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) 958 return 0; 959 960 iommu->ga_log = iommu_alloc_pages_sz(GFP_KERNEL, GA_LOG_SIZE); 961 if (!iommu->ga_log) 962 goto err_out; 963 964 iommu->ga_log_tail = iommu_alloc_pages_sz(GFP_KERNEL, 8); 965 if (!iommu->ga_log_tail) 966 goto err_out; 967 968 return 0; 969 err_out: 970 free_ga_log(iommu); 971 return -EINVAL; 972 } 973 #endif /* CONFIG_IRQ_REMAP */ 974 975 static int __init alloc_cwwb_sem(struct amd_iommu *iommu) 976 { 977 iommu->cmd_sem = iommu_alloc_4k_pages(iommu, GFP_KERNEL, 1); 978 if (!iommu->cmd_sem) 979 return -ENOMEM; 980 iommu->cmd_sem_paddr = iommu_virt_to_phys((void *)iommu->cmd_sem); 981 return 0; 982 } 983 984 static int __init remap_event_buffer(struct amd_iommu *iommu) 985 { 986 u64 paddr; 987 988 pr_info_once("Re-using event buffer from the previous kernel\n"); 989 paddr = readq(iommu->mmio_base + MMIO_EVT_BUF_OFFSET) & PM_ADDR_MASK; 990 iommu->evt_buf = iommu_memremap(paddr, EVT_BUFFER_SIZE); 991 992 return iommu->evt_buf ? 0 : -ENOMEM; 993 } 994 995 static int __init remap_command_buffer(struct amd_iommu *iommu) 996 { 997 u64 paddr; 998 999 pr_info_once("Re-using command buffer from the previous kernel\n"); 1000 paddr = readq(iommu->mmio_base + MMIO_CMD_BUF_OFFSET) & PM_ADDR_MASK; 1001 iommu->cmd_buf = iommu_memremap(paddr, CMD_BUFFER_SIZE); 1002 1003 return iommu->cmd_buf ? 0 : -ENOMEM; 1004 } 1005 1006 static int __init remap_or_alloc_cwwb_sem(struct amd_iommu *iommu) 1007 { 1008 u64 paddr; 1009 1010 if (check_feature(FEATURE_SNP)) { 1011 /* 1012 * When SNP is enabled, the exclusion base register is used for the 1013 * completion wait buffer (CWB) address. Read and re-use it. 1014 */ 1015 pr_info_once("Re-using CWB buffers from the previous kernel\n"); 1016 paddr = readq(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET) & PM_ADDR_MASK; 1017 iommu->cmd_sem = iommu_memremap(paddr, PAGE_SIZE); 1018 if (!iommu->cmd_sem) 1019 return -ENOMEM; 1020 iommu->cmd_sem_paddr = paddr; 1021 } else { 1022 return alloc_cwwb_sem(iommu); 1023 } 1024 1025 return 0; 1026 } 1027 1028 static int __init alloc_iommu_buffers(struct amd_iommu *iommu) 1029 { 1030 int ret; 1031 1032 /* 1033 * Reuse/Remap the previous kernel's allocated completion wait 1034 * command and event buffers for kdump boot. 1035 */ 1036 if (is_kdump_kernel()) { 1037 ret = remap_or_alloc_cwwb_sem(iommu); 1038 if (ret) 1039 return ret; 1040 1041 ret = remap_command_buffer(iommu); 1042 if (ret) 1043 return ret; 1044 1045 ret = remap_event_buffer(iommu); 1046 if (ret) 1047 return ret; 1048 } else { 1049 ret = alloc_cwwb_sem(iommu); 1050 if (ret) 1051 return ret; 1052 1053 ret = alloc_command_buffer(iommu); 1054 if (ret) 1055 return ret; 1056 1057 ret = alloc_event_buffer(iommu); 1058 if (ret) 1059 return ret; 1060 } 1061 1062 return 0; 1063 } 1064 1065 static void __init free_cwwb_sem(struct amd_iommu *iommu) 1066 { 1067 if (iommu->cmd_sem) 1068 iommu_free_pages((void *)iommu->cmd_sem); 1069 } 1070 static void __init unmap_cwwb_sem(struct amd_iommu *iommu) 1071 { 1072 if (iommu->cmd_sem) { 1073 if (check_feature(FEATURE_SNP)) 1074 memunmap((void *)iommu->cmd_sem); 1075 else 1076 iommu_free_pages((void *)iommu->cmd_sem); 1077 } 1078 } 1079 1080 static void __init unmap_command_buffer(struct amd_iommu *iommu) 1081 { 1082 memunmap((void *)iommu->cmd_buf); 1083 } 1084 1085 static void __init unmap_event_buffer(struct amd_iommu *iommu) 1086 { 1087 memunmap(iommu->evt_buf); 1088 } 1089 1090 static void __init free_iommu_buffers(struct amd_iommu *iommu) 1091 { 1092 if (is_kdump_kernel()) { 1093 unmap_cwwb_sem(iommu); 1094 unmap_command_buffer(iommu); 1095 unmap_event_buffer(iommu); 1096 } else { 1097 free_cwwb_sem(iommu); 1098 free_command_buffer(iommu); 1099 free_event_buffer(iommu); 1100 } 1101 } 1102 1103 static void iommu_enable_xt(struct amd_iommu *iommu) 1104 { 1105 #ifdef CONFIG_IRQ_REMAP 1106 /* 1107 * XT mode (32-bit APIC destination ID) requires 1108 * GA mode (128-bit IRTE support) as a prerequisite. 1109 */ 1110 if (AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir) && 1111 amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE) 1112 iommu_feature_enable(iommu, CONTROL_XT_EN); 1113 #endif /* CONFIG_IRQ_REMAP */ 1114 } 1115 1116 static void iommu_enable_gt(struct amd_iommu *iommu) 1117 { 1118 if (!check_feature(FEATURE_GT)) 1119 return; 1120 1121 iommu_feature_enable(iommu, CONTROL_GT_EN); 1122 1123 /* 1124 * This feature needs to be enabled prior to a call 1125 * to iommu_snp_enable(). Since this function is called 1126 * in early_enable_iommu(), it is safe to enable here. 1127 */ 1128 if (check_feature2(FEATURE_GCR3TRPMODE)) 1129 iommu_feature_enable(iommu, CONTROL_GCR3TRPMODE); 1130 } 1131 1132 /* sets a specific bit in the device table entry. */ 1133 static void set_dte_bit(struct dev_table_entry *dte, u8 bit) 1134 { 1135 int i = (bit >> 6) & 0x03; 1136 int _bit = bit & 0x3f; 1137 1138 dte->data[i] |= (1UL << _bit); 1139 } 1140 1141 static bool __reuse_device_table(struct amd_iommu *iommu) 1142 { 1143 struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg; 1144 struct dev_table_entry *old_dev_tbl_entry; 1145 u32 lo, hi, old_devtb_size, devid; 1146 phys_addr_t old_devtb_phys; 1147 u16 dom_id; 1148 bool dte_v; 1149 u64 entry; 1150 1151 /* Each IOMMU use separate device table with the same size */ 1152 lo = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET); 1153 hi = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET + 4); 1154 entry = (((u64) hi) << 32) + lo; 1155 1156 old_devtb_size = ((entry & ~PAGE_MASK) + 1) << 12; 1157 if (old_devtb_size != pci_seg->dev_table_size) { 1158 pr_err("The device table size of IOMMU:%d is not expected!\n", 1159 iommu->index); 1160 return false; 1161 } 1162 1163 /* 1164 * When SME is enabled in the first kernel, the entry includes the 1165 * memory encryption mask(sme_me_mask), we must remove the memory 1166 * encryption mask to obtain the true physical address in kdump kernel. 1167 */ 1168 old_devtb_phys = __sme_clr(entry) & PAGE_MASK; 1169 1170 if (old_devtb_phys >= 0x100000000ULL) { 1171 pr_err("The address of old device table is above 4G, not trustworthy!\n"); 1172 return false; 1173 } 1174 1175 /* 1176 * Re-use the previous kernel's device table for kdump. 1177 */ 1178 pci_seg->old_dev_tbl_cpy = iommu_memremap(old_devtb_phys, pci_seg->dev_table_size); 1179 if (pci_seg->old_dev_tbl_cpy == NULL) { 1180 pr_err("Failed to remap memory for reusing old device table!\n"); 1181 return false; 1182 } 1183 1184 for (devid = 0; devid <= pci_seg->last_bdf; devid++) { 1185 old_dev_tbl_entry = &pci_seg->old_dev_tbl_cpy[devid]; 1186 dte_v = FIELD_GET(DTE_FLAG_V, old_dev_tbl_entry->data[0]); 1187 dom_id = FIELD_GET(DTE_DOMID_MASK, old_dev_tbl_entry->data[1]); 1188 1189 if (!dte_v || !dom_id) 1190 continue; 1191 /* 1192 * ID reservation can fail with -ENOSPC when there 1193 * are multiple devices present in the same domain, 1194 * hence check only for -ENOMEM. 1195 */ 1196 if (amd_iommu_pdom_id_reserve(dom_id, GFP_KERNEL) == -ENOMEM) 1197 return false; 1198 } 1199 1200 return true; 1201 } 1202 1203 static bool reuse_device_table(void) 1204 { 1205 struct amd_iommu *iommu; 1206 struct amd_iommu_pci_seg *pci_seg; 1207 1208 if (!amd_iommu_pre_enabled) 1209 return false; 1210 1211 pr_warn("Translation is already enabled - trying to reuse translation structures\n"); 1212 1213 /* 1214 * All IOMMUs within PCI segment shares common device table. 1215 * Hence reuse device table only once per PCI segment. 1216 */ 1217 for_each_pci_segment(pci_seg) { 1218 for_each_iommu(iommu) { 1219 if (pci_seg->id != iommu->pci_seg->id) 1220 continue; 1221 if (!__reuse_device_table(iommu)) 1222 return false; 1223 break; 1224 } 1225 } 1226 1227 return true; 1228 } 1229 1230 struct dev_table_entry *amd_iommu_get_ivhd_dte_flags(u16 segid, u16 devid) 1231 { 1232 struct ivhd_dte_flags *e; 1233 unsigned int best_len = UINT_MAX; 1234 struct dev_table_entry *dte = NULL; 1235 1236 for_each_ivhd_dte_flags(e) { 1237 /* 1238 * Need to go through the whole list to find the smallest range, 1239 * which contains the devid. 1240 */ 1241 if ((e->segid == segid) && 1242 (e->devid_first <= devid) && (devid <= e->devid_last)) { 1243 unsigned int len = e->devid_last - e->devid_first; 1244 1245 if (len < best_len) { 1246 dte = &(e->dte); 1247 best_len = len; 1248 } 1249 } 1250 } 1251 return dte; 1252 } 1253 1254 static bool search_ivhd_dte_flags(u16 segid, u16 first, u16 last) 1255 { 1256 struct ivhd_dte_flags *e; 1257 1258 for_each_ivhd_dte_flags(e) { 1259 if ((e->segid == segid) && 1260 (e->devid_first == first) && 1261 (e->devid_last == last)) 1262 return true; 1263 } 1264 return false; 1265 } 1266 1267 /* 1268 * This function takes the device specific flags read from the ACPI 1269 * table and sets up the device table entry with that information 1270 */ 1271 static void __init 1272 set_dev_entry_from_acpi_range(struct amd_iommu *iommu, u16 first, u16 last, 1273 u32 flags, u32 ext_flags) 1274 { 1275 int i; 1276 struct dev_table_entry dte = {}; 1277 1278 /* Parse IVHD DTE setting flags and store information */ 1279 if (flags) { 1280 struct ivhd_dte_flags *d; 1281 1282 if (search_ivhd_dte_flags(iommu->pci_seg->id, first, last)) 1283 return; 1284 1285 d = kzalloc_obj(struct ivhd_dte_flags); 1286 if (!d) 1287 return; 1288 1289 pr_debug("%s: devid range %#x:%#x\n", __func__, first, last); 1290 1291 if (flags & ACPI_DEVFLAG_INITPASS) 1292 set_dte_bit(&dte, DEV_ENTRY_INIT_PASS); 1293 if (flags & ACPI_DEVFLAG_EXTINT) 1294 set_dte_bit(&dte, DEV_ENTRY_EINT_PASS); 1295 if (flags & ACPI_DEVFLAG_NMI) 1296 set_dte_bit(&dte, DEV_ENTRY_NMI_PASS); 1297 if (flags & ACPI_DEVFLAG_SYSMGT1) 1298 set_dte_bit(&dte, DEV_ENTRY_SYSMGT1); 1299 if (flags & ACPI_DEVFLAG_SYSMGT2) 1300 set_dte_bit(&dte, DEV_ENTRY_SYSMGT2); 1301 if (flags & ACPI_DEVFLAG_LINT0) 1302 set_dte_bit(&dte, DEV_ENTRY_LINT0_PASS); 1303 if (flags & ACPI_DEVFLAG_LINT1) 1304 set_dte_bit(&dte, DEV_ENTRY_LINT1_PASS); 1305 1306 /* Apply erratum 63, which needs info in initial_dte */ 1307 if (FIELD_GET(DTE_DATA1_SYSMGT_MASK, dte.data[1]) == 0x1) 1308 dte.data[0] |= DTE_FLAG_IW; 1309 1310 memcpy(&d->dte, &dte, sizeof(dte)); 1311 d->segid = iommu->pci_seg->id; 1312 d->devid_first = first; 1313 d->devid_last = last; 1314 list_add_tail(&d->list, &amd_ivhd_dev_flags_list); 1315 } 1316 1317 for (i = first; i <= last; i++) { 1318 if (flags) { 1319 struct dev_table_entry *dev_table = get_dev_table(iommu); 1320 1321 memcpy(&dev_table[i], &dte, sizeof(dte)); 1322 } 1323 amd_iommu_set_rlookup_table(iommu, i); 1324 } 1325 } 1326 1327 static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu, 1328 u16 devid, u32 flags, u32 ext_flags) 1329 { 1330 set_dev_entry_from_acpi_range(iommu, devid, devid, flags, ext_flags); 1331 } 1332 1333 int __init add_special_device(u8 type, u8 id, u32 *devid, bool cmd_line) 1334 { 1335 struct devid_map *entry; 1336 struct list_head *list; 1337 1338 if (type == IVHD_SPECIAL_IOAPIC) 1339 list = &ioapic_map; 1340 else if (type == IVHD_SPECIAL_HPET) 1341 list = &hpet_map; 1342 else 1343 return -EINVAL; 1344 1345 list_for_each_entry(entry, list, list) { 1346 if (!(entry->id == id && entry->cmd_line)) 1347 continue; 1348 1349 pr_info("Command-line override present for %s id %d - ignoring\n", 1350 type == IVHD_SPECIAL_IOAPIC ? "IOAPIC" : "HPET", id); 1351 1352 *devid = entry->devid; 1353 1354 return 0; 1355 } 1356 1357 entry = kzalloc_obj(*entry); 1358 if (!entry) 1359 return -ENOMEM; 1360 1361 entry->id = id; 1362 entry->devid = *devid; 1363 entry->cmd_line = cmd_line; 1364 1365 list_add_tail(&entry->list, list); 1366 1367 return 0; 1368 } 1369 1370 static int __init add_acpi_hid_device(u8 *hid, u8 *uid, u32 *devid, 1371 bool cmd_line) 1372 { 1373 struct acpihid_map_entry *entry; 1374 struct list_head *list = &acpihid_map; 1375 1376 list_for_each_entry(entry, list, list) { 1377 if (strcmp(entry->hid, hid) || 1378 (*uid && *entry->uid && strcmp(entry->uid, uid)) || 1379 !entry->cmd_line) 1380 continue; 1381 1382 pr_info("Command-line override for hid:%s uid:%s\n", 1383 hid, uid); 1384 *devid = entry->devid; 1385 return 0; 1386 } 1387 1388 entry = kzalloc_obj(*entry); 1389 if (!entry) 1390 return -ENOMEM; 1391 1392 memcpy(entry->uid, uid, strlen(uid)); 1393 memcpy(entry->hid, hid, strlen(hid)); 1394 entry->devid = *devid; 1395 entry->cmd_line = cmd_line; 1396 entry->root_devid = (entry->devid & (~0x7)); 1397 1398 pr_info("%s, add hid:%s, uid:%s, rdevid:%#x\n", 1399 entry->cmd_line ? "cmd" : "ivrs", 1400 entry->hid, entry->uid, entry->root_devid); 1401 1402 list_add_tail(&entry->list, list); 1403 return 0; 1404 } 1405 1406 static int __init add_early_maps(void) 1407 { 1408 int i, ret; 1409 1410 for (i = 0; i < early_ioapic_map_size; ++i) { 1411 ret = add_special_device(IVHD_SPECIAL_IOAPIC, 1412 early_ioapic_map[i].id, 1413 &early_ioapic_map[i].devid, 1414 early_ioapic_map[i].cmd_line); 1415 if (ret) 1416 return ret; 1417 } 1418 1419 for (i = 0; i < early_hpet_map_size; ++i) { 1420 ret = add_special_device(IVHD_SPECIAL_HPET, 1421 early_hpet_map[i].id, 1422 &early_hpet_map[i].devid, 1423 early_hpet_map[i].cmd_line); 1424 if (ret) 1425 return ret; 1426 } 1427 1428 for (i = 0; i < early_acpihid_map_size; ++i) { 1429 ret = add_acpi_hid_device(early_acpihid_map[i].hid, 1430 early_acpihid_map[i].uid, 1431 &early_acpihid_map[i].devid, 1432 early_acpihid_map[i].cmd_line); 1433 if (ret) 1434 return ret; 1435 } 1436 1437 return 0; 1438 } 1439 1440 /* 1441 * Takes a pointer to an AMD IOMMU entry in the ACPI table and 1442 * initializes the hardware and our data structures with it. 1443 */ 1444 static int __init init_iommu_from_acpi(struct amd_iommu *iommu, 1445 struct ivhd_header *h) 1446 { 1447 u8 *p = (u8 *)h; 1448 u8 *end = p, flags = 0; 1449 u16 devid = 0, devid_start = 0, devid_to = 0, seg_id; 1450 u32 dev_i, ext_flags = 0; 1451 bool alias = false; 1452 struct ivhd_entry *e; 1453 struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg; 1454 u32 ivhd_size; 1455 int ret; 1456 1457 1458 ret = add_early_maps(); 1459 if (ret) 1460 return ret; 1461 1462 amd_iommu_apply_ivrs_quirks(); 1463 1464 /* 1465 * First save the recommended feature enable bits from ACPI 1466 */ 1467 iommu->acpi_flags = h->flags; 1468 1469 /* 1470 * Done. Now parse the device entries 1471 */ 1472 ivhd_size = get_ivhd_header_size(h); 1473 if (!ivhd_size) { 1474 pr_err("Unsupported IVHD type %#x\n", h->type); 1475 return -EINVAL; 1476 } 1477 1478 p += ivhd_size; 1479 1480 end += h->length; 1481 1482 1483 while (p < end) { 1484 e = (struct ivhd_entry *)p; 1485 seg_id = pci_seg->id; 1486 1487 switch (e->type) { 1488 case IVHD_DEV_ALL: 1489 1490 DUMP_printk(" DEV_ALL\t\t\tsetting: %#02x\n", e->flags); 1491 set_dev_entry_from_acpi_range(iommu, 0, pci_seg->last_bdf, e->flags, 0); 1492 break; 1493 case IVHD_DEV_SELECT: 1494 1495 DUMP_printk(" DEV_SELECT\t\t\tdevid: %04x:%02x:%02x.%x flags: %#02x\n", 1496 seg_id, PCI_BUS_NUM(e->devid), 1497 PCI_SLOT(e->devid), 1498 PCI_FUNC(e->devid), 1499 e->flags); 1500 1501 devid = e->devid; 1502 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); 1503 break; 1504 case IVHD_DEV_SELECT_RANGE_START: 1505 1506 DUMP_printk(" DEV_SELECT_RANGE_START\tdevid: %04x:%02x:%02x.%x flags: %#02x\n", 1507 seg_id, PCI_BUS_NUM(e->devid), 1508 PCI_SLOT(e->devid), 1509 PCI_FUNC(e->devid), 1510 e->flags); 1511 1512 devid_start = e->devid; 1513 flags = e->flags; 1514 ext_flags = 0; 1515 alias = false; 1516 break; 1517 case IVHD_DEV_ALIAS: 1518 1519 DUMP_printk(" DEV_ALIAS\t\t\tdevid: %04x:%02x:%02x.%x flags: %#02x devid_to: %02x:%02x.%x\n", 1520 seg_id, PCI_BUS_NUM(e->devid), 1521 PCI_SLOT(e->devid), 1522 PCI_FUNC(e->devid), 1523 e->flags, 1524 PCI_BUS_NUM(e->ext >> 8), 1525 PCI_SLOT(e->ext >> 8), 1526 PCI_FUNC(e->ext >> 8)); 1527 1528 devid = e->devid; 1529 devid_to = e->ext >> 8; 1530 set_dev_entry_from_acpi(iommu, devid , e->flags, 0); 1531 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0); 1532 pci_seg->alias_table[devid] = devid_to; 1533 break; 1534 case IVHD_DEV_ALIAS_RANGE: 1535 1536 DUMP_printk(" DEV_ALIAS_RANGE\t\tdevid: %04x:%02x:%02x.%x flags: %#02x devid_to: %04x:%02x:%02x.%x\n", 1537 seg_id, PCI_BUS_NUM(e->devid), 1538 PCI_SLOT(e->devid), 1539 PCI_FUNC(e->devid), 1540 e->flags, 1541 seg_id, PCI_BUS_NUM(e->ext >> 8), 1542 PCI_SLOT(e->ext >> 8), 1543 PCI_FUNC(e->ext >> 8)); 1544 1545 devid_start = e->devid; 1546 flags = e->flags; 1547 devid_to = e->ext >> 8; 1548 ext_flags = 0; 1549 alias = true; 1550 break; 1551 case IVHD_DEV_EXT_SELECT: 1552 1553 DUMP_printk(" DEV_EXT_SELECT\t\tdevid: %04x:%02x:%02x.%x flags: %#02x ext: %08x\n", 1554 seg_id, PCI_BUS_NUM(e->devid), 1555 PCI_SLOT(e->devid), 1556 PCI_FUNC(e->devid), 1557 e->flags, e->ext); 1558 1559 devid = e->devid; 1560 set_dev_entry_from_acpi(iommu, devid, e->flags, 1561 e->ext); 1562 break; 1563 case IVHD_DEV_EXT_SELECT_RANGE: 1564 1565 DUMP_printk(" DEV_EXT_SELECT_RANGE\tdevid: %04x:%02x:%02x.%x flags: %#02x ext: %08x\n", 1566 seg_id, PCI_BUS_NUM(e->devid), 1567 PCI_SLOT(e->devid), 1568 PCI_FUNC(e->devid), 1569 e->flags, e->ext); 1570 1571 devid_start = e->devid; 1572 flags = e->flags; 1573 ext_flags = e->ext; 1574 alias = false; 1575 break; 1576 case IVHD_DEV_RANGE_END: 1577 1578 DUMP_printk(" DEV_RANGE_END\t\tdevid: %04x:%02x:%02x.%x\n", 1579 seg_id, PCI_BUS_NUM(e->devid), 1580 PCI_SLOT(e->devid), 1581 PCI_FUNC(e->devid)); 1582 1583 devid = e->devid; 1584 if (alias) { 1585 for (dev_i = devid_start; dev_i <= devid; ++dev_i) 1586 pci_seg->alias_table[dev_i] = devid_to; 1587 set_dev_entry_from_acpi(iommu, devid_to, flags, ext_flags); 1588 } 1589 set_dev_entry_from_acpi_range(iommu, devid_start, devid, flags, ext_flags); 1590 break; 1591 case IVHD_DEV_SPECIAL: { 1592 u8 handle, type; 1593 const char *var; 1594 u32 devid; 1595 int ret; 1596 1597 handle = e->ext & 0xff; 1598 devid = PCI_SEG_DEVID_TO_SBDF(seg_id, (e->ext >> 8)); 1599 type = (e->ext >> 24) & 0xff; 1600 1601 if (type == IVHD_SPECIAL_IOAPIC) 1602 var = "IOAPIC"; 1603 else if (type == IVHD_SPECIAL_HPET) 1604 var = "HPET"; 1605 else 1606 var = "UNKNOWN"; 1607 1608 DUMP_printk(" DEV_SPECIAL(%s[%d])\t\tdevid: %04x:%02x:%02x.%x, flags: %#02x\n", 1609 var, (int)handle, 1610 seg_id, PCI_BUS_NUM(devid), 1611 PCI_SLOT(devid), 1612 PCI_FUNC(devid), 1613 e->flags); 1614 1615 ret = add_special_device(type, handle, &devid, false); 1616 if (ret) 1617 return ret; 1618 1619 /* 1620 * add_special_device might update the devid in case a 1621 * command-line override is present. So call 1622 * set_dev_entry_from_acpi after add_special_device. 1623 */ 1624 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); 1625 1626 break; 1627 } 1628 case IVHD_DEV_ACPI_HID: { 1629 u32 devid; 1630 u8 hid[ACPIHID_HID_LEN]; 1631 u8 uid[ACPIHID_UID_LEN]; 1632 int ret; 1633 1634 if (h->type != 0x40) { 1635 pr_err(FW_BUG "Invalid IVHD device type %#x\n", 1636 e->type); 1637 break; 1638 } 1639 1640 BUILD_BUG_ON(sizeof(e->ext_hid) != ACPIHID_HID_LEN - 1); 1641 memcpy(hid, &e->ext_hid, ACPIHID_HID_LEN - 1); 1642 hid[ACPIHID_HID_LEN - 1] = '\0'; 1643 1644 if (!(*hid)) { 1645 pr_err(FW_BUG "Invalid HID.\n"); 1646 break; 1647 } 1648 1649 uid[0] = '\0'; 1650 switch (e->uidf) { 1651 case UID_NOT_PRESENT: 1652 1653 if (e->uidl != 0) 1654 pr_warn(FW_BUG "Invalid UID length.\n"); 1655 1656 break; 1657 case UID_IS_INTEGER: 1658 1659 sprintf(uid, "%d", e->uid); 1660 1661 break; 1662 case UID_IS_CHARACTER: 1663 1664 memcpy(uid, &e->uid, e->uidl); 1665 uid[e->uidl] = '\0'; 1666 1667 break; 1668 default: 1669 break; 1670 } 1671 1672 devid = PCI_SEG_DEVID_TO_SBDF(seg_id, e->devid); 1673 DUMP_printk(" DEV_ACPI_HID(%s[%s])\t\tdevid: %04x:%02x:%02x.%x, flags: %#02x\n", 1674 hid, uid, seg_id, 1675 PCI_BUS_NUM(devid), 1676 PCI_SLOT(devid), 1677 PCI_FUNC(devid), 1678 e->flags); 1679 1680 flags = e->flags; 1681 1682 ret = add_acpi_hid_device(hid, uid, &devid, false); 1683 if (ret) 1684 return ret; 1685 1686 /* 1687 * add_special_device might update the devid in case a 1688 * command-line override is present. So call 1689 * set_dev_entry_from_acpi after add_special_device. 1690 */ 1691 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); 1692 1693 break; 1694 } 1695 default: 1696 break; 1697 } 1698 1699 p += ivhd_entry_length(p); 1700 } 1701 1702 return 0; 1703 } 1704 1705 /* Allocate PCI segment data structure */ 1706 static struct amd_iommu_pci_seg *__init alloc_pci_segment(u16 id, 1707 struct acpi_table_header *ivrs_base) 1708 { 1709 struct amd_iommu_pci_seg *pci_seg; 1710 int last_bdf; 1711 1712 /* 1713 * First parse ACPI tables to find the largest Bus/Dev/Func we need to 1714 * handle in this PCI segment. Upon this information the shared data 1715 * structures for the PCI segments in the system will be allocated. 1716 */ 1717 last_bdf = find_last_devid_acpi(ivrs_base, id); 1718 if (last_bdf < 0) 1719 return NULL; 1720 1721 pci_seg = kzalloc_obj(struct amd_iommu_pci_seg); 1722 if (pci_seg == NULL) 1723 return NULL; 1724 1725 pci_seg->last_bdf = last_bdf; 1726 DUMP_printk("PCI segment : 0x%0x, last bdf : 0x%04x\n", id, last_bdf); 1727 pci_seg->dev_table_size = 1728 max(roundup_pow_of_two((last_bdf + 1) * DEV_TABLE_ENTRY_SIZE), 1729 SZ_4K); 1730 1731 pci_seg->id = id; 1732 init_llist_head(&pci_seg->dev_data_list); 1733 INIT_LIST_HEAD(&pci_seg->unity_map); 1734 list_add_tail(&pci_seg->list, &amd_iommu_pci_seg_list); 1735 1736 if (alloc_dev_table(pci_seg)) 1737 goto err_free_pci_seg; 1738 if (alloc_alias_table(pci_seg)) 1739 goto err_free_dev_table; 1740 if (alloc_rlookup_table(pci_seg)) 1741 goto err_free_alias_table; 1742 1743 return pci_seg; 1744 1745 err_free_alias_table: 1746 free_alias_table(pci_seg); 1747 err_free_dev_table: 1748 free_dev_table(pci_seg); 1749 err_free_pci_seg: 1750 list_del(&pci_seg->list); 1751 kfree(pci_seg); 1752 return NULL; 1753 } 1754 1755 static struct amd_iommu_pci_seg *__init get_pci_segment(u16 id, 1756 struct acpi_table_header *ivrs_base) 1757 { 1758 struct amd_iommu_pci_seg *pci_seg; 1759 1760 for_each_pci_segment(pci_seg) { 1761 if (pci_seg->id == id) 1762 return pci_seg; 1763 } 1764 1765 return alloc_pci_segment(id, ivrs_base); 1766 } 1767 1768 static void __init free_pci_segments(void) 1769 { 1770 struct amd_iommu_pci_seg *pci_seg, *next; 1771 1772 for_each_pci_segment_safe(pci_seg, next) { 1773 list_del(&pci_seg->list); 1774 free_irq_lookup_table(pci_seg); 1775 free_rlookup_table(pci_seg); 1776 free_alias_table(pci_seg); 1777 free_dev_table(pci_seg); 1778 kfree(pci_seg); 1779 } 1780 } 1781 1782 static void __init free_sysfs(struct amd_iommu *iommu) 1783 { 1784 if (iommu->iommu.dev) { 1785 iommu_device_unregister(&iommu->iommu); 1786 iommu_device_sysfs_remove(&iommu->iommu); 1787 } 1788 } 1789 1790 static void __init free_iommu_one(struct amd_iommu *iommu) 1791 { 1792 free_sysfs(iommu); 1793 free_iommu_buffers(iommu); 1794 amd_iommu_free_ppr_log(iommu); 1795 free_ga_log(iommu); 1796 iommu_unmap_mmio_space(iommu); 1797 amd_iommu_iopf_uninit(iommu); 1798 } 1799 1800 static void __init free_iommu_all(void) 1801 { 1802 struct amd_iommu *iommu, *next; 1803 1804 for_each_iommu_safe(iommu, next) { 1805 list_del(&iommu->list); 1806 free_iommu_one(iommu); 1807 kfree(iommu); 1808 } 1809 } 1810 1811 /* 1812 * Family15h Model 10h-1fh erratum 746 (IOMMU Logging May Stall Translations) 1813 * Workaround: 1814 * BIOS should disable L2B micellaneous clock gating by setting 1815 * L2_L2B_CK_GATE_CONTROL[CKGateL2BMiscDisable](D0F2xF4_x90[2]) = 1b 1816 */ 1817 static void amd_iommu_erratum_746_workaround(struct amd_iommu *iommu) 1818 { 1819 u32 value; 1820 1821 if ((boot_cpu_data.x86 != 0x15) || 1822 (boot_cpu_data.x86_model < 0x10) || 1823 (boot_cpu_data.x86_model > 0x1f)) 1824 return; 1825 1826 pci_write_config_dword(iommu->dev, 0xf0, 0x90); 1827 pci_read_config_dword(iommu->dev, 0xf4, &value); 1828 1829 if (value & BIT(2)) 1830 return; 1831 1832 /* Select NB indirect register 0x90 and enable writing */ 1833 pci_write_config_dword(iommu->dev, 0xf0, 0x90 | (1 << 8)); 1834 1835 pci_write_config_dword(iommu->dev, 0xf4, value | 0x4); 1836 pci_info(iommu->dev, "Applying erratum 746 workaround\n"); 1837 1838 /* Clear the enable writing bit */ 1839 pci_write_config_dword(iommu->dev, 0xf0, 0x90); 1840 } 1841 1842 /* 1843 * Family15h Model 30h-3fh (IOMMU Mishandles ATS Write Permission) 1844 * Workaround: 1845 * BIOS should enable ATS write permission check by setting 1846 * L2_DEBUG_3[AtsIgnoreIWDis](D0F2xF4_x47[0]) = 1b 1847 */ 1848 static void amd_iommu_ats_write_check_workaround(struct amd_iommu *iommu) 1849 { 1850 u32 value; 1851 1852 if ((boot_cpu_data.x86 != 0x15) || 1853 (boot_cpu_data.x86_model < 0x30) || 1854 (boot_cpu_data.x86_model > 0x3f)) 1855 return; 1856 1857 /* Test L2_DEBUG_3[AtsIgnoreIWDis] == 1 */ 1858 value = iommu_read_l2(iommu, 0x47); 1859 1860 if (value & BIT(0)) 1861 return; 1862 1863 /* Set L2_DEBUG_3[AtsIgnoreIWDis] = 1 */ 1864 iommu_write_l2(iommu, 0x47, value | BIT(0)); 1865 1866 pci_info(iommu->dev, "Applying ATS write check workaround\n"); 1867 } 1868 1869 /* 1870 * This function glues the initialization function for one IOMMU 1871 * together and also allocates the command buffer and programs the 1872 * hardware. It does NOT enable the IOMMU. This is done afterwards. 1873 */ 1874 static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h, 1875 struct acpi_table_header *ivrs_base) 1876 { 1877 struct amd_iommu_pci_seg *pci_seg; 1878 1879 pci_seg = get_pci_segment(h->pci_seg, ivrs_base); 1880 if (pci_seg == NULL) 1881 return -ENOMEM; 1882 iommu->pci_seg = pci_seg; 1883 1884 raw_spin_lock_init(&iommu->lock); 1885 iommu->cmd_sem_val = 0; 1886 1887 /* Add IOMMU to internal data structures */ 1888 list_add_tail(&iommu->list, &amd_iommu_list); 1889 iommu->index = amd_iommus_present++; 1890 1891 if (unlikely(iommu->index >= MAX_IOMMUS)) { 1892 WARN(1, "System has more IOMMUs than supported by this driver\n"); 1893 return -ENOSYS; 1894 } 1895 1896 /* 1897 * Copy data from ACPI table entry to the iommu struct 1898 */ 1899 iommu->devid = h->devid; 1900 iommu->cap_ptr = h->cap_ptr; 1901 iommu->mmio_phys = h->mmio_phys; 1902 1903 switch (h->type) { 1904 case 0x10: 1905 /* Check if IVHD EFR contains proper max banks/counters */ 1906 if ((h->efr_attr != 0) && 1907 ((h->efr_attr & (0xF << 13)) != 0) && 1908 ((h->efr_attr & (0x3F << 17)) != 0)) 1909 iommu->mmio_phys_end = MMIO_REG_END_OFFSET; 1910 else 1911 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET; 1912 1913 /* GAM requires GA mode. */ 1914 if ((h->efr_attr & (0x1 << IOMMU_FEAT_GASUP_SHIFT)) == 0) 1915 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY; 1916 break; 1917 case 0x11: 1918 case 0x40: 1919 if (h->efr_reg & (1 << 9)) 1920 iommu->mmio_phys_end = MMIO_REG_END_OFFSET; 1921 else 1922 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET; 1923 1924 /* XT and GAM require GA mode. */ 1925 if ((h->efr_reg & (0x1 << IOMMU_EFR_GASUP_SHIFT)) == 0) { 1926 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY; 1927 break; 1928 } 1929 1930 if (h->efr_reg & BIT(IOMMU_EFR_XTSUP_SHIFT)) 1931 amd_iommu_xt_mode = IRQ_REMAP_X2APIC_MODE; 1932 1933 if (h->efr_attr & BIT(IOMMU_IVHD_ATTR_HATDIS_SHIFT)) { 1934 pr_warn_once("Host Address Translation is not supported.\n"); 1935 amd_iommu_hatdis = true; 1936 } 1937 1938 early_iommu_features_init(iommu, h); 1939 1940 break; 1941 default: 1942 return -EINVAL; 1943 } 1944 1945 iommu->mmio_base = iommu_map_mmio_space(iommu->mmio_phys, 1946 iommu->mmio_phys_end); 1947 if (!iommu->mmio_base) 1948 return -ENOMEM; 1949 1950 return init_iommu_from_acpi(iommu, h); 1951 } 1952 1953 static int __init init_iommu_one_late(struct amd_iommu *iommu) 1954 { 1955 int ret; 1956 1957 ret = alloc_iommu_buffers(iommu); 1958 if (ret) 1959 return ret; 1960 1961 iommu->int_enabled = false; 1962 1963 init_translation_status(iommu); 1964 if (translation_pre_enabled(iommu) && !is_kdump_kernel()) { 1965 iommu_disable(iommu); 1966 clear_translation_pre_enabled(iommu); 1967 pr_warn("Translation was enabled for IOMMU:%d but we are not in kdump mode\n", 1968 iommu->index); 1969 } 1970 if (amd_iommu_pre_enabled) 1971 amd_iommu_pre_enabled = translation_pre_enabled(iommu); 1972 1973 if (amd_iommu_irq_remap) { 1974 ret = amd_iommu_create_irq_domain(iommu); 1975 if (ret) 1976 return ret; 1977 } 1978 1979 /* 1980 * Make sure IOMMU is not considered to translate itself. The IVRS 1981 * table tells us so, but this is a lie! 1982 */ 1983 iommu->pci_seg->rlookup_table[iommu->devid] = NULL; 1984 1985 return 0; 1986 } 1987 1988 /** 1989 * get_highest_supported_ivhd_type - Look up the appropriate IVHD type 1990 * @ivrs: Pointer to the IVRS header 1991 * 1992 * This function search through all IVDB of the maximum supported IVHD 1993 */ 1994 static u8 get_highest_supported_ivhd_type(struct acpi_table_header *ivrs) 1995 { 1996 u8 *base = (u8 *)ivrs; 1997 struct ivhd_header *ivhd = (struct ivhd_header *) 1998 (base + IVRS_HEADER_LENGTH); 1999 u8 last_type = ivhd->type; 2000 u16 devid = ivhd->devid; 2001 2002 while (((u8 *)ivhd - base < ivrs->length) && 2003 (ivhd->type <= ACPI_IVHD_TYPE_MAX_SUPPORTED)) { 2004 u8 *p = (u8 *) ivhd; 2005 2006 if (ivhd->devid == devid) 2007 last_type = ivhd->type; 2008 ivhd = (struct ivhd_header *)(p + ivhd->length); 2009 } 2010 2011 return last_type; 2012 } 2013 2014 /* 2015 * Iterates over all IOMMU entries in the ACPI table, allocates the 2016 * IOMMU structure and initializes it with init_iommu_one() 2017 */ 2018 static int __init init_iommu_all(struct acpi_table_header *table) 2019 { 2020 u8 *p = (u8 *)table, *end = (u8 *)table; 2021 struct ivhd_header *h; 2022 struct amd_iommu *iommu; 2023 int ret; 2024 2025 end += table->length; 2026 p += IVRS_HEADER_LENGTH; 2027 2028 /* Phase 1: Process all IVHD blocks */ 2029 while (p < end) { 2030 h = (struct ivhd_header *)p; 2031 if (*p == amd_iommu_target_ivhd_type) { 2032 2033 DUMP_printk("device: %04x:%02x:%02x.%01x cap: %04x " 2034 "flags: %01x info %04x\n", 2035 h->pci_seg, PCI_BUS_NUM(h->devid), 2036 PCI_SLOT(h->devid), PCI_FUNC(h->devid), 2037 h->cap_ptr, h->flags, h->info); 2038 DUMP_printk(" mmio-addr: %016llx\n", 2039 h->mmio_phys); 2040 2041 iommu = kzalloc_obj(struct amd_iommu); 2042 if (iommu == NULL) 2043 return -ENOMEM; 2044 2045 ret = init_iommu_one(iommu, h, table); 2046 if (ret) 2047 return ret; 2048 } 2049 p += h->length; 2050 2051 } 2052 WARN_ON(p != end); 2053 2054 /* Phase 2 : Early feature support check */ 2055 get_global_efr(); 2056 2057 /* Phase 3 : Enabling IOMMU features */ 2058 for_each_iommu(iommu) { 2059 ret = init_iommu_one_late(iommu); 2060 if (ret) 2061 return ret; 2062 } 2063 2064 return 0; 2065 } 2066 2067 static void init_iommu_perf_ctr(struct amd_iommu *iommu) 2068 { 2069 u64 val; 2070 struct pci_dev *pdev = iommu->dev; 2071 2072 if (!check_feature(FEATURE_PC)) 2073 return; 2074 2075 amd_iommu_pc_present = true; 2076 2077 pci_info(pdev, "IOMMU performance counters supported\n"); 2078 2079 val = readl(iommu->mmio_base + MMIO_CNTR_CONF_OFFSET); 2080 iommu->max_banks = (u8) ((val >> 12) & 0x3f); 2081 iommu->max_counters = (u8) ((val >> 7) & 0xf); 2082 2083 return; 2084 } 2085 2086 static ssize_t amd_iommu_show_cap(struct device *dev, 2087 struct device_attribute *attr, 2088 char *buf) 2089 { 2090 struct amd_iommu *iommu = dev_to_amd_iommu(dev); 2091 return sysfs_emit(buf, "%x\n", iommu->cap); 2092 } 2093 static DEVICE_ATTR(cap, S_IRUGO, amd_iommu_show_cap, NULL); 2094 2095 static ssize_t amd_iommu_show_features(struct device *dev, 2096 struct device_attribute *attr, 2097 char *buf) 2098 { 2099 return sysfs_emit(buf, "%llx:%llx\n", amd_iommu_efr, amd_iommu_efr2); 2100 } 2101 static DEVICE_ATTR(features, S_IRUGO, amd_iommu_show_features, NULL); 2102 2103 static struct attribute *amd_iommu_attrs[] = { 2104 &dev_attr_cap.attr, 2105 &dev_attr_features.attr, 2106 NULL, 2107 }; 2108 2109 static struct attribute_group amd_iommu_group = { 2110 .name = "amd-iommu", 2111 .attrs = amd_iommu_attrs, 2112 }; 2113 2114 static const struct attribute_group *amd_iommu_groups[] = { 2115 &amd_iommu_group, 2116 NULL, 2117 }; 2118 2119 /* 2120 * Note: IVHD 0x11 and 0x40 also contains exact copy 2121 * of the IOMMU Extended Feature Register [MMIO Offset 0030h]. 2122 * Default to EFR in IVHD since it is available sooner (i.e. before PCI init). 2123 */ 2124 static void __init late_iommu_features_init(struct amd_iommu *iommu) 2125 { 2126 u64 features, features2; 2127 2128 if (!(iommu->cap & (1 << IOMMU_CAP_EFR))) 2129 return; 2130 2131 /* read extended feature bits */ 2132 features = readq(iommu->mmio_base + MMIO_EXT_FEATURES); 2133 features2 = readq(iommu->mmio_base + MMIO_EXT_FEATURES2); 2134 2135 if (!amd_iommu_efr) { 2136 amd_iommu_efr = features; 2137 amd_iommu_efr2 = features2; 2138 return; 2139 } 2140 2141 /* 2142 * Sanity check and warn if EFR values from 2143 * IVHD and MMIO conflict. 2144 */ 2145 if (features != amd_iommu_efr || 2146 features2 != amd_iommu_efr2) { 2147 pr_warn(FW_WARN 2148 "EFR mismatch. Use IVHD EFR (%#llx : %#llx), EFR2 (%#llx : %#llx).\n", 2149 features, amd_iommu_efr, 2150 features2, amd_iommu_efr2); 2151 } 2152 } 2153 2154 static int __init iommu_init_pci(struct amd_iommu *iommu) 2155 { 2156 int cap_ptr = iommu->cap_ptr; 2157 int ret; 2158 2159 iommu->dev = pci_get_domain_bus_and_slot(iommu->pci_seg->id, 2160 PCI_BUS_NUM(iommu->devid), 2161 iommu->devid & 0xff); 2162 if (!iommu->dev) 2163 return -ENODEV; 2164 2165 /* ACPI _PRT won't have an IRQ for IOMMU */ 2166 iommu->dev->irq_managed = 1; 2167 2168 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET, 2169 &iommu->cap); 2170 2171 if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB))) 2172 amd_iommu_iotlb_sup = false; 2173 2174 late_iommu_features_init(iommu); 2175 2176 if (check_feature(FEATURE_GT)) { 2177 int glxval; 2178 u64 pasmax; 2179 2180 pasmax = FIELD_GET(FEATURE_PASMAX, amd_iommu_efr); 2181 iommu->iommu.max_pasids = (1 << (pasmax + 1)) - 1; 2182 2183 BUG_ON(iommu->iommu.max_pasids & ~PASID_MASK); 2184 2185 glxval = FIELD_GET(FEATURE_GLX, amd_iommu_efr); 2186 2187 if (amd_iommu_max_glx_val == -1) 2188 amd_iommu_max_glx_val = glxval; 2189 else 2190 amd_iommu_max_glx_val = min(amd_iommu_max_glx_val, glxval); 2191 2192 iommu_enable_gt(iommu); 2193 } 2194 2195 if (check_feature(FEATURE_PPR) && amd_iommu_alloc_ppr_log(iommu)) 2196 return -ENOMEM; 2197 2198 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE)) { 2199 pr_info("Using strict mode due to virtualization\n"); 2200 iommu_set_dma_strict(); 2201 amd_iommu_np_cache = true; 2202 } 2203 2204 init_iommu_perf_ctr(iommu); 2205 2206 if (is_rd890_iommu(iommu->dev)) { 2207 int i, j; 2208 2209 iommu->root_pdev = 2210 pci_get_domain_bus_and_slot(iommu->pci_seg->id, 2211 iommu->dev->bus->number, 2212 PCI_DEVFN(0, 0)); 2213 2214 /* 2215 * Some rd890 systems may not be fully reconfigured by the 2216 * BIOS, so it's necessary for us to store this information so 2217 * it can be reprogrammed on resume 2218 */ 2219 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4, 2220 &iommu->stored_addr_lo); 2221 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8, 2222 &iommu->stored_addr_hi); 2223 2224 /* Low bit locks writes to configuration space */ 2225 iommu->stored_addr_lo &= ~1; 2226 2227 for (i = 0; i < 6; i++) 2228 for (j = 0; j < 0x12; j++) 2229 iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j); 2230 2231 for (i = 0; i < 0x83; i++) 2232 iommu->stored_l2[i] = iommu_read_l2(iommu, i); 2233 } 2234 2235 amd_iommu_erratum_746_workaround(iommu); 2236 amd_iommu_ats_write_check_workaround(iommu); 2237 2238 ret = iommu_device_sysfs_add(&iommu->iommu, &iommu->dev->dev, 2239 amd_iommu_groups, "ivhd%d", iommu->index); 2240 if (ret) 2241 return ret; 2242 2243 /* 2244 * Allocate per IOMMU IOPF queue here so that in attach device path, 2245 * PRI capable device can be added to IOPF queue 2246 */ 2247 if (amd_iommu_gt_ppr_supported()) { 2248 ret = amd_iommu_iopf_init(iommu); 2249 if (ret) 2250 return ret; 2251 } 2252 2253 ret = iommu_device_register(&iommu->iommu, &amd_iommu_ops, NULL); 2254 if (ret || amd_iommu_pgtable == PD_MODE_NONE) { 2255 /* 2256 * Remove sysfs if DMA translation is not supported by the 2257 * IOMMU. Do not return an error to enable IRQ remapping 2258 * in state_next(), DTE[V, TV] must eventually be set to 0. 2259 */ 2260 iommu_device_sysfs_remove(&iommu->iommu); 2261 } 2262 2263 return pci_enable_device(iommu->dev); 2264 } 2265 2266 static void print_iommu_info(void) 2267 { 2268 int i; 2269 static const char * const feat_str[] = { 2270 "PreF", "PPR", "X2APIC", "NX", "GT", "[5]", 2271 "IA", "GA", "HE", "PC" 2272 }; 2273 2274 if (amd_iommu_efr) { 2275 pr_info("Extended features (%#llx, %#llx):", amd_iommu_efr, amd_iommu_efr2); 2276 2277 for (i = 0; i < ARRAY_SIZE(feat_str); ++i) { 2278 if (check_feature(1ULL << i)) 2279 pr_cont(" %s", feat_str[i]); 2280 } 2281 2282 if (check_feature(FEATURE_GAM_VAPIC)) 2283 pr_cont(" GA_vAPIC"); 2284 2285 if (check_feature(FEATURE_SNP)) 2286 pr_cont(" SNP"); 2287 2288 if (check_feature2(FEATURE_SEVSNPIO_SUP)) 2289 pr_cont(" SEV-TIO"); 2290 2291 pr_cont("\n"); 2292 } 2293 2294 if (irq_remapping_enabled) { 2295 pr_info("Interrupt remapping enabled\n"); 2296 if (amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE) 2297 pr_info("X2APIC enabled\n"); 2298 } 2299 if (amd_iommu_pgtable == PD_MODE_V2) { 2300 pr_info("V2 page table enabled (Paging mode : %d level)\n", 2301 amd_iommu_gpt_level); 2302 } 2303 } 2304 2305 static int __init amd_iommu_init_pci(void) 2306 { 2307 struct amd_iommu *iommu; 2308 struct amd_iommu_pci_seg *pci_seg; 2309 int ret; 2310 2311 /* Init global identity domain before registering IOMMU */ 2312 amd_iommu_init_identity_domain(); 2313 2314 for_each_iommu(iommu) { 2315 ret = iommu_init_pci(iommu); 2316 if (ret) { 2317 pr_err("IOMMU%d: Failed to initialize IOMMU Hardware (error=%d)!\n", 2318 iommu->index, ret); 2319 goto out; 2320 } 2321 /* Need to setup range after PCI init */ 2322 iommu_set_cwwb_range(iommu); 2323 } 2324 2325 /* 2326 * Order is important here to make sure any unity map requirements are 2327 * fulfilled. The unity mappings are created and written to the device 2328 * table during the iommu_init_pci() call. 2329 * 2330 * After that we call init_device_table_dma() to make sure any 2331 * uninitialized DTE will block DMA, and in the end we flush the caches 2332 * of all IOMMUs to make sure the changes to the device table are 2333 * active. 2334 */ 2335 for_each_pci_segment(pci_seg) 2336 init_device_table_dma(pci_seg); 2337 2338 for_each_iommu(iommu) 2339 amd_iommu_flush_all_caches(iommu); 2340 2341 print_iommu_info(); 2342 2343 out: 2344 return ret; 2345 } 2346 2347 /**************************************************************************** 2348 * 2349 * The following functions initialize the MSI interrupts for all IOMMUs 2350 * in the system. It's a bit challenging because there could be multiple 2351 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per 2352 * pci_dev. 2353 * 2354 ****************************************************************************/ 2355 2356 static int iommu_setup_msi(struct amd_iommu *iommu) 2357 { 2358 int r; 2359 2360 r = pci_enable_msi(iommu->dev); 2361 if (r) 2362 return r; 2363 2364 r = request_threaded_irq(iommu->dev->irq, NULL, amd_iommu_int_thread, 2365 IRQF_ONESHOT, "AMD-Vi", iommu); 2366 if (r) { 2367 pci_disable_msi(iommu->dev); 2368 return r; 2369 } 2370 2371 return 0; 2372 } 2373 2374 union intcapxt { 2375 u64 capxt; 2376 struct { 2377 u64 reserved_0 : 2, 2378 dest_mode_logical : 1, 2379 reserved_1 : 5, 2380 destid_0_23 : 24, 2381 vector : 8, 2382 reserved_2 : 16, 2383 destid_24_31 : 8; 2384 }; 2385 } __attribute__ ((packed)); 2386 2387 2388 static struct irq_chip intcapxt_controller; 2389 2390 static int intcapxt_irqdomain_activate(struct irq_domain *domain, 2391 struct irq_data *irqd, bool reserve) 2392 { 2393 return 0; 2394 } 2395 2396 static void intcapxt_irqdomain_deactivate(struct irq_domain *domain, 2397 struct irq_data *irqd) 2398 { 2399 } 2400 2401 2402 static int intcapxt_irqdomain_alloc(struct irq_domain *domain, unsigned int virq, 2403 unsigned int nr_irqs, void *arg) 2404 { 2405 struct irq_alloc_info *info = arg; 2406 int i, ret; 2407 2408 if (!info || info->type != X86_IRQ_ALLOC_TYPE_AMDVI) 2409 return -EINVAL; 2410 2411 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg); 2412 if (ret < 0) 2413 return ret; 2414 2415 for (i = virq; i < virq + nr_irqs; i++) { 2416 struct irq_data *irqd = irq_domain_get_irq_data(domain, i); 2417 2418 irqd->chip = &intcapxt_controller; 2419 irqd->hwirq = info->hwirq; 2420 irqd->chip_data = info->data; 2421 __irq_set_handler(i, handle_edge_irq, 0, "edge"); 2422 } 2423 2424 return ret; 2425 } 2426 2427 static void intcapxt_irqdomain_free(struct irq_domain *domain, unsigned int virq, 2428 unsigned int nr_irqs) 2429 { 2430 irq_domain_free_irqs_top(domain, virq, nr_irqs); 2431 } 2432 2433 2434 static void intcapxt_unmask_irq(struct irq_data *irqd) 2435 { 2436 struct amd_iommu *iommu = irqd->chip_data; 2437 struct irq_cfg *cfg = irqd_cfg(irqd); 2438 union intcapxt xt; 2439 2440 xt.capxt = 0ULL; 2441 xt.dest_mode_logical = apic->dest_mode_logical; 2442 xt.vector = cfg->vector; 2443 xt.destid_0_23 = cfg->dest_apicid & GENMASK(23, 0); 2444 xt.destid_24_31 = cfg->dest_apicid >> 24; 2445 2446 writeq(xt.capxt, iommu->mmio_base + irqd->hwirq); 2447 } 2448 2449 static void intcapxt_mask_irq(struct irq_data *irqd) 2450 { 2451 struct amd_iommu *iommu = irqd->chip_data; 2452 2453 writeq(0, iommu->mmio_base + irqd->hwirq); 2454 } 2455 2456 2457 static int intcapxt_set_affinity(struct irq_data *irqd, 2458 const struct cpumask *mask, bool force) 2459 { 2460 struct irq_data *parent = irqd->parent_data; 2461 int ret; 2462 2463 ret = parent->chip->irq_set_affinity(parent, mask, force); 2464 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE) 2465 return ret; 2466 return 0; 2467 } 2468 2469 static int intcapxt_set_wake(struct irq_data *irqd, unsigned int on) 2470 { 2471 return on ? -EOPNOTSUPP : 0; 2472 } 2473 2474 static struct irq_chip intcapxt_controller = { 2475 .name = "IOMMU-MSI", 2476 .irq_unmask = intcapxt_unmask_irq, 2477 .irq_mask = intcapxt_mask_irq, 2478 .irq_ack = irq_chip_ack_parent, 2479 .irq_retrigger = irq_chip_retrigger_hierarchy, 2480 .irq_set_affinity = intcapxt_set_affinity, 2481 .irq_set_wake = intcapxt_set_wake, 2482 .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_MOVE_DEFERRED, 2483 }; 2484 2485 static const struct irq_domain_ops intcapxt_domain_ops = { 2486 .alloc = intcapxt_irqdomain_alloc, 2487 .free = intcapxt_irqdomain_free, 2488 .activate = intcapxt_irqdomain_activate, 2489 .deactivate = intcapxt_irqdomain_deactivate, 2490 }; 2491 2492 2493 static struct irq_domain *iommu_irqdomain; 2494 2495 static struct irq_domain *iommu_get_irqdomain(void) 2496 { 2497 struct fwnode_handle *fn; 2498 2499 /* No need for locking here (yet) as the init is single-threaded */ 2500 if (iommu_irqdomain) 2501 return iommu_irqdomain; 2502 2503 fn = irq_domain_alloc_named_fwnode("AMD-Vi-MSI"); 2504 if (!fn) 2505 return NULL; 2506 2507 iommu_irqdomain = irq_domain_create_hierarchy(x86_vector_domain, 0, 0, 2508 fn, &intcapxt_domain_ops, 2509 NULL); 2510 if (!iommu_irqdomain) 2511 irq_domain_free_fwnode(fn); 2512 2513 return iommu_irqdomain; 2514 } 2515 2516 static int __iommu_setup_intcapxt(struct amd_iommu *iommu, const char *devname, 2517 int hwirq, irq_handler_t thread_fn) 2518 { 2519 struct irq_domain *domain; 2520 struct irq_alloc_info info; 2521 int irq, ret; 2522 int node = dev_to_node(&iommu->dev->dev); 2523 2524 domain = iommu_get_irqdomain(); 2525 if (!domain) 2526 return -ENXIO; 2527 2528 init_irq_alloc_info(&info, NULL); 2529 info.type = X86_IRQ_ALLOC_TYPE_AMDVI; 2530 info.data = iommu; 2531 info.hwirq = hwirq; 2532 2533 irq = irq_domain_alloc_irqs(domain, 1, node, &info); 2534 if (irq < 0) { 2535 irq_domain_remove(domain); 2536 return irq; 2537 } 2538 2539 ret = request_threaded_irq(irq, NULL, thread_fn, IRQF_ONESHOT, devname, 2540 iommu); 2541 if (ret) { 2542 irq_domain_free_irqs(irq, 1); 2543 irq_domain_remove(domain); 2544 return ret; 2545 } 2546 2547 return 0; 2548 } 2549 2550 static int iommu_setup_intcapxt(struct amd_iommu *iommu) 2551 { 2552 int ret; 2553 2554 snprintf(iommu->evt_irq_name, sizeof(iommu->evt_irq_name), 2555 "AMD-Vi%d-Evt", iommu->index); 2556 ret = __iommu_setup_intcapxt(iommu, iommu->evt_irq_name, 2557 MMIO_INTCAPXT_EVT_OFFSET, 2558 amd_iommu_int_thread_evtlog); 2559 if (ret) 2560 return ret; 2561 2562 snprintf(iommu->ppr_irq_name, sizeof(iommu->ppr_irq_name), 2563 "AMD-Vi%d-PPR", iommu->index); 2564 ret = __iommu_setup_intcapxt(iommu, iommu->ppr_irq_name, 2565 MMIO_INTCAPXT_PPR_OFFSET, 2566 amd_iommu_int_thread_pprlog); 2567 if (ret) 2568 return ret; 2569 2570 #ifdef CONFIG_IRQ_REMAP 2571 snprintf(iommu->ga_irq_name, sizeof(iommu->ga_irq_name), 2572 "AMD-Vi%d-GA", iommu->index); 2573 ret = __iommu_setup_intcapxt(iommu, iommu->ga_irq_name, 2574 MMIO_INTCAPXT_GALOG_OFFSET, 2575 amd_iommu_int_thread_galog); 2576 #endif 2577 2578 return ret; 2579 } 2580 2581 static int iommu_init_irq(struct amd_iommu *iommu) 2582 { 2583 int ret; 2584 2585 if (iommu->int_enabled) 2586 goto enable_faults; 2587 2588 if (amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE) 2589 ret = iommu_setup_intcapxt(iommu); 2590 else if (iommu->dev->msi_cap) 2591 ret = iommu_setup_msi(iommu); 2592 else 2593 ret = -ENODEV; 2594 2595 if (ret) 2596 return ret; 2597 2598 iommu->int_enabled = true; 2599 enable_faults: 2600 2601 if (amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE) 2602 iommu_feature_enable(iommu, CONTROL_INTCAPXT_EN); 2603 2604 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN); 2605 2606 return 0; 2607 } 2608 2609 /**************************************************************************** 2610 * 2611 * The next functions belong to the third pass of parsing the ACPI 2612 * table. In this last pass the memory mapping requirements are 2613 * gathered (like exclusion and unity mapping ranges). 2614 * 2615 ****************************************************************************/ 2616 2617 static void __init free_unity_maps(void) 2618 { 2619 struct unity_map_entry *entry, *next; 2620 struct amd_iommu_pci_seg *p, *pci_seg; 2621 2622 for_each_pci_segment_safe(pci_seg, p) { 2623 list_for_each_entry_safe(entry, next, &pci_seg->unity_map, list) { 2624 list_del(&entry->list); 2625 kfree(entry); 2626 } 2627 } 2628 } 2629 2630 /* called for unity map ACPI definition */ 2631 static int __init init_unity_map_range(struct ivmd_header *m, 2632 struct acpi_table_header *ivrs_base) 2633 { 2634 struct unity_map_entry *e = NULL; 2635 struct amd_iommu_pci_seg *pci_seg; 2636 char *s; 2637 2638 pci_seg = get_pci_segment(m->pci_seg, ivrs_base); 2639 if (pci_seg == NULL) 2640 return -ENOMEM; 2641 2642 e = kzalloc_obj(*e); 2643 if (e == NULL) 2644 return -ENOMEM; 2645 2646 switch (m->type) { 2647 default: 2648 kfree(e); 2649 return 0; 2650 case ACPI_IVMD_TYPE: 2651 s = "IVMD_TYPEi\t\t\t"; 2652 e->devid_start = e->devid_end = m->devid; 2653 break; 2654 case ACPI_IVMD_TYPE_ALL: 2655 s = "IVMD_TYPE_ALL\t\t"; 2656 e->devid_start = 0; 2657 e->devid_end = pci_seg->last_bdf; 2658 break; 2659 case ACPI_IVMD_TYPE_RANGE: 2660 s = "IVMD_TYPE_RANGE\t\t"; 2661 e->devid_start = m->devid; 2662 e->devid_end = m->aux; 2663 break; 2664 } 2665 e->address_start = PAGE_ALIGN(m->range_start); 2666 e->address_end = e->address_start + PAGE_ALIGN(m->range_length); 2667 e->prot = m->flags >> 1; 2668 2669 /* 2670 * Treat per-device exclusion ranges as r/w unity-mapped regions 2671 * since some buggy BIOSes might lead to the overwritten exclusion 2672 * range (exclusion_start and exclusion_length members). This 2673 * happens when there are multiple exclusion ranges (IVMD entries) 2674 * defined in ACPI table. 2675 */ 2676 if (m->flags & IVMD_FLAG_EXCL_RANGE) 2677 e->prot = (IVMD_FLAG_IW | IVMD_FLAG_IR) >> 1; 2678 2679 DUMP_printk("%s devid_start: %04x:%02x:%02x.%x devid_end: " 2680 "%04x:%02x:%02x.%x range_start: %016llx range_end: %016llx" 2681 " flags: %x\n", s, m->pci_seg, 2682 PCI_BUS_NUM(e->devid_start), PCI_SLOT(e->devid_start), 2683 PCI_FUNC(e->devid_start), m->pci_seg, 2684 PCI_BUS_NUM(e->devid_end), 2685 PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end), 2686 e->address_start, e->address_end, m->flags); 2687 2688 list_add_tail(&e->list, &pci_seg->unity_map); 2689 2690 return 0; 2691 } 2692 2693 /* iterates over all memory definitions we find in the ACPI table */ 2694 static int __init init_memory_definitions(struct acpi_table_header *table) 2695 { 2696 u8 *p = (u8 *)table, *end = (u8 *)table; 2697 struct ivmd_header *m; 2698 2699 end += table->length; 2700 p += IVRS_HEADER_LENGTH; 2701 2702 while (p < end) { 2703 m = (struct ivmd_header *)p; 2704 if (m->flags & (IVMD_FLAG_UNITY_MAP | IVMD_FLAG_EXCL_RANGE)) 2705 init_unity_map_range(m, table); 2706 2707 p += m->length; 2708 } 2709 2710 return 0; 2711 } 2712 2713 /* 2714 * Init the device table to not allow DMA access for devices 2715 */ 2716 static void init_device_table_dma(struct amd_iommu_pci_seg *pci_seg) 2717 { 2718 u32 devid; 2719 struct dev_table_entry *dev_table = pci_seg->dev_table; 2720 2721 if (!dev_table || amd_iommu_pgtable == PD_MODE_NONE) 2722 return; 2723 2724 for (devid = 0; devid <= pci_seg->last_bdf; ++devid) { 2725 set_dte_bit(&dev_table[devid], DEV_ENTRY_VALID); 2726 if (!amd_iommu_snp_en) 2727 set_dte_bit(&dev_table[devid], DEV_ENTRY_TRANSLATION); 2728 } 2729 } 2730 2731 static void __init uninit_device_table_dma(struct amd_iommu_pci_seg *pci_seg) 2732 { 2733 u32 devid; 2734 struct dev_table_entry *dev_table = pci_seg->dev_table; 2735 2736 if (dev_table == NULL) 2737 return; 2738 2739 for (devid = 0; devid <= pci_seg->last_bdf; ++devid) { 2740 dev_table[devid].data[0] = 0ULL; 2741 dev_table[devid].data[1] = 0ULL; 2742 } 2743 } 2744 2745 static void init_device_table(void) 2746 { 2747 struct amd_iommu_pci_seg *pci_seg; 2748 u32 devid; 2749 2750 if (!amd_iommu_irq_remap) 2751 return; 2752 2753 for_each_pci_segment(pci_seg) { 2754 for (devid = 0; devid <= pci_seg->last_bdf; ++devid) 2755 set_dte_bit(&pci_seg->dev_table[devid], DEV_ENTRY_IRQ_TBL_EN); 2756 } 2757 } 2758 2759 static void iommu_init_flags(struct amd_iommu *iommu) 2760 { 2761 iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ? 2762 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) : 2763 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN); 2764 2765 iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ? 2766 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) : 2767 iommu_feature_disable(iommu, CONTROL_PASSPW_EN); 2768 2769 iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ? 2770 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) : 2771 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN); 2772 2773 iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ? 2774 iommu_feature_enable(iommu, CONTROL_ISOC_EN) : 2775 iommu_feature_disable(iommu, CONTROL_ISOC_EN); 2776 2777 /* 2778 * make IOMMU memory accesses cache coherent 2779 */ 2780 iommu_feature_enable(iommu, CONTROL_COHERENT_EN); 2781 2782 /* Set IOTLB invalidation timeout to 1s */ 2783 iommu_feature_set(iommu, CTRL_INV_TO_1S, CTRL_INV_TO_MASK, CONTROL_INV_TIMEOUT); 2784 2785 /* Enable Enhanced Peripheral Page Request Handling */ 2786 if (check_feature(FEATURE_EPHSUP)) 2787 iommu_feature_enable(iommu, CONTROL_EPH_EN); 2788 } 2789 2790 static void iommu_apply_resume_quirks(struct amd_iommu *iommu) 2791 { 2792 int i, j; 2793 u32 ioc_feature_control; 2794 struct pci_dev *pdev = iommu->root_pdev; 2795 2796 /* RD890 BIOSes may not have completely reconfigured the iommu */ 2797 if (!is_rd890_iommu(iommu->dev) || !pdev) 2798 return; 2799 2800 /* 2801 * First, we need to ensure that the iommu is enabled. This is 2802 * controlled by a register in the northbridge 2803 */ 2804 2805 /* Select Northbridge indirect register 0x75 and enable writing */ 2806 pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7)); 2807 pci_read_config_dword(pdev, 0x64, &ioc_feature_control); 2808 2809 /* Enable the iommu */ 2810 if (!(ioc_feature_control & 0x1)) 2811 pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1); 2812 2813 /* Restore the iommu BAR */ 2814 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4, 2815 iommu->stored_addr_lo); 2816 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8, 2817 iommu->stored_addr_hi); 2818 2819 /* Restore the l1 indirect regs for each of the 6 l1s */ 2820 for (i = 0; i < 6; i++) 2821 for (j = 0; j < 0x12; j++) 2822 iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]); 2823 2824 /* Restore the l2 indirect regs */ 2825 for (i = 0; i < 0x83; i++) 2826 iommu_write_l2(iommu, i, iommu->stored_l2[i]); 2827 2828 /* Lock PCI setup registers */ 2829 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4, 2830 iommu->stored_addr_lo | 1); 2831 } 2832 2833 static void iommu_enable_ga(struct amd_iommu *iommu) 2834 { 2835 #ifdef CONFIG_IRQ_REMAP 2836 switch (amd_iommu_guest_ir) { 2837 case AMD_IOMMU_GUEST_IR_VAPIC: 2838 case AMD_IOMMU_GUEST_IR_LEGACY_GA: 2839 iommu_feature_enable(iommu, CONTROL_GA_EN); 2840 iommu->irte_ops = &irte_128_ops; 2841 break; 2842 default: 2843 iommu->irte_ops = &irte_32_ops; 2844 break; 2845 } 2846 #endif 2847 } 2848 2849 static void iommu_disable_irtcachedis(struct amd_iommu *iommu) 2850 { 2851 iommu_feature_disable(iommu, CONTROL_IRTCACHEDIS); 2852 } 2853 2854 static void iommu_enable_irtcachedis(struct amd_iommu *iommu) 2855 { 2856 u64 ctrl; 2857 2858 if (!amd_iommu_irtcachedis) 2859 return; 2860 2861 /* 2862 * Note: 2863 * The support for IRTCacheDis feature is dertermined by 2864 * checking if the bit is writable. 2865 */ 2866 iommu_feature_enable(iommu, CONTROL_IRTCACHEDIS); 2867 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); 2868 ctrl &= (1ULL << CONTROL_IRTCACHEDIS); 2869 if (ctrl) 2870 iommu->irtcachedis_enabled = true; 2871 pr_info("iommu%d (%#06x) : IRT cache is %s\n", 2872 iommu->index, iommu->devid, 2873 iommu->irtcachedis_enabled ? "disabled" : "enabled"); 2874 } 2875 2876 static void iommu_enable_2k_int(struct amd_iommu *iommu) 2877 { 2878 if (!FEATURE_NUM_INT_REMAP_SUP_2K(amd_iommu_efr2)) 2879 return; 2880 2881 iommu_feature_set(iommu, 2882 CONTROL_NUM_INT_REMAP_MODE_2K, 2883 CONTROL_NUM_INT_REMAP_MODE_MASK, 2884 CONTROL_NUM_INT_REMAP_MODE); 2885 } 2886 2887 static void early_enable_iommu(struct amd_iommu *iommu) 2888 { 2889 iommu_disable(iommu); 2890 iommu_init_flags(iommu); 2891 iommu_set_device_table(iommu); 2892 iommu_enable_command_buffer(iommu); 2893 iommu_enable_event_buffer(iommu); 2894 iommu_set_exclusion_range(iommu); 2895 iommu_enable_gt(iommu); 2896 iommu_enable_ga(iommu); 2897 iommu_enable_xt(iommu); 2898 iommu_enable_irtcachedis(iommu); 2899 iommu_enable_2k_int(iommu); 2900 iommu_enable(iommu); 2901 amd_iommu_flush_all_caches(iommu); 2902 } 2903 2904 /* 2905 * This function finally enables all IOMMUs found in the system after 2906 * they have been initialized. 2907 * 2908 * Or if in kdump kernel and IOMMUs are all pre-enabled, try to reuse 2909 * the old content of device table entries. Not this case or reuse failed, 2910 * just continue as normal kernel does. 2911 */ 2912 static void early_enable_iommus(void) 2913 { 2914 struct amd_iommu *iommu; 2915 struct amd_iommu_pci_seg *pci_seg; 2916 2917 if (!reuse_device_table()) { 2918 /* 2919 * If come here because of failure in reusing device table from old 2920 * kernel with all IOMMUs enabled, print error message and try to 2921 * free allocated old_dev_tbl_cpy. 2922 */ 2923 if (amd_iommu_pre_enabled) { 2924 pr_err("Failed to reuse DEV table from previous kernel.\n"); 2925 /* 2926 * Bail out early if unable to remap/reuse DEV table from 2927 * previous kernel if SNP enabled as IOMMU commands will 2928 * time out without DEV table and cause kdump boot panic. 2929 */ 2930 BUG_ON(check_feature(FEATURE_SNP)); 2931 } 2932 2933 for_each_pci_segment(pci_seg) { 2934 if (pci_seg->old_dev_tbl_cpy != NULL) { 2935 memunmap((void *)pci_seg->old_dev_tbl_cpy); 2936 pci_seg->old_dev_tbl_cpy = NULL; 2937 } 2938 } 2939 2940 for_each_iommu(iommu) { 2941 clear_translation_pre_enabled(iommu); 2942 early_enable_iommu(iommu); 2943 } 2944 } else { 2945 pr_info("Reused DEV table from previous kernel.\n"); 2946 2947 for_each_pci_segment(pci_seg) { 2948 iommu_free_pages(pci_seg->dev_table); 2949 pci_seg->dev_table = pci_seg->old_dev_tbl_cpy; 2950 } 2951 2952 for_each_iommu(iommu) { 2953 iommu_disable_command_buffer(iommu); 2954 iommu_disable_event_buffer(iommu); 2955 iommu_disable_irtcachedis(iommu); 2956 iommu_enable_command_buffer(iommu); 2957 iommu_enable_event_buffer(iommu); 2958 iommu_enable_ga(iommu); 2959 iommu_enable_xt(iommu); 2960 iommu_enable_irtcachedis(iommu); 2961 iommu_enable_2k_int(iommu); 2962 iommu_set_device_table(iommu); 2963 amd_iommu_flush_all_caches(iommu); 2964 } 2965 } 2966 } 2967 2968 static void enable_iommus_ppr(void) 2969 { 2970 struct amd_iommu *iommu; 2971 2972 if (!amd_iommu_gt_ppr_supported()) 2973 return; 2974 2975 for_each_iommu(iommu) 2976 amd_iommu_enable_ppr_log(iommu); 2977 } 2978 2979 static void enable_iommus_vapic(void) 2980 { 2981 #ifdef CONFIG_IRQ_REMAP 2982 u32 status, i; 2983 struct amd_iommu *iommu; 2984 2985 for_each_iommu(iommu) { 2986 /* 2987 * Disable GALog if already running. It could have been enabled 2988 * in the previous boot before kdump. 2989 */ 2990 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); 2991 if (!(status & MMIO_STATUS_GALOG_RUN_MASK)) 2992 continue; 2993 2994 iommu_feature_disable(iommu, CONTROL_GALOG_EN); 2995 iommu_feature_disable(iommu, CONTROL_GAINT_EN); 2996 2997 /* 2998 * Need to set and poll check the GALOGRun bit to zero before 2999 * we can set/ modify GA Log registers safely. 3000 */ 3001 for (i = 0; i < MMIO_STATUS_TIMEOUT; ++i) { 3002 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); 3003 if (!(status & MMIO_STATUS_GALOG_RUN_MASK)) 3004 break; 3005 udelay(10); 3006 } 3007 3008 if (WARN_ON(i >= MMIO_STATUS_TIMEOUT)) 3009 return; 3010 } 3011 3012 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) && 3013 !check_feature(FEATURE_GAM_VAPIC)) { 3014 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY_GA; 3015 return; 3016 } 3017 3018 if (amd_iommu_snp_en && 3019 !FEATURE_SNPAVICSUP_GAM(amd_iommu_efr2)) { 3020 pr_warn("Force to disable Virtual APIC due to SNP\n"); 3021 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY_GA; 3022 return; 3023 } 3024 3025 /* Enabling GAM and SNPAVIC support */ 3026 for_each_iommu(iommu) { 3027 if (iommu_init_ga_log(iommu) || 3028 iommu_ga_log_enable(iommu)) 3029 return; 3030 3031 iommu_feature_enable(iommu, CONTROL_GAM_EN); 3032 if (amd_iommu_snp_en) 3033 iommu_feature_enable(iommu, CONTROL_SNPAVIC_EN); 3034 } 3035 3036 amd_iommu_irq_ops.capability |= (1 << IRQ_POSTING_CAP); 3037 pr_info("Virtual APIC enabled\n"); 3038 #endif 3039 } 3040 3041 static void disable_iommus(void) 3042 { 3043 struct amd_iommu *iommu; 3044 3045 for_each_iommu(iommu) 3046 iommu_disable(iommu); 3047 3048 #ifdef CONFIG_IRQ_REMAP 3049 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) 3050 amd_iommu_irq_ops.capability &= ~(1 << IRQ_POSTING_CAP); 3051 #endif 3052 } 3053 3054 /* 3055 * Suspend/Resume support 3056 * disable suspend until real resume implemented 3057 */ 3058 3059 static void amd_iommu_resume(void *data) 3060 { 3061 struct amd_iommu *iommu; 3062 3063 for_each_iommu(iommu) 3064 iommu_apply_resume_quirks(iommu); 3065 3066 /* re-load the hardware */ 3067 for_each_iommu(iommu) 3068 early_enable_iommu(iommu); 3069 3070 amd_iommu_enable_interrupts(); 3071 } 3072 3073 static int amd_iommu_suspend(void *data) 3074 { 3075 /* disable IOMMUs to go out of the way for BIOS */ 3076 disable_iommus(); 3077 3078 return 0; 3079 } 3080 3081 static const struct syscore_ops amd_iommu_syscore_ops = { 3082 .suspend = amd_iommu_suspend, 3083 .resume = amd_iommu_resume, 3084 }; 3085 3086 static struct syscore amd_iommu_syscore = { 3087 .ops = &amd_iommu_syscore_ops, 3088 }; 3089 3090 static void __init free_iommu_resources(void) 3091 { 3092 free_iommu_all(); 3093 free_pci_segments(); 3094 } 3095 3096 /* SB IOAPIC is always on this device in AMD systems */ 3097 #define IOAPIC_SB_DEVID ((0x00 << 8) | PCI_DEVFN(0x14, 0)) 3098 3099 static bool __init check_ioapic_information(void) 3100 { 3101 const char *fw_bug = FW_BUG; 3102 bool ret, has_sb_ioapic; 3103 int idx; 3104 3105 has_sb_ioapic = false; 3106 ret = false; 3107 3108 /* 3109 * If we have map overrides on the kernel command line the 3110 * messages in this function might not describe firmware bugs 3111 * anymore - so be careful 3112 */ 3113 if (cmdline_maps) 3114 fw_bug = ""; 3115 3116 for (idx = 0; idx < nr_ioapics; idx++) { 3117 int devid, id = mpc_ioapic_id(idx); 3118 3119 devid = get_ioapic_devid(id); 3120 if (devid < 0) { 3121 pr_err("%s: IOAPIC[%d] not in IVRS table\n", 3122 fw_bug, id); 3123 ret = false; 3124 } else if (devid == IOAPIC_SB_DEVID) { 3125 has_sb_ioapic = true; 3126 ret = true; 3127 } 3128 } 3129 3130 if (!has_sb_ioapic) { 3131 /* 3132 * We expect the SB IOAPIC to be listed in the IVRS 3133 * table. The system timer is connected to the SB IOAPIC 3134 * and if we don't have it in the list the system will 3135 * panic at boot time. This situation usually happens 3136 * when the BIOS is buggy and provides us the wrong 3137 * device id for the IOAPIC in the system. 3138 */ 3139 pr_err("%s: No southbridge IOAPIC found\n", fw_bug); 3140 } 3141 3142 if (!ret) 3143 pr_err("Disabling interrupt remapping\n"); 3144 3145 return ret; 3146 } 3147 3148 static void __init free_dma_resources(void) 3149 { 3150 amd_iommu_pdom_id_destroy(); 3151 free_unity_maps(); 3152 } 3153 3154 static void __init ivinfo_init(void *ivrs) 3155 { 3156 amd_iommu_ivinfo = *((u32 *)(ivrs + IOMMU_IVINFO_OFFSET)); 3157 } 3158 3159 /* 3160 * This is the hardware init function for AMD IOMMU in the system. 3161 * This function is called either from amd_iommu_init or from the interrupt 3162 * remapping setup code. 3163 * 3164 * This function basically parses the ACPI table for AMD IOMMU (IVRS) 3165 * four times: 3166 * 3167 * 1 pass) Discover the most comprehensive IVHD type to use. 3168 * 3169 * 2 pass) Find the highest PCI device id the driver has to handle. 3170 * Upon this information the size of the data structures is 3171 * determined that needs to be allocated. 3172 * 3173 * 3 pass) Initialize the data structures just allocated with the 3174 * information in the ACPI table about available AMD IOMMUs 3175 * in the system. It also maps the PCI devices in the 3176 * system to specific IOMMUs 3177 * 3178 * 4 pass) After the basic data structures are allocated and 3179 * initialized we update them with information about memory 3180 * remapping requirements parsed out of the ACPI table in 3181 * this last pass. 3182 * 3183 * After everything is set up the IOMMUs are enabled and the necessary 3184 * hotplug and suspend notifiers are registered. 3185 */ 3186 static int __init early_amd_iommu_init(void) 3187 { 3188 struct acpi_table_header *ivrs_base; 3189 int ret; 3190 acpi_status status; 3191 u8 efr_hats; 3192 3193 if (!amd_iommu_detected) 3194 return -ENODEV; 3195 3196 status = acpi_get_table("IVRS", 0, &ivrs_base); 3197 if (status == AE_NOT_FOUND) 3198 return -ENODEV; 3199 else if (ACPI_FAILURE(status)) { 3200 const char *err = acpi_format_exception(status); 3201 pr_err("IVRS table error: %s\n", err); 3202 return -EINVAL; 3203 } 3204 3205 if (!boot_cpu_has(X86_FEATURE_CX16)) { 3206 pr_err("Failed to initialize. The CMPXCHG16B feature is required.\n"); 3207 ret = -EINVAL; 3208 goto out; 3209 } 3210 3211 /* 3212 * Validate checksum here so we don't need to do it when 3213 * we actually parse the table 3214 */ 3215 ret = check_ivrs_checksum(ivrs_base); 3216 if (ret) 3217 goto out; 3218 3219 ivinfo_init(ivrs_base); 3220 3221 amd_iommu_target_ivhd_type = get_highest_supported_ivhd_type(ivrs_base); 3222 DUMP_printk("Using IVHD type %#x\n", amd_iommu_target_ivhd_type); 3223 3224 /* 3225 * now the data structures are allocated and basically initialized 3226 * start the real acpi table scan 3227 */ 3228 ret = init_iommu_all(ivrs_base); 3229 if (ret) 3230 goto out; 3231 3232 /* 5 level guest page table */ 3233 if (cpu_feature_enabled(X86_FEATURE_LA57) && 3234 FIELD_GET(FEATURE_GATS, amd_iommu_efr) == GUEST_PGTABLE_5_LEVEL) 3235 amd_iommu_gpt_level = PAGE_MODE_5_LEVEL; 3236 3237 efr_hats = FIELD_GET(FEATURE_HATS, amd_iommu_efr); 3238 if (efr_hats != 0x3) { 3239 /* 3240 * efr[HATS] bits specify the maximum host translation level 3241 * supported, with LEVEL 4 being initial max level. 3242 */ 3243 amd_iommu_hpt_level = efr_hats + PAGE_MODE_4_LEVEL; 3244 } else { 3245 pr_warn_once(FW_BUG "Disable host address translation due to invalid translation level (%#x).\n", 3246 efr_hats); 3247 amd_iommu_hatdis = true; 3248 } 3249 3250 if (amd_iommu_pgtable == PD_MODE_V2) { 3251 if (!amd_iommu_v2_pgtbl_supported()) { 3252 pr_warn("Cannot enable v2 page table for DMA-API. Fallback to v1.\n"); 3253 amd_iommu_pgtable = PD_MODE_V1; 3254 } 3255 } 3256 3257 if (amd_iommu_hatdis) { 3258 /* 3259 * Host (v1) page table is not available. Attempt to use 3260 * Guest (v2) page table. 3261 */ 3262 if (amd_iommu_v2_pgtbl_supported()) 3263 amd_iommu_pgtable = PD_MODE_V2; 3264 else 3265 amd_iommu_pgtable = PD_MODE_NONE; 3266 } 3267 3268 /* Disable any previously enabled IOMMUs */ 3269 if (!is_kdump_kernel() || amd_iommu_disabled) 3270 disable_iommus(); 3271 3272 if (amd_iommu_irq_remap) 3273 amd_iommu_irq_remap = check_ioapic_information(); 3274 3275 if (amd_iommu_irq_remap) { 3276 struct amd_iommu_pci_seg *pci_seg; 3277 ret = -ENOMEM; 3278 for_each_pci_segment(pci_seg) { 3279 if (alloc_irq_lookup_table(pci_seg)) 3280 goto out; 3281 } 3282 } 3283 3284 ret = init_memory_definitions(ivrs_base); 3285 if (ret) 3286 goto out; 3287 3288 /* init the device table */ 3289 init_device_table(); 3290 3291 out: 3292 /* Don't leak any ACPI memory */ 3293 acpi_put_table(ivrs_base); 3294 3295 return ret; 3296 } 3297 3298 static int amd_iommu_enable_interrupts(void) 3299 { 3300 struct amd_iommu *iommu; 3301 int ret = 0; 3302 3303 for_each_iommu(iommu) { 3304 ret = iommu_init_irq(iommu); 3305 if (ret) 3306 goto out; 3307 } 3308 3309 /* 3310 * Interrupt handler is ready to process interrupts. Enable 3311 * PPR and GA log interrupt for all IOMMUs. 3312 */ 3313 enable_iommus_vapic(); 3314 enable_iommus_ppr(); 3315 3316 out: 3317 return ret; 3318 } 3319 3320 static bool __init detect_ivrs(void) 3321 { 3322 struct acpi_table_header *ivrs_base; 3323 acpi_status status; 3324 int i; 3325 3326 status = acpi_get_table("IVRS", 0, &ivrs_base); 3327 if (status == AE_NOT_FOUND) 3328 return false; 3329 else if (ACPI_FAILURE(status)) { 3330 const char *err = acpi_format_exception(status); 3331 pr_err("IVRS table error: %s\n", err); 3332 return false; 3333 } 3334 3335 acpi_put_table(ivrs_base); 3336 3337 if (amd_iommu_force_enable) 3338 goto out; 3339 3340 /* Don't use IOMMU if there is Stoney Ridge graphics */ 3341 for (i = 0; i < 32; i++) { 3342 u32 pci_id; 3343 3344 pci_id = read_pci_config(0, i, 0, 0); 3345 if ((pci_id & 0xffff) == 0x1002 && (pci_id >> 16) == 0x98e4) { 3346 pr_info("Disable IOMMU on Stoney Ridge\n"); 3347 return false; 3348 } 3349 } 3350 3351 out: 3352 /* Make sure ACS will be enabled during PCI probe */ 3353 pci_request_acs(); 3354 3355 return true; 3356 } 3357 3358 static __init void iommu_snp_enable(void) 3359 { 3360 #ifdef CONFIG_KVM_AMD_SEV 3361 if (!cc_platform_has(CC_ATTR_HOST_SEV_SNP)) 3362 return; 3363 /* 3364 * The SNP support requires that IOMMU must be enabled, and is 3365 * configured with V1 page table (DTE[Mode] = 0 is not supported). 3366 */ 3367 if (no_iommu || iommu_default_passthrough()) { 3368 pr_warn("SNP: IOMMU disabled or configured in passthrough mode, SNP cannot be supported.\n"); 3369 goto disable_snp; 3370 } 3371 3372 if (amd_iommu_pgtable != PD_MODE_V1) { 3373 pr_warn("SNP: IOMMU is configured with V2 page table mode, SNP cannot be supported.\n"); 3374 goto disable_snp; 3375 } 3376 3377 amd_iommu_snp_en = check_feature(FEATURE_SNP); 3378 if (!amd_iommu_snp_en) { 3379 pr_warn("SNP: IOMMU SNP feature not enabled, SNP cannot be supported.\n"); 3380 goto disable_snp; 3381 } 3382 3383 /* 3384 * Enable host SNP support once SNP support is checked on IOMMU. 3385 */ 3386 if (snp_rmptable_init()) { 3387 pr_warn("SNP: RMP initialization failed, SNP cannot be supported.\n"); 3388 goto disable_snp; 3389 } 3390 3391 pr_info("IOMMU SNP support enabled.\n"); 3392 return; 3393 3394 disable_snp: 3395 cc_platform_clear(CC_ATTR_HOST_SEV_SNP); 3396 #endif 3397 } 3398 3399 /**************************************************************************** 3400 * 3401 * AMD IOMMU Initialization State Machine 3402 * 3403 ****************************************************************************/ 3404 3405 static int __init state_next(void) 3406 { 3407 int ret = 0; 3408 3409 switch (init_state) { 3410 case IOMMU_START_STATE: 3411 if (!detect_ivrs()) { 3412 init_state = IOMMU_NOT_FOUND; 3413 ret = -ENODEV; 3414 } else { 3415 init_state = IOMMU_IVRS_DETECTED; 3416 } 3417 break; 3418 case IOMMU_IVRS_DETECTED: 3419 if (amd_iommu_disabled) { 3420 init_state = IOMMU_CMDLINE_DISABLED; 3421 ret = -EINVAL; 3422 } else { 3423 ret = early_amd_iommu_init(); 3424 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_ACPI_FINISHED; 3425 } 3426 break; 3427 case IOMMU_ACPI_FINISHED: 3428 early_enable_iommus(); 3429 x86_platform.iommu_shutdown = disable_iommus; 3430 init_state = IOMMU_ENABLED; 3431 break; 3432 case IOMMU_ENABLED: 3433 register_syscore(&amd_iommu_syscore); 3434 iommu_snp_enable(); 3435 ret = amd_iommu_init_pci(); 3436 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_PCI_INIT; 3437 break; 3438 case IOMMU_PCI_INIT: 3439 ret = amd_iommu_enable_interrupts(); 3440 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_INTERRUPTS_EN; 3441 break; 3442 case IOMMU_INTERRUPTS_EN: 3443 init_state = IOMMU_INITIALIZED; 3444 break; 3445 case IOMMU_INITIALIZED: 3446 /* Nothing to do */ 3447 break; 3448 case IOMMU_NOT_FOUND: 3449 case IOMMU_INIT_ERROR: 3450 case IOMMU_CMDLINE_DISABLED: 3451 /* Error states => do nothing */ 3452 ret = -EINVAL; 3453 break; 3454 default: 3455 /* Unknown state */ 3456 BUG(); 3457 } 3458 3459 if (ret) { 3460 free_dma_resources(); 3461 if (!irq_remapping_enabled) { 3462 disable_iommus(); 3463 free_iommu_resources(); 3464 } else { 3465 struct amd_iommu *iommu; 3466 struct amd_iommu_pci_seg *pci_seg; 3467 3468 for_each_pci_segment(pci_seg) 3469 uninit_device_table_dma(pci_seg); 3470 3471 for_each_iommu(iommu) 3472 amd_iommu_flush_all_caches(iommu); 3473 } 3474 } 3475 return ret; 3476 } 3477 3478 static int __init iommu_go_to_state(enum iommu_init_state state) 3479 { 3480 int ret = -EINVAL; 3481 3482 while (init_state != state) { 3483 if (init_state == IOMMU_NOT_FOUND || 3484 init_state == IOMMU_INIT_ERROR || 3485 init_state == IOMMU_CMDLINE_DISABLED) 3486 break; 3487 ret = state_next(); 3488 } 3489 3490 /* 3491 * SNP platform initilazation requires IOMMUs to be fully configured. 3492 * If the SNP support on IOMMUs has NOT been checked, simply mark SNP 3493 * as unsupported. If the SNP support on IOMMUs has been checked and 3494 * host SNP support enabled but RMP enforcement has not been enabled 3495 * in IOMMUs, then the system is in a half-baked state, but can limp 3496 * along as all memory should be Hypervisor-Owned in the RMP. WARN, 3497 * but leave SNP as "supported" to avoid confusing the kernel. 3498 */ 3499 if (ret && cc_platform_has(CC_ATTR_HOST_SEV_SNP) && 3500 !WARN_ON_ONCE(amd_iommu_snp_en)) 3501 cc_platform_clear(CC_ATTR_HOST_SEV_SNP); 3502 3503 return ret; 3504 } 3505 3506 #ifdef CONFIG_IRQ_REMAP 3507 int __init amd_iommu_prepare(void) 3508 { 3509 int ret; 3510 3511 amd_iommu_irq_remap = true; 3512 3513 ret = iommu_go_to_state(IOMMU_ACPI_FINISHED); 3514 if (ret) { 3515 amd_iommu_irq_remap = false; 3516 return ret; 3517 } 3518 3519 return amd_iommu_irq_remap ? 0 : -ENODEV; 3520 } 3521 3522 int __init amd_iommu_enable(void) 3523 { 3524 int ret; 3525 3526 ret = iommu_go_to_state(IOMMU_ENABLED); 3527 if (ret) 3528 return ret; 3529 3530 irq_remapping_enabled = 1; 3531 return amd_iommu_xt_mode; 3532 } 3533 3534 void amd_iommu_disable(void) 3535 { 3536 amd_iommu_suspend(NULL); 3537 } 3538 3539 int amd_iommu_reenable(int mode) 3540 { 3541 amd_iommu_resume(NULL); 3542 3543 return 0; 3544 } 3545 3546 int amd_iommu_enable_faulting(unsigned int cpu) 3547 { 3548 /* We enable MSI later when PCI is initialized */ 3549 return 0; 3550 } 3551 #endif 3552 3553 /* 3554 * This is the core init function for AMD IOMMU hardware in the system. 3555 * This function is called from the generic x86 DMA layer initialization 3556 * code. 3557 */ 3558 static int __init amd_iommu_init(void) 3559 { 3560 int ret; 3561 3562 ret = iommu_go_to_state(IOMMU_INITIALIZED); 3563 #ifdef CONFIG_GART_IOMMU 3564 if (ret && list_empty(&amd_iommu_list)) { 3565 /* 3566 * We failed to initialize the AMD IOMMU - try fallback 3567 * to GART if possible. 3568 */ 3569 gart_iommu_init(); 3570 } 3571 #endif 3572 3573 if (!ret) 3574 amd_iommu_debugfs_setup(); 3575 3576 return ret; 3577 } 3578 3579 static bool amd_iommu_sme_check(void) 3580 { 3581 if (!cc_platform_has(CC_ATTR_HOST_MEM_ENCRYPT) || 3582 (boot_cpu_data.x86 != 0x17)) 3583 return true; 3584 3585 /* For Fam17h, a specific level of support is required */ 3586 if (boot_cpu_data.microcode >= 0x08001205) 3587 return true; 3588 3589 if ((boot_cpu_data.microcode >= 0x08001126) && 3590 (boot_cpu_data.microcode <= 0x080011ff)) 3591 return true; 3592 3593 pr_notice("IOMMU not currently supported when SME is active\n"); 3594 3595 return false; 3596 } 3597 3598 /**************************************************************************** 3599 * 3600 * Early detect code. This code runs at IOMMU detection time in the DMA 3601 * layer. It just looks if there is an IVRS ACPI table to detect AMD 3602 * IOMMUs 3603 * 3604 ****************************************************************************/ 3605 void __init amd_iommu_detect(void) 3606 { 3607 int ret; 3608 3609 if (no_iommu || (iommu_detected && !gart_iommu_aperture)) 3610 goto disable_snp; 3611 3612 if (!amd_iommu_sme_check()) 3613 goto disable_snp; 3614 3615 ret = iommu_go_to_state(IOMMU_IVRS_DETECTED); 3616 if (ret) 3617 goto disable_snp; 3618 3619 amd_iommu_detected = true; 3620 iommu_detected = 1; 3621 x86_init.iommu.iommu_init = amd_iommu_init; 3622 return; 3623 3624 disable_snp: 3625 if (cc_platform_has(CC_ATTR_HOST_SEV_SNP)) 3626 cc_platform_clear(CC_ATTR_HOST_SEV_SNP); 3627 } 3628 3629 /**************************************************************************** 3630 * 3631 * Parsing functions for the AMD IOMMU specific kernel command line 3632 * options. 3633 * 3634 ****************************************************************************/ 3635 3636 static int __init parse_amd_iommu_dump(char *str) 3637 { 3638 amd_iommu_dump = true; 3639 3640 return 1; 3641 } 3642 3643 static int __init parse_amd_iommu_intr(char *str) 3644 { 3645 for (; *str; ++str) { 3646 if (strncmp(str, "legacy", 6) == 0) { 3647 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY_GA; 3648 break; 3649 } 3650 if (strncmp(str, "vapic", 5) == 0) { 3651 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC; 3652 break; 3653 } 3654 } 3655 return 1; 3656 } 3657 3658 static int __init parse_amd_iommu_options(char *str) 3659 { 3660 if (!str) 3661 return -EINVAL; 3662 3663 while (*str) { 3664 if (strncmp(str, "fullflush", 9) == 0) { 3665 pr_warn("amd_iommu=fullflush deprecated; use iommu.strict=1 instead\n"); 3666 iommu_set_dma_strict(); 3667 } else if (strncmp(str, "force_enable", 12) == 0) { 3668 amd_iommu_force_enable = true; 3669 } else if (strncmp(str, "off", 3) == 0) { 3670 amd_iommu_disabled = true; 3671 } else if (strncmp(str, "force_isolation", 15) == 0) { 3672 amd_iommu_force_isolation = true; 3673 } else if (strncmp(str, "pgtbl_v1", 8) == 0) { 3674 amd_iommu_pgtable = PD_MODE_V1; 3675 } else if (strncmp(str, "pgtbl_v2", 8) == 0) { 3676 amd_iommu_pgtable = PD_MODE_V2; 3677 } else if (strncmp(str, "irtcachedis", 11) == 0) { 3678 amd_iommu_irtcachedis = true; 3679 } else if (strncmp(str, "nohugepages", 11) == 0) { 3680 pr_info("Restricting V1 page-sizes to 4KiB"); 3681 amd_iommu_pgsize_bitmap = AMD_IOMMU_PGSIZES_4K; 3682 } else if (strncmp(str, "v2_pgsizes_only", 15) == 0) { 3683 pr_info("Restricting V1 page-sizes to 4KiB/2MiB/1GiB"); 3684 amd_iommu_pgsize_bitmap = AMD_IOMMU_PGSIZES_V2; 3685 } else { 3686 pr_notice("Unknown option - '%s'\n", str); 3687 } 3688 3689 str += strcspn(str, ","); 3690 while (*str == ',') 3691 str++; 3692 } 3693 3694 return 1; 3695 } 3696 3697 static int __init parse_ivrs_ioapic(char *str) 3698 { 3699 u32 seg = 0, bus, dev, fn; 3700 int id, i; 3701 u32 devid; 3702 3703 if (sscanf(str, "=%d@%x:%x.%x", &id, &bus, &dev, &fn) == 4 || 3704 sscanf(str, "=%d@%x:%x:%x.%x", &id, &seg, &bus, &dev, &fn) == 5) 3705 goto found; 3706 3707 if (sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn) == 4 || 3708 sscanf(str, "[%d]=%x:%x:%x.%x", &id, &seg, &bus, &dev, &fn) == 5) { 3709 pr_warn("ivrs_ioapic%s option format deprecated; use ivrs_ioapic=%d@%04x:%02x:%02x.%d instead\n", 3710 str, id, seg, bus, dev, fn); 3711 goto found; 3712 } 3713 3714 pr_err("Invalid command line: ivrs_ioapic%s\n", str); 3715 return 1; 3716 3717 found: 3718 if (early_ioapic_map_size == EARLY_MAP_SIZE) { 3719 pr_err("Early IOAPIC map overflow - ignoring ivrs_ioapic%s\n", 3720 str); 3721 return 1; 3722 } 3723 3724 devid = IVRS_GET_SBDF_ID(seg, bus, dev, fn); 3725 3726 cmdline_maps = true; 3727 i = early_ioapic_map_size++; 3728 early_ioapic_map[i].id = id; 3729 early_ioapic_map[i].devid = devid; 3730 early_ioapic_map[i].cmd_line = true; 3731 3732 return 1; 3733 } 3734 3735 static int __init parse_ivrs_hpet(char *str) 3736 { 3737 u32 seg = 0, bus, dev, fn; 3738 int id, i; 3739 u32 devid; 3740 3741 if (sscanf(str, "=%d@%x:%x.%x", &id, &bus, &dev, &fn) == 4 || 3742 sscanf(str, "=%d@%x:%x:%x.%x", &id, &seg, &bus, &dev, &fn) == 5) 3743 goto found; 3744 3745 if (sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn) == 4 || 3746 sscanf(str, "[%d]=%x:%x:%x.%x", &id, &seg, &bus, &dev, &fn) == 5) { 3747 pr_warn("ivrs_hpet%s option format deprecated; use ivrs_hpet=%d@%04x:%02x:%02x.%d instead\n", 3748 str, id, seg, bus, dev, fn); 3749 goto found; 3750 } 3751 3752 pr_err("Invalid command line: ivrs_hpet%s\n", str); 3753 return 1; 3754 3755 found: 3756 if (early_hpet_map_size == EARLY_MAP_SIZE) { 3757 pr_err("Early HPET map overflow - ignoring ivrs_hpet%s\n", 3758 str); 3759 return 1; 3760 } 3761 3762 devid = IVRS_GET_SBDF_ID(seg, bus, dev, fn); 3763 3764 cmdline_maps = true; 3765 i = early_hpet_map_size++; 3766 early_hpet_map[i].id = id; 3767 early_hpet_map[i].devid = devid; 3768 early_hpet_map[i].cmd_line = true; 3769 3770 return 1; 3771 } 3772 3773 #define ACPIID_LEN (ACPIHID_UID_LEN + ACPIHID_HID_LEN) 3774 3775 static int __init parse_ivrs_acpihid(char *str) 3776 { 3777 u32 seg = 0, bus, dev, fn; 3778 char *hid, *uid, *p, *addr; 3779 char acpiid[ACPIID_LEN + 1] = { }; /* size with NULL terminator */ 3780 int i; 3781 3782 addr = strchr(str, '@'); 3783 if (!addr) { 3784 addr = strchr(str, '='); 3785 if (!addr) 3786 goto not_found; 3787 3788 ++addr; 3789 3790 if (strlen(addr) > ACPIID_LEN) 3791 goto not_found; 3792 3793 if (sscanf(str, "[%x:%x.%x]=%s", &bus, &dev, &fn, acpiid) == 4 || 3794 sscanf(str, "[%x:%x:%x.%x]=%s", &seg, &bus, &dev, &fn, acpiid) == 5) { 3795 pr_warn("ivrs_acpihid%s option format deprecated; use ivrs_acpihid=%s@%04x:%02x:%02x.%d instead\n", 3796 str, acpiid, seg, bus, dev, fn); 3797 goto found; 3798 } 3799 goto not_found; 3800 } 3801 3802 /* We have the '@', make it the terminator to get just the acpiid */ 3803 *addr++ = 0; 3804 3805 if (strlen(str) > ACPIID_LEN) 3806 goto not_found; 3807 3808 if (sscanf(str, "=%s", acpiid) != 1) 3809 goto not_found; 3810 3811 if (sscanf(addr, "%x:%x.%x", &bus, &dev, &fn) == 3 || 3812 sscanf(addr, "%x:%x:%x.%x", &seg, &bus, &dev, &fn) == 4) 3813 goto found; 3814 3815 not_found: 3816 pr_err("Invalid command line: ivrs_acpihid%s\n", str); 3817 return 1; 3818 3819 found: 3820 p = acpiid; 3821 hid = strsep(&p, ":"); 3822 uid = p; 3823 3824 if (!hid || !(*hid) || !uid) { 3825 pr_err("Invalid command line: hid or uid\n"); 3826 return 1; 3827 } 3828 3829 /* 3830 * Ignore leading zeroes after ':', so e.g., AMDI0095:00 3831 * will match AMDI0095:0 in the second strcmp in acpi_dev_hid_uid_match 3832 */ 3833 while (*uid == '0' && *(uid + 1)) 3834 uid++; 3835 3836 if (strlen(hid) >= ACPIHID_HID_LEN) { 3837 pr_err("Invalid command line: hid is too long\n"); 3838 return 1; 3839 } else if (strlen(uid) >= ACPIHID_UID_LEN) { 3840 pr_err("Invalid command line: uid is too long\n"); 3841 return 1; 3842 } 3843 3844 i = early_acpihid_map_size++; 3845 memcpy(early_acpihid_map[i].hid, hid, strlen(hid)); 3846 memcpy(early_acpihid_map[i].uid, uid, strlen(uid)); 3847 early_acpihid_map[i].devid = IVRS_GET_SBDF_ID(seg, bus, dev, fn); 3848 early_acpihid_map[i].cmd_line = true; 3849 3850 return 1; 3851 } 3852 3853 __setup("amd_iommu_dump", parse_amd_iommu_dump); 3854 __setup("amd_iommu=", parse_amd_iommu_options); 3855 __setup("amd_iommu_intr=", parse_amd_iommu_intr); 3856 __setup("ivrs_ioapic", parse_ivrs_ioapic); 3857 __setup("ivrs_hpet", parse_ivrs_hpet); 3858 __setup("ivrs_acpihid", parse_ivrs_acpihid); 3859 3860 bool amd_iommu_pasid_supported(void) 3861 { 3862 /* CPU page table size should match IOMMU guest page table size */ 3863 if (cpu_feature_enabled(X86_FEATURE_LA57) && 3864 amd_iommu_gpt_level != PAGE_MODE_5_LEVEL) 3865 return false; 3866 3867 /* 3868 * Since DTE[Mode]=0 is prohibited on SNP-enabled system 3869 * (i.e. EFR[SNPSup]=1), IOMMUv2 page table cannot be used without 3870 * setting up IOMMUv1 page table. 3871 */ 3872 return amd_iommu_gt_ppr_supported() && !amd_iommu_snp_en; 3873 } 3874 3875 struct amd_iommu *get_amd_iommu(unsigned int idx) 3876 { 3877 unsigned int i = 0; 3878 struct amd_iommu *iommu; 3879 3880 for_each_iommu(iommu) 3881 if (i++ == idx) 3882 return iommu; 3883 return NULL; 3884 } 3885 3886 /**************************************************************************** 3887 * 3888 * IOMMU EFR Performance Counter support functionality. This code allows 3889 * access to the IOMMU PC functionality. 3890 * 3891 ****************************************************************************/ 3892 3893 u8 amd_iommu_pc_get_max_banks(unsigned int idx) 3894 { 3895 struct amd_iommu *iommu = get_amd_iommu(idx); 3896 3897 if (iommu) 3898 return iommu->max_banks; 3899 3900 return 0; 3901 } 3902 3903 bool amd_iommu_pc_supported(void) 3904 { 3905 return amd_iommu_pc_present; 3906 } 3907 3908 u8 amd_iommu_pc_get_max_counters(unsigned int idx) 3909 { 3910 struct amd_iommu *iommu = get_amd_iommu(idx); 3911 3912 if (iommu) 3913 return iommu->max_counters; 3914 3915 return 0; 3916 } 3917 3918 static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, 3919 u8 fxn, u64 *value, bool is_write) 3920 { 3921 u32 offset; 3922 u32 max_offset_lim; 3923 3924 /* Make sure the IOMMU PC resource is available */ 3925 if (!amd_iommu_pc_present) 3926 return -ENODEV; 3927 3928 /* Check for valid iommu and pc register indexing */ 3929 if (WARN_ON(!iommu || (fxn > 0x28) || (fxn & 7))) 3930 return -ENODEV; 3931 3932 offset = (u32)(((0x40 | bank) << 12) | (cntr << 8) | fxn); 3933 3934 /* Limit the offset to the hw defined mmio region aperture */ 3935 max_offset_lim = (u32)(((0x40 | iommu->max_banks) << 12) | 3936 (iommu->max_counters << 8) | 0x28); 3937 if ((offset < MMIO_CNTR_REG_OFFSET) || 3938 (offset > max_offset_lim)) 3939 return -EINVAL; 3940 3941 if (is_write) { 3942 u64 val = *value & GENMASK_ULL(47, 0); 3943 3944 writel((u32)val, iommu->mmio_base + offset); 3945 writel((val >> 32), iommu->mmio_base + offset + 4); 3946 } else { 3947 *value = readl(iommu->mmio_base + offset + 4); 3948 *value <<= 32; 3949 *value |= readl(iommu->mmio_base + offset); 3950 *value &= GENMASK_ULL(47, 0); 3951 } 3952 3953 return 0; 3954 } 3955 3956 int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value) 3957 { 3958 if (!iommu) 3959 return -EINVAL; 3960 3961 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, false); 3962 } 3963 3964 int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value) 3965 { 3966 if (!iommu) 3967 return -EINVAL; 3968 3969 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, true); 3970 } 3971 3972 #ifdef CONFIG_KVM_AMD_SEV 3973 static int iommu_page_make_shared(void *page) 3974 { 3975 unsigned long paddr, pfn; 3976 3977 paddr = iommu_virt_to_phys(page); 3978 /* Cbit maybe set in the paddr */ 3979 pfn = __sme_clr(paddr) >> PAGE_SHIFT; 3980 3981 if (!(pfn % PTRS_PER_PMD)) { 3982 int ret, level; 3983 bool assigned; 3984 3985 ret = snp_lookup_rmpentry(pfn, &assigned, &level); 3986 if (ret) { 3987 pr_warn("IOMMU PFN %lx RMP lookup failed, ret %d\n", pfn, ret); 3988 return ret; 3989 } 3990 3991 if (!assigned) { 3992 pr_warn("IOMMU PFN %lx not assigned in RMP table\n", pfn); 3993 return -EINVAL; 3994 } 3995 3996 if (level > PG_LEVEL_4K) { 3997 ret = psmash(pfn); 3998 if (!ret) 3999 goto done; 4000 4001 pr_warn("PSMASH failed for IOMMU PFN %lx huge RMP entry, ret: %d, level: %d\n", 4002 pfn, ret, level); 4003 return ret; 4004 } 4005 } 4006 4007 done: 4008 return rmp_make_shared(pfn, PG_LEVEL_4K); 4009 } 4010 4011 static int iommu_make_shared(void *va, size_t size) 4012 { 4013 void *page; 4014 int ret; 4015 4016 if (!va) 4017 return 0; 4018 4019 for (page = va; page < (va + size); page += PAGE_SIZE) { 4020 ret = iommu_page_make_shared(page); 4021 if (ret) 4022 return ret; 4023 } 4024 4025 return 0; 4026 } 4027 4028 int amd_iommu_snp_disable(void) 4029 { 4030 struct amd_iommu *iommu; 4031 int ret; 4032 4033 if (!amd_iommu_snp_en) 4034 return 0; 4035 4036 for_each_iommu(iommu) { 4037 ret = iommu_make_shared(iommu->evt_buf, EVT_BUFFER_SIZE); 4038 if (ret) 4039 return ret; 4040 4041 ret = iommu_make_shared(iommu->ppr_log, PPR_LOG_SIZE); 4042 if (ret) 4043 return ret; 4044 4045 ret = iommu_make_shared((void *)iommu->cmd_sem, PAGE_SIZE); 4046 if (ret) 4047 return ret; 4048 } 4049 4050 return 0; 4051 } 4052 EXPORT_SYMBOL_GPL(amd_iommu_snp_disable); 4053 4054 bool amd_iommu_sev_tio_supported(void) 4055 { 4056 return check_feature2(FEATURE_SEVSNPIO_SUP); 4057 } 4058 EXPORT_SYMBOL_GPL(amd_iommu_sev_tio_supported); 4059 #endif 4060