1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2009-2010 Advanced Micro Devices, Inc. 4 * Author: Joerg Roedel <jroedel@suse.de> 5 */ 6 7 #ifndef AMD_IOMMU_H 8 #define AMD_IOMMU_H 9 10 #include <linux/iommu.h> 11 12 #include "amd_iommu_types.h" 13 14 irqreturn_t amd_iommu_int_thread(int irq, void *data); 15 irqreturn_t amd_iommu_int_thread_evtlog(int irq, void *data); 16 irqreturn_t amd_iommu_int_thread_pprlog(int irq, void *data); 17 irqreturn_t amd_iommu_int_thread_galog(int irq, void *data); 18 irqreturn_t amd_iommu_int_handler(int irq, void *data); 19 void amd_iommu_apply_erratum_63(struct amd_iommu *iommu, u16 devid); 20 void amd_iommu_restart_event_logging(struct amd_iommu *iommu); 21 void amd_iommu_restart_ga_log(struct amd_iommu *iommu); 22 void amd_iommu_restart_ppr_log(struct amd_iommu *iommu); 23 void amd_iommu_set_rlookup_table(struct amd_iommu *iommu, u16 devid); 24 25 #ifdef CONFIG_AMD_IOMMU_DEBUGFS 26 void amd_iommu_debugfs_setup(struct amd_iommu *iommu); 27 #else 28 static inline void amd_iommu_debugfs_setup(struct amd_iommu *iommu) {} 29 #endif 30 31 /* Needed for interrupt remapping */ 32 int amd_iommu_prepare(void); 33 int amd_iommu_enable(void); 34 void amd_iommu_disable(void); 35 int amd_iommu_reenable(int mode); 36 int amd_iommu_enable_faulting(void); 37 extern int amd_iommu_guest_ir; 38 extern enum io_pgtable_fmt amd_iommu_pgtable; 39 extern int amd_iommu_gpt_level; 40 41 bool amd_iommu_v2_supported(void); 42 struct amd_iommu *get_amd_iommu(unsigned int idx); 43 u8 amd_iommu_pc_get_max_banks(unsigned int idx); 44 bool amd_iommu_pc_supported(void); 45 u8 amd_iommu_pc_get_max_counters(unsigned int idx); 46 int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, 47 u8 fxn, u64 *value); 48 int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, 49 u8 fxn, u64 *value); 50 51 /* Device capabilities */ 52 int amd_iommu_pdev_enable_cap_pri(struct pci_dev *pdev); 53 void amd_iommu_pdev_disable_cap_pri(struct pci_dev *pdev); 54 55 int amd_iommu_flush_page(struct iommu_domain *dom, u32 pasid, u64 address); 56 /* 57 * This function flushes all internal caches of 58 * the IOMMU used by this driver. 59 */ 60 void amd_iommu_flush_all_caches(struct amd_iommu *iommu); 61 void amd_iommu_update_and_flush_device_table(struct protection_domain *domain); 62 void amd_iommu_domain_update(struct protection_domain *domain); 63 void amd_iommu_domain_flush_complete(struct protection_domain *domain); 64 void amd_iommu_domain_flush_pages(struct protection_domain *domain, 65 u64 address, size_t size); 66 int amd_iommu_flush_tlb(struct iommu_domain *dom, u32 pasid); 67 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, u32 pasid, 68 unsigned long cr3); 69 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, u32 pasid); 70 71 #ifdef CONFIG_IRQ_REMAP 72 int amd_iommu_create_irq_domain(struct amd_iommu *iommu); 73 #else 74 static inline int amd_iommu_create_irq_domain(struct amd_iommu *iommu) 75 { 76 return 0; 77 } 78 #endif 79 80 #define PPR_SUCCESS 0x0 81 #define PPR_INVALID 0x1 82 #define PPR_FAILURE 0xf 83 84 int amd_iommu_complete_ppr(struct pci_dev *pdev, u32 pasid, 85 int status, int tag); 86 87 static inline bool is_rd890_iommu(struct pci_dev *pdev) 88 { 89 return (pdev->vendor == PCI_VENDOR_ID_ATI) && 90 (pdev->device == PCI_DEVICE_ID_RD890_IOMMU); 91 } 92 93 static inline bool check_feature(u64 mask) 94 { 95 return (amd_iommu_efr & mask); 96 } 97 98 static inline bool check_feature2(u64 mask) 99 { 100 return (amd_iommu_efr2 & mask); 101 } 102 103 static inline int check_feature_gpt_level(void) 104 { 105 return ((amd_iommu_efr >> FEATURE_GATS_SHIFT) & FEATURE_GATS_MASK); 106 } 107 108 static inline bool amd_iommu_gt_ppr_supported(void) 109 { 110 return (check_feature(FEATURE_GT) && 111 check_feature(FEATURE_PPR)); 112 } 113 114 static inline u64 iommu_virt_to_phys(void *vaddr) 115 { 116 return (u64)__sme_set(virt_to_phys(vaddr)); 117 } 118 119 static inline void *iommu_phys_to_virt(unsigned long paddr) 120 { 121 return phys_to_virt(__sme_clr(paddr)); 122 } 123 124 static inline 125 void amd_iommu_domain_set_pt_root(struct protection_domain *domain, u64 root) 126 { 127 domain->iop.root = (u64 *)(root & PAGE_MASK); 128 domain->iop.mode = root & 7; /* lowest 3 bits encode pgtable mode */ 129 } 130 131 static inline 132 void amd_iommu_domain_clr_pt_root(struct protection_domain *domain) 133 { 134 amd_iommu_domain_set_pt_root(domain, 0); 135 } 136 137 static inline int get_pci_sbdf_id(struct pci_dev *pdev) 138 { 139 int seg = pci_domain_nr(pdev->bus); 140 u16 devid = pci_dev_id(pdev); 141 142 return PCI_SEG_DEVID_TO_SBDF(seg, devid); 143 } 144 145 static inline void *alloc_pgtable_page(int nid, gfp_t gfp) 146 { 147 struct page *page; 148 149 page = alloc_pages_node(nid, gfp | __GFP_ZERO, 0); 150 return page ? page_address(page) : NULL; 151 } 152 153 bool translation_pre_enabled(struct amd_iommu *iommu); 154 bool amd_iommu_is_attach_deferred(struct device *dev); 155 int __init add_special_device(u8 type, u8 id, u32 *devid, bool cmd_line); 156 157 #ifdef CONFIG_DMI 158 void amd_iommu_apply_ivrs_quirks(void); 159 #else 160 static inline void amd_iommu_apply_ivrs_quirks(void) { } 161 #endif 162 163 void amd_iommu_domain_set_pgtable(struct protection_domain *domain, 164 u64 *root, int mode); 165 struct dev_table_entry *get_dev_table(struct amd_iommu *iommu); 166 167 extern bool amd_iommu_snp_en; 168 #endif 169