1ab493a0fSOhad Ben-Cohen# IOMMU_API always gets selected by whoever wants it. 2ab493a0fSOhad Ben-Cohenconfig IOMMU_API 3ab493a0fSOhad Ben-Cohen bool 4b10f127eSOhad Ben-Cohen 568255b62SJoerg Roedelmenuconfig IOMMU_SUPPORT 668255b62SJoerg Roedel bool "IOMMU Hardware Support" 768255b62SJoerg Roedel default y 868255b62SJoerg Roedel ---help--- 968255b62SJoerg Roedel Say Y here if you want to compile device drivers for IO Memory 1068255b62SJoerg Roedel Management Units into the kernel. These devices usually allow to 1168255b62SJoerg Roedel remap DMA requests and/or remap interrupts from other devices on the 1268255b62SJoerg Roedel system. 1368255b62SJoerg Roedel 1468255b62SJoerg Roedelif IOMMU_SUPPORT 1568255b62SJoerg Roedel 16fdb1d7beSWill Deaconmenu "Generic IOMMU Pagetable Support" 17fdb1d7beSWill Deacon 18fdb1d7beSWill Deacon# Selected by the actual pagetable implementations 19fdb1d7beSWill Deaconconfig IOMMU_IO_PGTABLE 20fdb1d7beSWill Deacon bool 21fdb1d7beSWill Deacon 22e1d3c0fdSWill Deaconconfig IOMMU_IO_PGTABLE_LPAE 23e1d3c0fdSWill Deacon bool "ARMv7/v8 Long Descriptor Format" 24e1d3c0fdSWill Deacon select IOMMU_IO_PGTABLE 25e1d3c0fdSWill Deacon help 26e1d3c0fdSWill Deacon Enable support for the ARM long descriptor pagetable format. 27e1d3c0fdSWill Deacon This allocator supports 4K/2M/1G, 16K/32M and 64K/512M page 28e1d3c0fdSWill Deacon sizes at both stage-1 and stage-2, as well as address spaces 29e1d3c0fdSWill Deacon up to 48-bits in size. 30e1d3c0fdSWill Deacon 31fe4b991dSWill Deaconconfig IOMMU_IO_PGTABLE_LPAE_SELFTEST 32fe4b991dSWill Deacon bool "LPAE selftests" 33fe4b991dSWill Deacon depends on IOMMU_IO_PGTABLE_LPAE 34fe4b991dSWill Deacon help 35fe4b991dSWill Deacon Enable self-tests for LPAE page table allocator. This performs 36fe4b991dSWill Deacon a series of page-table consistency checks during boot. 37fe4b991dSWill Deacon 38fe4b991dSWill Deacon If unsure, say N here. 39fe4b991dSWill Deacon 40fdb1d7beSWill Deaconendmenu 41fdb1d7beSWill Deacon 424e0ee78fSHiroshi Doyuconfig OF_IOMMU 434e0ee78fSHiroshi Doyu def_bool y 447eba1d51SWill Deacon depends on OF && IOMMU_API 454e0ee78fSHiroshi Doyu 46695093e3SVarun Sethiconfig FSL_PAMU 47695093e3SVarun Sethi bool "Freescale IOMMU support" 48695093e3SVarun Sethi depends on PPC_E500MC 49695093e3SVarun Sethi select IOMMU_API 50695093e3SVarun Sethi select GENERIC_ALLOCATOR 51695093e3SVarun Sethi help 52695093e3SVarun Sethi Freescale PAMU support. PAMU is the IOMMU present on Freescale QorIQ platforms. 53695093e3SVarun Sethi PAMU can authorize memory access, remap the memory address, and remap I/O 54695093e3SVarun Sethi transaction types. 55695093e3SVarun Sethi 56b10f127eSOhad Ben-Cohen# MSM IOMMU support 57b10f127eSOhad Ben-Cohenconfig MSM_IOMMU 58b10f127eSOhad Ben-Cohen bool "MSM IOMMU Support" 59b10f127eSOhad Ben-Cohen depends on ARCH_MSM8X60 || ARCH_MSM8960 60b10f127eSOhad Ben-Cohen select IOMMU_API 61b10f127eSOhad Ben-Cohen help 62b10f127eSOhad Ben-Cohen Support for the IOMMUs found on certain Qualcomm SOCs. 63b10f127eSOhad Ben-Cohen These IOMMUs allow virtualization of the address space used by most 64b10f127eSOhad Ben-Cohen cores within the multimedia subsystem. 65b10f127eSOhad Ben-Cohen 66b10f127eSOhad Ben-Cohen If unsure, say N here. 67b10f127eSOhad Ben-Cohen 68b10f127eSOhad Ben-Cohenconfig IOMMU_PGTABLES_L2 69b10f127eSOhad Ben-Cohen def_bool y 70b10f127eSOhad Ben-Cohen depends on MSM_IOMMU && MMU && SMP && CPU_DCACHE_DISABLE=n 7129b68415SOhad Ben-Cohen 7229b68415SOhad Ben-Cohen# AMD IOMMU support 7329b68415SOhad Ben-Cohenconfig AMD_IOMMU 7429b68415SOhad Ben-Cohen bool "AMD IOMMU support" 7529b68415SOhad Ben-Cohen select SWIOTLB 7629b68415SOhad Ben-Cohen select PCI_MSI 7752815b75SJoerg Roedel select PCI_ATS 7852815b75SJoerg Roedel select PCI_PRI 7952815b75SJoerg Roedel select PCI_PASID 8029b68415SOhad Ben-Cohen select IOMMU_API 810dbc6078SThomas Petazzoni depends on X86_64 && PCI && ACPI 8229b68415SOhad Ben-Cohen ---help--- 8329b68415SOhad Ben-Cohen With this option you can enable support for AMD IOMMU hardware in 8429b68415SOhad Ben-Cohen your system. An IOMMU is a hardware component which provides 8529b68415SOhad Ben-Cohen remapping of DMA memory accesses from devices. With an AMD IOMMU you 8659bf8964SMasanari Iida can isolate the DMA memory of different devices and protect the 8729b68415SOhad Ben-Cohen system from misbehaving device drivers or hardware. 8829b68415SOhad Ben-Cohen 8929b68415SOhad Ben-Cohen You can find out if your system has an AMD IOMMU if you look into 9029b68415SOhad Ben-Cohen your BIOS for an option to enable it or if you have an IVRS ACPI 9129b68415SOhad Ben-Cohen table. 9229b68415SOhad Ben-Cohen 9329b68415SOhad Ben-Cohenconfig AMD_IOMMU_STATS 9429b68415SOhad Ben-Cohen bool "Export AMD IOMMU statistics to debugfs" 9529b68415SOhad Ben-Cohen depends on AMD_IOMMU 9629b68415SOhad Ben-Cohen select DEBUG_FS 9729b68415SOhad Ben-Cohen ---help--- 9829b68415SOhad Ben-Cohen This option enables code in the AMD IOMMU driver to collect various 9929b68415SOhad Ben-Cohen statistics about whats happening in the driver and exports that 10029b68415SOhad Ben-Cohen information to userspace via debugfs. 10129b68415SOhad Ben-Cohen If unsure, say N. 102166e9278SOhad Ben-Cohen 103e3c495c7SJoerg Roedelconfig AMD_IOMMU_V2 104a446e219SKees Cook tristate "AMD IOMMU Version 2 driver" 105e5cac32cSBorislav Petkov depends on AMD_IOMMU 1068736b2c3SJoerg Roedel select MMU_NOTIFIER 107e3c495c7SJoerg Roedel ---help--- 108e3c495c7SJoerg Roedel This option enables support for the AMD IOMMUv2 features of the IOMMU 109e3c495c7SJoerg Roedel hardware. Select this option if you want to use devices that support 11059bf8964SMasanari Iida the PCI PRI and PASID interface. 111e3c495c7SJoerg Roedel 112166e9278SOhad Ben-Cohen# Intel IOMMU support 113d3f13810SSuresh Siddhaconfig DMAR_TABLE 114d3f13810SSuresh Siddha bool 115d3f13810SSuresh Siddha 116d3f13810SSuresh Siddhaconfig INTEL_IOMMU 117d3f13810SSuresh Siddha bool "Support for Intel IOMMU using DMA Remapping Devices" 118166e9278SOhad Ben-Cohen depends on PCI_MSI && ACPI && (X86 || IA64_GENERIC) 119166e9278SOhad Ben-Cohen select IOMMU_API 120d3f13810SSuresh Siddha select DMAR_TABLE 121166e9278SOhad Ben-Cohen help 122166e9278SOhad Ben-Cohen DMA remapping (DMAR) devices support enables independent address 123166e9278SOhad Ben-Cohen translations for Direct Memory Access (DMA) from devices. 124166e9278SOhad Ben-Cohen These DMA remapping devices are reported via ACPI tables 125166e9278SOhad Ben-Cohen and include PCI device scope covered by these DMA 126166e9278SOhad Ben-Cohen remapping devices. 127166e9278SOhad Ben-Cohen 128d3f13810SSuresh Siddhaconfig INTEL_IOMMU_DEFAULT_ON 129166e9278SOhad Ben-Cohen def_bool y 130d3f13810SSuresh Siddha prompt "Enable Intel DMA Remapping Devices by default" 131d3f13810SSuresh Siddha depends on INTEL_IOMMU 132166e9278SOhad Ben-Cohen help 133166e9278SOhad Ben-Cohen Selecting this option will enable a DMAR device at boot time if 134166e9278SOhad Ben-Cohen one is found. If this option is not selected, DMAR support can 135166e9278SOhad Ben-Cohen be enabled by passing intel_iommu=on to the kernel. 136166e9278SOhad Ben-Cohen 137d3f13810SSuresh Siddhaconfig INTEL_IOMMU_BROKEN_GFX_WA 138166e9278SOhad Ben-Cohen bool "Workaround broken graphics drivers (going away soon)" 139d3f13810SSuresh Siddha depends on INTEL_IOMMU && BROKEN && X86 140166e9278SOhad Ben-Cohen ---help--- 141166e9278SOhad Ben-Cohen Current Graphics drivers tend to use physical address 142166e9278SOhad Ben-Cohen for DMA and avoid using DMA APIs. Setting this config 143166e9278SOhad Ben-Cohen option permits the IOMMU driver to set a unity map for 144166e9278SOhad Ben-Cohen all the OS-visible memory. Hence the driver can continue 145166e9278SOhad Ben-Cohen to use physical addresses for DMA, at least until this 146166e9278SOhad Ben-Cohen option is removed in the 2.6.32 kernel. 147166e9278SOhad Ben-Cohen 148d3f13810SSuresh Siddhaconfig INTEL_IOMMU_FLOPPY_WA 149166e9278SOhad Ben-Cohen def_bool y 150d3f13810SSuresh Siddha depends on INTEL_IOMMU && X86 151166e9278SOhad Ben-Cohen ---help--- 152166e9278SOhad Ben-Cohen Floppy disk drivers are known to bypass DMA API calls 153166e9278SOhad Ben-Cohen thereby failing to work when IOMMU is enabled. This 154166e9278SOhad Ben-Cohen workaround will setup a 1:1 mapping for the first 155166e9278SOhad Ben-Cohen 16MiB to make floppy (an ISA device) work. 156166e9278SOhad Ben-Cohen 157d3f13810SSuresh Siddhaconfig IRQ_REMAP 158a446e219SKees Cook bool "Support for Interrupt Remapping" 159a446e219SKees Cook depends on X86_64 && X86_IO_APIC && PCI_MSI && ACPI 160d3f13810SSuresh Siddha select DMAR_TABLE 161166e9278SOhad Ben-Cohen ---help--- 162166e9278SOhad Ben-Cohen Supports Interrupt remapping for IO-APIC and MSI devices. 163166e9278SOhad Ben-Cohen To use x2apic mode in the CPU's which support x2APIC enhancements or 164166e9278SOhad Ben-Cohen to support platforms with CPU's having > 8 bit APIC ID, say Y. 16568255b62SJoerg Roedel 166fcf3a6efSOhad Ben-Cohen# OMAP IOMMU support 167fcf3a6efSOhad Ben-Cohenconfig OMAP_IOMMU 168fcf3a6efSOhad Ben-Cohen bool "OMAP IOMMU Support" 169ae191589SArnd Bergmann depends on ARCH_OMAP2PLUS 170fcf3a6efSOhad Ben-Cohen select IOMMU_API 171fcf3a6efSOhad Ben-Cohen 172fcf3a6efSOhad Ben-Cohenconfig OMAP_IOMMU_DEBUG 17361c75352SSuman Anna bool "Export OMAP IOMMU internals in DebugFS" 174baaa7b5dSLaurent Pinchart depends on OMAP_IOMMU && DEBUG_FS 17561c75352SSuman Anna ---help--- 176fcf3a6efSOhad Ben-Cohen Select this to see extensive information about 177baaa7b5dSLaurent Pinchart the internal state of OMAP IOMMU in debugfs. 178fcf3a6efSOhad Ben-Cohen 179fcf3a6efSOhad Ben-Cohen Say N unless you know you need this. 180fcf3a6efSOhad Ben-Cohen 181c68a2921SDaniel Kurtzconfig ROCKCHIP_IOMMU 182c68a2921SDaniel Kurtz bool "Rockchip IOMMU Support" 18311175886SJoerg Roedel depends on ARM 18411175886SJoerg Roedel depends on ARCH_ROCKCHIP || COMPILE_TEST 185c68a2921SDaniel Kurtz select IOMMU_API 186c68a2921SDaniel Kurtz select ARM_DMA_USE_IOMMU 187c68a2921SDaniel Kurtz help 188c68a2921SDaniel Kurtz Support for IOMMUs found on Rockchip rk32xx SOCs. 189c68a2921SDaniel Kurtz These IOMMUs allow virtualization of the address space used by most 190c68a2921SDaniel Kurtz cores within the multimedia subsystem. 191c68a2921SDaniel Kurtz Say Y here if you are using a Rockchip SoC that includes an IOMMU 192c68a2921SDaniel Kurtz device. 193c68a2921SDaniel Kurtz 194d53e54b4SHiroshi DOYUconfig TEGRA_IOMMU_GART 195d53e54b4SHiroshi DOYU bool "Tegra GART IOMMU Support" 196d53e54b4SHiroshi DOYU depends on ARCH_TEGRA_2x_SOC 197d53e54b4SHiroshi DOYU select IOMMU_API 198d53e54b4SHiroshi DOYU help 199d53e54b4SHiroshi DOYU Enables support for remapping discontiguous physical memory 200d53e54b4SHiroshi DOYU shared with the operating system into contiguous I/O virtual 201d53e54b4SHiroshi DOYU space through the GART (Graphics Address Relocation Table) 202d53e54b4SHiroshi DOYU hardware included on Tegra SoCs. 203d53e54b4SHiroshi DOYU 2047a31f6f4SHiroshi DOYUconfig TEGRA_IOMMU_SMMU 20589184651SThierry Reding bool "NVIDIA Tegra SMMU Support" 20689184651SThierry Reding depends on ARCH_TEGRA 20789184651SThierry Reding depends on TEGRA_AHB 20889184651SThierry Reding depends on TEGRA_MC 2097a31f6f4SHiroshi DOYU select IOMMU_API 2107a31f6f4SHiroshi DOYU help 21189184651SThierry Reding This driver supports the IOMMU hardware (SMMU) found on NVIDIA Tegra 21289184651SThierry Reding SoCs (Tegra30 up to Tegra124). 2137a31f6f4SHiroshi DOYU 2142a96536eSKyongHo Choconfig EXYNOS_IOMMU 2152a96536eSKyongHo Cho bool "Exynos IOMMU Support" 21620911ce6SMark Brown depends on ARCH_EXYNOS && ARM 2172a96536eSKyongHo Cho select IOMMU_API 2184802c1d0STushar Behera select ARM_DMA_USE_IOMMU 2192a96536eSKyongHo Cho help 2202a96536eSKyongHo Cho Support for the IOMMU (System MMU) of Samsung Exynos application 2215455d700SSachin Kamat processor family. This enables H/W multimedia accelerators to see 2225455d700SSachin Kamat non-linear physical memory chunks as linear memory in their 2235455d700SSachin Kamat address space. 2242a96536eSKyongHo Cho 2252a96536eSKyongHo Cho If unsure, say N here. 2262a96536eSKyongHo Cho 2272a96536eSKyongHo Choconfig EXYNOS_IOMMU_DEBUG 2282a96536eSKyongHo Cho bool "Debugging log for Exynos IOMMU" 2292a96536eSKyongHo Cho depends on EXYNOS_IOMMU 2302a96536eSKyongHo Cho help 2312a96536eSKyongHo Cho Select this to see the detailed log message that shows what 2325455d700SSachin Kamat happens in the IOMMU driver. 2332a96536eSKyongHo Cho 2345455d700SSachin Kamat Say N unless you need kernel log message for IOMMU debugging. 2352a96536eSKyongHo Cho 236c2c460f7SHideki EIRAKUconfig SHMOBILE_IPMMU 237c2c460f7SHideki EIRAKU bool 238c2c460f7SHideki EIRAKU 239c2c460f7SHideki EIRAKUconfig SHMOBILE_IPMMU_TLB 240c2c460f7SHideki EIRAKU bool 241c2c460f7SHideki EIRAKU 242c2c460f7SHideki EIRAKUconfig SHMOBILE_IOMMU 243c2c460f7SHideki EIRAKU bool "IOMMU for Renesas IPMMU/IPMMUI" 244c2c460f7SHideki EIRAKU default n 245f63c4824SLinus Torvalds depends on ARM 246b8354439SPaul Bolle depends on ARCH_SHMOBILE || COMPILE_TEST 247c2c460f7SHideki EIRAKU select IOMMU_API 248c2c460f7SHideki EIRAKU select ARM_DMA_USE_IOMMU 249c2c460f7SHideki EIRAKU select SHMOBILE_IPMMU 250c2c460f7SHideki EIRAKU select SHMOBILE_IPMMU_TLB 251c2c460f7SHideki EIRAKU help 252c2c460f7SHideki EIRAKU Support for Renesas IPMMU/IPMMUI. This option enables 253c2c460f7SHideki EIRAKU remapping of DMA memory accesses from all of the IP blocks 254c2c460f7SHideki EIRAKU on the ICB. 255c2c460f7SHideki EIRAKU 256c2c460f7SHideki EIRAKU Warning: Drivers (including userspace drivers of UIO 257c2c460f7SHideki EIRAKU devices) of the IP blocks on the ICB *must* use addresses 258c2c460f7SHideki EIRAKU allocated from the IPMMU (iova) for DMA with this option 259c2c460f7SHideki EIRAKU enabled. 260c2c460f7SHideki EIRAKU 261c2c460f7SHideki EIRAKU If unsure, say N. 262c2c460f7SHideki EIRAKU 263c2c460f7SHideki EIRAKUchoice 264c2c460f7SHideki EIRAKU prompt "IPMMU/IPMMUI address space size" 265c2c460f7SHideki EIRAKU default SHMOBILE_IOMMU_ADDRSIZE_2048MB 266c2c460f7SHideki EIRAKU depends on SHMOBILE_IOMMU 267c2c460f7SHideki EIRAKU help 268c2c460f7SHideki EIRAKU This option sets IPMMU/IPMMUI address space size by 269c2c460f7SHideki EIRAKU adjusting the 1st level page table size. The page table size 270c2c460f7SHideki EIRAKU is calculated as follows: 271c2c460f7SHideki EIRAKU 272c2c460f7SHideki EIRAKU page table size = number of page table entries * 4 bytes 273c2c460f7SHideki EIRAKU number of page table entries = address space size / 1 MiB 274c2c460f7SHideki EIRAKU 275c2c460f7SHideki EIRAKU For example, when the address space size is 2048 MiB, the 276c2c460f7SHideki EIRAKU 1st level page table size is 8192 bytes. 277c2c460f7SHideki EIRAKU 278c2c460f7SHideki EIRAKU config SHMOBILE_IOMMU_ADDRSIZE_2048MB 279c2c460f7SHideki EIRAKU bool "2 GiB" 280c2c460f7SHideki EIRAKU 281c2c460f7SHideki EIRAKU config SHMOBILE_IOMMU_ADDRSIZE_1024MB 282c2c460f7SHideki EIRAKU bool "1 GiB" 283c2c460f7SHideki EIRAKU 284c2c460f7SHideki EIRAKU config SHMOBILE_IOMMU_ADDRSIZE_512MB 285c2c460f7SHideki EIRAKU bool "512 MiB" 286c2c460f7SHideki EIRAKU 287c2c460f7SHideki EIRAKU config SHMOBILE_IOMMU_ADDRSIZE_256MB 288c2c460f7SHideki EIRAKU bool "256 MiB" 289c2c460f7SHideki EIRAKU 290c2c460f7SHideki EIRAKU config SHMOBILE_IOMMU_ADDRSIZE_128MB 291c2c460f7SHideki EIRAKU bool "128 MiB" 292c2c460f7SHideki EIRAKU 293c2c460f7SHideki EIRAKU config SHMOBILE_IOMMU_ADDRSIZE_64MB 294c2c460f7SHideki EIRAKU bool "64 MiB" 295c2c460f7SHideki EIRAKU 296c2c460f7SHideki EIRAKU config SHMOBILE_IOMMU_ADDRSIZE_32MB 297c2c460f7SHideki EIRAKU bool "32 MiB" 298c2c460f7SHideki EIRAKU 299c2c460f7SHideki EIRAKUendchoice 300c2c460f7SHideki EIRAKU 301c2c460f7SHideki EIRAKUconfig SHMOBILE_IOMMU_L1SIZE 302c2c460f7SHideki EIRAKU int 303c2c460f7SHideki EIRAKU default 8192 if SHMOBILE_IOMMU_ADDRSIZE_2048MB 304c2c460f7SHideki EIRAKU default 4096 if SHMOBILE_IOMMU_ADDRSIZE_1024MB 305c2c460f7SHideki EIRAKU default 2048 if SHMOBILE_IOMMU_ADDRSIZE_512MB 306c2c460f7SHideki EIRAKU default 1024 if SHMOBILE_IOMMU_ADDRSIZE_256MB 307c2c460f7SHideki EIRAKU default 512 if SHMOBILE_IOMMU_ADDRSIZE_128MB 308c2c460f7SHideki EIRAKU default 256 if SHMOBILE_IOMMU_ADDRSIZE_64MB 309c2c460f7SHideki EIRAKU default 128 if SHMOBILE_IOMMU_ADDRSIZE_32MB 310c2c460f7SHideki EIRAKU 311d25a2a16SLaurent Pinchartconfig IPMMU_VMSA 312d25a2a16SLaurent Pinchart bool "Renesas VMSA-compatible IPMMU" 313d25a2a16SLaurent Pinchart depends on ARM_LPAE 314d25a2a16SLaurent Pinchart depends on ARCH_SHMOBILE || COMPILE_TEST 315d25a2a16SLaurent Pinchart select IOMMU_API 316*f20ed39fSLaurent Pinchart select IOMMU_IO_PGTABLE_LPAE 317d25a2a16SLaurent Pinchart select ARM_DMA_USE_IOMMU 318d25a2a16SLaurent Pinchart help 319d25a2a16SLaurent Pinchart Support for the Renesas VMSA-compatible IPMMU Renesas found in the 320d25a2a16SLaurent Pinchart R-Mobile APE6 and R-Car H2/M2 SoCs. 321d25a2a16SLaurent Pinchart 322d25a2a16SLaurent Pinchart If unsure, say N. 323d25a2a16SLaurent Pinchart 3244e13c1acSAlexey Kardashevskiyconfig SPAPR_TCE_IOMMU 3254e13c1acSAlexey Kardashevskiy bool "sPAPR TCE IOMMU Support" 3265b25199eSAlexey Kardashevskiy depends on PPC_POWERNV || PPC_PSERIES 3274e13c1acSAlexey Kardashevskiy select IOMMU_API 3284e13c1acSAlexey Kardashevskiy help 3294e13c1acSAlexey Kardashevskiy Enables bits of IOMMU API required by VFIO. The iommu_ops 3304e13c1acSAlexey Kardashevskiy is not implemented as it is not necessary for VFIO. 3314e13c1acSAlexey Kardashevskiy 33245ae7cffSWill Deaconconfig ARM_SMMU 33345ae7cffSWill Deacon bool "ARM Ltd. System MMU (SMMU) Support" 334518f7136SWill Deacon depends on ARM64 || ARM 33545ae7cffSWill Deacon select IOMMU_API 336518f7136SWill Deacon select IOMMU_IO_PGTABLE_LPAE 33745ae7cffSWill Deacon select ARM_DMA_USE_IOMMU if ARM 33845ae7cffSWill Deacon help 33945ae7cffSWill Deacon Support for implementations of the ARM System MMU architecture 340518f7136SWill Deacon versions 1 and 2. 34145ae7cffSWill Deacon 34245ae7cffSWill Deacon Say Y here if your SoC includes an IOMMU device implementing 34345ae7cffSWill Deacon the ARM SMMU architecture. 34445ae7cffSWill Deacon 34568255b62SJoerg Roedelendif # IOMMU_SUPPORT 346