1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2023, Linaro Limited 5 * 6 */ 7 8 #include <linux/device.h> 9 #include <linux/interconnect.h> 10 #include <linux/interconnect-provider.h> 11 #include <linux/module.h> 12 #include <linux/of_platform.h> 13 #include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h> 14 15 #include "bcm-voter.h" 16 #include "icc-common.h" 17 #include "icc-rpmh.h" 18 #include "x1e80100.h" 19 20 static struct qcom_icc_node qhm_qspi = { 21 .name = "qhm_qspi", 22 .id = X1E80100_MASTER_QSPI_0, 23 .channels = 1, 24 .buswidth = 4, 25 .num_links = 1, 26 .links = { X1E80100_SLAVE_A1NOC_SNOC }, 27 }; 28 29 static struct qcom_icc_node qhm_qup1 = { 30 .name = "qhm_qup1", 31 .id = X1E80100_MASTER_QUP_1, 32 .channels = 1, 33 .buswidth = 4, 34 .num_links = 1, 35 .links = { X1E80100_SLAVE_A1NOC_SNOC }, 36 }; 37 38 static struct qcom_icc_node xm_sdc4 = { 39 .name = "xm_sdc4", 40 .id = X1E80100_MASTER_SDCC_4, 41 .channels = 1, 42 .buswidth = 8, 43 .num_links = 1, 44 .links = { X1E80100_SLAVE_A1NOC_SNOC }, 45 }; 46 47 static struct qcom_icc_node xm_ufs_mem = { 48 .name = "xm_ufs_mem", 49 .id = X1E80100_MASTER_UFS_MEM, 50 .channels = 1, 51 .buswidth = 16, 52 .num_links = 1, 53 .links = { X1E80100_SLAVE_A1NOC_SNOC }, 54 }; 55 56 static struct qcom_icc_node qhm_qup0 = { 57 .name = "qhm_qup0", 58 .id = X1E80100_MASTER_QUP_0, 59 .channels = 1, 60 .buswidth = 4, 61 .num_links = 1, 62 .links = { X1E80100_SLAVE_A2NOC_SNOC }, 63 }; 64 65 static struct qcom_icc_node qhm_qup2 = { 66 .name = "qhm_qup2", 67 .id = X1E80100_MASTER_QUP_2, 68 .channels = 1, 69 .buswidth = 4, 70 .num_links = 1, 71 .links = { X1E80100_SLAVE_A2NOC_SNOC }, 72 }; 73 74 static struct qcom_icc_node qxm_crypto = { 75 .name = "qxm_crypto", 76 .id = X1E80100_MASTER_CRYPTO, 77 .channels = 1, 78 .buswidth = 8, 79 .num_links = 1, 80 .links = { X1E80100_SLAVE_A2NOC_SNOC }, 81 }; 82 83 static struct qcom_icc_node qxm_sp = { 84 .name = "qxm_sp", 85 .id = X1E80100_MASTER_SP, 86 .channels = 1, 87 .buswidth = 8, 88 .num_links = 1, 89 .links = { X1E80100_SLAVE_A2NOC_SNOC }, 90 }; 91 92 static struct qcom_icc_node xm_qdss_etr_0 = { 93 .name = "xm_qdss_etr_0", 94 .id = X1E80100_MASTER_QDSS_ETR, 95 .channels = 1, 96 .buswidth = 8, 97 .num_links = 1, 98 .links = { X1E80100_SLAVE_A2NOC_SNOC }, 99 }; 100 101 static struct qcom_icc_node xm_qdss_etr_1 = { 102 .name = "xm_qdss_etr_1", 103 .id = X1E80100_MASTER_QDSS_ETR_1, 104 .channels = 1, 105 .buswidth = 8, 106 .num_links = 1, 107 .links = { X1E80100_SLAVE_A2NOC_SNOC }, 108 }; 109 110 static struct qcom_icc_node xm_sdc2 = { 111 .name = "xm_sdc2", 112 .id = X1E80100_MASTER_SDCC_2, 113 .channels = 1, 114 .buswidth = 8, 115 .num_links = 1, 116 .links = { X1E80100_SLAVE_A2NOC_SNOC }, 117 }; 118 119 static struct qcom_icc_node ddr_perf_mode_master = { 120 .name = "ddr_perf_mode_master", 121 .id = X1E80100_MASTER_DDR_PERF_MODE, 122 .channels = 1, 123 .buswidth = 4, 124 .num_links = 1, 125 .links = { X1E80100_SLAVE_DDR_PERF_MODE }, 126 }; 127 128 static struct qcom_icc_node qup0_core_master = { 129 .name = "qup0_core_master", 130 .id = X1E80100_MASTER_QUP_CORE_0, 131 .channels = 1, 132 .buswidth = 4, 133 .num_links = 1, 134 .links = { X1E80100_SLAVE_QUP_CORE_0 }, 135 }; 136 137 static struct qcom_icc_node qup1_core_master = { 138 .name = "qup1_core_master", 139 .id = X1E80100_MASTER_QUP_CORE_1, 140 .channels = 1, 141 .buswidth = 4, 142 .num_links = 1, 143 .links = { X1E80100_SLAVE_QUP_CORE_1 }, 144 }; 145 146 static struct qcom_icc_node qup2_core_master = { 147 .name = "qup2_core_master", 148 .id = X1E80100_MASTER_QUP_CORE_2, 149 .channels = 1, 150 .buswidth = 4, 151 .num_links = 1, 152 .links = { X1E80100_SLAVE_QUP_CORE_2 }, 153 }; 154 155 static struct qcom_icc_node qsm_cfg = { 156 .name = "qsm_cfg", 157 .id = X1E80100_MASTER_CNOC_CFG, 158 .channels = 1, 159 .buswidth = 4, 160 .num_links = 47, 161 .links = { X1E80100_SLAVE_AHB2PHY_SOUTH, X1E80100_SLAVE_AHB2PHY_NORTH, 162 X1E80100_SLAVE_AHB2PHY_2, X1E80100_SLAVE_AV1_ENC_CFG, 163 X1E80100_SLAVE_CAMERA_CFG, X1E80100_SLAVE_CLK_CTL, 164 X1E80100_SLAVE_CRYPTO_0_CFG, X1E80100_SLAVE_DISPLAY_CFG, 165 X1E80100_SLAVE_GFX3D_CFG, X1E80100_SLAVE_IMEM_CFG, 166 X1E80100_SLAVE_IPC_ROUTER_CFG, X1E80100_SLAVE_PCIE_0_CFG, 167 X1E80100_SLAVE_PCIE_1_CFG, X1E80100_SLAVE_PCIE_2_CFG, 168 X1E80100_SLAVE_PCIE_3_CFG, X1E80100_SLAVE_PCIE_4_CFG, 169 X1E80100_SLAVE_PCIE_5_CFG, X1E80100_SLAVE_PCIE_6A_CFG, 170 X1E80100_SLAVE_PCIE_6B_CFG, X1E80100_SLAVE_PCIE_RSC_CFG, 171 X1E80100_SLAVE_PDM, X1E80100_SLAVE_PRNG, 172 X1E80100_SLAVE_QDSS_CFG, X1E80100_SLAVE_QSPI_0, 173 X1E80100_SLAVE_QUP_0, X1E80100_SLAVE_QUP_1, 174 X1E80100_SLAVE_QUP_2, X1E80100_SLAVE_SDCC_2, 175 X1E80100_SLAVE_SDCC_4, X1E80100_SLAVE_SMMUV3_CFG, 176 X1E80100_SLAVE_TCSR, X1E80100_SLAVE_TLMM, 177 X1E80100_SLAVE_UFS_MEM_CFG, X1E80100_SLAVE_USB2, 178 X1E80100_SLAVE_USB3_0, X1E80100_SLAVE_USB3_1, 179 X1E80100_SLAVE_USB3_2, X1E80100_SLAVE_USB3_MP, 180 X1E80100_SLAVE_USB4_0, X1E80100_SLAVE_USB4_1, 181 X1E80100_SLAVE_USB4_2, X1E80100_SLAVE_VENUS_CFG, 182 X1E80100_SLAVE_LPASS_QTB_CFG, X1E80100_SLAVE_CNOC_MNOC_CFG, 183 X1E80100_SLAVE_NSP_QTB_CFG, X1E80100_SLAVE_QDSS_STM, 184 X1E80100_SLAVE_TCU }, 185 }; 186 187 static struct qcom_icc_node qnm_gemnoc_cnoc = { 188 .name = "qnm_gemnoc_cnoc", 189 .id = X1E80100_MASTER_GEM_NOC_CNOC, 190 .channels = 1, 191 .buswidth = 16, 192 .num_links = 6, 193 .links = { X1E80100_SLAVE_AOSS, X1E80100_SLAVE_TME_CFG, 194 X1E80100_SLAVE_APPSS, X1E80100_SLAVE_CNOC_CFG, 195 X1E80100_SLAVE_BOOT_IMEM, X1E80100_SLAVE_IMEM }, 196 }; 197 198 static struct qcom_icc_node qnm_gemnoc_pcie = { 199 .name = "qnm_gemnoc_pcie", 200 .id = X1E80100_MASTER_GEM_NOC_PCIE_SNOC, 201 .channels = 1, 202 .buswidth = 32, 203 .num_links = 8, 204 .links = { X1E80100_SLAVE_PCIE_0, X1E80100_SLAVE_PCIE_1, 205 X1E80100_SLAVE_PCIE_2, X1E80100_SLAVE_PCIE_3, 206 X1E80100_SLAVE_PCIE_4, X1E80100_SLAVE_PCIE_5, 207 X1E80100_SLAVE_PCIE_6A, X1E80100_SLAVE_PCIE_6B }, 208 }; 209 210 static struct qcom_icc_node alm_gpu_tcu = { 211 .name = "alm_gpu_tcu", 212 .id = X1E80100_MASTER_GPU_TCU, 213 .channels = 1, 214 .buswidth = 8, 215 .num_links = 2, 216 .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC }, 217 }; 218 219 static struct qcom_icc_node alm_pcie_tcu = { 220 .name = "alm_pcie_tcu", 221 .id = X1E80100_MASTER_PCIE_TCU, 222 .channels = 1, 223 .buswidth = 8, 224 .num_links = 2, 225 .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC }, 226 }; 227 228 static struct qcom_icc_node alm_sys_tcu = { 229 .name = "alm_sys_tcu", 230 .id = X1E80100_MASTER_SYS_TCU, 231 .channels = 1, 232 .buswidth = 8, 233 .num_links = 2, 234 .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC }, 235 }; 236 237 static struct qcom_icc_node chm_apps = { 238 .name = "chm_apps", 239 .id = X1E80100_MASTER_APPSS_PROC, 240 .channels = 6, 241 .buswidth = 32, 242 .num_links = 3, 243 .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC, 244 X1E80100_SLAVE_MEM_NOC_PCIE_SNOC }, 245 }; 246 247 static struct qcom_icc_node qnm_gpu = { 248 .name = "qnm_gpu", 249 .id = X1E80100_MASTER_GFX3D, 250 .channels = 4, 251 .buswidth = 32, 252 .num_links = 2, 253 .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC }, 254 }; 255 256 static struct qcom_icc_node qnm_lpass = { 257 .name = "qnm_lpass", 258 .id = X1E80100_MASTER_LPASS_GEM_NOC, 259 .channels = 1, 260 .buswidth = 16, 261 .num_links = 3, 262 .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC, 263 X1E80100_SLAVE_MEM_NOC_PCIE_SNOC }, 264 }; 265 266 static struct qcom_icc_node qnm_mnoc_hf = { 267 .name = "qnm_mnoc_hf", 268 .id = X1E80100_MASTER_MNOC_HF_MEM_NOC, 269 .channels = 2, 270 .buswidth = 32, 271 .num_links = 2, 272 .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC }, 273 }; 274 275 static struct qcom_icc_node qnm_mnoc_sf = { 276 .name = "qnm_mnoc_sf", 277 .id = X1E80100_MASTER_MNOC_SF_MEM_NOC, 278 .channels = 2, 279 .buswidth = 32, 280 .num_links = 2, 281 .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC }, 282 }; 283 284 static struct qcom_icc_node qnm_nsp_noc = { 285 .name = "qnm_nsp_noc", 286 .id = X1E80100_MASTER_COMPUTE_NOC, 287 .channels = 2, 288 .buswidth = 32, 289 .num_links = 3, 290 .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC, 291 X1E80100_SLAVE_MEM_NOC_PCIE_SNOC }, 292 }; 293 294 static struct qcom_icc_node qnm_pcie = { 295 .name = "qnm_pcie", 296 .id = X1E80100_MASTER_ANOC_PCIE_GEM_NOC, 297 .channels = 1, 298 .buswidth = 64, 299 .num_links = 2, 300 .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC }, 301 }; 302 303 static struct qcom_icc_node qnm_snoc_sf = { 304 .name = "qnm_snoc_sf", 305 .id = X1E80100_MASTER_SNOC_SF_MEM_NOC, 306 .channels = 1, 307 .buswidth = 64, 308 .num_links = 3, 309 .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC, 310 X1E80100_SLAVE_MEM_NOC_PCIE_SNOC }, 311 }; 312 313 static struct qcom_icc_node xm_gic = { 314 .name = "xm_gic", 315 .id = X1E80100_MASTER_GIC2, 316 .channels = 1, 317 .buswidth = 8, 318 .num_links = 1, 319 .links = { X1E80100_SLAVE_LLCC }, 320 }; 321 322 static struct qcom_icc_node qnm_lpiaon_noc = { 323 .name = "qnm_lpiaon_noc", 324 .id = X1E80100_MASTER_LPIAON_NOC, 325 .channels = 1, 326 .buswidth = 16, 327 .num_links = 1, 328 .links = { X1E80100_SLAVE_LPASS_GEM_NOC }, 329 }; 330 331 static struct qcom_icc_node qnm_lpass_lpinoc = { 332 .name = "qnm_lpass_lpinoc", 333 .id = X1E80100_MASTER_LPASS_LPINOC, 334 .channels = 1, 335 .buswidth = 16, 336 .num_links = 1, 337 .links = { X1E80100_SLAVE_LPIAON_NOC_LPASS_AG_NOC }, 338 }; 339 340 static struct qcom_icc_node qxm_lpinoc_dsp_axim = { 341 .name = "qxm_lpinoc_dsp_axim", 342 .id = X1E80100_MASTER_LPASS_PROC, 343 .channels = 1, 344 .buswidth = 16, 345 .num_links = 1, 346 .links = { X1E80100_SLAVE_LPICX_NOC_LPIAON_NOC }, 347 }; 348 349 static struct qcom_icc_node llcc_mc = { 350 .name = "llcc_mc", 351 .id = X1E80100_MASTER_LLCC, 352 .channels = 8, 353 .buswidth = 4, 354 .num_links = 1, 355 .links = { X1E80100_SLAVE_EBI1 }, 356 }; 357 358 static struct qcom_icc_node qnm_av1_enc = { 359 .name = "qnm_av1_enc", 360 .id = X1E80100_MASTER_AV1_ENC, 361 .channels = 1, 362 .buswidth = 32, 363 .num_links = 1, 364 .links = { X1E80100_SLAVE_MNOC_SF_MEM_NOC }, 365 }; 366 367 static struct qcom_icc_node qnm_camnoc_hf = { 368 .name = "qnm_camnoc_hf", 369 .id = X1E80100_MASTER_CAMNOC_HF, 370 .channels = 2, 371 .buswidth = 32, 372 .num_links = 1, 373 .links = { X1E80100_SLAVE_MNOC_HF_MEM_NOC }, 374 }; 375 376 static struct qcom_icc_node qnm_camnoc_icp = { 377 .name = "qnm_camnoc_icp", 378 .id = X1E80100_MASTER_CAMNOC_ICP, 379 .channels = 1, 380 .buswidth = 8, 381 .num_links = 1, 382 .links = { X1E80100_SLAVE_MNOC_SF_MEM_NOC }, 383 }; 384 385 static struct qcom_icc_node qnm_camnoc_sf = { 386 .name = "qnm_camnoc_sf", 387 .id = X1E80100_MASTER_CAMNOC_SF, 388 .channels = 2, 389 .buswidth = 32, 390 .num_links = 1, 391 .links = { X1E80100_SLAVE_MNOC_SF_MEM_NOC }, 392 }; 393 394 static struct qcom_icc_node qnm_eva = { 395 .name = "qnm_eva", 396 .id = X1E80100_MASTER_EVA, 397 .channels = 1, 398 .buswidth = 32, 399 .num_links = 1, 400 .links = { X1E80100_SLAVE_MNOC_SF_MEM_NOC }, 401 }; 402 403 static struct qcom_icc_node qnm_mdp = { 404 .name = "qnm_mdp", 405 .id = X1E80100_MASTER_MDP, 406 .channels = 2, 407 .buswidth = 32, 408 .num_links = 1, 409 .links = { X1E80100_SLAVE_MNOC_HF_MEM_NOC }, 410 }; 411 412 static struct qcom_icc_node qnm_video = { 413 .name = "qnm_video", 414 .id = X1E80100_MASTER_VIDEO, 415 .channels = 2, 416 .buswidth = 32, 417 .num_links = 1, 418 .links = { X1E80100_SLAVE_MNOC_SF_MEM_NOC }, 419 }; 420 421 static struct qcom_icc_node qnm_video_cv_cpu = { 422 .name = "qnm_video_cv_cpu", 423 .id = X1E80100_MASTER_VIDEO_CV_PROC, 424 .channels = 1, 425 .buswidth = 8, 426 .num_links = 1, 427 .links = { X1E80100_SLAVE_MNOC_SF_MEM_NOC }, 428 }; 429 430 static struct qcom_icc_node qnm_video_v_cpu = { 431 .name = "qnm_video_v_cpu", 432 .id = X1E80100_MASTER_VIDEO_V_PROC, 433 .channels = 1, 434 .buswidth = 8, 435 .num_links = 1, 436 .links = { X1E80100_SLAVE_MNOC_SF_MEM_NOC }, 437 }; 438 439 static struct qcom_icc_node qsm_mnoc_cfg = { 440 .name = "qsm_mnoc_cfg", 441 .id = X1E80100_MASTER_CNOC_MNOC_CFG, 442 .channels = 1, 443 .buswidth = 4, 444 .num_links = 1, 445 .links = { X1E80100_SLAVE_SERVICE_MNOC }, 446 }; 447 448 static struct qcom_icc_node qxm_nsp = { 449 .name = "qxm_nsp", 450 .id = X1E80100_MASTER_CDSP_PROC, 451 .channels = 2, 452 .buswidth = 32, 453 .num_links = 1, 454 .links = { X1E80100_SLAVE_CDSP_MEM_NOC }, 455 }; 456 457 static struct qcom_icc_node qnm_pcie_north_gem_noc = { 458 .name = "qnm_pcie_north_gem_noc", 459 .id = X1E80100_MASTER_PCIE_NORTH, 460 .channels = 1, 461 .buswidth = 64, 462 .num_links = 1, 463 .links = { X1E80100_SLAVE_ANOC_PCIE_GEM_NOC }, 464 }; 465 466 static struct qcom_icc_node qnm_pcie_south_gem_noc = { 467 .name = "qnm_pcie_south_gem_noc", 468 .id = X1E80100_MASTER_PCIE_SOUTH, 469 .channels = 1, 470 .buswidth = 64, 471 .num_links = 1, 472 .links = { X1E80100_SLAVE_ANOC_PCIE_GEM_NOC }, 473 }; 474 475 static struct qcom_icc_node xm_pcie_3 = { 476 .name = "xm_pcie_3", 477 .id = X1E80100_MASTER_PCIE_3, 478 .channels = 1, 479 .buswidth = 64, 480 .num_links = 1, 481 .links = { X1E80100_SLAVE_PCIE_NORTH }, 482 }; 483 484 static struct qcom_icc_node xm_pcie_4 = { 485 .name = "xm_pcie_4", 486 .id = X1E80100_MASTER_PCIE_4, 487 .channels = 1, 488 .buswidth = 8, 489 .num_links = 1, 490 .links = { X1E80100_SLAVE_PCIE_NORTH }, 491 }; 492 493 static struct qcom_icc_node xm_pcie_5 = { 494 .name = "xm_pcie_5", 495 .id = X1E80100_MASTER_PCIE_5, 496 .channels = 1, 497 .buswidth = 8, 498 .num_links = 1, 499 .links = { X1E80100_SLAVE_PCIE_NORTH }, 500 }; 501 502 static struct qcom_icc_node xm_pcie_0 = { 503 .name = "xm_pcie_0", 504 .id = X1E80100_MASTER_PCIE_0, 505 .channels = 1, 506 .buswidth = 16, 507 .num_links = 1, 508 .links = { X1E80100_SLAVE_PCIE_SOUTH }, 509 }; 510 511 static struct qcom_icc_node xm_pcie_1 = { 512 .name = "xm_pcie_1", 513 .id = X1E80100_MASTER_PCIE_1, 514 .channels = 1, 515 .buswidth = 16, 516 .num_links = 1, 517 .links = { X1E80100_SLAVE_PCIE_SOUTH }, 518 }; 519 520 static struct qcom_icc_node xm_pcie_2 = { 521 .name = "xm_pcie_2", 522 .id = X1E80100_MASTER_PCIE_2, 523 .channels = 1, 524 .buswidth = 16, 525 .num_links = 1, 526 .links = { X1E80100_SLAVE_PCIE_SOUTH }, 527 }; 528 529 static struct qcom_icc_node xm_pcie_6a = { 530 .name = "xm_pcie_6a", 531 .id = X1E80100_MASTER_PCIE_6A, 532 .channels = 1, 533 .buswidth = 32, 534 .num_links = 1, 535 .links = { X1E80100_SLAVE_PCIE_SOUTH }, 536 }; 537 538 static struct qcom_icc_node xm_pcie_6b = { 539 .name = "xm_pcie_6b", 540 .id = X1E80100_MASTER_PCIE_6B, 541 .channels = 1, 542 .buswidth = 16, 543 .num_links = 1, 544 .links = { X1E80100_SLAVE_PCIE_SOUTH }, 545 }; 546 547 static struct qcom_icc_node qnm_aggre1_noc = { 548 .name = "qnm_aggre1_noc", 549 .id = X1E80100_MASTER_A1NOC_SNOC, 550 .channels = 1, 551 .buswidth = 16, 552 .num_links = 1, 553 .links = { X1E80100_SLAVE_SNOC_GEM_NOC_SF }, 554 }; 555 556 static struct qcom_icc_node qnm_aggre2_noc = { 557 .name = "qnm_aggre2_noc", 558 .id = X1E80100_MASTER_A2NOC_SNOC, 559 .channels = 1, 560 .buswidth = 16, 561 .num_links = 1, 562 .links = { X1E80100_SLAVE_SNOC_GEM_NOC_SF }, 563 }; 564 565 static struct qcom_icc_node qnm_gic = { 566 .name = "qnm_gic", 567 .id = X1E80100_MASTER_GIC1, 568 .channels = 1, 569 .buswidth = 8, 570 .num_links = 1, 571 .links = { X1E80100_SLAVE_SNOC_GEM_NOC_SF }, 572 }; 573 574 static struct qcom_icc_node qnm_usb_anoc = { 575 .name = "qnm_usb_anoc", 576 .id = X1E80100_MASTER_USB_NOC_SNOC, 577 .channels = 1, 578 .buswidth = 64, 579 .num_links = 1, 580 .links = { X1E80100_SLAVE_SNOC_GEM_NOC_SF }, 581 }; 582 583 static struct qcom_icc_node qnm_aggre_usb_north_snoc = { 584 .name = "qnm_aggre_usb_north_snoc", 585 .id = X1E80100_MASTER_AGGRE_USB_NORTH, 586 .channels = 1, 587 .buswidth = 64, 588 .num_links = 1, 589 .links = { X1E80100_SLAVE_USB_NOC_SNOC }, 590 }; 591 592 static struct qcom_icc_node qnm_aggre_usb_south_snoc = { 593 .name = "qnm_aggre_usb_south_snoc", 594 .id = X1E80100_MASTER_AGGRE_USB_SOUTH, 595 .channels = 1, 596 .buswidth = 64, 597 .num_links = 1, 598 .links = { X1E80100_SLAVE_USB_NOC_SNOC }, 599 }; 600 601 static struct qcom_icc_node xm_usb2_0 = { 602 .name = "xm_usb2_0", 603 .id = X1E80100_MASTER_USB2, 604 .channels = 1, 605 .buswidth = 8, 606 .num_links = 1, 607 .links = { X1E80100_SLAVE_AGGRE_USB_NORTH }, 608 }; 609 610 static struct qcom_icc_node xm_usb3_mp = { 611 .name = "xm_usb3_mp", 612 .id = X1E80100_MASTER_USB3_MP, 613 .channels = 1, 614 .buswidth = 16, 615 .num_links = 1, 616 .links = { X1E80100_SLAVE_AGGRE_USB_NORTH }, 617 }; 618 619 static struct qcom_icc_node xm_usb3_0 = { 620 .name = "xm_usb3_0", 621 .id = X1E80100_MASTER_USB3_0, 622 .channels = 1, 623 .buswidth = 8, 624 .num_links = 1, 625 .links = { X1E80100_SLAVE_AGGRE_USB_SOUTH }, 626 }; 627 628 static struct qcom_icc_node xm_usb3_1 = { 629 .name = "xm_usb3_1", 630 .id = X1E80100_MASTER_USB3_1, 631 .channels = 1, 632 .buswidth = 8, 633 .num_links = 1, 634 .links = { X1E80100_SLAVE_AGGRE_USB_SOUTH }, 635 }; 636 637 static struct qcom_icc_node xm_usb3_2 = { 638 .name = "xm_usb3_2", 639 .id = X1E80100_MASTER_USB3_2, 640 .channels = 1, 641 .buswidth = 8, 642 .num_links = 1, 643 .links = { X1E80100_SLAVE_AGGRE_USB_SOUTH }, 644 }; 645 646 static struct qcom_icc_node xm_usb4_0 = { 647 .name = "xm_usb4_0", 648 .id = X1E80100_MASTER_USB4_0, 649 .channels = 1, 650 .buswidth = 16, 651 .num_links = 1, 652 .links = { X1E80100_SLAVE_AGGRE_USB_SOUTH }, 653 }; 654 655 static struct qcom_icc_node xm_usb4_1 = { 656 .name = "xm_usb4_1", 657 .id = X1E80100_MASTER_USB4_1, 658 .channels = 1, 659 .buswidth = 16, 660 .num_links = 1, 661 .links = { X1E80100_SLAVE_AGGRE_USB_SOUTH }, 662 }; 663 664 static struct qcom_icc_node xm_usb4_2 = { 665 .name = "xm_usb4_2", 666 .id = X1E80100_MASTER_USB4_2, 667 .channels = 1, 668 .buswidth = 16, 669 .num_links = 1, 670 .links = { X1E80100_SLAVE_AGGRE_USB_SOUTH }, 671 }; 672 673 static struct qcom_icc_node qnm_mnoc_hf_disp = { 674 .name = "qnm_mnoc_hf_disp", 675 .id = X1E80100_MASTER_MNOC_HF_MEM_NOC_DISP, 676 .channels = 2, 677 .buswidth = 32, 678 .num_links = 1, 679 .links = { X1E80100_SLAVE_LLCC_DISP }, 680 }; 681 682 static struct qcom_icc_node qnm_pcie_disp = { 683 .name = "qnm_pcie_disp", 684 .id = X1E80100_MASTER_ANOC_PCIE_GEM_NOC_DISP, 685 .channels = 1, 686 .buswidth = 64, 687 .num_links = 1, 688 .links = { X1E80100_SLAVE_LLCC_DISP }, 689 }; 690 691 static struct qcom_icc_node llcc_mc_disp = { 692 .name = "llcc_mc_disp", 693 .id = X1E80100_MASTER_LLCC_DISP, 694 .channels = 8, 695 .buswidth = 4, 696 .num_links = 1, 697 .links = { X1E80100_SLAVE_EBI1_DISP }, 698 }; 699 700 static struct qcom_icc_node qnm_mdp_disp = { 701 .name = "qnm_mdp_disp", 702 .id = X1E80100_MASTER_MDP_DISP, 703 .channels = 2, 704 .buswidth = 32, 705 .num_links = 1, 706 .links = { X1E80100_SLAVE_MNOC_HF_MEM_NOC_DISP }, 707 }; 708 709 static struct qcom_icc_node qnm_pcie_pcie = { 710 .name = "qnm_pcie_pcie", 711 .id = X1E80100_MASTER_ANOC_PCIE_GEM_NOC_PCIE, 712 .channels = 1, 713 .buswidth = 64, 714 .num_links = 1, 715 .links = { X1E80100_SLAVE_LLCC_PCIE }, 716 }; 717 718 static struct qcom_icc_node llcc_mc_pcie = { 719 .name = "llcc_mc_pcie", 720 .id = X1E80100_MASTER_LLCC_PCIE, 721 .channels = 8, 722 .buswidth = 4, 723 .num_links = 1, 724 .links = { X1E80100_SLAVE_EBI1_PCIE }, 725 }; 726 727 static struct qcom_icc_node qnm_pcie_north_gem_noc_pcie = { 728 .name = "qnm_pcie_north_gem_noc_pcie", 729 .id = X1E80100_MASTER_PCIE_NORTH_PCIE, 730 .channels = 1, 731 .buswidth = 64, 732 .num_links = 1, 733 .links = { X1E80100_SLAVE_ANOC_PCIE_GEM_NOC_PCIE }, 734 }; 735 736 static struct qcom_icc_node qnm_pcie_south_gem_noc_pcie = { 737 .name = "qnm_pcie_south_gem_noc_pcie", 738 .id = X1E80100_MASTER_PCIE_SOUTH_PCIE, 739 .channels = 1, 740 .buswidth = 64, 741 .num_links = 1, 742 .links = { X1E80100_SLAVE_ANOC_PCIE_GEM_NOC_PCIE }, 743 }; 744 745 static struct qcom_icc_node xm_pcie_3_pcie = { 746 .name = "xm_pcie_3_pcie", 747 .id = X1E80100_MASTER_PCIE_3_PCIE, 748 .channels = 1, 749 .buswidth = 64, 750 .num_links = 1, 751 .links = { X1E80100_SLAVE_PCIE_NORTH_PCIE }, 752 }; 753 754 static struct qcom_icc_node xm_pcie_4_pcie = { 755 .name = "xm_pcie_4_pcie", 756 .id = X1E80100_MASTER_PCIE_4_PCIE, 757 .channels = 1, 758 .buswidth = 8, 759 .num_links = 1, 760 .links = { X1E80100_SLAVE_PCIE_NORTH_PCIE }, 761 }; 762 763 static struct qcom_icc_node xm_pcie_5_pcie = { 764 .name = "xm_pcie_5_pcie", 765 .id = X1E80100_MASTER_PCIE_5_PCIE, 766 .channels = 1, 767 .buswidth = 8, 768 .num_links = 1, 769 .links = { X1E80100_SLAVE_PCIE_NORTH_PCIE }, 770 }; 771 772 static struct qcom_icc_node xm_pcie_0_pcie = { 773 .name = "xm_pcie_0_pcie", 774 .id = X1E80100_MASTER_PCIE_0_PCIE, 775 .channels = 1, 776 .buswidth = 16, 777 .num_links = 1, 778 .links = { X1E80100_SLAVE_PCIE_SOUTH_PCIE }, 779 }; 780 781 static struct qcom_icc_node xm_pcie_1_pcie = { 782 .name = "xm_pcie_1_pcie", 783 .id = X1E80100_MASTER_PCIE_1_PCIE, 784 .channels = 1, 785 .buswidth = 16, 786 .num_links = 1, 787 .links = { X1E80100_SLAVE_PCIE_SOUTH_PCIE }, 788 }; 789 790 static struct qcom_icc_node xm_pcie_2_pcie = { 791 .name = "xm_pcie_2_pcie", 792 .id = X1E80100_MASTER_PCIE_2_PCIE, 793 .channels = 1, 794 .buswidth = 16, 795 .num_links = 1, 796 .links = { X1E80100_SLAVE_PCIE_SOUTH_PCIE }, 797 }; 798 799 static struct qcom_icc_node xm_pcie_6a_pcie = { 800 .name = "xm_pcie_6a_pcie", 801 .id = X1E80100_MASTER_PCIE_6A_PCIE, 802 .channels = 1, 803 .buswidth = 32, 804 .num_links = 1, 805 .links = { X1E80100_SLAVE_PCIE_SOUTH_PCIE }, 806 }; 807 808 static struct qcom_icc_node xm_pcie_6b_pcie = { 809 .name = "xm_pcie_6b_pcie", 810 .id = X1E80100_MASTER_PCIE_6B_PCIE, 811 .channels = 1, 812 .buswidth = 16, 813 .num_links = 1, 814 .links = { X1E80100_SLAVE_PCIE_SOUTH_PCIE }, 815 }; 816 817 static struct qcom_icc_node qns_a1noc_snoc = { 818 .name = "qns_a1noc_snoc", 819 .id = X1E80100_SLAVE_A1NOC_SNOC, 820 .channels = 1, 821 .buswidth = 16, 822 .num_links = 1, 823 .links = { X1E80100_MASTER_A1NOC_SNOC }, 824 }; 825 826 static struct qcom_icc_node qns_a2noc_snoc = { 827 .name = "qns_a2noc_snoc", 828 .id = X1E80100_SLAVE_A2NOC_SNOC, 829 .channels = 1, 830 .buswidth = 16, 831 .num_links = 1, 832 .links = { X1E80100_MASTER_A2NOC_SNOC }, 833 }; 834 835 static struct qcom_icc_node ddr_perf_mode_slave = { 836 .name = "ddr_perf_mode_slave", 837 .id = X1E80100_SLAVE_DDR_PERF_MODE, 838 .channels = 1, 839 .buswidth = 4, 840 .num_links = 0, 841 }; 842 843 static struct qcom_icc_node qup0_core_slave = { 844 .name = "qup0_core_slave", 845 .id = X1E80100_SLAVE_QUP_CORE_0, 846 .channels = 1, 847 .buswidth = 4, 848 .num_links = 0, 849 }; 850 851 static struct qcom_icc_node qup1_core_slave = { 852 .name = "qup1_core_slave", 853 .id = X1E80100_SLAVE_QUP_CORE_1, 854 .channels = 1, 855 .buswidth = 4, 856 .num_links = 0, 857 }; 858 859 static struct qcom_icc_node qup2_core_slave = { 860 .name = "qup2_core_slave", 861 .id = X1E80100_SLAVE_QUP_CORE_2, 862 .channels = 1, 863 .buswidth = 4, 864 .num_links = 0, 865 }; 866 867 static struct qcom_icc_node qhs_ahb2phy0 = { 868 .name = "qhs_ahb2phy0", 869 .id = X1E80100_SLAVE_AHB2PHY_SOUTH, 870 .channels = 1, 871 .buswidth = 4, 872 .num_links = 0, 873 }; 874 875 static struct qcom_icc_node qhs_ahb2phy1 = { 876 .name = "qhs_ahb2phy1", 877 .id = X1E80100_SLAVE_AHB2PHY_NORTH, 878 .channels = 1, 879 .buswidth = 4, 880 .num_links = 0, 881 }; 882 883 static struct qcom_icc_node qhs_ahb2phy2 = { 884 .name = "qhs_ahb2phy2", 885 .id = X1E80100_SLAVE_AHB2PHY_2, 886 .channels = 1, 887 .buswidth = 4, 888 .num_links = 0, 889 }; 890 891 static struct qcom_icc_node qhs_av1_enc_cfg = { 892 .name = "qhs_av1_enc_cfg", 893 .id = X1E80100_SLAVE_AV1_ENC_CFG, 894 .channels = 1, 895 .buswidth = 4, 896 .num_links = 0, 897 }; 898 899 static struct qcom_icc_node qhs_camera_cfg = { 900 .name = "qhs_camera_cfg", 901 .id = X1E80100_SLAVE_CAMERA_CFG, 902 .channels = 1, 903 .buswidth = 4, 904 .num_links = 0, 905 }; 906 907 static struct qcom_icc_node qhs_clk_ctl = { 908 .name = "qhs_clk_ctl", 909 .id = X1E80100_SLAVE_CLK_CTL, 910 .channels = 1, 911 .buswidth = 4, 912 .num_links = 0, 913 }; 914 915 static struct qcom_icc_node qhs_crypto0_cfg = { 916 .name = "qhs_crypto0_cfg", 917 .id = X1E80100_SLAVE_CRYPTO_0_CFG, 918 .channels = 1, 919 .buswidth = 4, 920 .num_links = 0, 921 }; 922 923 static struct qcom_icc_node qhs_display_cfg = { 924 .name = "qhs_display_cfg", 925 .id = X1E80100_SLAVE_DISPLAY_CFG, 926 .channels = 1, 927 .buswidth = 4, 928 .num_links = 0, 929 }; 930 931 static struct qcom_icc_node qhs_gpuss_cfg = { 932 .name = "qhs_gpuss_cfg", 933 .id = X1E80100_SLAVE_GFX3D_CFG, 934 .channels = 1, 935 .buswidth = 8, 936 .num_links = 0, 937 }; 938 939 static struct qcom_icc_node qhs_imem_cfg = { 940 .name = "qhs_imem_cfg", 941 .id = X1E80100_SLAVE_IMEM_CFG, 942 .channels = 1, 943 .buswidth = 4, 944 .num_links = 0, 945 }; 946 947 static struct qcom_icc_node qhs_ipc_router = { 948 .name = "qhs_ipc_router", 949 .id = X1E80100_SLAVE_IPC_ROUTER_CFG, 950 .channels = 1, 951 .buswidth = 4, 952 .num_links = 0, 953 }; 954 955 static struct qcom_icc_node qhs_pcie0_cfg = { 956 .name = "qhs_pcie0_cfg", 957 .id = X1E80100_SLAVE_PCIE_0_CFG, 958 .channels = 1, 959 .buswidth = 4, 960 .num_links = 0, 961 }; 962 963 static struct qcom_icc_node qhs_pcie1_cfg = { 964 .name = "qhs_pcie1_cfg", 965 .id = X1E80100_SLAVE_PCIE_1_CFG, 966 .channels = 1, 967 .buswidth = 4, 968 .num_links = 0, 969 }; 970 971 static struct qcom_icc_node qhs_pcie2_cfg = { 972 .name = "qhs_pcie2_cfg", 973 .id = X1E80100_SLAVE_PCIE_2_CFG, 974 .channels = 1, 975 .buswidth = 4, 976 .num_links = 0, 977 }; 978 979 static struct qcom_icc_node qhs_pcie3_cfg = { 980 .name = "qhs_pcie3_cfg", 981 .id = X1E80100_SLAVE_PCIE_3_CFG, 982 .channels = 1, 983 .buswidth = 4, 984 .num_links = 0, 985 }; 986 987 static struct qcom_icc_node qhs_pcie4_cfg = { 988 .name = "qhs_pcie4_cfg", 989 .id = X1E80100_SLAVE_PCIE_4_CFG, 990 .channels = 1, 991 .buswidth = 4, 992 .num_links = 0, 993 }; 994 995 static struct qcom_icc_node qhs_pcie5_cfg = { 996 .name = "qhs_pcie5_cfg", 997 .id = X1E80100_SLAVE_PCIE_5_CFG, 998 .channels = 1, 999 .buswidth = 4, 1000 .num_links = 0, 1001 }; 1002 1003 static struct qcom_icc_node qhs_pcie6a_cfg = { 1004 .name = "qhs_pcie6a_cfg", 1005 .id = X1E80100_SLAVE_PCIE_6A_CFG, 1006 .channels = 1, 1007 .buswidth = 4, 1008 .num_links = 0, 1009 }; 1010 1011 static struct qcom_icc_node qhs_pcie6b_cfg = { 1012 .name = "qhs_pcie6b_cfg", 1013 .id = X1E80100_SLAVE_PCIE_6B_CFG, 1014 .channels = 1, 1015 .buswidth = 4, 1016 .num_links = 0, 1017 }; 1018 1019 static struct qcom_icc_node qhs_pcie_rsc_cfg = { 1020 .name = "qhs_pcie_rsc_cfg", 1021 .id = X1E80100_SLAVE_PCIE_RSC_CFG, 1022 .channels = 1, 1023 .buswidth = 4, 1024 .num_links = 0, 1025 }; 1026 1027 static struct qcom_icc_node qhs_pdm = { 1028 .name = "qhs_pdm", 1029 .id = X1E80100_SLAVE_PDM, 1030 .channels = 1, 1031 .buswidth = 4, 1032 .num_links = 0, 1033 }; 1034 1035 static struct qcom_icc_node qhs_prng = { 1036 .name = "qhs_prng", 1037 .id = X1E80100_SLAVE_PRNG, 1038 .channels = 1, 1039 .buswidth = 4, 1040 .num_links = 0, 1041 }; 1042 1043 static struct qcom_icc_node qhs_qdss_cfg = { 1044 .name = "qhs_qdss_cfg", 1045 .id = X1E80100_SLAVE_QDSS_CFG, 1046 .channels = 1, 1047 .buswidth = 4, 1048 .num_links = 0, 1049 }; 1050 1051 static struct qcom_icc_node qhs_qspi = { 1052 .name = "qhs_qspi", 1053 .id = X1E80100_SLAVE_QSPI_0, 1054 .channels = 1, 1055 .buswidth = 4, 1056 .num_links = 0, 1057 }; 1058 1059 static struct qcom_icc_node qhs_qup0 = { 1060 .name = "qhs_qup0", 1061 .id = X1E80100_SLAVE_QUP_0, 1062 .channels = 1, 1063 .buswidth = 4, 1064 .num_links = 0, 1065 }; 1066 1067 static struct qcom_icc_node qhs_qup1 = { 1068 .name = "qhs_qup1", 1069 .id = X1E80100_SLAVE_QUP_1, 1070 .channels = 1, 1071 .buswidth = 4, 1072 .num_links = 0, 1073 }; 1074 1075 static struct qcom_icc_node qhs_qup2 = { 1076 .name = "qhs_qup2", 1077 .id = X1E80100_SLAVE_QUP_2, 1078 .channels = 1, 1079 .buswidth = 4, 1080 .num_links = 0, 1081 }; 1082 1083 static struct qcom_icc_node qhs_sdc2 = { 1084 .name = "qhs_sdc2", 1085 .id = X1E80100_SLAVE_SDCC_2, 1086 .channels = 1, 1087 .buswidth = 4, 1088 .num_links = 0, 1089 }; 1090 1091 static struct qcom_icc_node qhs_sdc4 = { 1092 .name = "qhs_sdc4", 1093 .id = X1E80100_SLAVE_SDCC_4, 1094 .channels = 1, 1095 .buswidth = 4, 1096 .num_links = 0, 1097 }; 1098 1099 static struct qcom_icc_node qhs_smmuv3_cfg = { 1100 .name = "qhs_smmuv3_cfg", 1101 .id = X1E80100_SLAVE_SMMUV3_CFG, 1102 .channels = 1, 1103 .buswidth = 8, 1104 .num_links = 0, 1105 }; 1106 1107 static struct qcom_icc_node qhs_tcsr = { 1108 .name = "qhs_tcsr", 1109 .id = X1E80100_SLAVE_TCSR, 1110 .channels = 1, 1111 .buswidth = 4, 1112 .num_links = 0, 1113 }; 1114 1115 static struct qcom_icc_node qhs_tlmm = { 1116 .name = "qhs_tlmm", 1117 .id = X1E80100_SLAVE_TLMM, 1118 .channels = 1, 1119 .buswidth = 4, 1120 .num_links = 0, 1121 }; 1122 1123 static struct qcom_icc_node qhs_ufs_mem_cfg = { 1124 .name = "qhs_ufs_mem_cfg", 1125 .id = X1E80100_SLAVE_UFS_MEM_CFG, 1126 .channels = 1, 1127 .buswidth = 4, 1128 .num_links = 0, 1129 }; 1130 1131 static struct qcom_icc_node qhs_usb2_0_cfg = { 1132 .name = "qhs_usb2_0_cfg", 1133 .id = X1E80100_SLAVE_USB2, 1134 .channels = 1, 1135 .buswidth = 4, 1136 .num_links = 0, 1137 }; 1138 1139 static struct qcom_icc_node qhs_usb3_0_cfg = { 1140 .name = "qhs_usb3_0_cfg", 1141 .id = X1E80100_SLAVE_USB3_0, 1142 .channels = 1, 1143 .buswidth = 4, 1144 .num_links = 0, 1145 }; 1146 1147 static struct qcom_icc_node qhs_usb3_1_cfg = { 1148 .name = "qhs_usb3_1_cfg", 1149 .id = X1E80100_SLAVE_USB3_1, 1150 .channels = 1, 1151 .buswidth = 4, 1152 .num_links = 0, 1153 }; 1154 1155 static struct qcom_icc_node qhs_usb3_2_cfg = { 1156 .name = "qhs_usb3_2_cfg", 1157 .id = X1E80100_SLAVE_USB3_2, 1158 .channels = 1, 1159 .buswidth = 4, 1160 .num_links = 0, 1161 }; 1162 1163 static struct qcom_icc_node qhs_usb3_mp_cfg = { 1164 .name = "qhs_usb3_mp_cfg", 1165 .id = X1E80100_SLAVE_USB3_MP, 1166 .channels = 1, 1167 .buswidth = 4, 1168 .num_links = 0, 1169 }; 1170 1171 static struct qcom_icc_node qhs_usb4_0_cfg = { 1172 .name = "qhs_usb4_0_cfg", 1173 .id = X1E80100_SLAVE_USB4_0, 1174 .channels = 1, 1175 .buswidth = 4, 1176 .num_links = 0, 1177 }; 1178 1179 static struct qcom_icc_node qhs_usb4_1_cfg = { 1180 .name = "qhs_usb4_1_cfg", 1181 .id = X1E80100_SLAVE_USB4_1, 1182 .channels = 1, 1183 .buswidth = 4, 1184 .num_links = 0, 1185 }; 1186 1187 static struct qcom_icc_node qhs_usb4_2_cfg = { 1188 .name = "qhs_usb4_2_cfg", 1189 .id = X1E80100_SLAVE_USB4_2, 1190 .channels = 1, 1191 .buswidth = 4, 1192 .num_links = 0, 1193 }; 1194 1195 static struct qcom_icc_node qhs_venus_cfg = { 1196 .name = "qhs_venus_cfg", 1197 .id = X1E80100_SLAVE_VENUS_CFG, 1198 .channels = 1, 1199 .buswidth = 4, 1200 .num_links = 0, 1201 }; 1202 1203 static struct qcom_icc_node qss_lpass_qtb_cfg = { 1204 .name = "qss_lpass_qtb_cfg", 1205 .id = X1E80100_SLAVE_LPASS_QTB_CFG, 1206 .channels = 1, 1207 .buswidth = 4, 1208 .num_links = 0, 1209 }; 1210 1211 static struct qcom_icc_node qss_mnoc_cfg = { 1212 .name = "qss_mnoc_cfg", 1213 .id = X1E80100_SLAVE_CNOC_MNOC_CFG, 1214 .channels = 1, 1215 .buswidth = 4, 1216 .num_links = 1, 1217 .links = { X1E80100_MASTER_CNOC_MNOC_CFG }, 1218 }; 1219 1220 static struct qcom_icc_node qss_nsp_qtb_cfg = { 1221 .name = "qss_nsp_qtb_cfg", 1222 .id = X1E80100_SLAVE_NSP_QTB_CFG, 1223 .channels = 1, 1224 .buswidth = 4, 1225 .num_links = 0, 1226 }; 1227 1228 static struct qcom_icc_node xs_qdss_stm = { 1229 .name = "xs_qdss_stm", 1230 .id = X1E80100_SLAVE_QDSS_STM, 1231 .channels = 1, 1232 .buswidth = 4, 1233 .num_links = 0, 1234 }; 1235 1236 static struct qcom_icc_node xs_sys_tcu_cfg = { 1237 .name = "xs_sys_tcu_cfg", 1238 .id = X1E80100_SLAVE_TCU, 1239 .channels = 1, 1240 .buswidth = 8, 1241 .num_links = 0, 1242 }; 1243 1244 static struct qcom_icc_node qhs_aoss = { 1245 .name = "qhs_aoss", 1246 .id = X1E80100_SLAVE_AOSS, 1247 .channels = 1, 1248 .buswidth = 4, 1249 .num_links = 0, 1250 }; 1251 1252 static struct qcom_icc_node qhs_tme_cfg = { 1253 .name = "qhs_tme_cfg", 1254 .id = X1E80100_SLAVE_TME_CFG, 1255 .channels = 1, 1256 .buswidth = 4, 1257 .num_links = 0, 1258 }; 1259 1260 static struct qcom_icc_node qns_apss = { 1261 .name = "qns_apss", 1262 .id = X1E80100_SLAVE_APPSS, 1263 .channels = 1, 1264 .buswidth = 8, 1265 .num_links = 0, 1266 }; 1267 1268 static struct qcom_icc_node qss_cfg = { 1269 .name = "qss_cfg", 1270 .id = X1E80100_SLAVE_CNOC_CFG, 1271 .channels = 1, 1272 .buswidth = 4, 1273 .num_links = 1, 1274 .links = { X1E80100_MASTER_CNOC_CFG }, 1275 }; 1276 1277 static struct qcom_icc_node qxs_boot_imem = { 1278 .name = "qxs_boot_imem", 1279 .id = X1E80100_SLAVE_BOOT_IMEM, 1280 .channels = 1, 1281 .buswidth = 16, 1282 .num_links = 0, 1283 }; 1284 1285 static struct qcom_icc_node qxs_imem = { 1286 .name = "qxs_imem", 1287 .id = X1E80100_SLAVE_IMEM, 1288 .channels = 1, 1289 .buswidth = 8, 1290 .num_links = 0, 1291 }; 1292 1293 static struct qcom_icc_node xs_pcie_0 = { 1294 .name = "xs_pcie_0", 1295 .id = X1E80100_SLAVE_PCIE_0, 1296 .channels = 1, 1297 .buswidth = 16, 1298 .num_links = 0, 1299 }; 1300 1301 static struct qcom_icc_node xs_pcie_1 = { 1302 .name = "xs_pcie_1", 1303 .id = X1E80100_SLAVE_PCIE_1, 1304 .channels = 1, 1305 .buswidth = 16, 1306 .num_links = 0, 1307 }; 1308 1309 static struct qcom_icc_node xs_pcie_2 = { 1310 .name = "xs_pcie_2", 1311 .id = X1E80100_SLAVE_PCIE_2, 1312 .channels = 1, 1313 .buswidth = 16, 1314 .num_links = 0, 1315 }; 1316 1317 static struct qcom_icc_node xs_pcie_3 = { 1318 .name = "xs_pcie_3", 1319 .id = X1E80100_SLAVE_PCIE_3, 1320 .channels = 1, 1321 .buswidth = 64, 1322 .num_links = 0, 1323 }; 1324 1325 static struct qcom_icc_node xs_pcie_4 = { 1326 .name = "xs_pcie_4", 1327 .id = X1E80100_SLAVE_PCIE_4, 1328 .channels = 1, 1329 .buswidth = 8, 1330 .num_links = 0, 1331 }; 1332 1333 static struct qcom_icc_node xs_pcie_5 = { 1334 .name = "xs_pcie_5", 1335 .id = X1E80100_SLAVE_PCIE_5, 1336 .channels = 1, 1337 .buswidth = 8, 1338 .num_links = 0, 1339 }; 1340 1341 static struct qcom_icc_node xs_pcie_6a = { 1342 .name = "xs_pcie_6a", 1343 .id = X1E80100_SLAVE_PCIE_6A, 1344 .channels = 1, 1345 .buswidth = 32, 1346 .num_links = 0, 1347 }; 1348 1349 static struct qcom_icc_node xs_pcie_6b = { 1350 .name = "xs_pcie_6b", 1351 .id = X1E80100_SLAVE_PCIE_6B, 1352 .channels = 1, 1353 .buswidth = 16, 1354 .num_links = 0, 1355 }; 1356 1357 static struct qcom_icc_node qns_gem_noc_cnoc = { 1358 .name = "qns_gem_noc_cnoc", 1359 .id = X1E80100_SLAVE_GEM_NOC_CNOC, 1360 .channels = 1, 1361 .buswidth = 16, 1362 .num_links = 1, 1363 .links = { X1E80100_MASTER_GEM_NOC_CNOC }, 1364 }; 1365 1366 static struct qcom_icc_node qns_llcc = { 1367 .name = "qns_llcc", 1368 .id = X1E80100_SLAVE_LLCC, 1369 .channels = 8, 1370 .buswidth = 16, 1371 .num_links = 1, 1372 .links = { X1E80100_MASTER_LLCC }, 1373 }; 1374 1375 static struct qcom_icc_node qns_pcie = { 1376 .name = "qns_pcie", 1377 .id = X1E80100_SLAVE_MEM_NOC_PCIE_SNOC, 1378 .channels = 1, 1379 .buswidth = 32, 1380 .num_links = 1, 1381 .links = { X1E80100_MASTER_GEM_NOC_PCIE_SNOC }, 1382 }; 1383 1384 static struct qcom_icc_node qns_lpass_ag_noc_gemnoc = { 1385 .name = "qns_lpass_ag_noc_gemnoc", 1386 .id = X1E80100_SLAVE_LPASS_GEM_NOC, 1387 .channels = 1, 1388 .buswidth = 16, 1389 .num_links = 1, 1390 .links = { X1E80100_MASTER_LPASS_GEM_NOC }, 1391 }; 1392 1393 static struct qcom_icc_node qns_lpass_aggnoc = { 1394 .name = "qns_lpass_aggnoc", 1395 .id = X1E80100_SLAVE_LPIAON_NOC_LPASS_AG_NOC, 1396 .channels = 1, 1397 .buswidth = 16, 1398 .num_links = 1, 1399 .links = { X1E80100_MASTER_LPIAON_NOC }, 1400 }; 1401 1402 static struct qcom_icc_node qns_lpi_aon_noc = { 1403 .name = "qns_lpi_aon_noc", 1404 .id = X1E80100_SLAVE_LPICX_NOC_LPIAON_NOC, 1405 .channels = 1, 1406 .buswidth = 16, 1407 .num_links = 1, 1408 .links = { X1E80100_MASTER_LPASS_LPINOC }, 1409 }; 1410 1411 static struct qcom_icc_node ebi = { 1412 .name = "ebi", 1413 .id = X1E80100_SLAVE_EBI1, 1414 .channels = 8, 1415 .buswidth = 4, 1416 .num_links = 0, 1417 }; 1418 1419 static struct qcom_icc_node qns_mem_noc_hf = { 1420 .name = "qns_mem_noc_hf", 1421 .id = X1E80100_SLAVE_MNOC_HF_MEM_NOC, 1422 .channels = 2, 1423 .buswidth = 32, 1424 .num_links = 1, 1425 .links = { X1E80100_MASTER_MNOC_HF_MEM_NOC }, 1426 }; 1427 1428 static struct qcom_icc_node qns_mem_noc_sf = { 1429 .name = "qns_mem_noc_sf", 1430 .id = X1E80100_SLAVE_MNOC_SF_MEM_NOC, 1431 .channels = 2, 1432 .buswidth = 32, 1433 .num_links = 1, 1434 .links = { X1E80100_MASTER_MNOC_SF_MEM_NOC }, 1435 }; 1436 1437 static struct qcom_icc_node srvc_mnoc = { 1438 .name = "srvc_mnoc", 1439 .id = X1E80100_SLAVE_SERVICE_MNOC, 1440 .channels = 1, 1441 .buswidth = 4, 1442 .num_links = 0, 1443 }; 1444 1445 static struct qcom_icc_node qns_nsp_gemnoc = { 1446 .name = "qns_nsp_gemnoc", 1447 .id = X1E80100_SLAVE_CDSP_MEM_NOC, 1448 .channels = 2, 1449 .buswidth = 32, 1450 .num_links = 1, 1451 .links = { X1E80100_MASTER_COMPUTE_NOC }, 1452 }; 1453 1454 static struct qcom_icc_node qns_pcie_mem_noc = { 1455 .name = "qns_pcie_mem_noc", 1456 .id = X1E80100_SLAVE_ANOC_PCIE_GEM_NOC, 1457 .channels = 1, 1458 .buswidth = 64, 1459 .num_links = 1, 1460 .links = { X1E80100_MASTER_ANOC_PCIE_GEM_NOC }, 1461 }; 1462 1463 static struct qcom_icc_node qns_pcie_north_gem_noc = { 1464 .name = "qns_pcie_north_gem_noc", 1465 .id = X1E80100_SLAVE_PCIE_NORTH, 1466 .channels = 1, 1467 .buswidth = 64, 1468 .num_links = 1, 1469 .links = { X1E80100_MASTER_PCIE_NORTH }, 1470 }; 1471 1472 static struct qcom_icc_node qns_pcie_south_gem_noc = { 1473 .name = "qns_pcie_south_gem_noc", 1474 .id = X1E80100_SLAVE_PCIE_SOUTH, 1475 .channels = 1, 1476 .buswidth = 64, 1477 .num_links = 1, 1478 .links = { X1E80100_MASTER_PCIE_SOUTH }, 1479 }; 1480 1481 static struct qcom_icc_node qns_gemnoc_sf = { 1482 .name = "qns_gemnoc_sf", 1483 .id = X1E80100_SLAVE_SNOC_GEM_NOC_SF, 1484 .channels = 1, 1485 .buswidth = 64, 1486 .num_links = 1, 1487 .links = { X1E80100_MASTER_SNOC_SF_MEM_NOC }, 1488 }; 1489 1490 static struct qcom_icc_node qns_aggre_usb_snoc = { 1491 .name = "qns_aggre_usb_snoc", 1492 .id = X1E80100_SLAVE_USB_NOC_SNOC, 1493 .channels = 1, 1494 .buswidth = 64, 1495 .num_links = 1, 1496 .links = { X1E80100_MASTER_USB_NOC_SNOC }, 1497 }; 1498 1499 static struct qcom_icc_node qns_aggre_usb_north_snoc = { 1500 .name = "qns_aggre_usb_north_snoc", 1501 .id = X1E80100_SLAVE_AGGRE_USB_NORTH, 1502 .channels = 1, 1503 .buswidth = 64, 1504 .num_links = 1, 1505 .links = { X1E80100_MASTER_AGGRE_USB_NORTH }, 1506 }; 1507 1508 static struct qcom_icc_node qns_aggre_usb_south_snoc = { 1509 .name = "qns_aggre_usb_south_snoc", 1510 .id = X1E80100_SLAVE_AGGRE_USB_SOUTH, 1511 .channels = 1, 1512 .buswidth = 64, 1513 .num_links = 1, 1514 .links = { X1E80100_MASTER_AGGRE_USB_SOUTH }, 1515 }; 1516 1517 static struct qcom_icc_node qns_llcc_disp = { 1518 .name = "qns_llcc_disp", 1519 .id = X1E80100_SLAVE_LLCC_DISP, 1520 .channels = 8, 1521 .buswidth = 16, 1522 .num_links = 1, 1523 .links = { X1E80100_MASTER_LLCC_DISP }, 1524 }; 1525 1526 static struct qcom_icc_node ebi_disp = { 1527 .name = "ebi_disp", 1528 .id = X1E80100_SLAVE_EBI1_DISP, 1529 .channels = 8, 1530 .buswidth = 4, 1531 .num_links = 0, 1532 }; 1533 1534 static struct qcom_icc_node qns_mem_noc_hf_disp = { 1535 .name = "qns_mem_noc_hf_disp", 1536 .id = X1E80100_SLAVE_MNOC_HF_MEM_NOC_DISP, 1537 .channels = 2, 1538 .buswidth = 32, 1539 .num_links = 1, 1540 .links = { X1E80100_MASTER_MNOC_HF_MEM_NOC_DISP }, 1541 }; 1542 1543 static struct qcom_icc_node qns_llcc_pcie = { 1544 .name = "qns_llcc_pcie", 1545 .id = X1E80100_SLAVE_LLCC_PCIE, 1546 .channels = 8, 1547 .buswidth = 16, 1548 .num_links = 1, 1549 .links = { X1E80100_MASTER_LLCC_PCIE }, 1550 }; 1551 1552 static struct qcom_icc_node ebi_pcie = { 1553 .name = "ebi_pcie", 1554 .id = X1E80100_SLAVE_EBI1_PCIE, 1555 .channels = 8, 1556 .buswidth = 4, 1557 .num_links = 0, 1558 }; 1559 1560 static struct qcom_icc_node qns_pcie_mem_noc_pcie = { 1561 .name = "qns_pcie_mem_noc_pcie", 1562 .id = X1E80100_SLAVE_ANOC_PCIE_GEM_NOC_PCIE, 1563 .channels = 1, 1564 .buswidth = 64, 1565 .num_links = 1, 1566 .links = { X1E80100_MASTER_ANOC_PCIE_GEM_NOC_PCIE }, 1567 }; 1568 1569 static struct qcom_icc_node qns_pcie_north_gem_noc_pcie = { 1570 .name = "qns_pcie_north_gem_noc_pcie", 1571 .id = X1E80100_SLAVE_PCIE_NORTH_PCIE, 1572 .channels = 1, 1573 .buswidth = 64, 1574 .num_links = 1, 1575 .links = { X1E80100_MASTER_PCIE_NORTH_PCIE }, 1576 }; 1577 1578 static struct qcom_icc_node qns_pcie_south_gem_noc_pcie = { 1579 .name = "qns_pcie_south_gem_noc_pcie", 1580 .id = X1E80100_SLAVE_PCIE_SOUTH_PCIE, 1581 .channels = 1, 1582 .buswidth = 64, 1583 .num_links = 1, 1584 .links = { X1E80100_MASTER_PCIE_SOUTH_PCIE }, 1585 }; 1586 1587 static struct qcom_icc_bcm bcm_acv = { 1588 .name = "ACV", 1589 .enable_mask = BIT(3), 1590 .num_nodes = 1, 1591 .nodes = { &ebi }, 1592 }; 1593 1594 static struct qcom_icc_bcm bcm_acv_perf = { 1595 .name = "ACV_PERF", 1596 .num_nodes = 1, 1597 .nodes = { &ddr_perf_mode_slave }, 1598 }; 1599 1600 static struct qcom_icc_bcm bcm_ce0 = { 1601 .name = "CE0", 1602 .num_nodes = 1, 1603 .nodes = { &qxm_crypto }, 1604 }; 1605 1606 static struct qcom_icc_bcm bcm_cn0 = { 1607 .name = "CN0", 1608 .keepalive = true, 1609 .num_nodes = 63, 1610 .nodes = { &qsm_cfg, &qhs_ahb2phy0, 1611 &qhs_ahb2phy1, &qhs_ahb2phy2, 1612 &qhs_av1_enc_cfg, &qhs_camera_cfg, 1613 &qhs_clk_ctl, &qhs_crypto0_cfg, 1614 &qhs_gpuss_cfg, &qhs_imem_cfg, 1615 &qhs_ipc_router, &qhs_pcie0_cfg, 1616 &qhs_pcie1_cfg, &qhs_pcie2_cfg, 1617 &qhs_pcie3_cfg, &qhs_pcie4_cfg, 1618 &qhs_pcie5_cfg, &qhs_pcie6a_cfg, 1619 &qhs_pcie6b_cfg, &qhs_pcie_rsc_cfg, 1620 &qhs_pdm, &qhs_prng, 1621 &qhs_qdss_cfg, &qhs_qspi, 1622 &qhs_qup0, &qhs_qup1, 1623 &qhs_qup2, &qhs_sdc2, 1624 &qhs_sdc4, &qhs_smmuv3_cfg, 1625 &qhs_tcsr, &qhs_tlmm, 1626 &qhs_ufs_mem_cfg, &qhs_usb2_0_cfg, 1627 &qhs_usb3_0_cfg, &qhs_usb3_1_cfg, 1628 &qhs_usb3_2_cfg, &qhs_usb3_mp_cfg, 1629 &qhs_usb4_0_cfg, &qhs_usb4_1_cfg, 1630 &qhs_usb4_2_cfg, &qhs_venus_cfg, 1631 &qss_lpass_qtb_cfg, &qss_mnoc_cfg, 1632 &qss_nsp_qtb_cfg, &xs_qdss_stm, 1633 &xs_sys_tcu_cfg, &qnm_gemnoc_cnoc, 1634 &qnm_gemnoc_pcie, &qhs_aoss, 1635 &qhs_tme_cfg, &qns_apss, 1636 &qss_cfg, &qxs_boot_imem, 1637 &qxs_imem, &xs_pcie_0, 1638 &xs_pcie_1, &xs_pcie_2, 1639 &xs_pcie_3, &xs_pcie_4, 1640 &xs_pcie_5, &xs_pcie_6a, 1641 &xs_pcie_6b }, 1642 }; 1643 1644 static struct qcom_icc_bcm bcm_cn1 = { 1645 .name = "CN1", 1646 .num_nodes = 1, 1647 .nodes = { &qhs_display_cfg }, 1648 }; 1649 1650 static struct qcom_icc_bcm bcm_co0 = { 1651 .name = "CO0", 1652 .num_nodes = 2, 1653 .nodes = { &qxm_nsp, &qns_nsp_gemnoc }, 1654 }; 1655 1656 static struct qcom_icc_bcm bcm_lp0 = { 1657 .name = "LP0", 1658 .num_nodes = 2, 1659 .nodes = { &qnm_lpass_lpinoc, &qns_lpass_aggnoc }, 1660 }; 1661 1662 static struct qcom_icc_bcm bcm_mc0 = { 1663 .name = "MC0", 1664 .keepalive = true, 1665 .num_nodes = 1, 1666 .nodes = { &ebi }, 1667 }; 1668 1669 static struct qcom_icc_bcm bcm_mm0 = { 1670 .name = "MM0", 1671 .num_nodes = 1, 1672 .nodes = { &qns_mem_noc_hf }, 1673 }; 1674 1675 static struct qcom_icc_bcm bcm_mm1 = { 1676 .name = "MM1", 1677 .num_nodes = 10, 1678 .nodes = { &qnm_av1_enc, &qnm_camnoc_hf, 1679 &qnm_camnoc_icp, &qnm_camnoc_sf, 1680 &qnm_eva, &qnm_mdp, 1681 &qnm_video, &qnm_video_cv_cpu, 1682 &qnm_video_v_cpu, &qns_mem_noc_sf }, 1683 }; 1684 1685 static struct qcom_icc_bcm bcm_pc0 = { 1686 .name = "PC0", 1687 .num_nodes = 1, 1688 .nodes = { &qns_pcie_mem_noc }, 1689 }; 1690 1691 static struct qcom_icc_bcm bcm_qup0 = { 1692 .name = "QUP0", 1693 .keepalive = true, 1694 .vote_scale = 1, 1695 .num_nodes = 1, 1696 .nodes = { &qup0_core_slave }, 1697 }; 1698 1699 static struct qcom_icc_bcm bcm_qup1 = { 1700 .name = "QUP1", 1701 .keepalive = true, 1702 .vote_scale = 1, 1703 .num_nodes = 1, 1704 .nodes = { &qup1_core_slave }, 1705 }; 1706 1707 static struct qcom_icc_bcm bcm_qup2 = { 1708 .name = "QUP2", 1709 .keepalive = true, 1710 .vote_scale = 1, 1711 .num_nodes = 1, 1712 .nodes = { &qup2_core_slave }, 1713 }; 1714 1715 static struct qcom_icc_bcm bcm_sh0 = { 1716 .name = "SH0", 1717 .keepalive = true, 1718 .num_nodes = 1, 1719 .nodes = { &qns_llcc }, 1720 }; 1721 1722 static struct qcom_icc_bcm bcm_sh1 = { 1723 .name = "SH1", 1724 .num_nodes = 13, 1725 .nodes = { &alm_gpu_tcu, &alm_pcie_tcu, 1726 &alm_sys_tcu, &chm_apps, 1727 &qnm_gpu, &qnm_lpass, 1728 &qnm_mnoc_hf, &qnm_mnoc_sf, 1729 &qnm_nsp_noc, &qnm_pcie, 1730 &xm_gic, &qns_gem_noc_cnoc, 1731 &qns_pcie }, 1732 }; 1733 1734 static struct qcom_icc_bcm bcm_sn0 = { 1735 .name = "SN0", 1736 .keepalive = true, 1737 .num_nodes = 1, 1738 .nodes = { &qns_gemnoc_sf }, 1739 }; 1740 1741 static struct qcom_icc_bcm bcm_sn2 = { 1742 .name = "SN2", 1743 .num_nodes = 1, 1744 .nodes = { &qnm_aggre1_noc }, 1745 }; 1746 1747 static struct qcom_icc_bcm bcm_sn3 = { 1748 .name = "SN3", 1749 .num_nodes = 1, 1750 .nodes = { &qnm_aggre2_noc }, 1751 }; 1752 1753 static struct qcom_icc_bcm bcm_sn4 = { 1754 .name = "SN4", 1755 .num_nodes = 1, 1756 .nodes = { &qnm_usb_anoc }, 1757 }; 1758 1759 static struct qcom_icc_bcm bcm_acv_disp = { 1760 .name = "ACV", 1761 .num_nodes = 1, 1762 .nodes = { &ebi_disp }, 1763 }; 1764 1765 static struct qcom_icc_bcm bcm_mc0_disp = { 1766 .name = "MC0", 1767 .num_nodes = 1, 1768 .nodes = { &ebi_disp }, 1769 }; 1770 1771 static struct qcom_icc_bcm bcm_mm0_disp = { 1772 .name = "MM0", 1773 .num_nodes = 1, 1774 .nodes = { &qns_mem_noc_hf_disp }, 1775 }; 1776 1777 static struct qcom_icc_bcm bcm_mm1_disp = { 1778 .name = "MM1", 1779 .num_nodes = 1, 1780 .nodes = { &qnm_mdp_disp }, 1781 }; 1782 1783 static struct qcom_icc_bcm bcm_sh0_disp = { 1784 .name = "SH0", 1785 .num_nodes = 1, 1786 .nodes = { &qns_llcc_disp }, 1787 }; 1788 1789 static struct qcom_icc_bcm bcm_sh1_disp = { 1790 .name = "SH1", 1791 .num_nodes = 2, 1792 .nodes = { &qnm_mnoc_hf_disp, &qnm_pcie_disp }, 1793 }; 1794 1795 static struct qcom_icc_bcm bcm_acv_pcie = { 1796 .name = "ACV", 1797 .num_nodes = 1, 1798 .nodes = { &ebi_pcie }, 1799 }; 1800 1801 static struct qcom_icc_bcm bcm_mc0_pcie = { 1802 .name = "MC0", 1803 .num_nodes = 1, 1804 .nodes = { &ebi_pcie }, 1805 }; 1806 1807 static struct qcom_icc_bcm bcm_pc0_pcie = { 1808 .name = "PC0", 1809 .num_nodes = 1, 1810 .nodes = { &qns_pcie_mem_noc_pcie }, 1811 }; 1812 1813 static struct qcom_icc_bcm bcm_sh0_pcie = { 1814 .name = "SH0", 1815 .num_nodes = 1, 1816 .nodes = { &qns_llcc_pcie }, 1817 }; 1818 1819 static struct qcom_icc_bcm bcm_sh1_pcie = { 1820 .name = "SH1", 1821 .num_nodes = 1, 1822 .nodes = { &qnm_pcie_pcie }, 1823 }; 1824 1825 static struct qcom_icc_bcm *aggre1_noc_bcms[] = { 1826 }; 1827 1828 static struct qcom_icc_node * const aggre1_noc_nodes[] = { 1829 [MASTER_QSPI_0] = &qhm_qspi, 1830 [MASTER_QUP_1] = &qhm_qup1, 1831 [MASTER_SDCC_4] = &xm_sdc4, 1832 [MASTER_UFS_MEM] = &xm_ufs_mem, 1833 [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc, 1834 }; 1835 1836 static const struct qcom_icc_desc x1e80100_aggre1_noc = { 1837 .nodes = aggre1_noc_nodes, 1838 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), 1839 .bcms = aggre1_noc_bcms, 1840 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), 1841 }; 1842 1843 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { 1844 &bcm_ce0, 1845 }; 1846 1847 static struct qcom_icc_node * const aggre2_noc_nodes[] = { 1848 [MASTER_QUP_0] = &qhm_qup0, 1849 [MASTER_QUP_2] = &qhm_qup2, 1850 [MASTER_CRYPTO] = &qxm_crypto, 1851 [MASTER_SP] = &qxm_sp, 1852 [MASTER_QDSS_ETR] = &xm_qdss_etr_0, 1853 [MASTER_QDSS_ETR_1] = &xm_qdss_etr_1, 1854 [MASTER_SDCC_2] = &xm_sdc2, 1855 [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc, 1856 }; 1857 1858 static const struct qcom_icc_desc x1e80100_aggre2_noc = { 1859 .nodes = aggre2_noc_nodes, 1860 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), 1861 .bcms = aggre2_noc_bcms, 1862 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), 1863 }; 1864 1865 static struct qcom_icc_bcm * const clk_virt_bcms[] = { 1866 &bcm_acv_perf, 1867 &bcm_qup0, 1868 &bcm_qup1, 1869 &bcm_qup2, 1870 }; 1871 1872 static struct qcom_icc_node * const clk_virt_nodes[] = { 1873 [MASTER_DDR_PERF_MODE] = &ddr_perf_mode_master, 1874 [MASTER_QUP_CORE_0] = &qup0_core_master, 1875 [MASTER_QUP_CORE_1] = &qup1_core_master, 1876 [MASTER_QUP_CORE_2] = &qup2_core_master, 1877 [SLAVE_DDR_PERF_MODE] = &ddr_perf_mode_slave, 1878 [SLAVE_QUP_CORE_0] = &qup0_core_slave, 1879 [SLAVE_QUP_CORE_1] = &qup1_core_slave, 1880 [SLAVE_QUP_CORE_2] = &qup2_core_slave, 1881 }; 1882 1883 static const struct qcom_icc_desc x1e80100_clk_virt = { 1884 .nodes = clk_virt_nodes, 1885 .num_nodes = ARRAY_SIZE(clk_virt_nodes), 1886 .bcms = clk_virt_bcms, 1887 .num_bcms = ARRAY_SIZE(clk_virt_bcms), 1888 }; 1889 1890 static struct qcom_icc_bcm * const cnoc_cfg_bcms[] = { 1891 &bcm_cn0, 1892 &bcm_cn1, 1893 }; 1894 1895 static struct qcom_icc_node * const cnoc_cfg_nodes[] = { 1896 [MASTER_CNOC_CFG] = &qsm_cfg, 1897 [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0, 1898 [SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1, 1899 [SLAVE_AHB2PHY_2] = &qhs_ahb2phy2, 1900 [SLAVE_AV1_ENC_CFG] = &qhs_av1_enc_cfg, 1901 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, 1902 [SLAVE_CLK_CTL] = &qhs_clk_ctl, 1903 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, 1904 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg, 1905 [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg, 1906 [SLAVE_IMEM_CFG] = &qhs_imem_cfg, 1907 [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router, 1908 [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg, 1909 [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg, 1910 [SLAVE_PCIE_2_CFG] = &qhs_pcie2_cfg, 1911 [SLAVE_PCIE_3_CFG] = &qhs_pcie3_cfg, 1912 [SLAVE_PCIE_4_CFG] = &qhs_pcie4_cfg, 1913 [SLAVE_PCIE_5_CFG] = &qhs_pcie5_cfg, 1914 [SLAVE_PCIE_6A_CFG] = &qhs_pcie6a_cfg, 1915 [SLAVE_PCIE_6B_CFG] = &qhs_pcie6b_cfg, 1916 [SLAVE_PCIE_RSC_CFG] = &qhs_pcie_rsc_cfg, 1917 [SLAVE_PDM] = &qhs_pdm, 1918 [SLAVE_PRNG] = &qhs_prng, 1919 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, 1920 [SLAVE_QSPI_0] = &qhs_qspi, 1921 [SLAVE_QUP_0] = &qhs_qup0, 1922 [SLAVE_QUP_1] = &qhs_qup1, 1923 [SLAVE_QUP_2] = &qhs_qup2, 1924 [SLAVE_SDCC_2] = &qhs_sdc2, 1925 [SLAVE_SDCC_4] = &qhs_sdc4, 1926 [SLAVE_SMMUV3_CFG] = &qhs_smmuv3_cfg, 1927 [SLAVE_TCSR] = &qhs_tcsr, 1928 [SLAVE_TLMM] = &qhs_tlmm, 1929 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, 1930 [SLAVE_USB2] = &qhs_usb2_0_cfg, 1931 [SLAVE_USB3_0] = &qhs_usb3_0_cfg, 1932 [SLAVE_USB3_1] = &qhs_usb3_1_cfg, 1933 [SLAVE_USB3_2] = &qhs_usb3_2_cfg, 1934 [SLAVE_USB3_MP] = &qhs_usb3_mp_cfg, 1935 [SLAVE_USB4_0] = &qhs_usb4_0_cfg, 1936 [SLAVE_USB4_1] = &qhs_usb4_1_cfg, 1937 [SLAVE_USB4_2] = &qhs_usb4_2_cfg, 1938 [SLAVE_VENUS_CFG] = &qhs_venus_cfg, 1939 [SLAVE_LPASS_QTB_CFG] = &qss_lpass_qtb_cfg, 1940 [SLAVE_CNOC_MNOC_CFG] = &qss_mnoc_cfg, 1941 [SLAVE_NSP_QTB_CFG] = &qss_nsp_qtb_cfg, 1942 [SLAVE_QDSS_STM] = &xs_qdss_stm, 1943 [SLAVE_TCU] = &xs_sys_tcu_cfg, 1944 }; 1945 1946 static const struct qcom_icc_desc x1e80100_cnoc_cfg = { 1947 .nodes = cnoc_cfg_nodes, 1948 .num_nodes = ARRAY_SIZE(cnoc_cfg_nodes), 1949 .bcms = cnoc_cfg_bcms, 1950 .num_bcms = ARRAY_SIZE(cnoc_cfg_bcms), 1951 }; 1952 1953 static struct qcom_icc_bcm * const cnoc_main_bcms[] = { 1954 &bcm_cn0, 1955 }; 1956 1957 static struct qcom_icc_node * const cnoc_main_nodes[] = { 1958 [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc, 1959 [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie, 1960 [SLAVE_AOSS] = &qhs_aoss, 1961 [SLAVE_TME_CFG] = &qhs_tme_cfg, 1962 [SLAVE_APPSS] = &qns_apss, 1963 [SLAVE_CNOC_CFG] = &qss_cfg, 1964 [SLAVE_BOOT_IMEM] = &qxs_boot_imem, 1965 [SLAVE_IMEM] = &qxs_imem, 1966 [SLAVE_PCIE_0] = &xs_pcie_0, 1967 [SLAVE_PCIE_1] = &xs_pcie_1, 1968 [SLAVE_PCIE_2] = &xs_pcie_2, 1969 [SLAVE_PCIE_3] = &xs_pcie_3, 1970 [SLAVE_PCIE_4] = &xs_pcie_4, 1971 [SLAVE_PCIE_5] = &xs_pcie_5, 1972 [SLAVE_PCIE_6A] = &xs_pcie_6a, 1973 [SLAVE_PCIE_6B] = &xs_pcie_6b, 1974 }; 1975 1976 static const struct qcom_icc_desc x1e80100_cnoc_main = { 1977 .nodes = cnoc_main_nodes, 1978 .num_nodes = ARRAY_SIZE(cnoc_main_nodes), 1979 .bcms = cnoc_main_bcms, 1980 .num_bcms = ARRAY_SIZE(cnoc_main_bcms), 1981 }; 1982 1983 static struct qcom_icc_bcm * const gem_noc_bcms[] = { 1984 &bcm_sh0, 1985 &bcm_sh1, 1986 &bcm_sh0_disp, 1987 &bcm_sh1_disp, 1988 &bcm_sh0_pcie, 1989 &bcm_sh1_pcie, 1990 }; 1991 1992 static struct qcom_icc_node * const gem_noc_nodes[] = { 1993 [MASTER_GPU_TCU] = &alm_gpu_tcu, 1994 [MASTER_PCIE_TCU] = &alm_pcie_tcu, 1995 [MASTER_SYS_TCU] = &alm_sys_tcu, 1996 [MASTER_APPSS_PROC] = &chm_apps, 1997 [MASTER_GFX3D] = &qnm_gpu, 1998 [MASTER_LPASS_GEM_NOC] = &qnm_lpass, 1999 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, 2000 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, 2001 [MASTER_COMPUTE_NOC] = &qnm_nsp_noc, 2002 [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie, 2003 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, 2004 [MASTER_GIC2] = &xm_gic, 2005 [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc, 2006 [SLAVE_LLCC] = &qns_llcc, 2007 [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie, 2008 [MASTER_MNOC_HF_MEM_NOC_DISP] = &qnm_mnoc_hf_disp, 2009 [MASTER_ANOC_PCIE_GEM_NOC_DISP] = &qnm_pcie_disp, 2010 [SLAVE_LLCC_DISP] = &qns_llcc_disp, 2011 [MASTER_ANOC_PCIE_GEM_NOC_PCIE] = &qnm_pcie_pcie, 2012 [SLAVE_LLCC_PCIE] = &qns_llcc_pcie, 2013 }; 2014 2015 static const struct qcom_icc_desc x1e80100_gem_noc = { 2016 .nodes = gem_noc_nodes, 2017 .num_nodes = ARRAY_SIZE(gem_noc_nodes), 2018 .bcms = gem_noc_bcms, 2019 .num_bcms = ARRAY_SIZE(gem_noc_bcms), 2020 }; 2021 2022 static struct qcom_icc_bcm *lpass_ag_noc_bcms[] = { 2023 }; 2024 2025 static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { 2026 [MASTER_LPIAON_NOC] = &qnm_lpiaon_noc, 2027 [SLAVE_LPASS_GEM_NOC] = &qns_lpass_ag_noc_gemnoc, 2028 }; 2029 2030 static const struct qcom_icc_desc x1e80100_lpass_ag_noc = { 2031 .nodes = lpass_ag_noc_nodes, 2032 .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), 2033 .bcms = lpass_ag_noc_bcms, 2034 .num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms), 2035 }; 2036 2037 static struct qcom_icc_bcm * const lpass_lpiaon_noc_bcms[] = { 2038 &bcm_lp0, 2039 }; 2040 2041 static struct qcom_icc_node * const lpass_lpiaon_noc_nodes[] = { 2042 [MASTER_LPASS_LPINOC] = &qnm_lpass_lpinoc, 2043 [SLAVE_LPIAON_NOC_LPASS_AG_NOC] = &qns_lpass_aggnoc, 2044 }; 2045 2046 static const struct qcom_icc_desc x1e80100_lpass_lpiaon_noc = { 2047 .nodes = lpass_lpiaon_noc_nodes, 2048 .num_nodes = ARRAY_SIZE(lpass_lpiaon_noc_nodes), 2049 .bcms = lpass_lpiaon_noc_bcms, 2050 .num_bcms = ARRAY_SIZE(lpass_lpiaon_noc_bcms), 2051 }; 2052 2053 static struct qcom_icc_bcm * const lpass_lpicx_noc_bcms[] = { 2054 }; 2055 2056 static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] = { 2057 [MASTER_LPASS_PROC] = &qxm_lpinoc_dsp_axim, 2058 [SLAVE_LPICX_NOC_LPIAON_NOC] = &qns_lpi_aon_noc, 2059 }; 2060 2061 static const struct qcom_icc_desc x1e80100_lpass_lpicx_noc = { 2062 .nodes = lpass_lpicx_noc_nodes, 2063 .num_nodes = ARRAY_SIZE(lpass_lpicx_noc_nodes), 2064 .bcms = lpass_lpicx_noc_bcms, 2065 .num_bcms = ARRAY_SIZE(lpass_lpicx_noc_bcms), 2066 }; 2067 2068 static struct qcom_icc_bcm * const mc_virt_bcms[] = { 2069 &bcm_acv, 2070 &bcm_mc0, 2071 &bcm_acv_disp, 2072 &bcm_mc0_disp, 2073 &bcm_acv_pcie, 2074 &bcm_mc0_pcie, 2075 }; 2076 2077 static struct qcom_icc_node * const mc_virt_nodes[] = { 2078 [MASTER_LLCC] = &llcc_mc, 2079 [SLAVE_EBI1] = &ebi, 2080 [MASTER_LLCC_DISP] = &llcc_mc_disp, 2081 [SLAVE_EBI1_DISP] = &ebi_disp, 2082 [MASTER_LLCC_PCIE] = &llcc_mc_pcie, 2083 [SLAVE_EBI1_PCIE] = &ebi_pcie, 2084 }; 2085 2086 static const struct qcom_icc_desc x1e80100_mc_virt = { 2087 .nodes = mc_virt_nodes, 2088 .num_nodes = ARRAY_SIZE(mc_virt_nodes), 2089 .bcms = mc_virt_bcms, 2090 .num_bcms = ARRAY_SIZE(mc_virt_bcms), 2091 }; 2092 2093 static struct qcom_icc_bcm * const mmss_noc_bcms[] = { 2094 &bcm_mm0, 2095 &bcm_mm1, 2096 &bcm_mm0_disp, 2097 &bcm_mm1_disp, 2098 }; 2099 2100 static struct qcom_icc_node * const mmss_noc_nodes[] = { 2101 [MASTER_AV1_ENC] = &qnm_av1_enc, 2102 [MASTER_CAMNOC_HF] = &qnm_camnoc_hf, 2103 [MASTER_CAMNOC_ICP] = &qnm_camnoc_icp, 2104 [MASTER_CAMNOC_SF] = &qnm_camnoc_sf, 2105 [MASTER_EVA] = &qnm_eva, 2106 [MASTER_MDP] = &qnm_mdp, 2107 [MASTER_VIDEO] = &qnm_video, 2108 [MASTER_VIDEO_CV_PROC] = &qnm_video_cv_cpu, 2109 [MASTER_VIDEO_V_PROC] = &qnm_video_v_cpu, 2110 [MASTER_CNOC_MNOC_CFG] = &qsm_mnoc_cfg, 2111 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, 2112 [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf, 2113 [SLAVE_SERVICE_MNOC] = &srvc_mnoc, 2114 [MASTER_MDP_DISP] = &qnm_mdp_disp, 2115 [SLAVE_MNOC_HF_MEM_NOC_DISP] = &qns_mem_noc_hf_disp, 2116 }; 2117 2118 static const struct qcom_icc_desc x1e80100_mmss_noc = { 2119 .nodes = mmss_noc_nodes, 2120 .num_nodes = ARRAY_SIZE(mmss_noc_nodes), 2121 .bcms = mmss_noc_bcms, 2122 .num_bcms = ARRAY_SIZE(mmss_noc_bcms), 2123 }; 2124 2125 static struct qcom_icc_bcm * const nsp_noc_bcms[] = { 2126 &bcm_co0, 2127 }; 2128 2129 static struct qcom_icc_node * const nsp_noc_nodes[] = { 2130 [MASTER_CDSP_PROC] = &qxm_nsp, 2131 [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc, 2132 }; 2133 2134 static const struct qcom_icc_desc x1e80100_nsp_noc = { 2135 .nodes = nsp_noc_nodes, 2136 .num_nodes = ARRAY_SIZE(nsp_noc_nodes), 2137 .bcms = nsp_noc_bcms, 2138 .num_bcms = ARRAY_SIZE(nsp_noc_bcms), 2139 }; 2140 2141 static struct qcom_icc_bcm * const pcie_center_anoc_bcms[] = { 2142 &bcm_pc0, 2143 &bcm_pc0_pcie, 2144 }; 2145 2146 static struct qcom_icc_node * const pcie_center_anoc_nodes[] = { 2147 [MASTER_PCIE_NORTH] = &qnm_pcie_north_gem_noc, 2148 [MASTER_PCIE_SOUTH] = &qnm_pcie_south_gem_noc, 2149 [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc, 2150 [MASTER_PCIE_NORTH_PCIE] = &qnm_pcie_north_gem_noc_pcie, 2151 [MASTER_PCIE_SOUTH_PCIE] = &qnm_pcie_south_gem_noc_pcie, 2152 [SLAVE_ANOC_PCIE_GEM_NOC_PCIE] = &qns_pcie_mem_noc_pcie, 2153 }; 2154 2155 static const struct qcom_icc_desc x1e80100_pcie_center_anoc = { 2156 .nodes = pcie_center_anoc_nodes, 2157 .num_nodes = ARRAY_SIZE(pcie_center_anoc_nodes), 2158 .bcms = pcie_center_anoc_bcms, 2159 .num_bcms = ARRAY_SIZE(pcie_center_anoc_bcms), 2160 }; 2161 2162 static struct qcom_icc_bcm * const pcie_north_anoc_bcms[] = { 2163 }; 2164 2165 static struct qcom_icc_node * const pcie_north_anoc_nodes[] = { 2166 [MASTER_PCIE_3] = &xm_pcie_3, 2167 [MASTER_PCIE_4] = &xm_pcie_4, 2168 [MASTER_PCIE_5] = &xm_pcie_5, 2169 [SLAVE_PCIE_NORTH] = &qns_pcie_north_gem_noc, 2170 [MASTER_PCIE_3_PCIE] = &xm_pcie_3_pcie, 2171 [MASTER_PCIE_4_PCIE] = &xm_pcie_4_pcie, 2172 [MASTER_PCIE_5_PCIE] = &xm_pcie_5_pcie, 2173 [SLAVE_PCIE_NORTH_PCIE] = &qns_pcie_north_gem_noc_pcie, 2174 }; 2175 2176 static const struct qcom_icc_desc x1e80100_pcie_north_anoc = { 2177 .nodes = pcie_north_anoc_nodes, 2178 .num_nodes = ARRAY_SIZE(pcie_north_anoc_nodes), 2179 .bcms = pcie_north_anoc_bcms, 2180 .num_bcms = ARRAY_SIZE(pcie_north_anoc_bcms), 2181 }; 2182 2183 static struct qcom_icc_bcm *pcie_south_anoc_bcms[] = { 2184 }; 2185 2186 static struct qcom_icc_node * const pcie_south_anoc_nodes[] = { 2187 [MASTER_PCIE_0] = &xm_pcie_0, 2188 [MASTER_PCIE_1] = &xm_pcie_1, 2189 [MASTER_PCIE_2] = &xm_pcie_2, 2190 [MASTER_PCIE_6A] = &xm_pcie_6a, 2191 [MASTER_PCIE_6B] = &xm_pcie_6b, 2192 [SLAVE_PCIE_SOUTH] = &qns_pcie_south_gem_noc, 2193 [MASTER_PCIE_0_PCIE] = &xm_pcie_0_pcie, 2194 [MASTER_PCIE_1_PCIE] = &xm_pcie_1_pcie, 2195 [MASTER_PCIE_2_PCIE] = &xm_pcie_2_pcie, 2196 [MASTER_PCIE_6A_PCIE] = &xm_pcie_6a_pcie, 2197 [MASTER_PCIE_6B_PCIE] = &xm_pcie_6b_pcie, 2198 [SLAVE_PCIE_SOUTH_PCIE] = &qns_pcie_south_gem_noc_pcie, 2199 }; 2200 2201 static const struct qcom_icc_desc x1e80100_pcie_south_anoc = { 2202 .nodes = pcie_south_anoc_nodes, 2203 .num_nodes = ARRAY_SIZE(pcie_south_anoc_nodes), 2204 .bcms = pcie_south_anoc_bcms, 2205 .num_bcms = ARRAY_SIZE(pcie_south_anoc_bcms), 2206 }; 2207 2208 static struct qcom_icc_bcm *system_noc_bcms[] = { 2209 &bcm_sn0, 2210 &bcm_sn2, 2211 &bcm_sn3, 2212 &bcm_sn4, 2213 }; 2214 2215 static struct qcom_icc_node * const system_noc_nodes[] = { 2216 [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc, 2217 [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc, 2218 [MASTER_GIC1] = &qnm_gic, 2219 [MASTER_USB_NOC_SNOC] = &qnm_usb_anoc, 2220 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, 2221 }; 2222 2223 static const struct qcom_icc_desc x1e80100_system_noc = { 2224 .nodes = system_noc_nodes, 2225 .num_nodes = ARRAY_SIZE(system_noc_nodes), 2226 .bcms = system_noc_bcms, 2227 .num_bcms = ARRAY_SIZE(system_noc_bcms), 2228 }; 2229 2230 static struct qcom_icc_bcm * const usb_center_anoc_bcms[] = { 2231 }; 2232 2233 static struct qcom_icc_node * const usb_center_anoc_nodes[] = { 2234 [MASTER_AGGRE_USB_NORTH] = &qnm_aggre_usb_north_snoc, 2235 [MASTER_AGGRE_USB_SOUTH] = &qnm_aggre_usb_south_snoc, 2236 [SLAVE_USB_NOC_SNOC] = &qns_aggre_usb_snoc, 2237 }; 2238 2239 static const struct qcom_icc_desc x1e80100_usb_center_anoc = { 2240 .nodes = usb_center_anoc_nodes, 2241 .num_nodes = ARRAY_SIZE(usb_center_anoc_nodes), 2242 .bcms = usb_center_anoc_bcms, 2243 .num_bcms = ARRAY_SIZE(usb_center_anoc_bcms), 2244 }; 2245 2246 static struct qcom_icc_bcm *usb_north_anoc_bcms[] = { 2247 }; 2248 2249 static struct qcom_icc_node * const usb_north_anoc_nodes[] = { 2250 [MASTER_USB2] = &xm_usb2_0, 2251 [MASTER_USB3_MP] = &xm_usb3_mp, 2252 [SLAVE_AGGRE_USB_NORTH] = &qns_aggre_usb_north_snoc, 2253 }; 2254 2255 static const struct qcom_icc_desc x1e80100_usb_north_anoc = { 2256 .nodes = usb_north_anoc_nodes, 2257 .num_nodes = ARRAY_SIZE(usb_north_anoc_nodes), 2258 .bcms = usb_north_anoc_bcms, 2259 .num_bcms = ARRAY_SIZE(usb_north_anoc_bcms), 2260 }; 2261 2262 static struct qcom_icc_bcm *usb_south_anoc_bcms[] = { 2263 }; 2264 2265 static struct qcom_icc_node * const usb_south_anoc_nodes[] = { 2266 [MASTER_USB3_0] = &xm_usb3_0, 2267 [MASTER_USB3_1] = &xm_usb3_1, 2268 [MASTER_USB3_2] = &xm_usb3_2, 2269 [MASTER_USB4_0] = &xm_usb4_0, 2270 [MASTER_USB4_1] = &xm_usb4_1, 2271 [MASTER_USB4_2] = &xm_usb4_2, 2272 [SLAVE_AGGRE_USB_SOUTH] = &qns_aggre_usb_south_snoc, 2273 }; 2274 2275 static const struct qcom_icc_desc x1e80100_usb_south_anoc = { 2276 .nodes = usb_south_anoc_nodes, 2277 .num_nodes = ARRAY_SIZE(usb_south_anoc_nodes), 2278 .bcms = usb_south_anoc_bcms, 2279 .num_bcms = ARRAY_SIZE(usb_south_anoc_bcms), 2280 }; 2281 2282 static const struct of_device_id qnoc_of_match[] = { 2283 { .compatible = "qcom,x1e80100-aggre1-noc", .data = &x1e80100_aggre1_noc}, 2284 { .compatible = "qcom,x1e80100-aggre2-noc", .data = &x1e80100_aggre2_noc}, 2285 { .compatible = "qcom,x1e80100-clk-virt", .data = &x1e80100_clk_virt}, 2286 { .compatible = "qcom,x1e80100-cnoc-cfg", .data = &x1e80100_cnoc_cfg}, 2287 { .compatible = "qcom,x1e80100-cnoc-main", .data = &x1e80100_cnoc_main}, 2288 { .compatible = "qcom,x1e80100-gem-noc", .data = &x1e80100_gem_noc}, 2289 { .compatible = "qcom,x1e80100-lpass-ag-noc", .data = &x1e80100_lpass_ag_noc}, 2290 { .compatible = "qcom,x1e80100-lpass-lpiaon-noc", .data = &x1e80100_lpass_lpiaon_noc}, 2291 { .compatible = "qcom,x1e80100-lpass-lpicx-noc", .data = &x1e80100_lpass_lpicx_noc}, 2292 { .compatible = "qcom,x1e80100-mc-virt", .data = &x1e80100_mc_virt}, 2293 { .compatible = "qcom,x1e80100-mmss-noc", .data = &x1e80100_mmss_noc}, 2294 { .compatible = "qcom,x1e80100-nsp-noc", .data = &x1e80100_nsp_noc}, 2295 { .compatible = "qcom,x1e80100-pcie-center-anoc", .data = &x1e80100_pcie_center_anoc}, 2296 { .compatible = "qcom,x1e80100-pcie-north-anoc", .data = &x1e80100_pcie_north_anoc}, 2297 { .compatible = "qcom,x1e80100-pcie-south-anoc", .data = &x1e80100_pcie_south_anoc}, 2298 { .compatible = "qcom,x1e80100-system-noc", .data = &x1e80100_system_noc}, 2299 { .compatible = "qcom,x1e80100-usb-center-anoc", .data = &x1e80100_usb_center_anoc}, 2300 { .compatible = "qcom,x1e80100-usb-north-anoc", .data = &x1e80100_usb_north_anoc}, 2301 { .compatible = "qcom,x1e80100-usb-south-anoc", .data = &x1e80100_usb_south_anoc}, 2302 { } 2303 }; 2304 MODULE_DEVICE_TABLE(of, qnoc_of_match); 2305 2306 static struct platform_driver qnoc_driver = { 2307 .probe = qcom_icc_rpmh_probe, 2308 .remove_new = qcom_icc_rpmh_remove, 2309 .driver = { 2310 .name = "qnoc-x1e80100", 2311 .of_match_table = qnoc_of_match, 2312 .sync_state = icc_sync_state, 2313 }, 2314 }; 2315 2316 static int __init qnoc_driver_init(void) 2317 { 2318 return platform_driver_register(&qnoc_driver); 2319 } 2320 core_initcall(qnoc_driver_init); 2321 2322 static void __exit qnoc_driver_exit(void) 2323 { 2324 platform_driver_unregister(&qnoc_driver); 2325 } 2326 module_exit(qnoc_driver_exit); 2327 2328 MODULE_DESCRIPTION("x1e80100 NoC driver"); 2329 MODULE_LICENSE("GPL"); 2330