1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2023, Linaro Limited 5 * 6 */ 7 8 #include <linux/device.h> 9 #include <linux/interconnect.h> 10 #include <linux/interconnect-provider.h> 11 #include <linux/module.h> 12 #include <linux/of_platform.h> 13 #include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h> 14 15 #include "bcm-voter.h" 16 #include "icc-common.h" 17 #include "icc-rpmh.h" 18 19 static struct qcom_icc_node qhm_qspi; 20 static struct qcom_icc_node qhm_qup1; 21 static struct qcom_icc_node xm_sdc4; 22 static struct qcom_icc_node xm_ufs_mem; 23 static struct qcom_icc_node qhm_qup0; 24 static struct qcom_icc_node qhm_qup2; 25 static struct qcom_icc_node qxm_crypto; 26 static struct qcom_icc_node qxm_sp; 27 static struct qcom_icc_node xm_qdss_etr_0; 28 static struct qcom_icc_node xm_qdss_etr_1; 29 static struct qcom_icc_node xm_sdc2; 30 static struct qcom_icc_node qup0_core_master; 31 static struct qcom_icc_node qup1_core_master; 32 static struct qcom_icc_node qup2_core_master; 33 static struct qcom_icc_node qsm_cfg; 34 static struct qcom_icc_node qnm_gemnoc_cnoc; 35 static struct qcom_icc_node qnm_gemnoc_pcie; 36 static struct qcom_icc_node alm_gpu_tcu; 37 static struct qcom_icc_node alm_pcie_tcu; 38 static struct qcom_icc_node alm_sys_tcu; 39 static struct qcom_icc_node chm_apps; 40 static struct qcom_icc_node qnm_gpu; 41 static struct qcom_icc_node qnm_lpass; 42 static struct qcom_icc_node qnm_mnoc_hf; 43 static struct qcom_icc_node qnm_mnoc_sf; 44 static struct qcom_icc_node qnm_nsp_noc; 45 static struct qcom_icc_node qnm_pcie; 46 static struct qcom_icc_node qnm_snoc_sf; 47 static struct qcom_icc_node xm_gic; 48 static struct qcom_icc_node qnm_lpiaon_noc; 49 static struct qcom_icc_node qnm_lpass_lpinoc; 50 static struct qcom_icc_node qxm_lpinoc_dsp_axim; 51 static struct qcom_icc_node llcc_mc; 52 static struct qcom_icc_node qnm_av1_enc; 53 static struct qcom_icc_node qnm_camnoc_hf; 54 static struct qcom_icc_node qnm_camnoc_icp; 55 static struct qcom_icc_node qnm_camnoc_sf; 56 static struct qcom_icc_node qnm_eva; 57 static struct qcom_icc_node qnm_mdp; 58 static struct qcom_icc_node qnm_video; 59 static struct qcom_icc_node qnm_video_cv_cpu; 60 static struct qcom_icc_node qnm_video_v_cpu; 61 static struct qcom_icc_node qsm_mnoc_cfg; 62 static struct qcom_icc_node qxm_nsp; 63 static struct qcom_icc_node qnm_pcie_north_gem_noc; 64 static struct qcom_icc_node qnm_pcie_south_gem_noc; 65 static struct qcom_icc_node xm_pcie_3; 66 static struct qcom_icc_node xm_pcie_4; 67 static struct qcom_icc_node xm_pcie_5; 68 static struct qcom_icc_node xm_pcie_0; 69 static struct qcom_icc_node xm_pcie_1; 70 static struct qcom_icc_node xm_pcie_2; 71 static struct qcom_icc_node xm_pcie_6a; 72 static struct qcom_icc_node xm_pcie_6b; 73 static struct qcom_icc_node qnm_aggre1_noc; 74 static struct qcom_icc_node qnm_aggre2_noc; 75 static struct qcom_icc_node qnm_gic; 76 static struct qcom_icc_node qnm_usb_anoc; 77 static struct qcom_icc_node qnm_aggre_usb_north_snoc; 78 static struct qcom_icc_node qnm_aggre_usb_south_snoc; 79 static struct qcom_icc_node xm_usb2_0; 80 static struct qcom_icc_node xm_usb3_mp; 81 static struct qcom_icc_node xm_usb3_0; 82 static struct qcom_icc_node xm_usb3_1; 83 static struct qcom_icc_node xm_usb3_2; 84 static struct qcom_icc_node xm_usb4_0; 85 static struct qcom_icc_node xm_usb4_1; 86 static struct qcom_icc_node xm_usb4_2; 87 static struct qcom_icc_node qns_a1noc_snoc; 88 static struct qcom_icc_node qns_a2noc_snoc; 89 static struct qcom_icc_node qup0_core_slave; 90 static struct qcom_icc_node qup1_core_slave; 91 static struct qcom_icc_node qup2_core_slave; 92 static struct qcom_icc_node qhs_ahb2phy0; 93 static struct qcom_icc_node qhs_ahb2phy1; 94 static struct qcom_icc_node qhs_ahb2phy2; 95 static struct qcom_icc_node qhs_av1_enc_cfg; 96 static struct qcom_icc_node qhs_camera_cfg; 97 static struct qcom_icc_node qhs_clk_ctl; 98 static struct qcom_icc_node qhs_crypto0_cfg; 99 static struct qcom_icc_node qhs_display_cfg; 100 static struct qcom_icc_node qhs_gpuss_cfg; 101 static struct qcom_icc_node qhs_imem_cfg; 102 static struct qcom_icc_node qhs_ipc_router; 103 static struct qcom_icc_node qhs_pcie0_cfg; 104 static struct qcom_icc_node qhs_pcie1_cfg; 105 static struct qcom_icc_node qhs_pcie2_cfg; 106 static struct qcom_icc_node qhs_pcie3_cfg; 107 static struct qcom_icc_node qhs_pcie4_cfg; 108 static struct qcom_icc_node qhs_pcie5_cfg; 109 static struct qcom_icc_node qhs_pcie6a_cfg; 110 static struct qcom_icc_node qhs_pcie6b_cfg; 111 static struct qcom_icc_node qhs_pcie_rsc_cfg; 112 static struct qcom_icc_node qhs_pdm; 113 static struct qcom_icc_node qhs_prng; 114 static struct qcom_icc_node qhs_qdss_cfg; 115 static struct qcom_icc_node qhs_qspi; 116 static struct qcom_icc_node qhs_qup0; 117 static struct qcom_icc_node qhs_qup1; 118 static struct qcom_icc_node qhs_qup2; 119 static struct qcom_icc_node qhs_sdc2; 120 static struct qcom_icc_node qhs_sdc4; 121 static struct qcom_icc_node qhs_smmuv3_cfg; 122 static struct qcom_icc_node qhs_tcsr; 123 static struct qcom_icc_node qhs_tlmm; 124 static struct qcom_icc_node qhs_ufs_mem_cfg; 125 static struct qcom_icc_node qhs_usb2_0_cfg; 126 static struct qcom_icc_node qhs_usb3_0_cfg; 127 static struct qcom_icc_node qhs_usb3_1_cfg; 128 static struct qcom_icc_node qhs_usb3_2_cfg; 129 static struct qcom_icc_node qhs_usb3_mp_cfg; 130 static struct qcom_icc_node qhs_usb4_0_cfg; 131 static struct qcom_icc_node qhs_usb4_1_cfg; 132 static struct qcom_icc_node qhs_usb4_2_cfg; 133 static struct qcom_icc_node qhs_venus_cfg; 134 static struct qcom_icc_node qss_lpass_qtb_cfg; 135 static struct qcom_icc_node qss_mnoc_cfg; 136 static struct qcom_icc_node qss_nsp_qtb_cfg; 137 static struct qcom_icc_node xs_qdss_stm; 138 static struct qcom_icc_node xs_sys_tcu_cfg; 139 static struct qcom_icc_node qhs_aoss; 140 static struct qcom_icc_node qhs_tme_cfg; 141 static struct qcom_icc_node qns_apss; 142 static struct qcom_icc_node qss_cfg; 143 static struct qcom_icc_node qxs_boot_imem; 144 static struct qcom_icc_node qxs_imem; 145 static struct qcom_icc_node xs_pcie_0; 146 static struct qcom_icc_node xs_pcie_1; 147 static struct qcom_icc_node xs_pcie_2; 148 static struct qcom_icc_node xs_pcie_3; 149 static struct qcom_icc_node xs_pcie_4; 150 static struct qcom_icc_node xs_pcie_5; 151 static struct qcom_icc_node xs_pcie_6a; 152 static struct qcom_icc_node xs_pcie_6b; 153 static struct qcom_icc_node qns_gem_noc_cnoc; 154 static struct qcom_icc_node qns_llcc; 155 static struct qcom_icc_node qns_pcie; 156 static struct qcom_icc_node qns_lpass_ag_noc_gemnoc; 157 static struct qcom_icc_node qns_lpass_aggnoc; 158 static struct qcom_icc_node qns_lpi_aon_noc; 159 static struct qcom_icc_node ebi; 160 static struct qcom_icc_node qns_mem_noc_hf; 161 static struct qcom_icc_node qns_mem_noc_sf; 162 static struct qcom_icc_node srvc_mnoc; 163 static struct qcom_icc_node qns_nsp_gemnoc; 164 static struct qcom_icc_node qns_pcie_mem_noc; 165 static struct qcom_icc_node qns_pcie_north_gem_noc; 166 static struct qcom_icc_node qns_pcie_south_gem_noc; 167 static struct qcom_icc_node qns_gemnoc_sf; 168 static struct qcom_icc_node qns_aggre_usb_snoc; 169 static struct qcom_icc_node qns_aggre_usb_north_snoc; 170 static struct qcom_icc_node qns_aggre_usb_south_snoc; 171 172 static struct qcom_icc_node qhm_qspi = { 173 .name = "qhm_qspi", 174 .channels = 1, 175 .buswidth = 4, 176 .qosbox = &(const struct qcom_icc_qosbox) { 177 .num_ports = 1, 178 .port_offsets = { 0xb000 }, 179 .prio = 2, 180 .urg_fwd = 0, 181 .prio_fwd_disable = 1, 182 }, 183 .num_links = 1, 184 .link_nodes = { &qns_a1noc_snoc }, 185 }; 186 187 static struct qcom_icc_node qhm_qup1 = { 188 .name = "qhm_qup1", 189 .channels = 1, 190 .buswidth = 4, 191 .qosbox = &(const struct qcom_icc_qosbox) { 192 .num_ports = 1, 193 .port_offsets = { 0xc000 }, 194 .prio = 2, 195 .urg_fwd = 0, 196 .prio_fwd_disable = 1, 197 }, 198 .num_links = 1, 199 .link_nodes = { &qns_a1noc_snoc }, 200 }; 201 202 static struct qcom_icc_node xm_sdc4 = { 203 .name = "xm_sdc4", 204 .channels = 1, 205 .buswidth = 8, 206 .qosbox = &(const struct qcom_icc_qosbox) { 207 .num_ports = 1, 208 .port_offsets = { 0xd000 }, 209 .prio = 2, 210 .urg_fwd = 0, 211 .prio_fwd_disable = 1, 212 }, 213 .num_links = 1, 214 .link_nodes = { &qns_a1noc_snoc }, 215 }; 216 217 static struct qcom_icc_node xm_ufs_mem = { 218 .name = "xm_ufs_mem", 219 .channels = 1, 220 .buswidth = 16, 221 .qosbox = &(const struct qcom_icc_qosbox) { 222 .num_ports = 1, 223 .port_offsets = { 0xe000 }, 224 .prio = 2, 225 .urg_fwd = 0, 226 .prio_fwd_disable = 1, 227 }, 228 .num_links = 1, 229 .link_nodes = { &qns_a1noc_snoc }, 230 }; 231 232 static struct qcom_icc_node qhm_qup0 = { 233 .name = "qhm_qup0", 234 .channels = 1, 235 .buswidth = 4, 236 .qosbox = &(const struct qcom_icc_qosbox) { 237 .num_ports = 1, 238 .port_offsets = { 0x16000 }, 239 .prio = 2, 240 .urg_fwd = 0, 241 .prio_fwd_disable = 1, 242 }, 243 .num_links = 1, 244 .link_nodes = { &qns_a2noc_snoc }, 245 }; 246 247 static struct qcom_icc_node qhm_qup2 = { 248 .name = "qhm_qup2", 249 .channels = 1, 250 .buswidth = 4, 251 .qosbox = &(const struct qcom_icc_qosbox) { 252 .num_ports = 1, 253 .port_offsets = { 0x11000 }, 254 .prio = 2, 255 .urg_fwd = 0, 256 .prio_fwd_disable = 1, 257 }, 258 .num_links = 1, 259 .link_nodes = { &qns_a2noc_snoc }, 260 }; 261 262 static struct qcom_icc_node qxm_crypto = { 263 .name = "qxm_crypto", 264 .channels = 1, 265 .buswidth = 8, 266 .qosbox = &(const struct qcom_icc_qosbox) { 267 .num_ports = 1, 268 .port_offsets = { 0x12000 }, 269 .prio = 2, 270 .urg_fwd = 0, 271 .prio_fwd_disable = 1, 272 }, 273 .num_links = 1, 274 .link_nodes = { &qns_a2noc_snoc }, 275 }; 276 277 static struct qcom_icc_node qxm_sp = { 278 .name = "qxm_sp", 279 .channels = 1, 280 .buswidth = 8, 281 .num_links = 1, 282 .link_nodes = { &qns_a2noc_snoc }, 283 }; 284 285 static struct qcom_icc_node xm_qdss_etr_0 = { 286 .name = "xm_qdss_etr_0", 287 .channels = 1, 288 .buswidth = 8, 289 .qosbox = &(const struct qcom_icc_qosbox) { 290 .num_ports = 1, 291 .port_offsets = { 0x13000 }, 292 .prio = 2, 293 .urg_fwd = 0, 294 .prio_fwd_disable = 1, 295 }, 296 .num_links = 1, 297 .link_nodes = { &qns_a2noc_snoc }, 298 }; 299 300 static struct qcom_icc_node xm_qdss_etr_1 = { 301 .name = "xm_qdss_etr_1", 302 .channels = 1, 303 .buswidth = 8, 304 .qosbox = &(const struct qcom_icc_qosbox) { 305 .num_ports = 1, 306 .port_offsets = { 0x14000 }, 307 .prio = 2, 308 .urg_fwd = 0, 309 .prio_fwd_disable = 1, 310 }, 311 .num_links = 1, 312 .link_nodes = { &qns_a2noc_snoc }, 313 }; 314 315 static struct qcom_icc_node xm_sdc2 = { 316 .name = "xm_sdc2", 317 .channels = 1, 318 .buswidth = 8, 319 .qosbox = &(const struct qcom_icc_qosbox) { 320 .num_ports = 1, 321 .port_offsets = { 0x15000 }, 322 .prio = 2, 323 .urg_fwd = 0, 324 .prio_fwd_disable = 1, 325 }, 326 .num_links = 1, 327 .link_nodes = { &qns_a2noc_snoc }, 328 }; 329 330 static struct qcom_icc_node qup0_core_master = { 331 .name = "qup0_core_master", 332 .channels = 1, 333 .buswidth = 4, 334 .num_links = 1, 335 .link_nodes = { &qup0_core_slave }, 336 }; 337 338 static struct qcom_icc_node qup1_core_master = { 339 .name = "qup1_core_master", 340 .channels = 1, 341 .buswidth = 4, 342 .num_links = 1, 343 .link_nodes = { &qup1_core_slave }, 344 }; 345 346 static struct qcom_icc_node qup2_core_master = { 347 .name = "qup2_core_master", 348 .channels = 1, 349 .buswidth = 4, 350 .num_links = 1, 351 .link_nodes = { &qup2_core_slave }, 352 }; 353 354 static struct qcom_icc_node qsm_cfg = { 355 .name = "qsm_cfg", 356 .channels = 1, 357 .buswidth = 4, 358 .num_links = 47, 359 .link_nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1, 360 &qhs_ahb2phy2, &qhs_av1_enc_cfg, 361 &qhs_camera_cfg, &qhs_clk_ctl, 362 &qhs_crypto0_cfg, &qhs_display_cfg, 363 &qhs_gpuss_cfg, &qhs_imem_cfg, 364 &qhs_ipc_router, &qhs_pcie0_cfg, 365 &qhs_pcie1_cfg, &qhs_pcie2_cfg, 366 &qhs_pcie3_cfg, &qhs_pcie4_cfg, 367 &qhs_pcie5_cfg, &qhs_pcie6a_cfg, 368 &qhs_pcie6b_cfg, &qhs_pcie_rsc_cfg, 369 &qhs_pdm, &qhs_prng, 370 &qhs_qdss_cfg, &qhs_qspi, 371 &qhs_qup0, &qhs_qup1, 372 &qhs_qup2, &qhs_sdc2, 373 &qhs_sdc4, &qhs_smmuv3_cfg, 374 &qhs_tcsr, &qhs_tlmm, 375 &qhs_ufs_mem_cfg, &qhs_usb2_0_cfg, 376 &qhs_usb3_0_cfg, &qhs_usb3_1_cfg, 377 &qhs_usb3_2_cfg, &qhs_usb3_mp_cfg, 378 &qhs_usb4_0_cfg, &qhs_usb4_1_cfg, 379 &qhs_usb4_2_cfg, &qhs_venus_cfg, 380 &qss_lpass_qtb_cfg, &qss_mnoc_cfg, 381 &qss_nsp_qtb_cfg, &xs_qdss_stm, 382 &xs_sys_tcu_cfg }, 383 }; 384 385 static struct qcom_icc_node qnm_gemnoc_cnoc = { 386 .name = "qnm_gemnoc_cnoc", 387 .channels = 1, 388 .buswidth = 16, 389 .num_links = 6, 390 .link_nodes = { &qhs_aoss, &qhs_tme_cfg, 391 &qns_apss, &qss_cfg, 392 &qxs_boot_imem, &qxs_imem }, 393 }; 394 395 static struct qcom_icc_node qnm_gemnoc_pcie = { 396 .name = "qnm_gemnoc_pcie", 397 .channels = 1, 398 .buswidth = 32, 399 .num_links = 8, 400 .link_nodes = { &xs_pcie_0, &xs_pcie_1, 401 &xs_pcie_2, &xs_pcie_3, 402 &xs_pcie_4, &xs_pcie_5, 403 &xs_pcie_6a, &xs_pcie_6b }, 404 }; 405 406 static struct qcom_icc_node alm_gpu_tcu = { 407 .name = "alm_gpu_tcu", 408 .channels = 1, 409 .buswidth = 8, 410 .qosbox = &(const struct qcom_icc_qosbox) { 411 .num_ports = 1, 412 .port_offsets = { 0x271000 }, 413 .prio = 1, 414 .urg_fwd = 0, 415 .prio_fwd_disable = 1, 416 }, 417 .num_links = 2, 418 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 419 }; 420 421 static struct qcom_icc_node alm_pcie_tcu = { 422 .name = "alm_pcie_tcu", 423 .channels = 1, 424 .buswidth = 8, 425 .qosbox = &(const struct qcom_icc_qosbox) { 426 .num_ports = 1, 427 .port_offsets = { 0x27d000 }, 428 .prio = 3, 429 .urg_fwd = 0, 430 .prio_fwd_disable = 1, 431 }, 432 .num_links = 2, 433 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 434 }; 435 436 static struct qcom_icc_node alm_sys_tcu = { 437 .name = "alm_sys_tcu", 438 .channels = 1, 439 .buswidth = 8, 440 .qosbox = &(const struct qcom_icc_qosbox) { 441 .num_ports = 1, 442 .port_offsets = { 0x273000 }, 443 .prio = 6, 444 .urg_fwd = 0, 445 .prio_fwd_disable = 1, 446 }, 447 .num_links = 2, 448 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 449 }; 450 451 static struct qcom_icc_node chm_apps = { 452 .name = "chm_apps", 453 .channels = 6, 454 .buswidth = 32, 455 .num_links = 3, 456 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, 457 &qns_pcie }, 458 }; 459 460 static struct qcom_icc_node qnm_gpu = { 461 .name = "qnm_gpu", 462 .channels = 4, 463 .buswidth = 32, 464 .qosbox = &(const struct qcom_icc_qosbox) { 465 .num_ports = 4, 466 .port_offsets = { 0x51000, 0x58000, 0xd1000, 0xd8000 }, 467 .prio = 0, 468 .urg_fwd = 0, 469 .prio_fwd_disable = 1, 470 }, 471 .num_links = 2, 472 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 473 }; 474 475 static struct qcom_icc_node qnm_lpass = { 476 .name = "qnm_lpass", 477 .channels = 1, 478 .buswidth = 16, 479 .qosbox = &(const struct qcom_icc_qosbox) { 480 .num_ports = 1, 481 .port_offsets = { 0x275000 }, 482 .prio = 0, 483 .urg_fwd = 1, 484 .prio_fwd_disable = 0, 485 }, 486 .num_links = 3, 487 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, 488 &qns_pcie }, 489 }; 490 491 static struct qcom_icc_node qnm_mnoc_hf = { 492 .name = "qnm_mnoc_hf", 493 .channels = 2, 494 .buswidth = 32, 495 .qosbox = &(const struct qcom_icc_qosbox) { 496 .num_ports = 2, 497 .port_offsets = { 0x53000, 0xd3000 }, 498 .prio = 0, 499 .urg_fwd = 1, 500 .prio_fwd_disable = 0, 501 }, 502 .num_links = 2, 503 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 504 }; 505 506 static struct qcom_icc_node qnm_mnoc_sf = { 507 .name = "qnm_mnoc_sf", 508 .channels = 2, 509 .buswidth = 32, 510 .qosbox = &(const struct qcom_icc_qosbox) { 511 .num_ports = 2, 512 .port_offsets = { 0x55000, 0xd5000 }, 513 .prio = 0, 514 .urg_fwd = 1, 515 .prio_fwd_disable = 0, 516 }, 517 .num_links = 2, 518 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 519 }; 520 521 static struct qcom_icc_node qnm_nsp_noc = { 522 .name = "qnm_nsp_noc", 523 .channels = 2, 524 .buswidth = 32, 525 .qosbox = &(const struct qcom_icc_qosbox) { 526 .num_ports = 2, 527 .port_offsets = { 0x57000, 0xd7000 }, 528 .prio = 0, 529 .urg_fwd = 0, 530 .prio_fwd_disable = 1, 531 }, 532 .num_links = 3, 533 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, 534 &qns_pcie }, 535 }; 536 537 static struct qcom_icc_node qnm_pcie = { 538 .name = "qnm_pcie", 539 .channels = 1, 540 .buswidth = 64, 541 .qosbox = &(const struct qcom_icc_qosbox) { 542 .num_ports = 1, 543 .port_offsets = { 0x277000 }, 544 .prio = 0, 545 .urg_fwd = 1, 546 .prio_fwd_disable = 0, 547 }, 548 .num_links = 2, 549 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 550 }; 551 552 static struct qcom_icc_node qnm_snoc_sf = { 553 .name = "qnm_snoc_sf", 554 .channels = 1, 555 .buswidth = 64, 556 .qosbox = &(const struct qcom_icc_qosbox) { 557 .num_ports = 1, 558 .port_offsets = { 0x27b000 }, 559 .prio = 2, 560 .urg_fwd = 1, 561 .prio_fwd_disable = 0, 562 }, 563 .num_links = 3, 564 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, 565 &qns_pcie }, 566 }; 567 568 static struct qcom_icc_node xm_gic = { 569 .name = "xm_gic", 570 .channels = 1, 571 .buswidth = 8, 572 .qosbox = &(const struct qcom_icc_qosbox) { 573 .num_ports = 1, 574 .port_offsets = { 0x27f000 }, 575 .prio = 2, 576 .urg_fwd = 0, 577 .prio_fwd_disable = 1, 578 }, 579 .num_links = 1, 580 .link_nodes = { &qns_llcc }, 581 }; 582 583 static struct qcom_icc_node qnm_lpiaon_noc = { 584 .name = "qnm_lpiaon_noc", 585 .channels = 1, 586 .buswidth = 16, 587 .num_links = 1, 588 .link_nodes = { &qns_lpass_ag_noc_gemnoc }, 589 }; 590 591 static struct qcom_icc_node qnm_lpass_lpinoc = { 592 .name = "qnm_lpass_lpinoc", 593 .channels = 1, 594 .buswidth = 16, 595 .num_links = 1, 596 .link_nodes = { &qns_lpass_aggnoc }, 597 }; 598 599 static struct qcom_icc_node qxm_lpinoc_dsp_axim = { 600 .name = "qxm_lpinoc_dsp_axim", 601 .channels = 1, 602 .buswidth = 16, 603 .num_links = 1, 604 .link_nodes = { &qns_lpi_aon_noc }, 605 }; 606 607 static struct qcom_icc_node llcc_mc = { 608 .name = "llcc_mc", 609 .channels = 8, 610 .buswidth = 4, 611 .num_links = 1, 612 .link_nodes = { &ebi }, 613 }; 614 615 static struct qcom_icc_node qnm_av1_enc = { 616 .name = "qnm_av1_enc", 617 .channels = 1, 618 .buswidth = 32, 619 .qosbox = &(const struct qcom_icc_qosbox) { 620 .num_ports = 1, 621 .port_offsets = { 0x2f000 }, 622 .prio = 4, 623 .urg_fwd = 0, 624 .prio_fwd_disable = 1, 625 }, 626 .num_links = 1, 627 .link_nodes = { &qns_mem_noc_sf }, 628 }; 629 630 static struct qcom_icc_node qnm_camnoc_hf = { 631 .name = "qnm_camnoc_hf", 632 .channels = 2, 633 .buswidth = 32, 634 .qosbox = &(const struct qcom_icc_qosbox) { 635 .num_ports = 2, 636 .port_offsets = { 0x28000, 0x29000 }, 637 .prio = 0, 638 .urg_fwd = 1, 639 .prio_fwd_disable = 0, 640 }, 641 .num_links = 1, 642 .link_nodes = { &qns_mem_noc_hf }, 643 }; 644 645 static struct qcom_icc_node qnm_camnoc_icp = { 646 .name = "qnm_camnoc_icp", 647 .channels = 1, 648 .buswidth = 8, 649 .qosbox = &(const struct qcom_icc_qosbox) { 650 .num_ports = 1, 651 .port_offsets = { 0x2a000 }, 652 .prio = 4, 653 .urg_fwd = 0, 654 .prio_fwd_disable = 1, 655 }, 656 .num_links = 1, 657 .link_nodes = { &qns_mem_noc_sf }, 658 }; 659 660 static struct qcom_icc_node qnm_camnoc_sf = { 661 .name = "qnm_camnoc_sf", 662 .channels = 2, 663 .buswidth = 32, 664 .qosbox = &(const struct qcom_icc_qosbox) { 665 .num_ports = 2, 666 .port_offsets = { 0x2b000, 0x2c000 }, 667 .prio = 0, 668 .urg_fwd = 1, 669 .prio_fwd_disable = 0, 670 }, 671 .num_links = 1, 672 .link_nodes = { &qns_mem_noc_sf }, 673 }; 674 675 static struct qcom_icc_node qnm_eva = { 676 .name = "qnm_eva", 677 .channels = 1, 678 .buswidth = 32, 679 .qosbox = &(const struct qcom_icc_qosbox) { 680 .num_ports = 1, 681 .port_offsets = { 0x33000 }, 682 .prio = 0, 683 .urg_fwd = 1, 684 .prio_fwd_disable = 0, 685 }, 686 .num_links = 1, 687 .link_nodes = { &qns_mem_noc_sf }, 688 }; 689 690 static struct qcom_icc_node qnm_mdp = { 691 .name = "qnm_mdp", 692 .channels = 2, 693 .buswidth = 32, 694 .qosbox = &(const struct qcom_icc_qosbox) { 695 .num_ports = 2, 696 .port_offsets = { 0x2d000, 0x2e000 }, 697 .prio = 0, 698 .urg_fwd = 1, 699 .prio_fwd_disable = 0, 700 }, 701 .num_links = 1, 702 .link_nodes = { &qns_mem_noc_hf }, 703 }; 704 705 static struct qcom_icc_node qnm_video = { 706 .name = "qnm_video", 707 .channels = 2, 708 .buswidth = 32, 709 .qosbox = &(const struct qcom_icc_qosbox) { 710 .num_ports = 2, 711 .port_offsets = { 0x30000, 0x31000 }, 712 .prio = 0, 713 .urg_fwd = 1, 714 .prio_fwd_disable = 0, 715 }, 716 .num_links = 1, 717 .link_nodes = { &qns_mem_noc_sf }, 718 }; 719 720 static struct qcom_icc_node qnm_video_cv_cpu = { 721 .name = "qnm_video_cv_cpu", 722 .channels = 1, 723 .buswidth = 8, 724 .qosbox = &(const struct qcom_icc_qosbox) { 725 .num_ports = 1, 726 .port_offsets = { 0x32000 }, 727 .prio = 4, 728 .urg_fwd = 0, 729 .prio_fwd_disable = 1, 730 }, 731 .num_links = 1, 732 .link_nodes = { &qns_mem_noc_sf }, 733 }; 734 735 static struct qcom_icc_node qnm_video_v_cpu = { 736 .name = "qnm_video_v_cpu", 737 .channels = 1, 738 .buswidth = 8, 739 .qosbox = &(const struct qcom_icc_qosbox) { 740 .num_ports = 1, 741 .port_offsets = { 0x34000 }, 742 .prio = 4, 743 .urg_fwd = 0, 744 .prio_fwd_disable = 1, 745 }, 746 .num_links = 1, 747 .link_nodes = { &qns_mem_noc_sf }, 748 }; 749 750 static struct qcom_icc_node qsm_mnoc_cfg = { 751 .name = "qsm_mnoc_cfg", 752 .channels = 1, 753 .buswidth = 4, 754 .num_links = 1, 755 .link_nodes = { &srvc_mnoc }, 756 }; 757 758 static struct qcom_icc_node qxm_nsp = { 759 .name = "qxm_nsp", 760 .channels = 2, 761 .buswidth = 32, 762 .num_links = 1, 763 .link_nodes = { &qns_nsp_gemnoc }, 764 }; 765 766 static struct qcom_icc_node qnm_pcie_north_gem_noc = { 767 .name = "qnm_pcie_north_gem_noc", 768 .channels = 1, 769 .buswidth = 64, 770 .num_links = 1, 771 .link_nodes = { &qns_pcie_mem_noc }, 772 }; 773 774 static struct qcom_icc_node qnm_pcie_south_gem_noc = { 775 .name = "qnm_pcie_south_gem_noc", 776 .channels = 1, 777 .buswidth = 64, 778 .num_links = 1, 779 .link_nodes = { &qns_pcie_mem_noc }, 780 }; 781 782 static struct qcom_icc_node xm_pcie_3 = { 783 .name = "xm_pcie_3", 784 .channels = 1, 785 .buswidth = 64, 786 .qosbox = &(const struct qcom_icc_qosbox) { 787 .num_ports = 1, 788 .port_offsets = { 0x7000 }, 789 .prio = 2, 790 .urg_fwd = 0, 791 .prio_fwd_disable = 1, 792 }, 793 .num_links = 1, 794 .link_nodes = { &qns_pcie_north_gem_noc }, 795 }; 796 797 static struct qcom_icc_node xm_pcie_4 = { 798 .name = "xm_pcie_4", 799 .channels = 1, 800 .buswidth = 8, 801 .qosbox = &(const struct qcom_icc_qosbox) { 802 .num_ports = 1, 803 .port_offsets = { 0x8000 }, 804 .prio = 2, 805 .urg_fwd = 0, 806 .prio_fwd_disable = 1, 807 }, 808 .num_links = 1, 809 .link_nodes = { &qns_pcie_north_gem_noc }, 810 }; 811 812 static struct qcom_icc_node xm_pcie_5 = { 813 .name = "xm_pcie_5", 814 .channels = 1, 815 .buswidth = 8, 816 .qosbox = &(const struct qcom_icc_qosbox) { 817 .num_ports = 1, 818 .port_offsets = { 0x9000 }, 819 .prio = 3, 820 .urg_fwd = 0, 821 .prio_fwd_disable = 1, 822 }, 823 .num_links = 1, 824 .link_nodes = { &qns_pcie_north_gem_noc }, 825 }; 826 827 static struct qcom_icc_node xm_pcie_0 = { 828 .name = "xm_pcie_0", 829 .channels = 1, 830 .buswidth = 16, 831 .qosbox = &(const struct qcom_icc_qosbox) { 832 .num_ports = 1, 833 .port_offsets = { 0x9000 }, 834 .prio = 2, 835 .urg_fwd = 0, 836 .prio_fwd_disable = 1, 837 }, 838 .num_links = 1, 839 .link_nodes = { &qns_pcie_south_gem_noc }, 840 }; 841 842 static struct qcom_icc_node xm_pcie_1 = { 843 .name = "xm_pcie_1", 844 .channels = 1, 845 .buswidth = 16, 846 .qosbox = &(const struct qcom_icc_qosbox) { 847 .num_ports = 1, 848 .port_offsets = { 0xa000 }, 849 .prio = 2, 850 .urg_fwd = 0, 851 .prio_fwd_disable = 1, 852 }, 853 .num_links = 1, 854 .link_nodes = { &qns_pcie_south_gem_noc }, 855 }; 856 857 static struct qcom_icc_node xm_pcie_2 = { 858 .name = "xm_pcie_2", 859 .channels = 1, 860 .buswidth = 16, 861 .qosbox = &(const struct qcom_icc_qosbox) { 862 .num_ports = 1, 863 .port_offsets = { 0xb000 }, 864 .prio = 2, 865 .urg_fwd = 0, 866 .prio_fwd_disable = 1, 867 }, 868 .num_links = 1, 869 .link_nodes = { &qns_pcie_south_gem_noc }, 870 }; 871 872 static struct qcom_icc_node xm_pcie_6a = { 873 .name = "xm_pcie_6a", 874 .channels = 1, 875 .buswidth = 32, 876 .qosbox = &(const struct qcom_icc_qosbox) { 877 .num_ports = 1, 878 .port_offsets = { 0xc000 }, 879 .prio = 2, 880 .urg_fwd = 0, 881 .prio_fwd_disable = 1, 882 }, 883 .num_links = 1, 884 .link_nodes = { &qns_pcie_south_gem_noc }, 885 }; 886 887 static struct qcom_icc_node xm_pcie_6b = { 888 .name = "xm_pcie_6b", 889 .channels = 1, 890 .buswidth = 16, 891 .qosbox = &(const struct qcom_icc_qosbox) { 892 .num_ports = 1, 893 .port_offsets = { 0xd000 }, 894 .prio = 2, 895 .urg_fwd = 0, 896 .prio_fwd_disable = 1, 897 }, 898 .num_links = 1, 899 .link_nodes = { &qns_pcie_south_gem_noc }, 900 }; 901 902 static struct qcom_icc_node qnm_aggre1_noc = { 903 .name = "qnm_aggre1_noc", 904 .channels = 1, 905 .buswidth = 16, 906 .num_links = 1, 907 .link_nodes = { &qns_gemnoc_sf }, 908 }; 909 910 static struct qcom_icc_node qnm_aggre2_noc = { 911 .name = "qnm_aggre2_noc", 912 .channels = 1, 913 .buswidth = 16, 914 .num_links = 1, 915 .link_nodes = { &qns_gemnoc_sf }, 916 }; 917 918 static struct qcom_icc_node qnm_gic = { 919 .name = "qnm_gic", 920 .channels = 1, 921 .buswidth = 8, 922 .qosbox = &(const struct qcom_icc_qosbox) { 923 .num_ports = 1, 924 .port_offsets = { 0x1c000 }, 925 .prio = 2, 926 .urg_fwd = 0, 927 .prio_fwd_disable = 1, 928 }, 929 .num_links = 1, 930 .link_nodes = { &qns_gemnoc_sf }, 931 }; 932 933 static struct qcom_icc_node qnm_usb_anoc = { 934 .name = "qnm_usb_anoc", 935 .channels = 1, 936 .buswidth = 64, 937 .num_links = 1, 938 .link_nodes = { &qns_gemnoc_sf }, 939 }; 940 941 static struct qcom_icc_node qnm_aggre_usb_north_snoc = { 942 .name = "qnm_aggre_usb_north_snoc", 943 .channels = 1, 944 .buswidth = 64, 945 .num_links = 1, 946 .link_nodes = { &qns_aggre_usb_snoc }, 947 }; 948 949 static struct qcom_icc_node qnm_aggre_usb_south_snoc = { 950 .name = "qnm_aggre_usb_south_snoc", 951 .channels = 1, 952 .buswidth = 64, 953 .num_links = 1, 954 .link_nodes = { &qns_aggre_usb_snoc }, 955 }; 956 957 static struct qcom_icc_node xm_usb2_0 = { 958 .name = "xm_usb2_0", 959 .channels = 1, 960 .buswidth = 8, 961 .qosbox = &(const struct qcom_icc_qosbox) { 962 .num_ports = 1, 963 .port_offsets = { 0x6000 }, 964 .prio = 2, 965 .urg_fwd = 0, 966 .prio_fwd_disable = 1, 967 }, 968 .num_links = 1, 969 .link_nodes = { &qns_aggre_usb_north_snoc }, 970 }; 971 972 static struct qcom_icc_node xm_usb3_mp = { 973 .name = "xm_usb3_mp", 974 .channels = 1, 975 .buswidth = 16, 976 .qosbox = &(const struct qcom_icc_qosbox) { 977 .num_ports = 1, 978 .port_offsets = { 0x7000 }, 979 .prio = 2, 980 .urg_fwd = 0, 981 .prio_fwd_disable = 1, 982 }, 983 .num_links = 1, 984 .link_nodes = { &qns_aggre_usb_north_snoc }, 985 }; 986 987 static struct qcom_icc_node xm_usb3_0 = { 988 .name = "xm_usb3_0", 989 .channels = 1, 990 .buswidth = 8, 991 .qosbox = &(const struct qcom_icc_qosbox) { 992 .num_ports = 1, 993 .port_offsets = { 0xa000 }, 994 .prio = 2, 995 .urg_fwd = 0, 996 .prio_fwd_disable = 1, 997 }, 998 .num_links = 1, 999 .link_nodes = { &qns_aggre_usb_south_snoc }, 1000 }; 1001 1002 static struct qcom_icc_node xm_usb3_1 = { 1003 .name = "xm_usb3_1", 1004 .channels = 1, 1005 .buswidth = 8, 1006 .qosbox = &(const struct qcom_icc_qosbox) { 1007 .num_ports = 1, 1008 .port_offsets = { 0xb000 }, 1009 .prio = 2, 1010 .urg_fwd = 0, 1011 .prio_fwd_disable = 1, 1012 }, 1013 .num_links = 1, 1014 .link_nodes = { &qns_aggre_usb_south_snoc }, 1015 }; 1016 1017 static struct qcom_icc_node xm_usb3_2 = { 1018 .name = "xm_usb3_2", 1019 .channels = 1, 1020 .buswidth = 8, 1021 .qosbox = &(const struct qcom_icc_qosbox) { 1022 .num_ports = 1, 1023 .port_offsets = { 0xc000 }, 1024 .prio = 2, 1025 .urg_fwd = 0, 1026 .prio_fwd_disable = 1, 1027 }, 1028 .num_links = 1, 1029 .link_nodes = { &qns_aggre_usb_south_snoc }, 1030 }; 1031 1032 static struct qcom_icc_node xm_usb4_0 = { 1033 .name = "xm_usb4_0", 1034 .channels = 1, 1035 .buswidth = 16, 1036 .qosbox = &(const struct qcom_icc_qosbox) { 1037 .num_ports = 1, 1038 .port_offsets = { 0xd000 }, 1039 .prio = 2, 1040 .urg_fwd = 0, 1041 .prio_fwd_disable = 1, 1042 }, 1043 .num_links = 1, 1044 .link_nodes = { &qns_aggre_usb_south_snoc }, 1045 }; 1046 1047 static struct qcom_icc_node xm_usb4_1 = { 1048 .name = "xm_usb4_1", 1049 .channels = 1, 1050 .buswidth = 16, 1051 .qosbox = &(const struct qcom_icc_qosbox) { 1052 .num_ports = 1, 1053 .port_offsets = { 0xe000 }, 1054 .prio = 2, 1055 .urg_fwd = 0, 1056 .prio_fwd_disable = 1, 1057 }, 1058 .num_links = 1, 1059 .link_nodes = { &qns_aggre_usb_south_snoc }, 1060 }; 1061 1062 static struct qcom_icc_node xm_usb4_2 = { 1063 .name = "xm_usb4_2", 1064 .channels = 1, 1065 .buswidth = 16, 1066 .qosbox = &(const struct qcom_icc_qosbox) { 1067 .num_ports = 1, 1068 .port_offsets = { 0xf000 }, 1069 .prio = 2, 1070 .urg_fwd = 0, 1071 .prio_fwd_disable = 1, 1072 }, 1073 .num_links = 1, 1074 .link_nodes = { &qns_aggre_usb_south_snoc }, 1075 }; 1076 1077 static struct qcom_icc_node qns_a1noc_snoc = { 1078 .name = "qns_a1noc_snoc", 1079 .channels = 1, 1080 .buswidth = 16, 1081 .num_links = 1, 1082 .link_nodes = { &qnm_aggre1_noc }, 1083 }; 1084 1085 static struct qcom_icc_node qns_a2noc_snoc = { 1086 .name = "qns_a2noc_snoc", 1087 .channels = 1, 1088 .buswidth = 16, 1089 .num_links = 1, 1090 .link_nodes = { &qnm_aggre2_noc }, 1091 }; 1092 1093 static struct qcom_icc_node qup0_core_slave = { 1094 .name = "qup0_core_slave", 1095 .channels = 1, 1096 .buswidth = 4, 1097 }; 1098 1099 static struct qcom_icc_node qup1_core_slave = { 1100 .name = "qup1_core_slave", 1101 .channels = 1, 1102 .buswidth = 4, 1103 }; 1104 1105 static struct qcom_icc_node qup2_core_slave = { 1106 .name = "qup2_core_slave", 1107 .channels = 1, 1108 .buswidth = 4, 1109 }; 1110 1111 static struct qcom_icc_node qhs_ahb2phy0 = { 1112 .name = "qhs_ahb2phy0", 1113 .channels = 1, 1114 .buswidth = 4, 1115 }; 1116 1117 static struct qcom_icc_node qhs_ahb2phy1 = { 1118 .name = "qhs_ahb2phy1", 1119 .channels = 1, 1120 .buswidth = 4, 1121 }; 1122 1123 static struct qcom_icc_node qhs_ahb2phy2 = { 1124 .name = "qhs_ahb2phy2", 1125 .channels = 1, 1126 .buswidth = 4, 1127 }; 1128 1129 static struct qcom_icc_node qhs_av1_enc_cfg = { 1130 .name = "qhs_av1_enc_cfg", 1131 .channels = 1, 1132 .buswidth = 4, 1133 }; 1134 1135 static struct qcom_icc_node qhs_camera_cfg = { 1136 .name = "qhs_camera_cfg", 1137 .channels = 1, 1138 .buswidth = 4, 1139 }; 1140 1141 static struct qcom_icc_node qhs_clk_ctl = { 1142 .name = "qhs_clk_ctl", 1143 .channels = 1, 1144 .buswidth = 4, 1145 }; 1146 1147 static struct qcom_icc_node qhs_crypto0_cfg = { 1148 .name = "qhs_crypto0_cfg", 1149 .channels = 1, 1150 .buswidth = 4, 1151 }; 1152 1153 static struct qcom_icc_node qhs_display_cfg = { 1154 .name = "qhs_display_cfg", 1155 .channels = 1, 1156 .buswidth = 4, 1157 }; 1158 1159 static struct qcom_icc_node qhs_gpuss_cfg = { 1160 .name = "qhs_gpuss_cfg", 1161 .channels = 1, 1162 .buswidth = 8, 1163 }; 1164 1165 static struct qcom_icc_node qhs_imem_cfg = { 1166 .name = "qhs_imem_cfg", 1167 .channels = 1, 1168 .buswidth = 4, 1169 }; 1170 1171 static struct qcom_icc_node qhs_ipc_router = { 1172 .name = "qhs_ipc_router", 1173 .channels = 1, 1174 .buswidth = 4, 1175 }; 1176 1177 static struct qcom_icc_node qhs_pcie0_cfg = { 1178 .name = "qhs_pcie0_cfg", 1179 .channels = 1, 1180 .buswidth = 4, 1181 }; 1182 1183 static struct qcom_icc_node qhs_pcie1_cfg = { 1184 .name = "qhs_pcie1_cfg", 1185 .channels = 1, 1186 .buswidth = 4, 1187 }; 1188 1189 static struct qcom_icc_node qhs_pcie2_cfg = { 1190 .name = "qhs_pcie2_cfg", 1191 .channels = 1, 1192 .buswidth = 4, 1193 }; 1194 1195 static struct qcom_icc_node qhs_pcie3_cfg = { 1196 .name = "qhs_pcie3_cfg", 1197 .channels = 1, 1198 .buswidth = 4, 1199 }; 1200 1201 static struct qcom_icc_node qhs_pcie4_cfg = { 1202 .name = "qhs_pcie4_cfg", 1203 .channels = 1, 1204 .buswidth = 4, 1205 }; 1206 1207 static struct qcom_icc_node qhs_pcie5_cfg = { 1208 .name = "qhs_pcie5_cfg", 1209 .channels = 1, 1210 .buswidth = 4, 1211 }; 1212 1213 static struct qcom_icc_node qhs_pcie6a_cfg = { 1214 .name = "qhs_pcie6a_cfg", 1215 .channels = 1, 1216 .buswidth = 4, 1217 }; 1218 1219 static struct qcom_icc_node qhs_pcie6b_cfg = { 1220 .name = "qhs_pcie6b_cfg", 1221 .channels = 1, 1222 .buswidth = 4, 1223 }; 1224 1225 static struct qcom_icc_node qhs_pcie_rsc_cfg = { 1226 .name = "qhs_pcie_rsc_cfg", 1227 .channels = 1, 1228 .buswidth = 4, 1229 }; 1230 1231 static struct qcom_icc_node qhs_pdm = { 1232 .name = "qhs_pdm", 1233 .channels = 1, 1234 .buswidth = 4, 1235 }; 1236 1237 static struct qcom_icc_node qhs_prng = { 1238 .name = "qhs_prng", 1239 .channels = 1, 1240 .buswidth = 4, 1241 }; 1242 1243 static struct qcom_icc_node qhs_qdss_cfg = { 1244 .name = "qhs_qdss_cfg", 1245 .channels = 1, 1246 .buswidth = 4, 1247 }; 1248 1249 static struct qcom_icc_node qhs_qspi = { 1250 .name = "qhs_qspi", 1251 .channels = 1, 1252 .buswidth = 4, 1253 }; 1254 1255 static struct qcom_icc_node qhs_qup0 = { 1256 .name = "qhs_qup0", 1257 .channels = 1, 1258 .buswidth = 4, 1259 }; 1260 1261 static struct qcom_icc_node qhs_qup1 = { 1262 .name = "qhs_qup1", 1263 .channels = 1, 1264 .buswidth = 4, 1265 }; 1266 1267 static struct qcom_icc_node qhs_qup2 = { 1268 .name = "qhs_qup2", 1269 .channels = 1, 1270 .buswidth = 4, 1271 }; 1272 1273 static struct qcom_icc_node qhs_sdc2 = { 1274 .name = "qhs_sdc2", 1275 .channels = 1, 1276 .buswidth = 4, 1277 }; 1278 1279 static struct qcom_icc_node qhs_sdc4 = { 1280 .name = "qhs_sdc4", 1281 .channels = 1, 1282 .buswidth = 4, 1283 }; 1284 1285 static struct qcom_icc_node qhs_smmuv3_cfg = { 1286 .name = "qhs_smmuv3_cfg", 1287 .channels = 1, 1288 .buswidth = 8, 1289 }; 1290 1291 static struct qcom_icc_node qhs_tcsr = { 1292 .name = "qhs_tcsr", 1293 .channels = 1, 1294 .buswidth = 4, 1295 }; 1296 1297 static struct qcom_icc_node qhs_tlmm = { 1298 .name = "qhs_tlmm", 1299 .channels = 1, 1300 .buswidth = 4, 1301 }; 1302 1303 static struct qcom_icc_node qhs_ufs_mem_cfg = { 1304 .name = "qhs_ufs_mem_cfg", 1305 .channels = 1, 1306 .buswidth = 4, 1307 }; 1308 1309 static struct qcom_icc_node qhs_usb2_0_cfg = { 1310 .name = "qhs_usb2_0_cfg", 1311 .channels = 1, 1312 .buswidth = 4, 1313 }; 1314 1315 static struct qcom_icc_node qhs_usb3_0_cfg = { 1316 .name = "qhs_usb3_0_cfg", 1317 .channels = 1, 1318 .buswidth = 4, 1319 }; 1320 1321 static struct qcom_icc_node qhs_usb3_1_cfg = { 1322 .name = "qhs_usb3_1_cfg", 1323 .channels = 1, 1324 .buswidth = 4, 1325 }; 1326 1327 static struct qcom_icc_node qhs_usb3_2_cfg = { 1328 .name = "qhs_usb3_2_cfg", 1329 .channels = 1, 1330 .buswidth = 4, 1331 }; 1332 1333 static struct qcom_icc_node qhs_usb3_mp_cfg = { 1334 .name = "qhs_usb3_mp_cfg", 1335 .channels = 1, 1336 .buswidth = 4, 1337 }; 1338 1339 static struct qcom_icc_node qhs_usb4_0_cfg = { 1340 .name = "qhs_usb4_0_cfg", 1341 .channels = 1, 1342 .buswidth = 4, 1343 }; 1344 1345 static struct qcom_icc_node qhs_usb4_1_cfg = { 1346 .name = "qhs_usb4_1_cfg", 1347 .channels = 1, 1348 .buswidth = 4, 1349 }; 1350 1351 static struct qcom_icc_node qhs_usb4_2_cfg = { 1352 .name = "qhs_usb4_2_cfg", 1353 .channels = 1, 1354 .buswidth = 4, 1355 }; 1356 1357 static struct qcom_icc_node qhs_venus_cfg = { 1358 .name = "qhs_venus_cfg", 1359 .channels = 1, 1360 .buswidth = 4, 1361 }; 1362 1363 static struct qcom_icc_node qss_lpass_qtb_cfg = { 1364 .name = "qss_lpass_qtb_cfg", 1365 .channels = 1, 1366 .buswidth = 4, 1367 }; 1368 1369 static struct qcom_icc_node qss_mnoc_cfg = { 1370 .name = "qss_mnoc_cfg", 1371 .channels = 1, 1372 .buswidth = 4, 1373 .num_links = 1, 1374 .link_nodes = { &qsm_mnoc_cfg }, 1375 }; 1376 1377 static struct qcom_icc_node qss_nsp_qtb_cfg = { 1378 .name = "qss_nsp_qtb_cfg", 1379 .channels = 1, 1380 .buswidth = 4, 1381 }; 1382 1383 static struct qcom_icc_node xs_qdss_stm = { 1384 .name = "xs_qdss_stm", 1385 .channels = 1, 1386 .buswidth = 4, 1387 }; 1388 1389 static struct qcom_icc_node xs_sys_tcu_cfg = { 1390 .name = "xs_sys_tcu_cfg", 1391 .channels = 1, 1392 .buswidth = 8, 1393 }; 1394 1395 static struct qcom_icc_node qhs_aoss = { 1396 .name = "qhs_aoss", 1397 .channels = 1, 1398 .buswidth = 4, 1399 }; 1400 1401 static struct qcom_icc_node qhs_tme_cfg = { 1402 .name = "qhs_tme_cfg", 1403 .channels = 1, 1404 .buswidth = 4, 1405 }; 1406 1407 static struct qcom_icc_node qns_apss = { 1408 .name = "qns_apss", 1409 .channels = 1, 1410 .buswidth = 8, 1411 }; 1412 1413 static struct qcom_icc_node qss_cfg = { 1414 .name = "qss_cfg", 1415 .channels = 1, 1416 .buswidth = 4, 1417 .num_links = 1, 1418 .link_nodes = { &qsm_cfg }, 1419 }; 1420 1421 static struct qcom_icc_node qxs_boot_imem = { 1422 .name = "qxs_boot_imem", 1423 .channels = 1, 1424 .buswidth = 16, 1425 }; 1426 1427 static struct qcom_icc_node qxs_imem = { 1428 .name = "qxs_imem", 1429 .channels = 1, 1430 .buswidth = 8, 1431 }; 1432 1433 static struct qcom_icc_node xs_pcie_0 = { 1434 .name = "xs_pcie_0", 1435 .channels = 1, 1436 .buswidth = 16, 1437 }; 1438 1439 static struct qcom_icc_node xs_pcie_1 = { 1440 .name = "xs_pcie_1", 1441 .channels = 1, 1442 .buswidth = 16, 1443 }; 1444 1445 static struct qcom_icc_node xs_pcie_2 = { 1446 .name = "xs_pcie_2", 1447 .channels = 1, 1448 .buswidth = 16, 1449 }; 1450 1451 static struct qcom_icc_node xs_pcie_3 = { 1452 .name = "xs_pcie_3", 1453 .channels = 1, 1454 .buswidth = 64, 1455 }; 1456 1457 static struct qcom_icc_node xs_pcie_4 = { 1458 .name = "xs_pcie_4", 1459 .channels = 1, 1460 .buswidth = 8, 1461 }; 1462 1463 static struct qcom_icc_node xs_pcie_5 = { 1464 .name = "xs_pcie_5", 1465 .channels = 1, 1466 .buswidth = 8, 1467 }; 1468 1469 static struct qcom_icc_node xs_pcie_6a = { 1470 .name = "xs_pcie_6a", 1471 .channels = 1, 1472 .buswidth = 32, 1473 }; 1474 1475 static struct qcom_icc_node xs_pcie_6b = { 1476 .name = "xs_pcie_6b", 1477 .channels = 1, 1478 .buswidth = 16, 1479 }; 1480 1481 static struct qcom_icc_node qns_gem_noc_cnoc = { 1482 .name = "qns_gem_noc_cnoc", 1483 .channels = 1, 1484 .buswidth = 16, 1485 .num_links = 1, 1486 .link_nodes = { &qnm_gemnoc_cnoc }, 1487 }; 1488 1489 static struct qcom_icc_node qns_llcc = { 1490 .name = "qns_llcc", 1491 .channels = 8, 1492 .buswidth = 16, 1493 .num_links = 1, 1494 .link_nodes = { &llcc_mc }, 1495 }; 1496 1497 static struct qcom_icc_node qns_pcie = { 1498 .name = "qns_pcie", 1499 .channels = 1, 1500 .buswidth = 32, 1501 .num_links = 1, 1502 .link_nodes = { &qnm_gemnoc_pcie }, 1503 }; 1504 1505 static struct qcom_icc_node qns_lpass_ag_noc_gemnoc = { 1506 .name = "qns_lpass_ag_noc_gemnoc", 1507 .channels = 1, 1508 .buswidth = 16, 1509 .num_links = 1, 1510 .link_nodes = { &qnm_lpass }, 1511 }; 1512 1513 static struct qcom_icc_node qns_lpass_aggnoc = { 1514 .name = "qns_lpass_aggnoc", 1515 .channels = 1, 1516 .buswidth = 16, 1517 .num_links = 1, 1518 .link_nodes = { &qnm_lpiaon_noc }, 1519 }; 1520 1521 static struct qcom_icc_node qns_lpi_aon_noc = { 1522 .name = "qns_lpi_aon_noc", 1523 .channels = 1, 1524 .buswidth = 16, 1525 .num_links = 1, 1526 .link_nodes = { &qnm_lpass_lpinoc }, 1527 }; 1528 1529 static struct qcom_icc_node ebi = { 1530 .name = "ebi", 1531 .channels = 8, 1532 .buswidth = 4, 1533 }; 1534 1535 static struct qcom_icc_node qns_mem_noc_hf = { 1536 .name = "qns_mem_noc_hf", 1537 .channels = 2, 1538 .buswidth = 32, 1539 .num_links = 1, 1540 .link_nodes = { &qnm_mnoc_hf }, 1541 }; 1542 1543 static struct qcom_icc_node qns_mem_noc_sf = { 1544 .name = "qns_mem_noc_sf", 1545 .channels = 2, 1546 .buswidth = 32, 1547 .num_links = 1, 1548 .link_nodes = { &qnm_mnoc_sf }, 1549 }; 1550 1551 static struct qcom_icc_node srvc_mnoc = { 1552 .name = "srvc_mnoc", 1553 .channels = 1, 1554 .buswidth = 4, 1555 }; 1556 1557 static struct qcom_icc_node qns_nsp_gemnoc = { 1558 .name = "qns_nsp_gemnoc", 1559 .channels = 2, 1560 .buswidth = 32, 1561 .num_links = 1, 1562 .link_nodes = { &qnm_nsp_noc }, 1563 }; 1564 1565 static struct qcom_icc_node qns_pcie_mem_noc = { 1566 .name = "qns_pcie_mem_noc", 1567 .channels = 1, 1568 .buswidth = 64, 1569 .num_links = 1, 1570 .link_nodes = { &qnm_pcie }, 1571 }; 1572 1573 static struct qcom_icc_node qns_pcie_north_gem_noc = { 1574 .name = "qns_pcie_north_gem_noc", 1575 .channels = 1, 1576 .buswidth = 64, 1577 .num_links = 1, 1578 .link_nodes = { &qnm_pcie_north_gem_noc }, 1579 }; 1580 1581 static struct qcom_icc_node qns_pcie_south_gem_noc = { 1582 .name = "qns_pcie_south_gem_noc", 1583 .channels = 1, 1584 .buswidth = 64, 1585 .num_links = 1, 1586 .link_nodes = { &qnm_pcie_south_gem_noc }, 1587 }; 1588 1589 static struct qcom_icc_node qns_gemnoc_sf = { 1590 .name = "qns_gemnoc_sf", 1591 .channels = 1, 1592 .buswidth = 64, 1593 .num_links = 1, 1594 .link_nodes = { &qnm_snoc_sf }, 1595 }; 1596 1597 static struct qcom_icc_node qns_aggre_usb_snoc = { 1598 .name = "qns_aggre_usb_snoc", 1599 .channels = 1, 1600 .buswidth = 64, 1601 .num_links = 1, 1602 .link_nodes = { &qnm_usb_anoc }, 1603 }; 1604 1605 static struct qcom_icc_node qns_aggre_usb_north_snoc = { 1606 .name = "qns_aggre_usb_north_snoc", 1607 .channels = 1, 1608 .buswidth = 64, 1609 .num_links = 1, 1610 .link_nodes = { &qnm_aggre_usb_north_snoc }, 1611 }; 1612 1613 static struct qcom_icc_node qns_aggre_usb_south_snoc = { 1614 .name = "qns_aggre_usb_south_snoc", 1615 .channels = 1, 1616 .buswidth = 64, 1617 .num_links = 1, 1618 .link_nodes = { &qnm_aggre_usb_south_snoc }, 1619 }; 1620 1621 static struct qcom_icc_bcm bcm_acv = { 1622 .name = "ACV", 1623 .enable_mask = BIT(3), 1624 .num_nodes = 1, 1625 .nodes = { &ebi }, 1626 }; 1627 1628 static struct qcom_icc_bcm bcm_ce0 = { 1629 .name = "CE0", 1630 .num_nodes = 1, 1631 .nodes = { &qxm_crypto }, 1632 }; 1633 1634 static struct qcom_icc_bcm bcm_cn0 = { 1635 .name = "CN0", 1636 .keepalive = true, 1637 .num_nodes = 63, 1638 .nodes = { &qsm_cfg, &qhs_ahb2phy0, 1639 &qhs_ahb2phy1, &qhs_ahb2phy2, 1640 &qhs_av1_enc_cfg, &qhs_camera_cfg, 1641 &qhs_clk_ctl, &qhs_crypto0_cfg, 1642 &qhs_gpuss_cfg, &qhs_imem_cfg, 1643 &qhs_ipc_router, &qhs_pcie0_cfg, 1644 &qhs_pcie1_cfg, &qhs_pcie2_cfg, 1645 &qhs_pcie3_cfg, &qhs_pcie4_cfg, 1646 &qhs_pcie5_cfg, &qhs_pcie6a_cfg, 1647 &qhs_pcie6b_cfg, &qhs_pcie_rsc_cfg, 1648 &qhs_pdm, &qhs_prng, 1649 &qhs_qdss_cfg, &qhs_qspi, 1650 &qhs_qup0, &qhs_qup1, 1651 &qhs_qup2, &qhs_sdc2, 1652 &qhs_sdc4, &qhs_smmuv3_cfg, 1653 &qhs_tcsr, &qhs_tlmm, 1654 &qhs_ufs_mem_cfg, &qhs_usb2_0_cfg, 1655 &qhs_usb3_0_cfg, &qhs_usb3_1_cfg, 1656 &qhs_usb3_2_cfg, &qhs_usb3_mp_cfg, 1657 &qhs_usb4_0_cfg, &qhs_usb4_1_cfg, 1658 &qhs_usb4_2_cfg, &qhs_venus_cfg, 1659 &qss_lpass_qtb_cfg, &qss_mnoc_cfg, 1660 &qss_nsp_qtb_cfg, &xs_qdss_stm, 1661 &xs_sys_tcu_cfg, &qnm_gemnoc_cnoc, 1662 &qnm_gemnoc_pcie, &qhs_aoss, 1663 &qhs_tme_cfg, &qns_apss, 1664 &qss_cfg, &qxs_boot_imem, 1665 &qxs_imem, &xs_pcie_0, 1666 &xs_pcie_1, &xs_pcie_2, 1667 &xs_pcie_3, &xs_pcie_4, 1668 &xs_pcie_5, &xs_pcie_6a, 1669 &xs_pcie_6b }, 1670 }; 1671 1672 static struct qcom_icc_bcm bcm_cn1 = { 1673 .name = "CN1", 1674 .num_nodes = 1, 1675 .nodes = { &qhs_display_cfg }, 1676 }; 1677 1678 static struct qcom_icc_bcm bcm_co0 = { 1679 .name = "CO0", 1680 .num_nodes = 2, 1681 .nodes = { &qxm_nsp, &qns_nsp_gemnoc }, 1682 }; 1683 1684 static struct qcom_icc_bcm bcm_lp0 = { 1685 .name = "LP0", 1686 .num_nodes = 2, 1687 .nodes = { &qnm_lpass_lpinoc, &qns_lpass_aggnoc }, 1688 }; 1689 1690 static struct qcom_icc_bcm bcm_mc0 = { 1691 .name = "MC0", 1692 .keepalive = true, 1693 .num_nodes = 1, 1694 .nodes = { &ebi }, 1695 }; 1696 1697 static struct qcom_icc_bcm bcm_mm0 = { 1698 .name = "MM0", 1699 .num_nodes = 1, 1700 .nodes = { &qns_mem_noc_hf }, 1701 }; 1702 1703 static struct qcom_icc_bcm bcm_mm1 = { 1704 .name = "MM1", 1705 .num_nodes = 10, 1706 .nodes = { &qnm_av1_enc, &qnm_camnoc_hf, 1707 &qnm_camnoc_icp, &qnm_camnoc_sf, 1708 &qnm_eva, &qnm_mdp, 1709 &qnm_video, &qnm_video_cv_cpu, 1710 &qnm_video_v_cpu, &qns_mem_noc_sf }, 1711 }; 1712 1713 static struct qcom_icc_bcm bcm_pc0 = { 1714 .name = "PC0", 1715 .num_nodes = 1, 1716 .nodes = { &qns_pcie_mem_noc }, 1717 }; 1718 1719 static struct qcom_icc_bcm bcm_qup0 = { 1720 .name = "QUP0", 1721 .keepalive = true, 1722 .vote_scale = 1, 1723 .num_nodes = 1, 1724 .nodes = { &qup0_core_slave }, 1725 }; 1726 1727 static struct qcom_icc_bcm bcm_qup1 = { 1728 .name = "QUP1", 1729 .keepalive = true, 1730 .vote_scale = 1, 1731 .num_nodes = 1, 1732 .nodes = { &qup1_core_slave }, 1733 }; 1734 1735 static struct qcom_icc_bcm bcm_qup2 = { 1736 .name = "QUP2", 1737 .keepalive = true, 1738 .vote_scale = 1, 1739 .num_nodes = 1, 1740 .nodes = { &qup2_core_slave }, 1741 }; 1742 1743 static struct qcom_icc_bcm bcm_sh0 = { 1744 .name = "SH0", 1745 .keepalive = true, 1746 .num_nodes = 1, 1747 .nodes = { &qns_llcc }, 1748 }; 1749 1750 static struct qcom_icc_bcm bcm_sh1 = { 1751 .name = "SH1", 1752 .num_nodes = 13, 1753 .nodes = { &alm_gpu_tcu, &alm_pcie_tcu, 1754 &alm_sys_tcu, &chm_apps, 1755 &qnm_gpu, &qnm_lpass, 1756 &qnm_mnoc_hf, &qnm_mnoc_sf, 1757 &qnm_nsp_noc, &qnm_pcie, 1758 &xm_gic, &qns_gem_noc_cnoc, 1759 &qns_pcie }, 1760 }; 1761 1762 static struct qcom_icc_bcm bcm_sn0 = { 1763 .name = "SN0", 1764 .keepalive = true, 1765 .num_nodes = 1, 1766 .nodes = { &qns_gemnoc_sf }, 1767 }; 1768 1769 static struct qcom_icc_bcm bcm_sn2 = { 1770 .name = "SN2", 1771 .num_nodes = 1, 1772 .nodes = { &qnm_aggre1_noc }, 1773 }; 1774 1775 static struct qcom_icc_bcm bcm_sn3 = { 1776 .name = "SN3", 1777 .num_nodes = 1, 1778 .nodes = { &qnm_aggre2_noc }, 1779 }; 1780 1781 static struct qcom_icc_bcm bcm_sn4 = { 1782 .name = "SN4", 1783 .num_nodes = 1, 1784 .nodes = { &qnm_usb_anoc }, 1785 }; 1786 1787 static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { 1788 }; 1789 1790 static struct qcom_icc_node * const aggre1_noc_nodes[] = { 1791 [MASTER_QSPI_0] = &qhm_qspi, 1792 [MASTER_QUP_1] = &qhm_qup1, 1793 [MASTER_SDCC_4] = &xm_sdc4, 1794 [MASTER_UFS_MEM] = &xm_ufs_mem, 1795 [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc, 1796 }; 1797 1798 static const struct regmap_config x1e80100_aggre1_noc_regmap_config = { 1799 .reg_bits = 32, 1800 .reg_stride = 4, 1801 .val_bits = 32, 1802 .max_register = 0x14400, 1803 .fast_io = true, 1804 }; 1805 1806 static const struct qcom_icc_desc x1e80100_aggre1_noc = { 1807 .config = &x1e80100_aggre1_noc_regmap_config, 1808 .nodes = aggre1_noc_nodes, 1809 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), 1810 .bcms = aggre1_noc_bcms, 1811 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), 1812 .qos_requires_clocks = true, 1813 }; 1814 1815 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { 1816 &bcm_ce0, 1817 }; 1818 1819 static struct qcom_icc_node * const aggre2_noc_nodes[] = { 1820 [MASTER_QUP_0] = &qhm_qup0, 1821 [MASTER_QUP_2] = &qhm_qup2, 1822 [MASTER_CRYPTO] = &qxm_crypto, 1823 [MASTER_SP] = &qxm_sp, 1824 [MASTER_QDSS_ETR] = &xm_qdss_etr_0, 1825 [MASTER_QDSS_ETR_1] = &xm_qdss_etr_1, 1826 [MASTER_SDCC_2] = &xm_sdc2, 1827 [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc, 1828 }; 1829 1830 static const struct regmap_config x1e80100_aggre2_noc_regmap_config = { 1831 .reg_bits = 32, 1832 .reg_stride = 4, 1833 .val_bits = 32, 1834 .max_register = 0x1c400, 1835 .fast_io = true, 1836 }; 1837 1838 static const struct qcom_icc_desc x1e80100_aggre2_noc = { 1839 .config = &x1e80100_aggre2_noc_regmap_config, 1840 .nodes = aggre2_noc_nodes, 1841 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), 1842 .bcms = aggre2_noc_bcms, 1843 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), 1844 }; 1845 1846 static struct qcom_icc_bcm * const clk_virt_bcms[] = { 1847 &bcm_qup0, 1848 &bcm_qup1, 1849 &bcm_qup2, 1850 }; 1851 1852 static struct qcom_icc_node * const clk_virt_nodes[] = { 1853 [MASTER_QUP_CORE_0] = &qup0_core_master, 1854 [MASTER_QUP_CORE_1] = &qup1_core_master, 1855 [MASTER_QUP_CORE_2] = &qup2_core_master, 1856 [SLAVE_QUP_CORE_0] = &qup0_core_slave, 1857 [SLAVE_QUP_CORE_1] = &qup1_core_slave, 1858 [SLAVE_QUP_CORE_2] = &qup2_core_slave, 1859 }; 1860 1861 static const struct qcom_icc_desc x1e80100_clk_virt = { 1862 .nodes = clk_virt_nodes, 1863 .num_nodes = ARRAY_SIZE(clk_virt_nodes), 1864 .bcms = clk_virt_bcms, 1865 .num_bcms = ARRAY_SIZE(clk_virt_bcms), 1866 }; 1867 1868 static struct qcom_icc_bcm * const cnoc_cfg_bcms[] = { 1869 &bcm_cn0, 1870 &bcm_cn1, 1871 }; 1872 1873 static struct qcom_icc_node * const cnoc_cfg_nodes[] = { 1874 [MASTER_CNOC_CFG] = &qsm_cfg, 1875 [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0, 1876 [SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1, 1877 [SLAVE_AHB2PHY_2] = &qhs_ahb2phy2, 1878 [SLAVE_AV1_ENC_CFG] = &qhs_av1_enc_cfg, 1879 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, 1880 [SLAVE_CLK_CTL] = &qhs_clk_ctl, 1881 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, 1882 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg, 1883 [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg, 1884 [SLAVE_IMEM_CFG] = &qhs_imem_cfg, 1885 [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router, 1886 [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg, 1887 [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg, 1888 [SLAVE_PCIE_2_CFG] = &qhs_pcie2_cfg, 1889 [SLAVE_PCIE_3_CFG] = &qhs_pcie3_cfg, 1890 [SLAVE_PCIE_4_CFG] = &qhs_pcie4_cfg, 1891 [SLAVE_PCIE_5_CFG] = &qhs_pcie5_cfg, 1892 [SLAVE_PCIE_6A_CFG] = &qhs_pcie6a_cfg, 1893 [SLAVE_PCIE_6B_CFG] = &qhs_pcie6b_cfg, 1894 [SLAVE_PCIE_RSC_CFG] = &qhs_pcie_rsc_cfg, 1895 [SLAVE_PDM] = &qhs_pdm, 1896 [SLAVE_PRNG] = &qhs_prng, 1897 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, 1898 [SLAVE_QSPI_0] = &qhs_qspi, 1899 [SLAVE_QUP_0] = &qhs_qup0, 1900 [SLAVE_QUP_1] = &qhs_qup1, 1901 [SLAVE_QUP_2] = &qhs_qup2, 1902 [SLAVE_SDCC_2] = &qhs_sdc2, 1903 [SLAVE_SDCC_4] = &qhs_sdc4, 1904 [SLAVE_SMMUV3_CFG] = &qhs_smmuv3_cfg, 1905 [SLAVE_TCSR] = &qhs_tcsr, 1906 [SLAVE_TLMM] = &qhs_tlmm, 1907 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, 1908 [SLAVE_USB2] = &qhs_usb2_0_cfg, 1909 [SLAVE_USB3_0] = &qhs_usb3_0_cfg, 1910 [SLAVE_USB3_1] = &qhs_usb3_1_cfg, 1911 [SLAVE_USB3_2] = &qhs_usb3_2_cfg, 1912 [SLAVE_USB3_MP] = &qhs_usb3_mp_cfg, 1913 [SLAVE_USB4_0] = &qhs_usb4_0_cfg, 1914 [SLAVE_USB4_1] = &qhs_usb4_1_cfg, 1915 [SLAVE_USB4_2] = &qhs_usb4_2_cfg, 1916 [SLAVE_VENUS_CFG] = &qhs_venus_cfg, 1917 [SLAVE_LPASS_QTB_CFG] = &qss_lpass_qtb_cfg, 1918 [SLAVE_CNOC_MNOC_CFG] = &qss_mnoc_cfg, 1919 [SLAVE_NSP_QTB_CFG] = &qss_nsp_qtb_cfg, 1920 [SLAVE_QDSS_STM] = &xs_qdss_stm, 1921 [SLAVE_TCU] = &xs_sys_tcu_cfg, 1922 }; 1923 1924 static const struct regmap_config x1e80100_cnoc_cfg_regmap_config = { 1925 .reg_bits = 32, 1926 .reg_stride = 4, 1927 .val_bits = 32, 1928 .max_register = 0x6600, 1929 .fast_io = true, 1930 }; 1931 1932 static const struct qcom_icc_desc x1e80100_cnoc_cfg = { 1933 .config = &x1e80100_cnoc_cfg_regmap_config, 1934 .nodes = cnoc_cfg_nodes, 1935 .num_nodes = ARRAY_SIZE(cnoc_cfg_nodes), 1936 .bcms = cnoc_cfg_bcms, 1937 .num_bcms = ARRAY_SIZE(cnoc_cfg_bcms), 1938 }; 1939 1940 static struct qcom_icc_bcm * const cnoc_main_bcms[] = { 1941 &bcm_cn0, 1942 }; 1943 1944 static struct qcom_icc_node * const cnoc_main_nodes[] = { 1945 [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc, 1946 [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie, 1947 [SLAVE_AOSS] = &qhs_aoss, 1948 [SLAVE_TME_CFG] = &qhs_tme_cfg, 1949 [SLAVE_APPSS] = &qns_apss, 1950 [SLAVE_CNOC_CFG] = &qss_cfg, 1951 [SLAVE_BOOT_IMEM] = &qxs_boot_imem, 1952 [SLAVE_IMEM] = &qxs_imem, 1953 [SLAVE_PCIE_0] = &xs_pcie_0, 1954 [SLAVE_PCIE_1] = &xs_pcie_1, 1955 [SLAVE_PCIE_2] = &xs_pcie_2, 1956 [SLAVE_PCIE_3] = &xs_pcie_3, 1957 [SLAVE_PCIE_4] = &xs_pcie_4, 1958 [SLAVE_PCIE_5] = &xs_pcie_5, 1959 [SLAVE_PCIE_6A] = &xs_pcie_6a, 1960 [SLAVE_PCIE_6B] = &xs_pcie_6b, 1961 }; 1962 1963 static const struct regmap_config x1e80100_cnoc_main_regmap_config = { 1964 .reg_bits = 32, 1965 .reg_stride = 4, 1966 .val_bits = 32, 1967 .max_register = 0x14400, 1968 .fast_io = true, 1969 }; 1970 1971 static const struct qcom_icc_desc x1e80100_cnoc_main = { 1972 .config = &x1e80100_cnoc_main_regmap_config, 1973 .nodes = cnoc_main_nodes, 1974 .num_nodes = ARRAY_SIZE(cnoc_main_nodes), 1975 .bcms = cnoc_main_bcms, 1976 .num_bcms = ARRAY_SIZE(cnoc_main_bcms), 1977 }; 1978 1979 static struct qcom_icc_bcm * const gem_noc_bcms[] = { 1980 &bcm_sh0, 1981 &bcm_sh1, 1982 }; 1983 1984 static struct qcom_icc_node * const gem_noc_nodes[] = { 1985 [MASTER_GPU_TCU] = &alm_gpu_tcu, 1986 [MASTER_PCIE_TCU] = &alm_pcie_tcu, 1987 [MASTER_SYS_TCU] = &alm_sys_tcu, 1988 [MASTER_APPSS_PROC] = &chm_apps, 1989 [MASTER_GFX3D] = &qnm_gpu, 1990 [MASTER_LPASS_GEM_NOC] = &qnm_lpass, 1991 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, 1992 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, 1993 [MASTER_COMPUTE_NOC] = &qnm_nsp_noc, 1994 [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie, 1995 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, 1996 [MASTER_GIC2] = &xm_gic, 1997 [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc, 1998 [SLAVE_LLCC] = &qns_llcc, 1999 [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie, 2000 }; 2001 2002 static const struct regmap_config x1e80100_gem_noc_regmap_config = { 2003 .reg_bits = 32, 2004 .reg_stride = 4, 2005 .val_bits = 32, 2006 .max_register = 0x311200, 2007 .fast_io = true, 2008 }; 2009 2010 static const struct qcom_icc_desc x1e80100_gem_noc = { 2011 .config = &x1e80100_gem_noc_regmap_config, 2012 .nodes = gem_noc_nodes, 2013 .num_nodes = ARRAY_SIZE(gem_noc_nodes), 2014 .bcms = gem_noc_bcms, 2015 .num_bcms = ARRAY_SIZE(gem_noc_bcms), 2016 }; 2017 2018 static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = { 2019 }; 2020 2021 static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { 2022 [MASTER_LPIAON_NOC] = &qnm_lpiaon_noc, 2023 [SLAVE_LPASS_GEM_NOC] = &qns_lpass_ag_noc_gemnoc, 2024 }; 2025 2026 static const struct regmap_config x1e80100_lpass_ag_noc_regmap_config = { 2027 .reg_bits = 32, 2028 .reg_stride = 4, 2029 .val_bits = 32, 2030 .max_register = 0xe080, 2031 .fast_io = true, 2032 }; 2033 2034 static const struct qcom_icc_desc x1e80100_lpass_ag_noc = { 2035 .config = &x1e80100_lpass_ag_noc_regmap_config, 2036 .nodes = lpass_ag_noc_nodes, 2037 .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), 2038 .bcms = lpass_ag_noc_bcms, 2039 .num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms), 2040 }; 2041 2042 static struct qcom_icc_bcm * const lpass_lpiaon_noc_bcms[] = { 2043 &bcm_lp0, 2044 }; 2045 2046 static struct qcom_icc_node * const lpass_lpiaon_noc_nodes[] = { 2047 [MASTER_LPASS_LPINOC] = &qnm_lpass_lpinoc, 2048 [SLAVE_LPIAON_NOC_LPASS_AG_NOC] = &qns_lpass_aggnoc, 2049 }; 2050 2051 static const struct regmap_config x1e80100_lpass_lpiaon_noc_regmap_config = { 2052 .reg_bits = 32, 2053 .reg_stride = 4, 2054 .val_bits = 32, 2055 .max_register = 0x19080, 2056 .fast_io = true, 2057 }; 2058 2059 static const struct qcom_icc_desc x1e80100_lpass_lpiaon_noc = { 2060 .config = &x1e80100_lpass_lpiaon_noc_regmap_config, 2061 .nodes = lpass_lpiaon_noc_nodes, 2062 .num_nodes = ARRAY_SIZE(lpass_lpiaon_noc_nodes), 2063 .bcms = lpass_lpiaon_noc_bcms, 2064 .num_bcms = ARRAY_SIZE(lpass_lpiaon_noc_bcms), 2065 }; 2066 2067 static struct qcom_icc_bcm * const lpass_lpicx_noc_bcms[] = { 2068 }; 2069 2070 static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] = { 2071 [MASTER_LPASS_PROC] = &qxm_lpinoc_dsp_axim, 2072 [SLAVE_LPICX_NOC_LPIAON_NOC] = &qns_lpi_aon_noc, 2073 }; 2074 2075 static const struct regmap_config x1e80100_lpass_lpicx_noc_regmap_config = { 2076 .reg_bits = 32, 2077 .reg_stride = 4, 2078 .val_bits = 32, 2079 .max_register = 0x3a200, 2080 .fast_io = true, 2081 }; 2082 2083 static const struct qcom_icc_desc x1e80100_lpass_lpicx_noc = { 2084 .config = &x1e80100_lpass_lpicx_noc_regmap_config, 2085 .nodes = lpass_lpicx_noc_nodes, 2086 .num_nodes = ARRAY_SIZE(lpass_lpicx_noc_nodes), 2087 .bcms = lpass_lpicx_noc_bcms, 2088 .num_bcms = ARRAY_SIZE(lpass_lpicx_noc_bcms), 2089 }; 2090 2091 static struct qcom_icc_bcm * const mc_virt_bcms[] = { 2092 &bcm_acv, 2093 &bcm_mc0, 2094 }; 2095 2096 static struct qcom_icc_node * const mc_virt_nodes[] = { 2097 [MASTER_LLCC] = &llcc_mc, 2098 [SLAVE_EBI1] = &ebi, 2099 }; 2100 2101 static const struct qcom_icc_desc x1e80100_mc_virt = { 2102 .nodes = mc_virt_nodes, 2103 .num_nodes = ARRAY_SIZE(mc_virt_nodes), 2104 .bcms = mc_virt_bcms, 2105 .num_bcms = ARRAY_SIZE(mc_virt_bcms), 2106 }; 2107 2108 static struct qcom_icc_bcm * const mmss_noc_bcms[] = { 2109 &bcm_mm0, 2110 &bcm_mm1, 2111 }; 2112 2113 static struct qcom_icc_node * const mmss_noc_nodes[] = { 2114 [MASTER_AV1_ENC] = &qnm_av1_enc, 2115 [MASTER_CAMNOC_HF] = &qnm_camnoc_hf, 2116 [MASTER_CAMNOC_ICP] = &qnm_camnoc_icp, 2117 [MASTER_CAMNOC_SF] = &qnm_camnoc_sf, 2118 [MASTER_EVA] = &qnm_eva, 2119 [MASTER_MDP] = &qnm_mdp, 2120 [MASTER_VIDEO] = &qnm_video, 2121 [MASTER_VIDEO_CV_PROC] = &qnm_video_cv_cpu, 2122 [MASTER_VIDEO_V_PROC] = &qnm_video_v_cpu, 2123 [MASTER_CNOC_MNOC_CFG] = &qsm_mnoc_cfg, 2124 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, 2125 [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf, 2126 [SLAVE_SERVICE_MNOC] = &srvc_mnoc, 2127 }; 2128 2129 static const struct regmap_config x1e80100_mmss_noc_regmap_config = { 2130 .reg_bits = 32, 2131 .reg_stride = 4, 2132 .val_bits = 32, 2133 .max_register = 0x5b800, 2134 .fast_io = true, 2135 }; 2136 2137 static const struct qcom_icc_desc x1e80100_mmss_noc = { 2138 .config = &x1e80100_mmss_noc_regmap_config, 2139 .nodes = mmss_noc_nodes, 2140 .num_nodes = ARRAY_SIZE(mmss_noc_nodes), 2141 .bcms = mmss_noc_bcms, 2142 .num_bcms = ARRAY_SIZE(mmss_noc_bcms), 2143 }; 2144 2145 static struct qcom_icc_bcm * const nsp_noc_bcms[] = { 2146 &bcm_co0, 2147 }; 2148 2149 static struct qcom_icc_node * const nsp_noc_nodes[] = { 2150 [MASTER_CDSP_PROC] = &qxm_nsp, 2151 [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc, 2152 }; 2153 2154 static const struct regmap_config x1e80100_nsp_noc_regmap_config = { 2155 .reg_bits = 32, 2156 .reg_stride = 4, 2157 .val_bits = 32, 2158 .max_register = 0xe080, 2159 .fast_io = true, 2160 }; 2161 2162 static const struct qcom_icc_desc x1e80100_nsp_noc = { 2163 .config = &x1e80100_nsp_noc_regmap_config, 2164 .nodes = nsp_noc_nodes, 2165 .num_nodes = ARRAY_SIZE(nsp_noc_nodes), 2166 .bcms = nsp_noc_bcms, 2167 .num_bcms = ARRAY_SIZE(nsp_noc_bcms), 2168 }; 2169 2170 static struct qcom_icc_bcm * const pcie_center_anoc_bcms[] = { 2171 &bcm_pc0, 2172 }; 2173 2174 static struct qcom_icc_node * const pcie_center_anoc_nodes[] = { 2175 [MASTER_PCIE_NORTH] = &qnm_pcie_north_gem_noc, 2176 [MASTER_PCIE_SOUTH] = &qnm_pcie_south_gem_noc, 2177 [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc, 2178 }; 2179 2180 static const struct regmap_config x1e80100_pcie_center_anoc_regmap_config = { 2181 .reg_bits = 32, 2182 .reg_stride = 4, 2183 .val_bits = 32, 2184 .max_register = 0x7000, 2185 .fast_io = true, 2186 }; 2187 2188 static const struct qcom_icc_desc x1e80100_pcie_center_anoc = { 2189 .config = &x1e80100_pcie_center_anoc_regmap_config, 2190 .nodes = pcie_center_anoc_nodes, 2191 .num_nodes = ARRAY_SIZE(pcie_center_anoc_nodes), 2192 .bcms = pcie_center_anoc_bcms, 2193 .num_bcms = ARRAY_SIZE(pcie_center_anoc_bcms), 2194 }; 2195 2196 static struct qcom_icc_bcm * const pcie_north_anoc_bcms[] = { 2197 }; 2198 2199 static struct qcom_icc_node * const pcie_north_anoc_nodes[] = { 2200 [MASTER_PCIE_3] = &xm_pcie_3, 2201 [MASTER_PCIE_4] = &xm_pcie_4, 2202 [MASTER_PCIE_5] = &xm_pcie_5, 2203 [SLAVE_PCIE_NORTH] = &qns_pcie_north_gem_noc, 2204 }; 2205 2206 static const struct regmap_config x1e80100_pcie_north_anoc_regmap_config = { 2207 .reg_bits = 32, 2208 .reg_stride = 4, 2209 .val_bits = 32, 2210 .max_register = 0x9080, 2211 .fast_io = true, 2212 }; 2213 2214 static const struct qcom_icc_desc x1e80100_pcie_north_anoc = { 2215 .config = &x1e80100_pcie_north_anoc_regmap_config, 2216 .nodes = pcie_north_anoc_nodes, 2217 .num_nodes = ARRAY_SIZE(pcie_north_anoc_nodes), 2218 .bcms = pcie_north_anoc_bcms, 2219 .num_bcms = ARRAY_SIZE(pcie_north_anoc_bcms), 2220 }; 2221 2222 static struct qcom_icc_bcm * const pcie_south_anoc_bcms[] = { 2223 }; 2224 2225 static struct qcom_icc_node * const pcie_south_anoc_nodes[] = { 2226 [MASTER_PCIE_0] = &xm_pcie_0, 2227 [MASTER_PCIE_1] = &xm_pcie_1, 2228 [MASTER_PCIE_2] = &xm_pcie_2, 2229 [MASTER_PCIE_6A] = &xm_pcie_6a, 2230 [MASTER_PCIE_6B] = &xm_pcie_6b, 2231 [SLAVE_PCIE_SOUTH] = &qns_pcie_south_gem_noc, 2232 }; 2233 2234 static const struct regmap_config x1e80100_pcie_south_anoc_regmap_config = { 2235 .reg_bits = 32, 2236 .reg_stride = 4, 2237 .val_bits = 32, 2238 .max_register = 0xd080, 2239 .fast_io = true, 2240 }; 2241 2242 static const struct qcom_icc_desc x1e80100_pcie_south_anoc = { 2243 .config = &x1e80100_pcie_south_anoc_regmap_config, 2244 .nodes = pcie_south_anoc_nodes, 2245 .num_nodes = ARRAY_SIZE(pcie_south_anoc_nodes), 2246 .bcms = pcie_south_anoc_bcms, 2247 .num_bcms = ARRAY_SIZE(pcie_south_anoc_bcms), 2248 }; 2249 2250 static struct qcom_icc_bcm * const system_noc_bcms[] = { 2251 &bcm_sn0, 2252 &bcm_sn2, 2253 &bcm_sn3, 2254 &bcm_sn4, 2255 }; 2256 2257 static struct qcom_icc_node * const system_noc_nodes[] = { 2258 [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc, 2259 [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc, 2260 [MASTER_GIC1] = &qnm_gic, 2261 [MASTER_USB_NOC_SNOC] = &qnm_usb_anoc, 2262 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, 2263 }; 2264 2265 static const struct regmap_config x1e80100_system_noc_regmap_config = { 2266 .reg_bits = 32, 2267 .reg_stride = 4, 2268 .val_bits = 32, 2269 .max_register = 0x1c080, 2270 .fast_io = true, 2271 }; 2272 2273 static const struct qcom_icc_desc x1e80100_system_noc = { 2274 .config = &x1e80100_system_noc_regmap_config, 2275 .nodes = system_noc_nodes, 2276 .num_nodes = ARRAY_SIZE(system_noc_nodes), 2277 .bcms = system_noc_bcms, 2278 .num_bcms = ARRAY_SIZE(system_noc_bcms), 2279 }; 2280 2281 static struct qcom_icc_bcm * const usb_center_anoc_bcms[] = { 2282 }; 2283 2284 static struct qcom_icc_node * const usb_center_anoc_nodes[] = { 2285 [MASTER_AGGRE_USB_NORTH] = &qnm_aggre_usb_north_snoc, 2286 [MASTER_AGGRE_USB_SOUTH] = &qnm_aggre_usb_south_snoc, 2287 [SLAVE_USB_NOC_SNOC] = &qns_aggre_usb_snoc, 2288 }; 2289 2290 static const struct regmap_config x1e80100_usb_center_anoc_regmap_config = { 2291 .reg_bits = 32, 2292 .reg_stride = 4, 2293 .val_bits = 32, 2294 .max_register = 0x8800, 2295 .fast_io = true, 2296 }; 2297 2298 static const struct qcom_icc_desc x1e80100_usb_center_anoc = { 2299 .config = &x1e80100_usb_center_anoc_regmap_config, 2300 .nodes = usb_center_anoc_nodes, 2301 .num_nodes = ARRAY_SIZE(usb_center_anoc_nodes), 2302 .bcms = usb_center_anoc_bcms, 2303 .num_bcms = ARRAY_SIZE(usb_center_anoc_bcms), 2304 }; 2305 2306 static struct qcom_icc_bcm * const usb_north_anoc_bcms[] = { 2307 }; 2308 2309 static struct qcom_icc_node * const usb_north_anoc_nodes[] = { 2310 [MASTER_USB2] = &xm_usb2_0, 2311 [MASTER_USB3_MP] = &xm_usb3_mp, 2312 [SLAVE_AGGRE_USB_NORTH] = &qns_aggre_usb_north_snoc, 2313 }; 2314 2315 static const struct regmap_config x1e80100_usb_north_anoc_regmap_config = { 2316 .reg_bits = 32, 2317 .reg_stride = 4, 2318 .val_bits = 32, 2319 .max_register = 0x7080, 2320 .fast_io = true, 2321 }; 2322 2323 static const struct qcom_icc_desc x1e80100_usb_north_anoc = { 2324 .config = &x1e80100_usb_north_anoc_regmap_config, 2325 .nodes = usb_north_anoc_nodes, 2326 .num_nodes = ARRAY_SIZE(usb_north_anoc_nodes), 2327 .bcms = usb_north_anoc_bcms, 2328 .num_bcms = ARRAY_SIZE(usb_north_anoc_bcms), 2329 .qos_requires_clocks = true, 2330 }; 2331 2332 static struct qcom_icc_bcm * const usb_south_anoc_bcms[] = { 2333 }; 2334 2335 static struct qcom_icc_node * const usb_south_anoc_nodes[] = { 2336 [MASTER_USB3_0] = &xm_usb3_0, 2337 [MASTER_USB3_1] = &xm_usb3_1, 2338 [MASTER_USB3_2] = &xm_usb3_2, 2339 [MASTER_USB4_0] = &xm_usb4_0, 2340 [MASTER_USB4_1] = &xm_usb4_1, 2341 [MASTER_USB4_2] = &xm_usb4_2, 2342 [SLAVE_AGGRE_USB_SOUTH] = &qns_aggre_usb_south_snoc, 2343 }; 2344 2345 static const struct regmap_config x1e80100_usb_south_anoc_regmap_config = { 2346 .reg_bits = 32, 2347 .reg_stride = 4, 2348 .val_bits = 32, 2349 .max_register = 0xf080, 2350 .fast_io = true, 2351 }; 2352 2353 static const struct qcom_icc_desc x1e80100_usb_south_anoc = { 2354 .config = &x1e80100_usb_south_anoc_regmap_config, 2355 .nodes = usb_south_anoc_nodes, 2356 .num_nodes = ARRAY_SIZE(usb_south_anoc_nodes), 2357 .bcms = usb_south_anoc_bcms, 2358 .num_bcms = ARRAY_SIZE(usb_south_anoc_bcms), 2359 .qos_requires_clocks = true, 2360 }; 2361 2362 static const struct of_device_id qnoc_of_match[] = { 2363 { .compatible = "qcom,x1e80100-aggre1-noc", .data = &x1e80100_aggre1_noc}, 2364 { .compatible = "qcom,x1e80100-aggre2-noc", .data = &x1e80100_aggre2_noc}, 2365 { .compatible = "qcom,x1e80100-clk-virt", .data = &x1e80100_clk_virt}, 2366 { .compatible = "qcom,x1e80100-cnoc-cfg", .data = &x1e80100_cnoc_cfg}, 2367 { .compatible = "qcom,x1e80100-cnoc-main", .data = &x1e80100_cnoc_main}, 2368 { .compatible = "qcom,x1e80100-gem-noc", .data = &x1e80100_gem_noc}, 2369 { .compatible = "qcom,x1e80100-lpass-ag-noc", .data = &x1e80100_lpass_ag_noc}, 2370 { .compatible = "qcom,x1e80100-lpass-lpiaon-noc", .data = &x1e80100_lpass_lpiaon_noc}, 2371 { .compatible = "qcom,x1e80100-lpass-lpicx-noc", .data = &x1e80100_lpass_lpicx_noc}, 2372 { .compatible = "qcom,x1e80100-mc-virt", .data = &x1e80100_mc_virt}, 2373 { .compatible = "qcom,x1e80100-mmss-noc", .data = &x1e80100_mmss_noc}, 2374 { .compatible = "qcom,x1e80100-nsp-noc", .data = &x1e80100_nsp_noc}, 2375 { .compatible = "qcom,x1e80100-pcie-center-anoc", .data = &x1e80100_pcie_center_anoc}, 2376 { .compatible = "qcom,x1e80100-pcie-north-anoc", .data = &x1e80100_pcie_north_anoc}, 2377 { .compatible = "qcom,x1e80100-pcie-south-anoc", .data = &x1e80100_pcie_south_anoc}, 2378 { .compatible = "qcom,x1e80100-system-noc", .data = &x1e80100_system_noc}, 2379 { .compatible = "qcom,x1e80100-usb-center-anoc", .data = &x1e80100_usb_center_anoc}, 2380 { .compatible = "qcom,x1e80100-usb-north-anoc", .data = &x1e80100_usb_north_anoc}, 2381 { .compatible = "qcom,x1e80100-usb-south-anoc", .data = &x1e80100_usb_south_anoc}, 2382 { } 2383 }; 2384 MODULE_DEVICE_TABLE(of, qnoc_of_match); 2385 2386 static struct platform_driver qnoc_driver = { 2387 .probe = qcom_icc_rpmh_probe, 2388 .remove = qcom_icc_rpmh_remove, 2389 .driver = { 2390 .name = "qnoc-x1e80100", 2391 .of_match_table = qnoc_of_match, 2392 .sync_state = icc_sync_state, 2393 }, 2394 }; 2395 2396 static int __init qnoc_driver_init(void) 2397 { 2398 return platform_driver_register(&qnoc_driver); 2399 } 2400 core_initcall(qnoc_driver_init); 2401 2402 static void __exit qnoc_driver_exit(void) 2403 { 2404 platform_driver_unregister(&qnoc_driver); 2405 } 2406 module_exit(qnoc_driver_exit); 2407 2408 MODULE_DESCRIPTION("x1e80100 NoC driver"); 2409 MODULE_LICENSE("GPL"); 2410