1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 5 * Copyright (c) 2023, Linaro Limited 6 */ 7 8 #include <linux/device.h> 9 #include <linux/interconnect.h> 10 #include <linux/interconnect-provider.h> 11 #include <linux/module.h> 12 #include <linux/of_platform.h> 13 #include <dt-bindings/interconnect/qcom,sm8650-rpmh.h> 14 15 #include "bcm-voter.h" 16 #include "icc-common.h" 17 #include "icc-rpmh.h" 18 #include "sm8650.h" 19 20 static const struct regmap_config icc_regmap_config = { 21 .reg_bits = 32, 22 .reg_stride = 4, 23 .val_bits = 32, 24 .fast_io = true, 25 }; 26 27 static struct qcom_icc_qosbox qhm_qspi_qos = { 28 .num_ports = 1, 29 .port_offsets = { 0xc000 }, 30 .prio = 2, 31 .urg_fwd = 0, 32 .prio_fwd_disable = 0, 33 }; 34 35 static struct qcom_icc_node qhm_qspi = { 36 .name = "qhm_qspi", 37 .id = SM8650_MASTER_QSPI_0, 38 .channels = 1, 39 .buswidth = 4, 40 .qosbox = &qhm_qspi_qos, 41 .num_links = 1, 42 .links = { SM8650_SLAVE_A1NOC_SNOC }, 43 }; 44 45 static struct qcom_icc_qosbox qhm_qup1_qos = { 46 .num_ports = 1, 47 .port_offsets = { 0xd000 }, 48 .prio = 2, 49 .urg_fwd = 0, 50 .prio_fwd_disable = 0, 51 }; 52 53 static struct qcom_icc_node qhm_qup1 = { 54 .name = "qhm_qup1", 55 .id = SM8650_MASTER_QUP_1, 56 .channels = 1, 57 .buswidth = 4, 58 .qosbox = &qhm_qup1_qos, 59 .num_links = 1, 60 .links = { SM8650_SLAVE_A1NOC_SNOC }, 61 }; 62 63 static struct qcom_icc_node qxm_qup02 = { 64 .name = "qxm_qup02", 65 .id = SM8650_MASTER_QUP_3, 66 .channels = 1, 67 .buswidth = 8, 68 .num_links = 1, 69 .links = { SM8650_SLAVE_A1NOC_SNOC }, 70 }; 71 72 static struct qcom_icc_qosbox xm_sdc4_qos = { 73 .num_ports = 1, 74 .port_offsets = { 0xe000 }, 75 .prio = 2, 76 .urg_fwd = 0, 77 .prio_fwd_disable = 0, 78 }; 79 80 static struct qcom_icc_node xm_sdc4 = { 81 .name = "xm_sdc4", 82 .id = SM8650_MASTER_SDCC_4, 83 .channels = 1, 84 .buswidth = 8, 85 .qosbox = &xm_sdc4_qos, 86 .num_links = 1, 87 .links = { SM8650_SLAVE_A1NOC_SNOC }, 88 }; 89 90 static struct qcom_icc_qosbox xm_ufs_mem_qos = { 91 .num_ports = 1, 92 .port_offsets = { 0xf000 }, 93 .prio = 2, 94 .urg_fwd = 0, 95 .prio_fwd_disable = 0, 96 }; 97 98 static struct qcom_icc_node xm_ufs_mem = { 99 .name = "xm_ufs_mem", 100 .id = SM8650_MASTER_UFS_MEM, 101 .channels = 1, 102 .buswidth = 16, 103 .qosbox = &xm_ufs_mem_qos, 104 .num_links = 1, 105 .links = { SM8650_SLAVE_A1NOC_SNOC }, 106 }; 107 108 static struct qcom_icc_qosbox xm_usb3_0_qos = { 109 .num_ports = 1, 110 .port_offsets = { 0x10000 }, 111 .prio = 2, 112 .urg_fwd = 0, 113 .prio_fwd_disable = 0, 114 }; 115 116 static struct qcom_icc_node xm_usb3_0 = { 117 .name = "xm_usb3_0", 118 .id = SM8650_MASTER_USB3_0, 119 .channels = 1, 120 .buswidth = 8, 121 .qosbox = &xm_usb3_0_qos, 122 .num_links = 1, 123 .links = { SM8650_SLAVE_A1NOC_SNOC }, 124 }; 125 126 static struct qcom_icc_qosbox qhm_qdss_bam_qos = { 127 .num_ports = 1, 128 .port_offsets = { 0x12000 }, 129 .prio = 2, 130 .urg_fwd = 0, 131 .prio_fwd_disable = 0, 132 }; 133 134 static struct qcom_icc_node qhm_qdss_bam = { 135 .name = "qhm_qdss_bam", 136 .id = SM8650_MASTER_QDSS_BAM, 137 .channels = 1, 138 .buswidth = 4, 139 .qosbox = &qhm_qdss_bam_qos, 140 .num_links = 1, 141 .links = { SM8650_SLAVE_A2NOC_SNOC }, 142 }; 143 144 static struct qcom_icc_qosbox qhm_qup2_qos = { 145 .num_ports = 1, 146 .port_offsets = { 0x13000 }, 147 .prio = 2, 148 .urg_fwd = 0, 149 .prio_fwd_disable = 0, 150 }; 151 152 static struct qcom_icc_node qhm_qup2 = { 153 .name = "qhm_qup2", 154 .id = SM8650_MASTER_QUP_2, 155 .channels = 1, 156 .buswidth = 4, 157 .qosbox = &qhm_qup2_qos, 158 .num_links = 1, 159 .links = { SM8650_SLAVE_A2NOC_SNOC }, 160 }; 161 162 static struct qcom_icc_qosbox qxm_crypto_qos = { 163 .num_ports = 1, 164 .port_offsets = { 0x15000 }, 165 .prio = 2, 166 .urg_fwd = 1, 167 .prio_fwd_disable = 0, 168 }; 169 170 static struct qcom_icc_node qxm_crypto = { 171 .name = "qxm_crypto", 172 .id = SM8650_MASTER_CRYPTO, 173 .channels = 1, 174 .buswidth = 8, 175 .qosbox = &qxm_crypto_qos, 176 .num_links = 1, 177 .links = { SM8650_SLAVE_A2NOC_SNOC }, 178 }; 179 180 static struct qcom_icc_qosbox qxm_ipa_qos = { 181 .num_ports = 1, 182 .port_offsets = { 0x16000 }, 183 .prio = 2, 184 .urg_fwd = 1, 185 .prio_fwd_disable = 0, 186 }; 187 188 static struct qcom_icc_node qxm_ipa = { 189 .name = "qxm_ipa", 190 .id = SM8650_MASTER_IPA, 191 .channels = 1, 192 .buswidth = 8, 193 .qosbox = &qxm_ipa_qos, 194 .num_links = 1, 195 .links = { SM8650_SLAVE_A2NOC_SNOC }, 196 }; 197 198 static struct qcom_icc_node qxm_sp = { 199 .name = "qxm_sp", 200 .id = SM8650_MASTER_SP, 201 .channels = 1, 202 .buswidth = 8, 203 .num_links = 1, 204 .links = { SM8650_SLAVE_A2NOC_SNOC }, 205 }; 206 207 static struct qcom_icc_qosbox xm_qdss_etr_0_qos = { 208 .num_ports = 1, 209 .port_offsets = { 0x17000 }, 210 .prio = 2, 211 .urg_fwd = 0, 212 .prio_fwd_disable = 0, 213 }; 214 215 static struct qcom_icc_node xm_qdss_etr_0 = { 216 .name = "xm_qdss_etr_0", 217 .id = SM8650_MASTER_QDSS_ETR, 218 .channels = 1, 219 .buswidth = 8, 220 .qosbox = &xm_qdss_etr_0_qos, 221 .num_links = 1, 222 .links = { SM8650_SLAVE_A2NOC_SNOC }, 223 }; 224 225 static struct qcom_icc_qosbox xm_qdss_etr_1_qos = { 226 .num_ports = 1, 227 .port_offsets = { 0x18000 }, 228 .prio = 2, 229 .urg_fwd = 0, 230 .prio_fwd_disable = 0, 231 }; 232 233 static struct qcom_icc_node xm_qdss_etr_1 = { 234 .name = "xm_qdss_etr_1", 235 .id = SM8650_MASTER_QDSS_ETR_1, 236 .channels = 1, 237 .buswidth = 8, 238 .qosbox = &xm_qdss_etr_1_qos, 239 .num_links = 1, 240 .links = { SM8650_SLAVE_A2NOC_SNOC }, 241 }; 242 243 static struct qcom_icc_qosbox xm_sdc2_qos = { 244 .num_ports = 1, 245 .port_offsets = { 0x19000 }, 246 .prio = 2, 247 .urg_fwd = 0, 248 .prio_fwd_disable = 0, 249 }; 250 251 static struct qcom_icc_node xm_sdc2 = { 252 .name = "xm_sdc2", 253 .id = SM8650_MASTER_SDCC_2, 254 .channels = 1, 255 .buswidth = 8, 256 .qosbox = &xm_sdc2_qos, 257 .num_links = 1, 258 .links = { SM8650_SLAVE_A2NOC_SNOC }, 259 }; 260 261 static struct qcom_icc_node qup0_core_master = { 262 .name = "qup0_core_master", 263 .id = SM8650_MASTER_QUP_CORE_0, 264 .channels = 1, 265 .buswidth = 4, 266 .num_links = 1, 267 .links = { SM8650_SLAVE_QUP_CORE_0 }, 268 }; 269 270 static struct qcom_icc_node qup1_core_master = { 271 .name = "qup1_core_master", 272 .id = SM8650_MASTER_QUP_CORE_1, 273 .channels = 1, 274 .buswidth = 4, 275 .num_links = 1, 276 .links = { SM8650_SLAVE_QUP_CORE_1 }, 277 }; 278 279 static struct qcom_icc_node qup2_core_master = { 280 .name = "qup2_core_master", 281 .id = SM8650_MASTER_QUP_CORE_2, 282 .channels = 1, 283 .buswidth = 4, 284 .num_links = 1, 285 .links = { SM8650_SLAVE_QUP_CORE_2 }, 286 }; 287 288 static struct qcom_icc_node qsm_cfg = { 289 .name = "qsm_cfg", 290 .id = SM8650_MASTER_CNOC_CFG, 291 .channels = 1, 292 .buswidth = 4, 293 .num_links = 46, 294 .links = { SM8650_SLAVE_AHB2PHY_SOUTH, SM8650_SLAVE_AHB2PHY_NORTH, 295 SM8650_SLAVE_CAMERA_CFG, SM8650_SLAVE_CLK_CTL, 296 SM8650_SLAVE_RBCPR_CX_CFG, SM8650_SLAVE_CPR_HMX, 297 SM8650_SLAVE_RBCPR_MMCX_CFG, SM8650_SLAVE_RBCPR_MXA_CFG, 298 SM8650_SLAVE_RBCPR_MXC_CFG, SM8650_SLAVE_CPR_NSPCX, 299 SM8650_SLAVE_CRYPTO_0_CFG, SM8650_SLAVE_CX_RDPM, 300 SM8650_SLAVE_DISPLAY_CFG, SM8650_SLAVE_GFX3D_CFG, 301 SM8650_SLAVE_I2C, SM8650_SLAVE_I3C_IBI0_CFG, 302 SM8650_SLAVE_I3C_IBI1_CFG, SM8650_SLAVE_IMEM_CFG, 303 SM8650_SLAVE_CNOC_MSS, SM8650_SLAVE_MX_2_RDPM, 304 SM8650_SLAVE_MX_RDPM, SM8650_SLAVE_PCIE_0_CFG, 305 SM8650_SLAVE_PCIE_1_CFG, SM8650_SLAVE_PCIE_RSCC, 306 SM8650_SLAVE_PDM, SM8650_SLAVE_PRNG, 307 SM8650_SLAVE_QDSS_CFG, SM8650_SLAVE_QSPI_0, 308 SM8650_SLAVE_QUP_3, SM8650_SLAVE_QUP_1, 309 SM8650_SLAVE_QUP_2, SM8650_SLAVE_SDCC_2, 310 SM8650_SLAVE_SDCC_4, SM8650_SLAVE_SPSS_CFG, 311 SM8650_SLAVE_TCSR, SM8650_SLAVE_TLMM, 312 SM8650_SLAVE_UFS_MEM_CFG, SM8650_SLAVE_USB3_0, 313 SM8650_SLAVE_VENUS_CFG, SM8650_SLAVE_VSENSE_CTRL_CFG, 314 SM8650_SLAVE_CNOC_MNOC_CFG, SM8650_SLAVE_NSP_QTB_CFG, 315 SM8650_SLAVE_PCIE_ANOC_CFG, SM8650_SLAVE_SERVICE_CNOC_CFG, 316 SM8650_SLAVE_QDSS_STM, SM8650_SLAVE_TCU }, 317 }; 318 319 static struct qcom_icc_node qnm_gemnoc_cnoc = { 320 .name = "qnm_gemnoc_cnoc", 321 .id = SM8650_MASTER_GEM_NOC_CNOC, 322 .channels = 1, 323 .buswidth = 16, 324 .num_links = 9, 325 .links = { SM8650_SLAVE_AOSS, SM8650_SLAVE_IPA_CFG, 326 SM8650_SLAVE_IPC_ROUTER_CFG, SM8650_SLAVE_TME_CFG, 327 SM8650_SLAVE_APPSS, SM8650_SLAVE_CNOC_CFG, 328 SM8650_SLAVE_DDRSS_CFG, SM8650_SLAVE_IMEM, 329 SM8650_SLAVE_SERVICE_CNOC }, 330 }; 331 332 static struct qcom_icc_node qnm_gemnoc_pcie = { 333 .name = "qnm_gemnoc_pcie", 334 .id = SM8650_MASTER_GEM_NOC_PCIE_SNOC, 335 .channels = 1, 336 .buswidth = 16, 337 .num_links = 2, 338 .links = { SM8650_SLAVE_PCIE_0, SM8650_SLAVE_PCIE_1 }, 339 }; 340 341 static struct qcom_icc_qosbox alm_gpu_tcu_qos = { 342 .num_ports = 1, 343 .port_offsets = { 0xbf000 }, 344 .prio = 1, 345 .urg_fwd = 0, 346 .prio_fwd_disable = 1, 347 }; 348 349 static struct qcom_icc_node alm_gpu_tcu = { 350 .name = "alm_gpu_tcu", 351 .id = SM8650_MASTER_GPU_TCU, 352 .channels = 1, 353 .buswidth = 8, 354 .qosbox = &alm_gpu_tcu_qos, 355 .num_links = 2, 356 .links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC }, 357 }; 358 359 static struct qcom_icc_qosbox alm_sys_tcu_qos = { 360 .num_ports = 1, 361 .port_offsets = { 0xc1000 }, 362 .prio = 6, 363 .urg_fwd = 0, 364 .prio_fwd_disable = 1, 365 }; 366 367 static struct qcom_icc_node alm_sys_tcu = { 368 .name = "alm_sys_tcu", 369 .id = SM8650_MASTER_SYS_TCU, 370 .channels = 1, 371 .buswidth = 8, 372 .qosbox = &alm_sys_tcu_qos, 373 .num_links = 2, 374 .links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC }, 375 }; 376 377 static struct qcom_icc_qosbox alm_ubwc_p_tcu_qos = { 378 .num_ports = 1, 379 .port_offsets = { 0xc5000 }, 380 .prio = 1, 381 .urg_fwd = 0, 382 .prio_fwd_disable = 1, 383 }; 384 385 static struct qcom_icc_node alm_ubwc_p_tcu = { 386 .name = "alm_ubwc_p_tcu", 387 .id = SM8650_MASTER_UBWC_P_TCU, 388 .channels = 1, 389 .buswidth = 8, 390 .qosbox = &alm_ubwc_p_tcu_qos, 391 .num_links = 2, 392 .links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC }, 393 }; 394 395 static struct qcom_icc_node chm_apps = { 396 .name = "chm_apps", 397 .id = SM8650_MASTER_APPSS_PROC, 398 .channels = 3, 399 .buswidth = 32, 400 .num_links = 3, 401 .links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC, 402 SM8650_SLAVE_MEM_NOC_PCIE_SNOC }, 403 }; 404 405 static struct qcom_icc_qosbox qnm_gpu_qos = { 406 .num_ports = 2, 407 .port_offsets = { 0x31000, 0x71000 }, 408 .prio = 0, 409 .urg_fwd = 1, 410 .prio_fwd_disable = 1, 411 }; 412 413 static struct qcom_icc_node qnm_gpu = { 414 .name = "qnm_gpu", 415 .id = SM8650_MASTER_GFX3D, 416 .channels = 2, 417 .buswidth = 32, 418 .qosbox = &qnm_gpu_qos, 419 .num_links = 2, 420 .links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC }, 421 }; 422 423 static struct qcom_icc_qosbox qnm_lpass_gemnoc_qos = { 424 .num_ports = 1, 425 .port_offsets = { 0xb5000 }, 426 .prio = 0, 427 .urg_fwd = 1, 428 .prio_fwd_disable = 0, 429 }; 430 431 static struct qcom_icc_node qnm_lpass_gemnoc = { 432 .name = "qnm_lpass_gemnoc", 433 .id = SM8650_MASTER_LPASS_GEM_NOC, 434 .channels = 1, 435 .buswidth = 16, 436 .qosbox = &qnm_lpass_gemnoc_qos, 437 .num_links = 3, 438 .links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC, 439 SM8650_SLAVE_MEM_NOC_PCIE_SNOC }, 440 }; 441 442 static struct qcom_icc_node qnm_mdsp = { 443 .name = "qnm_mdsp", 444 .id = SM8650_MASTER_MSS_PROC, 445 .channels = 1, 446 .buswidth = 16, 447 .num_links = 3, 448 .links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC, 449 SM8650_SLAVE_MEM_NOC_PCIE_SNOC }, 450 }; 451 452 static struct qcom_icc_qosbox qnm_mnoc_hf_qos = { 453 .num_ports = 2, 454 .port_offsets = { 0x33000, 0x73000 }, 455 .prio = 0, 456 .urg_fwd = 1, 457 .prio_fwd_disable = 0, 458 }; 459 460 static struct qcom_icc_node qnm_mnoc_hf = { 461 .name = "qnm_mnoc_hf", 462 .id = SM8650_MASTER_MNOC_HF_MEM_NOC, 463 .channels = 2, 464 .buswidth = 32, 465 .qosbox = &qnm_mnoc_hf_qos, 466 .num_links = 2, 467 .links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC }, 468 }; 469 470 static struct qcom_icc_qosbox qnm_mnoc_sf_qos = { 471 .num_ports = 2, 472 .port_offsets = { 0x35000, 0x75000 }, 473 .prio = 0, 474 .urg_fwd = 0, 475 .prio_fwd_disable = 0, 476 }; 477 478 static struct qcom_icc_node qnm_mnoc_sf = { 479 .name = "qnm_mnoc_sf", 480 .id = SM8650_MASTER_MNOC_SF_MEM_NOC, 481 .channels = 2, 482 .buswidth = 32, 483 .qosbox = &qnm_mnoc_sf_qos, 484 .num_links = 2, 485 .links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC }, 486 }; 487 488 static struct qcom_icc_qosbox qnm_nsp_gemnoc_qos = { 489 .num_ports = 2, 490 .port_offsets = { 0x37000, 0x77000 }, 491 .prio = 0, 492 .urg_fwd = 1, 493 .prio_fwd_disable = 1, 494 }; 495 496 static struct qcom_icc_node qnm_nsp_gemnoc = { 497 .name = "qnm_nsp_gemnoc", 498 .id = SM8650_MASTER_COMPUTE_NOC, 499 .channels = 2, 500 .buswidth = 32, 501 .qosbox = &qnm_nsp_gemnoc_qos, 502 .num_links = 3, 503 .links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC, 504 SM8650_SLAVE_MEM_NOC_PCIE_SNOC }, 505 }; 506 507 static struct qcom_icc_qosbox qnm_pcie_qos = { 508 .num_ports = 1, 509 .port_offsets = { 0xb7000 }, 510 .prio = 2, 511 .urg_fwd = 1, 512 .prio_fwd_disable = 0, 513 }; 514 515 static struct qcom_icc_node qnm_pcie = { 516 .name = "qnm_pcie", 517 .id = SM8650_MASTER_ANOC_PCIE_GEM_NOC, 518 .channels = 1, 519 .buswidth = 16, 520 .qosbox = &qnm_pcie_qos, 521 .num_links = 2, 522 .links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC }, 523 }; 524 525 static struct qcom_icc_qosbox qnm_snoc_sf_qos = { 526 .num_ports = 1, 527 .port_offsets = { 0xbb000 }, 528 .prio = 0, 529 .urg_fwd = 1, 530 .prio_fwd_disable = 0, 531 }; 532 533 static struct qcom_icc_node qnm_snoc_sf = { 534 .name = "qnm_snoc_sf", 535 .id = SM8650_MASTER_SNOC_SF_MEM_NOC, 536 .channels = 1, 537 .buswidth = 16, 538 .qosbox = &qnm_snoc_sf_qos, 539 .num_links = 3, 540 .links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC, 541 SM8650_SLAVE_MEM_NOC_PCIE_SNOC }, 542 }; 543 544 static struct qcom_icc_qosbox qnm_ubwc_p_qos = { 545 .num_ports = 1, 546 .port_offsets = { 0xc3000 }, 547 .prio = 1, 548 .urg_fwd = 1, 549 .prio_fwd_disable = 1, 550 }; 551 552 static struct qcom_icc_node qnm_ubwc_p = { 553 .name = "qnm_ubwc_p", 554 .id = SM8650_MASTER_UBWC_P, 555 .channels = 1, 556 .buswidth = 32, 557 .qosbox = &qnm_ubwc_p_qos, 558 .num_links = 1, 559 .links = { SM8650_SLAVE_LLCC }, 560 }; 561 562 static struct qcom_icc_qosbox xm_gic_qos = { 563 .num_ports = 1, 564 .port_offsets = { 0xb9000 }, 565 .prio = 4, 566 .urg_fwd = 0, 567 .prio_fwd_disable = 1, 568 }; 569 570 static struct qcom_icc_node xm_gic = { 571 .name = "xm_gic", 572 .id = SM8650_MASTER_GIC, 573 .channels = 1, 574 .buswidth = 8, 575 .qosbox = &xm_gic_qos, 576 .num_links = 1, 577 .links = { SM8650_SLAVE_LLCC }, 578 }; 579 580 static struct qcom_icc_node qnm_lpiaon_noc = { 581 .name = "qnm_lpiaon_noc", 582 .id = SM8650_MASTER_LPIAON_NOC, 583 .channels = 1, 584 .buswidth = 16, 585 .num_links = 1, 586 .links = { SM8650_SLAVE_LPASS_GEM_NOC }, 587 }; 588 589 static struct qcom_icc_node qnm_lpass_lpinoc = { 590 .name = "qnm_lpass_lpinoc", 591 .id = SM8650_MASTER_LPASS_LPINOC, 592 .channels = 1, 593 .buswidth = 16, 594 .num_links = 1, 595 .links = { SM8650_SLAVE_LPIAON_NOC_LPASS_AG_NOC }, 596 }; 597 598 static struct qcom_icc_node qxm_lpinoc_dsp_axim = { 599 .name = "qxm_lpinoc_dsp_axim", 600 .id = SM8650_MASTER_LPASS_PROC, 601 .channels = 1, 602 .buswidth = 16, 603 .num_links = 1, 604 .links = { SM8650_SLAVE_LPICX_NOC_LPIAON_NOC }, 605 }; 606 607 static struct qcom_icc_node llcc_mc = { 608 .name = "llcc_mc", 609 .id = SM8650_MASTER_LLCC, 610 .channels = 4, 611 .buswidth = 4, 612 .num_links = 1, 613 .links = { SM8650_SLAVE_EBI1 }, 614 }; 615 616 static struct qcom_icc_qosbox qnm_camnoc_hf_qos = { 617 .num_ports = 2, 618 .port_offsets = { 0x28000, 0x29000 }, 619 .prio = 0, 620 .urg_fwd = 1, 621 .prio_fwd_disable = 0, 622 }; 623 624 static struct qcom_icc_node qnm_camnoc_hf = { 625 .name = "qnm_camnoc_hf", 626 .id = SM8650_MASTER_CAMNOC_HF, 627 .channels = 2, 628 .buswidth = 32, 629 .qosbox = &qnm_camnoc_hf_qos, 630 .num_links = 1, 631 .links = { SM8650_SLAVE_MNOC_HF_MEM_NOC }, 632 }; 633 634 static struct qcom_icc_qosbox qnm_camnoc_icp_qos = { 635 .num_ports = 1, 636 .port_offsets = { 0x2a000 }, 637 .prio = 4, 638 .urg_fwd = 1, 639 .prio_fwd_disable = 0, 640 }; 641 642 static struct qcom_icc_node qnm_camnoc_icp = { 643 .name = "qnm_camnoc_icp", 644 .id = SM8650_MASTER_CAMNOC_ICP, 645 .channels = 1, 646 .buswidth = 8, 647 .qosbox = &qnm_camnoc_icp_qos, 648 .num_links = 1, 649 .links = { SM8650_SLAVE_MNOC_SF_MEM_NOC }, 650 }; 651 652 static struct qcom_icc_qosbox qnm_camnoc_sf_qos = { 653 .num_ports = 2, 654 .port_offsets = { 0x2b000, 0x2c000 }, 655 .prio = 0, 656 .urg_fwd = 1, 657 .prio_fwd_disable = 0, 658 }; 659 660 static struct qcom_icc_node qnm_camnoc_sf = { 661 .name = "qnm_camnoc_sf", 662 .id = SM8650_MASTER_CAMNOC_SF, 663 .channels = 2, 664 .buswidth = 32, 665 .qosbox = &qnm_camnoc_sf_qos, 666 .num_links = 1, 667 .links = { SM8650_SLAVE_MNOC_SF_MEM_NOC }, 668 }; 669 670 static struct qcom_icc_qosbox qnm_mdp_qos = { 671 .num_ports = 2, 672 .port_offsets = { 0x2d000, 0x2e000 }, 673 .prio = 0, 674 .urg_fwd = 1, 675 .prio_fwd_disable = 0, 676 }; 677 678 static struct qcom_icc_node qnm_mdp = { 679 .name = "qnm_mdp", 680 .id = SM8650_MASTER_MDP, 681 .channels = 2, 682 .buswidth = 32, 683 .qosbox = &qnm_mdp_qos, 684 .num_links = 1, 685 .links = { SM8650_SLAVE_MNOC_HF_MEM_NOC }, 686 }; 687 688 static struct qcom_icc_node qnm_vapss_hcp = { 689 .name = "qnm_vapss_hcp", 690 .id = SM8650_MASTER_CDSP_HCP, 691 .channels = 1, 692 .buswidth = 32, 693 .num_links = 1, 694 .links = { SM8650_SLAVE_MNOC_SF_MEM_NOC }, 695 }; 696 697 static struct qcom_icc_qosbox qnm_video_qos = { 698 .num_ports = 2, 699 .port_offsets = { 0x30000, 0x31000 }, 700 .prio = 0, 701 .urg_fwd = 1, 702 .prio_fwd_disable = 0, 703 }; 704 705 static struct qcom_icc_node qnm_video = { 706 .name = "qnm_video", 707 .id = SM8650_MASTER_VIDEO, 708 .channels = 2, 709 .buswidth = 32, 710 .qosbox = &qnm_video_qos, 711 .num_links = 1, 712 .links = { SM8650_SLAVE_MNOC_SF_MEM_NOC }, 713 }; 714 715 static struct qcom_icc_qosbox qnm_video_cv_cpu_qos = { 716 .num_ports = 1, 717 .port_offsets = { 0x32000 }, 718 .prio = 4, 719 .urg_fwd = 1, 720 .prio_fwd_disable = 0, 721 }; 722 723 static struct qcom_icc_node qnm_video_cv_cpu = { 724 .name = "qnm_video_cv_cpu", 725 .id = SM8650_MASTER_VIDEO_CV_PROC, 726 .channels = 1, 727 .buswidth = 8, 728 .qosbox = &qnm_video_cv_cpu_qos, 729 .num_links = 1, 730 .links = { SM8650_SLAVE_MNOC_SF_MEM_NOC }, 731 }; 732 733 static struct qcom_icc_qosbox qnm_video_cvp_qos = { 734 .num_ports = 2, 735 .port_offsets = { 0x33000, 0x34000 }, 736 .prio = 0, 737 .urg_fwd = 1, 738 .prio_fwd_disable = 0, 739 }; 740 741 static struct qcom_icc_node qnm_video_cvp = { 742 .name = "qnm_video_cvp", 743 .id = SM8650_MASTER_VIDEO_PROC, 744 .channels = 2, 745 .buswidth = 32, 746 .qosbox = &qnm_video_cvp_qos, 747 .num_links = 1, 748 .links = { SM8650_SLAVE_MNOC_SF_MEM_NOC }, 749 }; 750 751 static struct qcom_icc_qosbox qnm_video_v_cpu_qos = { 752 .num_ports = 1, 753 .port_offsets = { 0x35000 }, 754 .prio = 4, 755 .urg_fwd = 1, 756 .prio_fwd_disable = 0, 757 }; 758 759 static struct qcom_icc_node qnm_video_v_cpu = { 760 .name = "qnm_video_v_cpu", 761 .id = SM8650_MASTER_VIDEO_V_PROC, 762 .channels = 1, 763 .buswidth = 8, 764 .qosbox = &qnm_video_v_cpu_qos, 765 .num_links = 1, 766 .links = { SM8650_SLAVE_MNOC_SF_MEM_NOC }, 767 }; 768 769 static struct qcom_icc_node qsm_mnoc_cfg = { 770 .name = "qsm_mnoc_cfg", 771 .id = SM8650_MASTER_CNOC_MNOC_CFG, 772 .channels = 1, 773 .buswidth = 4, 774 .num_links = 1, 775 .links = { SM8650_SLAVE_SERVICE_MNOC }, 776 }; 777 778 static struct qcom_icc_node qnm_nsp = { 779 .name = "qnm_nsp", 780 .id = SM8650_MASTER_CDSP_PROC, 781 .channels = 2, 782 .buswidth = 32, 783 .num_links = 1, 784 .links = { SM8650_SLAVE_CDSP_MEM_NOC }, 785 }; 786 787 static struct qcom_icc_node qsm_pcie_anoc_cfg = { 788 .name = "qsm_pcie_anoc_cfg", 789 .id = SM8650_MASTER_PCIE_ANOC_CFG, 790 .channels = 1, 791 .buswidth = 4, 792 .num_links = 1, 793 .links = { SM8650_SLAVE_SERVICE_PCIE_ANOC }, 794 }; 795 796 static struct qcom_icc_qosbox xm_pcie3_0_qos = { 797 .num_ports = 1, 798 .port_offsets = { 0xb000 }, 799 .prio = 3, 800 .urg_fwd = 0, 801 .prio_fwd_disable = 0, 802 }; 803 804 static struct qcom_icc_node xm_pcie3_0 = { 805 .name = "xm_pcie3_0", 806 .id = SM8650_MASTER_PCIE_0, 807 .channels = 1, 808 .buswidth = 8, 809 .qosbox = &xm_pcie3_0_qos, 810 .num_links = 1, 811 .links = { SM8650_SLAVE_ANOC_PCIE_GEM_NOC }, 812 }; 813 814 static struct qcom_icc_qosbox xm_pcie3_1_qos = { 815 .num_ports = 1, 816 .port_offsets = { 0xc000 }, 817 .prio = 2, 818 .urg_fwd = 0, 819 .prio_fwd_disable = 0, 820 }; 821 822 static struct qcom_icc_node xm_pcie3_1 = { 823 .name = "xm_pcie3_1", 824 .id = SM8650_MASTER_PCIE_1, 825 .channels = 1, 826 .buswidth = 16, 827 .qosbox = &xm_pcie3_1_qos, 828 .num_links = 1, 829 .links = { SM8650_SLAVE_ANOC_PCIE_GEM_NOC }, 830 }; 831 832 static struct qcom_icc_node qnm_aggre1_noc = { 833 .name = "qnm_aggre1_noc", 834 .id = SM8650_MASTER_A1NOC_SNOC, 835 .channels = 1, 836 .buswidth = 16, 837 .num_links = 1, 838 .links = { SM8650_SLAVE_SNOC_GEM_NOC_SF }, 839 }; 840 841 static struct qcom_icc_node qnm_aggre2_noc = { 842 .name = "qnm_aggre2_noc", 843 .id = SM8650_MASTER_A2NOC_SNOC, 844 .channels = 1, 845 .buswidth = 16, 846 .num_links = 1, 847 .links = { SM8650_SLAVE_SNOC_GEM_NOC_SF }, 848 }; 849 850 static struct qcom_icc_qosbox qnm_apss_noc_qos = { 851 .num_ports = 1, 852 .port_offsets = { 0x1c000 }, 853 .prio = 2, 854 .urg_fwd = 0, 855 .prio_fwd_disable = 1, 856 }; 857 858 static struct qcom_icc_node qnm_apss_noc = { 859 .name = "qnm_apss_noc", 860 .id = SM8650_MASTER_APSS_NOC, 861 .channels = 1, 862 .buswidth = 4, 863 .qosbox = &qnm_apss_noc_qos, 864 .num_links = 1, 865 .links = { SM8650_SLAVE_SNOC_GEM_NOC_SF }, 866 }; 867 868 static struct qcom_icc_node qns_a1noc_snoc = { 869 .name = "qns_a1noc_snoc", 870 .id = SM8650_SLAVE_A1NOC_SNOC, 871 .channels = 1, 872 .buswidth = 16, 873 .num_links = 1, 874 .links = { SM8650_MASTER_A1NOC_SNOC }, 875 }; 876 877 static struct qcom_icc_node qns_a2noc_snoc = { 878 .name = "qns_a2noc_snoc", 879 .id = SM8650_SLAVE_A2NOC_SNOC, 880 .channels = 1, 881 .buswidth = 16, 882 .num_links = 1, 883 .links = { SM8650_MASTER_A2NOC_SNOC }, 884 }; 885 886 static struct qcom_icc_node qup0_core_slave = { 887 .name = "qup0_core_slave", 888 .id = SM8650_SLAVE_QUP_CORE_0, 889 .channels = 1, 890 .buswidth = 4, 891 .num_links = 0, 892 }; 893 894 static struct qcom_icc_node qup1_core_slave = { 895 .name = "qup1_core_slave", 896 .id = SM8650_SLAVE_QUP_CORE_1, 897 .channels = 1, 898 .buswidth = 4, 899 .num_links = 0, 900 }; 901 902 static struct qcom_icc_node qup2_core_slave = { 903 .name = "qup2_core_slave", 904 .id = SM8650_SLAVE_QUP_CORE_2, 905 .channels = 1, 906 .buswidth = 4, 907 .num_links = 0, 908 }; 909 910 static struct qcom_icc_node qhs_ahb2phy0 = { 911 .name = "qhs_ahb2phy0", 912 .id = SM8650_SLAVE_AHB2PHY_SOUTH, 913 .channels = 1, 914 .buswidth = 4, 915 .num_links = 0, 916 }; 917 918 static struct qcom_icc_node qhs_ahb2phy1 = { 919 .name = "qhs_ahb2phy1", 920 .id = SM8650_SLAVE_AHB2PHY_NORTH, 921 .channels = 1, 922 .buswidth = 4, 923 .num_links = 0, 924 }; 925 926 static struct qcom_icc_node qhs_camera_cfg = { 927 .name = "qhs_camera_cfg", 928 .id = SM8650_SLAVE_CAMERA_CFG, 929 .channels = 1, 930 .buswidth = 4, 931 .num_links = 0, 932 }; 933 934 static struct qcom_icc_node qhs_clk_ctl = { 935 .name = "qhs_clk_ctl", 936 .id = SM8650_SLAVE_CLK_CTL, 937 .channels = 1, 938 .buswidth = 4, 939 .num_links = 0, 940 }; 941 942 static struct qcom_icc_node qhs_cpr_cx = { 943 .name = "qhs_cpr_cx", 944 .id = SM8650_SLAVE_RBCPR_CX_CFG, 945 .channels = 1, 946 .buswidth = 4, 947 .num_links = 0, 948 }; 949 950 static struct qcom_icc_node qhs_cpr_hmx = { 951 .name = "qhs_cpr_hmx", 952 .id = SM8650_SLAVE_CPR_HMX, 953 .channels = 1, 954 .buswidth = 4, 955 .num_links = 0, 956 }; 957 958 static struct qcom_icc_node qhs_cpr_mmcx = { 959 .name = "qhs_cpr_mmcx", 960 .id = SM8650_SLAVE_RBCPR_MMCX_CFG, 961 .channels = 1, 962 .buswidth = 4, 963 .num_links = 0, 964 }; 965 966 static struct qcom_icc_node qhs_cpr_mxa = { 967 .name = "qhs_cpr_mxa", 968 .id = SM8650_SLAVE_RBCPR_MXA_CFG, 969 .channels = 1, 970 .buswidth = 4, 971 .num_links = 0, 972 }; 973 974 static struct qcom_icc_node qhs_cpr_mxc = { 975 .name = "qhs_cpr_mxc", 976 .id = SM8650_SLAVE_RBCPR_MXC_CFG, 977 .channels = 1, 978 .buswidth = 4, 979 .num_links = 0, 980 }; 981 982 static struct qcom_icc_node qhs_cpr_nspcx = { 983 .name = "qhs_cpr_nspcx", 984 .id = SM8650_SLAVE_CPR_NSPCX, 985 .channels = 1, 986 .buswidth = 4, 987 .num_links = 0, 988 }; 989 990 static struct qcom_icc_node qhs_crypto0_cfg = { 991 .name = "qhs_crypto0_cfg", 992 .id = SM8650_SLAVE_CRYPTO_0_CFG, 993 .channels = 1, 994 .buswidth = 4, 995 .num_links = 0, 996 }; 997 998 static struct qcom_icc_node qhs_cx_rdpm = { 999 .name = "qhs_cx_rdpm", 1000 .id = SM8650_SLAVE_CX_RDPM, 1001 .channels = 1, 1002 .buswidth = 4, 1003 .num_links = 0, 1004 }; 1005 1006 static struct qcom_icc_node qhs_display_cfg = { 1007 .name = "qhs_display_cfg", 1008 .id = SM8650_SLAVE_DISPLAY_CFG, 1009 .channels = 1, 1010 .buswidth = 4, 1011 .num_links = 0, 1012 }; 1013 1014 static struct qcom_icc_node qhs_gpuss_cfg = { 1015 .name = "qhs_gpuss_cfg", 1016 .id = SM8650_SLAVE_GFX3D_CFG, 1017 .channels = 1, 1018 .buswidth = 8, 1019 .num_links = 0, 1020 }; 1021 1022 static struct qcom_icc_node qhs_i2c = { 1023 .name = "qhs_i2c", 1024 .id = SM8650_SLAVE_I2C, 1025 .channels = 1, 1026 .buswidth = 4, 1027 .num_links = 0, 1028 }; 1029 1030 static struct qcom_icc_node qhs_i3c_ibi0_cfg = { 1031 .name = "qhs_i3c_ibi0_cfg", 1032 .id = SM8650_SLAVE_I3C_IBI0_CFG, 1033 .channels = 1, 1034 .buswidth = 4, 1035 .num_links = 0, 1036 }; 1037 1038 static struct qcom_icc_node qhs_i3c_ibi1_cfg = { 1039 .name = "qhs_i3c_ibi1_cfg", 1040 .id = SM8650_SLAVE_I3C_IBI1_CFG, 1041 .channels = 1, 1042 .buswidth = 4, 1043 .num_links = 0, 1044 }; 1045 1046 static struct qcom_icc_node qhs_imem_cfg = { 1047 .name = "qhs_imem_cfg", 1048 .id = SM8650_SLAVE_IMEM_CFG, 1049 .channels = 1, 1050 .buswidth = 4, 1051 .num_links = 0, 1052 }; 1053 1054 static struct qcom_icc_node qhs_mss_cfg = { 1055 .name = "qhs_mss_cfg", 1056 .id = SM8650_SLAVE_CNOC_MSS, 1057 .channels = 1, 1058 .buswidth = 4, 1059 .num_links = 0, 1060 }; 1061 1062 static struct qcom_icc_node qhs_mx_2_rdpm = { 1063 .name = "qhs_mx_2_rdpm", 1064 .id = SM8650_SLAVE_MX_2_RDPM, 1065 .channels = 1, 1066 .buswidth = 4, 1067 .num_links = 0, 1068 }; 1069 1070 static struct qcom_icc_node qhs_mx_rdpm = { 1071 .name = "qhs_mx_rdpm", 1072 .id = SM8650_SLAVE_MX_RDPM, 1073 .channels = 1, 1074 .buswidth = 4, 1075 .num_links = 0, 1076 }; 1077 1078 static struct qcom_icc_node qhs_pcie0_cfg = { 1079 .name = "qhs_pcie0_cfg", 1080 .id = SM8650_SLAVE_PCIE_0_CFG, 1081 .channels = 1, 1082 .buswidth = 4, 1083 .num_links = 0, 1084 }; 1085 1086 static struct qcom_icc_node qhs_pcie1_cfg = { 1087 .name = "qhs_pcie1_cfg", 1088 .id = SM8650_SLAVE_PCIE_1_CFG, 1089 .channels = 1, 1090 .buswidth = 4, 1091 .num_links = 0, 1092 }; 1093 1094 static struct qcom_icc_node qhs_pcie_rscc = { 1095 .name = "qhs_pcie_rscc", 1096 .id = SM8650_SLAVE_PCIE_RSCC, 1097 .channels = 1, 1098 .buswidth = 4, 1099 .num_links = 0, 1100 }; 1101 1102 static struct qcom_icc_node qhs_pdm = { 1103 .name = "qhs_pdm", 1104 .id = SM8650_SLAVE_PDM, 1105 .channels = 1, 1106 .buswidth = 4, 1107 .num_links = 0, 1108 }; 1109 1110 static struct qcom_icc_node qhs_prng = { 1111 .name = "qhs_prng", 1112 .id = SM8650_SLAVE_PRNG, 1113 .channels = 1, 1114 .buswidth = 4, 1115 .num_links = 0, 1116 }; 1117 1118 static struct qcom_icc_node qhs_qdss_cfg = { 1119 .name = "qhs_qdss_cfg", 1120 .id = SM8650_SLAVE_QDSS_CFG, 1121 .channels = 1, 1122 .buswidth = 4, 1123 .num_links = 0, 1124 }; 1125 1126 static struct qcom_icc_node qhs_qspi = { 1127 .name = "qhs_qspi", 1128 .id = SM8650_SLAVE_QSPI_0, 1129 .channels = 1, 1130 .buswidth = 4, 1131 .num_links = 0, 1132 }; 1133 1134 static struct qcom_icc_node qhs_qup02 = { 1135 .name = "qhs_qup02", 1136 .id = SM8650_SLAVE_QUP_3, 1137 .channels = 1, 1138 .buswidth = 4, 1139 .num_links = 0, 1140 }; 1141 1142 static struct qcom_icc_node qhs_qup1 = { 1143 .name = "qhs_qup1", 1144 .id = SM8650_SLAVE_QUP_1, 1145 .channels = 1, 1146 .buswidth = 4, 1147 .num_links = 0, 1148 }; 1149 1150 static struct qcom_icc_node qhs_qup2 = { 1151 .name = "qhs_qup2", 1152 .id = SM8650_SLAVE_QUP_2, 1153 .channels = 1, 1154 .buswidth = 4, 1155 .num_links = 0, 1156 }; 1157 1158 static struct qcom_icc_node qhs_sdc2 = { 1159 .name = "qhs_sdc2", 1160 .id = SM8650_SLAVE_SDCC_2, 1161 .channels = 1, 1162 .buswidth = 4, 1163 .num_links = 0, 1164 }; 1165 1166 static struct qcom_icc_node qhs_sdc4 = { 1167 .name = "qhs_sdc4", 1168 .id = SM8650_SLAVE_SDCC_4, 1169 .channels = 1, 1170 .buswidth = 4, 1171 .num_links = 0, 1172 }; 1173 1174 static struct qcom_icc_node qhs_spss_cfg = { 1175 .name = "qhs_spss_cfg", 1176 .id = SM8650_SLAVE_SPSS_CFG, 1177 .channels = 1, 1178 .buswidth = 4, 1179 .num_links = 0, 1180 }; 1181 1182 static struct qcom_icc_node qhs_tcsr = { 1183 .name = "qhs_tcsr", 1184 .id = SM8650_SLAVE_TCSR, 1185 .channels = 1, 1186 .buswidth = 4, 1187 .num_links = 0, 1188 }; 1189 1190 static struct qcom_icc_node qhs_tlmm = { 1191 .name = "qhs_tlmm", 1192 .id = SM8650_SLAVE_TLMM, 1193 .channels = 1, 1194 .buswidth = 4, 1195 .num_links = 0, 1196 }; 1197 1198 static struct qcom_icc_node qhs_ufs_mem_cfg = { 1199 .name = "qhs_ufs_mem_cfg", 1200 .id = SM8650_SLAVE_UFS_MEM_CFG, 1201 .channels = 1, 1202 .buswidth = 4, 1203 .num_links = 0, 1204 }; 1205 1206 static struct qcom_icc_node qhs_usb3_0 = { 1207 .name = "qhs_usb3_0", 1208 .id = SM8650_SLAVE_USB3_0, 1209 .channels = 1, 1210 .buswidth = 4, 1211 .num_links = 0, 1212 }; 1213 1214 static struct qcom_icc_node qhs_venus_cfg = { 1215 .name = "qhs_venus_cfg", 1216 .id = SM8650_SLAVE_VENUS_CFG, 1217 .channels = 1, 1218 .buswidth = 4, 1219 .num_links = 0, 1220 }; 1221 1222 static struct qcom_icc_node qhs_vsense_ctrl_cfg = { 1223 .name = "qhs_vsense_ctrl_cfg", 1224 .id = SM8650_SLAVE_VSENSE_CTRL_CFG, 1225 .channels = 1, 1226 .buswidth = 4, 1227 .num_links = 0, 1228 }; 1229 1230 static struct qcom_icc_node qss_mnoc_cfg = { 1231 .name = "qss_mnoc_cfg", 1232 .id = SM8650_SLAVE_CNOC_MNOC_CFG, 1233 .channels = 1, 1234 .buswidth = 4, 1235 .num_links = 1, 1236 .links = { SM8650_MASTER_CNOC_MNOC_CFG }, 1237 }; 1238 1239 static struct qcom_icc_node qss_nsp_qtb_cfg = { 1240 .name = "qss_nsp_qtb_cfg", 1241 .id = SM8650_SLAVE_NSP_QTB_CFG, 1242 .channels = 1, 1243 .buswidth = 4, 1244 .num_links = 0, 1245 }; 1246 1247 static struct qcom_icc_node qss_pcie_anoc_cfg = { 1248 .name = "qss_pcie_anoc_cfg", 1249 .id = SM8650_SLAVE_PCIE_ANOC_CFG, 1250 .channels = 1, 1251 .buswidth = 4, 1252 .num_links = 1, 1253 .links = { SM8650_MASTER_PCIE_ANOC_CFG }, 1254 }; 1255 1256 static struct qcom_icc_node srvc_cnoc_cfg = { 1257 .name = "srvc_cnoc_cfg", 1258 .id = SM8650_SLAVE_SERVICE_CNOC_CFG, 1259 .channels = 1, 1260 .buswidth = 4, 1261 .num_links = 0, 1262 }; 1263 1264 static struct qcom_icc_node xs_qdss_stm = { 1265 .name = "xs_qdss_stm", 1266 .id = SM8650_SLAVE_QDSS_STM, 1267 .channels = 1, 1268 .buswidth = 4, 1269 .num_links = 0, 1270 }; 1271 1272 static struct qcom_icc_node xs_sys_tcu_cfg = { 1273 .name = "xs_sys_tcu_cfg", 1274 .id = SM8650_SLAVE_TCU, 1275 .channels = 1, 1276 .buswidth = 8, 1277 .num_links = 0, 1278 }; 1279 1280 static struct qcom_icc_node qhs_aoss = { 1281 .name = "qhs_aoss", 1282 .id = SM8650_SLAVE_AOSS, 1283 .channels = 1, 1284 .buswidth = 4, 1285 .num_links = 0, 1286 }; 1287 1288 static struct qcom_icc_node qhs_ipa = { 1289 .name = "qhs_ipa", 1290 .id = SM8650_SLAVE_IPA_CFG, 1291 .channels = 1, 1292 .buswidth = 4, 1293 .num_links = 0, 1294 }; 1295 1296 static struct qcom_icc_node qhs_ipc_router = { 1297 .name = "qhs_ipc_router", 1298 .id = SM8650_SLAVE_IPC_ROUTER_CFG, 1299 .channels = 1, 1300 .buswidth = 4, 1301 .num_links = 0, 1302 }; 1303 1304 static struct qcom_icc_node qhs_tme_cfg = { 1305 .name = "qhs_tme_cfg", 1306 .id = SM8650_SLAVE_TME_CFG, 1307 .channels = 1, 1308 .buswidth = 4, 1309 .num_links = 0, 1310 }; 1311 1312 static struct qcom_icc_node qss_apss = { 1313 .name = "qss_apss", 1314 .id = SM8650_SLAVE_APPSS, 1315 .channels = 1, 1316 .buswidth = 4, 1317 .num_links = 0, 1318 }; 1319 1320 static struct qcom_icc_node qss_cfg = { 1321 .name = "qss_cfg", 1322 .id = SM8650_SLAVE_CNOC_CFG, 1323 .channels = 1, 1324 .buswidth = 4, 1325 .num_links = 1, 1326 .links = { SM8650_MASTER_CNOC_CFG }, 1327 }; 1328 1329 static struct qcom_icc_node qss_ddrss_cfg = { 1330 .name = "qss_ddrss_cfg", 1331 .id = SM8650_SLAVE_DDRSS_CFG, 1332 .channels = 1, 1333 .buswidth = 4, 1334 .num_links = 0, 1335 }; 1336 1337 static struct qcom_icc_node qxs_imem = { 1338 .name = "qxs_imem", 1339 .id = SM8650_SLAVE_IMEM, 1340 .channels = 1, 1341 .buswidth = 8, 1342 .num_links = 0, 1343 }; 1344 1345 static struct qcom_icc_node srvc_cnoc_main = { 1346 .name = "srvc_cnoc_main", 1347 .id = SM8650_SLAVE_SERVICE_CNOC, 1348 .channels = 1, 1349 .buswidth = 4, 1350 .num_links = 0, 1351 }; 1352 1353 static struct qcom_icc_node xs_pcie_0 = { 1354 .name = "xs_pcie_0", 1355 .id = SM8650_SLAVE_PCIE_0, 1356 .channels = 1, 1357 .buswidth = 8, 1358 .num_links = 0, 1359 }; 1360 1361 static struct qcom_icc_node xs_pcie_1 = { 1362 .name = "xs_pcie_1", 1363 .id = SM8650_SLAVE_PCIE_1, 1364 .channels = 1, 1365 .buswidth = 16, 1366 .num_links = 0, 1367 }; 1368 1369 static struct qcom_icc_node qns_gem_noc_cnoc = { 1370 .name = "qns_gem_noc_cnoc", 1371 .id = SM8650_SLAVE_GEM_NOC_CNOC, 1372 .channels = 1, 1373 .buswidth = 16, 1374 .num_links = 1, 1375 .links = { SM8650_MASTER_GEM_NOC_CNOC }, 1376 }; 1377 1378 static struct qcom_icc_node qns_llcc = { 1379 .name = "qns_llcc", 1380 .id = SM8650_SLAVE_LLCC, 1381 .channels = 4, 1382 .buswidth = 16, 1383 .num_links = 1, 1384 .links = { SM8650_MASTER_LLCC }, 1385 }; 1386 1387 static struct qcom_icc_node qns_pcie = { 1388 .name = "qns_pcie", 1389 .id = SM8650_SLAVE_MEM_NOC_PCIE_SNOC, 1390 .channels = 1, 1391 .buswidth = 8, 1392 .num_links = 1, 1393 .links = { SM8650_MASTER_GEM_NOC_PCIE_SNOC }, 1394 }; 1395 1396 static struct qcom_icc_node qns_lpass_ag_noc_gemnoc = { 1397 .name = "qns_lpass_ag_noc_gemnoc", 1398 .id = SM8650_SLAVE_LPASS_GEM_NOC, 1399 .channels = 1, 1400 .buswidth = 16, 1401 .num_links = 1, 1402 .links = { SM8650_MASTER_LPASS_GEM_NOC }, 1403 }; 1404 1405 static struct qcom_icc_node qns_lpass_aggnoc = { 1406 .name = "qns_lpass_aggnoc", 1407 .id = SM8650_SLAVE_LPIAON_NOC_LPASS_AG_NOC, 1408 .channels = 1, 1409 .buswidth = 16, 1410 .num_links = 1, 1411 .links = { SM8650_MASTER_LPIAON_NOC }, 1412 }; 1413 1414 static struct qcom_icc_node qns_lpi_aon_noc = { 1415 .name = "qns_lpi_aon_noc", 1416 .id = SM8650_SLAVE_LPICX_NOC_LPIAON_NOC, 1417 .channels = 1, 1418 .buswidth = 16, 1419 .num_links = 1, 1420 .links = { SM8650_MASTER_LPASS_LPINOC }, 1421 }; 1422 1423 static struct qcom_icc_node ebi = { 1424 .name = "ebi", 1425 .id = SM8650_SLAVE_EBI1, 1426 .channels = 4, 1427 .buswidth = 4, 1428 .num_links = 0, 1429 }; 1430 1431 static struct qcom_icc_node qns_mem_noc_hf = { 1432 .name = "qns_mem_noc_hf", 1433 .id = SM8650_SLAVE_MNOC_HF_MEM_NOC, 1434 .channels = 2, 1435 .buswidth = 32, 1436 .num_links = 1, 1437 .links = { SM8650_MASTER_MNOC_HF_MEM_NOC }, 1438 }; 1439 1440 static struct qcom_icc_node qns_mem_noc_sf = { 1441 .name = "qns_mem_noc_sf", 1442 .id = SM8650_SLAVE_MNOC_SF_MEM_NOC, 1443 .channels = 2, 1444 .buswidth = 32, 1445 .num_links = 1, 1446 .links = { SM8650_MASTER_MNOC_SF_MEM_NOC }, 1447 }; 1448 1449 static struct qcom_icc_node srvc_mnoc = { 1450 .name = "srvc_mnoc", 1451 .id = SM8650_SLAVE_SERVICE_MNOC, 1452 .channels = 1, 1453 .buswidth = 4, 1454 .num_links = 0, 1455 }; 1456 1457 static struct qcom_icc_node qns_nsp_gemnoc = { 1458 .name = "qns_nsp_gemnoc", 1459 .id = SM8650_SLAVE_CDSP_MEM_NOC, 1460 .channels = 2, 1461 .buswidth = 32, 1462 .num_links = 1, 1463 .links = { SM8650_MASTER_COMPUTE_NOC }, 1464 }; 1465 1466 static struct qcom_icc_node qns_pcie_mem_noc = { 1467 .name = "qns_pcie_mem_noc", 1468 .id = SM8650_SLAVE_ANOC_PCIE_GEM_NOC, 1469 .channels = 1, 1470 .buswidth = 16, 1471 .num_links = 1, 1472 .links = { SM8650_MASTER_ANOC_PCIE_GEM_NOC }, 1473 }; 1474 1475 static struct qcom_icc_node srvc_pcie_aggre_noc = { 1476 .name = "srvc_pcie_aggre_noc", 1477 .id = SM8650_SLAVE_SERVICE_PCIE_ANOC, 1478 .channels = 1, 1479 .buswidth = 4, 1480 .num_links = 0, 1481 }; 1482 1483 static struct qcom_icc_node qns_gemnoc_sf = { 1484 .name = "qns_gemnoc_sf", 1485 .id = SM8650_SLAVE_SNOC_GEM_NOC_SF, 1486 .channels = 1, 1487 .buswidth = 16, 1488 .num_links = 1, 1489 .links = { SM8650_MASTER_SNOC_SF_MEM_NOC }, 1490 }; 1491 1492 static struct qcom_icc_bcm bcm_acv = { 1493 .name = "ACV", 1494 .enable_mask = BIT(0), 1495 .num_nodes = 1, 1496 .nodes = { &ebi }, 1497 }; 1498 1499 static struct qcom_icc_bcm bcm_ce0 = { 1500 .name = "CE0", 1501 .num_nodes = 1, 1502 .nodes = { &qxm_crypto }, 1503 }; 1504 1505 static struct qcom_icc_bcm bcm_cn0 = { 1506 .name = "CN0", 1507 .enable_mask = BIT(0), 1508 .keepalive = true, 1509 .num_nodes = 59, 1510 .nodes = { &qsm_cfg, &qhs_ahb2phy0, 1511 &qhs_ahb2phy1, &qhs_camera_cfg, 1512 &qhs_clk_ctl, &qhs_cpr_cx, 1513 &qhs_cpr_hmx, &qhs_cpr_mmcx, 1514 &qhs_cpr_mxa, &qhs_cpr_mxc, 1515 &qhs_cpr_nspcx, &qhs_crypto0_cfg, 1516 &qhs_cx_rdpm, &qhs_display_cfg, 1517 &qhs_gpuss_cfg, &qhs_i2c, 1518 &qhs_i3c_ibi0_cfg, &qhs_i3c_ibi1_cfg, 1519 &qhs_imem_cfg, &qhs_mss_cfg, 1520 &qhs_mx_2_rdpm, &qhs_mx_rdpm, 1521 &qhs_pcie0_cfg, &qhs_pcie1_cfg, 1522 &qhs_pcie_rscc, &qhs_pdm, 1523 &qhs_prng, &qhs_qdss_cfg, 1524 &qhs_qspi, &qhs_qup02, 1525 &qhs_qup1, &qhs_qup2, 1526 &qhs_sdc2, &qhs_sdc4, 1527 &qhs_spss_cfg, &qhs_tcsr, 1528 &qhs_tlmm, &qhs_ufs_mem_cfg, 1529 &qhs_usb3_0, &qhs_venus_cfg, 1530 &qhs_vsense_ctrl_cfg, &qss_mnoc_cfg, 1531 &qss_nsp_qtb_cfg, &qss_pcie_anoc_cfg, 1532 &srvc_cnoc_cfg, &xs_qdss_stm, 1533 &xs_sys_tcu_cfg, &qnm_gemnoc_cnoc, 1534 &qnm_gemnoc_pcie, &qhs_aoss, 1535 &qhs_ipa, &qhs_ipc_router, 1536 &qhs_tme_cfg, &qss_apss, 1537 &qss_cfg, &qss_ddrss_cfg, 1538 &qxs_imem, &srvc_cnoc_main, 1539 &xs_pcie_0, &xs_pcie_1 }, 1540 }; 1541 1542 static struct qcom_icc_bcm bcm_co0 = { 1543 .name = "CO0", 1544 .enable_mask = BIT(0), 1545 .num_nodes = 2, 1546 .nodes = { &qnm_nsp, &qns_nsp_gemnoc }, 1547 }; 1548 1549 static struct qcom_icc_bcm bcm_lp0 = { 1550 .name = "LP0", 1551 .num_nodes = 2, 1552 .nodes = { &qnm_lpass_lpinoc, &qns_lpass_aggnoc }, 1553 }; 1554 1555 static struct qcom_icc_bcm bcm_mc0 = { 1556 .name = "MC0", 1557 .keepalive = true, 1558 .num_nodes = 1, 1559 .nodes = { &ebi }, 1560 }; 1561 1562 static struct qcom_icc_bcm bcm_mm0 = { 1563 .name = "MM0", 1564 .num_nodes = 1, 1565 .nodes = { &qns_mem_noc_hf }, 1566 }; 1567 1568 static struct qcom_icc_bcm bcm_mm1 = { 1569 .name = "MM1", 1570 .enable_mask = BIT(0), 1571 .num_nodes = 8, 1572 .nodes = { &qnm_camnoc_hf, &qnm_camnoc_icp, 1573 &qnm_camnoc_sf, &qnm_vapss_hcp, 1574 &qnm_video_cv_cpu, &qnm_video_cvp, 1575 &qnm_video_v_cpu, &qns_mem_noc_sf }, 1576 }; 1577 1578 static struct qcom_icc_bcm bcm_qup0 = { 1579 .name = "QUP0", 1580 .keepalive = true, 1581 .vote_scale = 1, 1582 .num_nodes = 1, 1583 .nodes = { &qup0_core_slave }, 1584 }; 1585 1586 static struct qcom_icc_bcm bcm_qup1 = { 1587 .name = "QUP1", 1588 .keepalive = true, 1589 .vote_scale = 1, 1590 .num_nodes = 1, 1591 .nodes = { &qup1_core_slave }, 1592 }; 1593 1594 static struct qcom_icc_bcm bcm_qup2 = { 1595 .name = "QUP2", 1596 .keepalive = true, 1597 .vote_scale = 1, 1598 .num_nodes = 1, 1599 .nodes = { &qup2_core_slave }, 1600 }; 1601 1602 static struct qcom_icc_bcm bcm_sh0 = { 1603 .name = "SH0", 1604 .keepalive = true, 1605 .num_nodes = 1, 1606 .nodes = { &qns_llcc }, 1607 }; 1608 1609 static struct qcom_icc_bcm bcm_sh1 = { 1610 .name = "SH1", 1611 .enable_mask = BIT(0), 1612 .num_nodes = 15, 1613 .nodes = { &alm_gpu_tcu, &alm_sys_tcu, 1614 &alm_ubwc_p_tcu, &chm_apps, 1615 &qnm_gpu, &qnm_mdsp, 1616 &qnm_mnoc_hf, &qnm_mnoc_sf, 1617 &qnm_nsp_gemnoc, &qnm_pcie, 1618 &qnm_snoc_sf, &qnm_ubwc_p, 1619 &xm_gic, &qns_gem_noc_cnoc, 1620 &qns_pcie }, 1621 }; 1622 1623 static struct qcom_icc_bcm bcm_sn0 = { 1624 .name = "SN0", 1625 .keepalive = true, 1626 .num_nodes = 1, 1627 .nodes = { &qns_gemnoc_sf }, 1628 }; 1629 1630 static struct qcom_icc_bcm bcm_sn2 = { 1631 .name = "SN2", 1632 .num_nodes = 1, 1633 .nodes = { &qnm_aggre1_noc }, 1634 }; 1635 1636 static struct qcom_icc_bcm bcm_sn3 = { 1637 .name = "SN3", 1638 .num_nodes = 1, 1639 .nodes = { &qnm_aggre2_noc }, 1640 }; 1641 1642 static struct qcom_icc_bcm bcm_sn4 = { 1643 .name = "SN4", 1644 .num_nodes = 1, 1645 .nodes = { &qns_pcie_mem_noc }, 1646 }; 1647 1648 static struct qcom_icc_node * const aggre1_noc_nodes[] = { 1649 [MASTER_QSPI_0] = &qhm_qspi, 1650 [MASTER_QUP_1] = &qhm_qup1, 1651 [MASTER_QUP_3] = &qxm_qup02, 1652 [MASTER_SDCC_4] = &xm_sdc4, 1653 [MASTER_UFS_MEM] = &xm_ufs_mem, 1654 [MASTER_USB3_0] = &xm_usb3_0, 1655 [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc, 1656 }; 1657 1658 static const struct qcom_icc_desc sm8650_aggre1_noc = { 1659 .config = &icc_regmap_config, 1660 .nodes = aggre1_noc_nodes, 1661 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), 1662 }; 1663 1664 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { 1665 &bcm_ce0, 1666 }; 1667 1668 static struct qcom_icc_node * const aggre2_noc_nodes[] = { 1669 [MASTER_QDSS_BAM] = &qhm_qdss_bam, 1670 [MASTER_QUP_2] = &qhm_qup2, 1671 [MASTER_CRYPTO] = &qxm_crypto, 1672 [MASTER_IPA] = &qxm_ipa, 1673 [MASTER_SP] = &qxm_sp, 1674 [MASTER_QDSS_ETR] = &xm_qdss_etr_0, 1675 [MASTER_QDSS_ETR_1] = &xm_qdss_etr_1, 1676 [MASTER_SDCC_2] = &xm_sdc2, 1677 [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc, 1678 }; 1679 1680 static const struct qcom_icc_desc sm8650_aggre2_noc = { 1681 .config = &icc_regmap_config, 1682 .nodes = aggre2_noc_nodes, 1683 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), 1684 .bcms = aggre2_noc_bcms, 1685 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), 1686 }; 1687 1688 static struct qcom_icc_bcm * const clk_virt_bcms[] = { 1689 &bcm_qup0, 1690 &bcm_qup1, 1691 &bcm_qup2, 1692 }; 1693 1694 static struct qcom_icc_node * const clk_virt_nodes[] = { 1695 [MASTER_QUP_CORE_0] = &qup0_core_master, 1696 [MASTER_QUP_CORE_1] = &qup1_core_master, 1697 [MASTER_QUP_CORE_2] = &qup2_core_master, 1698 [SLAVE_QUP_CORE_0] = &qup0_core_slave, 1699 [SLAVE_QUP_CORE_1] = &qup1_core_slave, 1700 [SLAVE_QUP_CORE_2] = &qup2_core_slave, 1701 }; 1702 1703 static const struct qcom_icc_desc sm8650_clk_virt = { 1704 .nodes = clk_virt_nodes, 1705 .num_nodes = ARRAY_SIZE(clk_virt_nodes), 1706 .bcms = clk_virt_bcms, 1707 .num_bcms = ARRAY_SIZE(clk_virt_bcms), 1708 }; 1709 1710 static struct qcom_icc_bcm * const config_noc_bcms[] = { 1711 &bcm_cn0, 1712 }; 1713 1714 static struct qcom_icc_node * const config_noc_nodes[] = { 1715 [MASTER_CNOC_CFG] = &qsm_cfg, 1716 [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0, 1717 [SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1, 1718 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, 1719 [SLAVE_CLK_CTL] = &qhs_clk_ctl, 1720 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx, 1721 [SLAVE_CPR_HMX] = &qhs_cpr_hmx, 1722 [SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx, 1723 [SLAVE_RBCPR_MXA_CFG] = &qhs_cpr_mxa, 1724 [SLAVE_RBCPR_MXC_CFG] = &qhs_cpr_mxc, 1725 [SLAVE_CPR_NSPCX] = &qhs_cpr_nspcx, 1726 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, 1727 [SLAVE_CX_RDPM] = &qhs_cx_rdpm, 1728 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg, 1729 [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg, 1730 [SLAVE_I2C] = &qhs_i2c, 1731 [SLAVE_I3C_IBI0_CFG] = &qhs_i3c_ibi0_cfg, 1732 [SLAVE_I3C_IBI1_CFG] = &qhs_i3c_ibi1_cfg, 1733 [SLAVE_IMEM_CFG] = &qhs_imem_cfg, 1734 [SLAVE_CNOC_MSS] = &qhs_mss_cfg, 1735 [SLAVE_MX_2_RDPM] = &qhs_mx_2_rdpm, 1736 [SLAVE_MX_RDPM] = &qhs_mx_rdpm, 1737 [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg, 1738 [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg, 1739 [SLAVE_PCIE_RSCC] = &qhs_pcie_rscc, 1740 [SLAVE_PDM] = &qhs_pdm, 1741 [SLAVE_PRNG] = &qhs_prng, 1742 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, 1743 [SLAVE_QSPI_0] = &qhs_qspi, 1744 [SLAVE_QUP_3] = &qhs_qup02, 1745 [SLAVE_QUP_1] = &qhs_qup1, 1746 [SLAVE_QUP_2] = &qhs_qup2, 1747 [SLAVE_SDCC_2] = &qhs_sdc2, 1748 [SLAVE_SDCC_4] = &qhs_sdc4, 1749 [SLAVE_SPSS_CFG] = &qhs_spss_cfg, 1750 [SLAVE_TCSR] = &qhs_tcsr, 1751 [SLAVE_TLMM] = &qhs_tlmm, 1752 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, 1753 [SLAVE_USB3_0] = &qhs_usb3_0, 1754 [SLAVE_VENUS_CFG] = &qhs_venus_cfg, 1755 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, 1756 [SLAVE_CNOC_MNOC_CFG] = &qss_mnoc_cfg, 1757 [SLAVE_NSP_QTB_CFG] = &qss_nsp_qtb_cfg, 1758 [SLAVE_PCIE_ANOC_CFG] = &qss_pcie_anoc_cfg, 1759 [SLAVE_SERVICE_CNOC_CFG] = &srvc_cnoc_cfg, 1760 [SLAVE_QDSS_STM] = &xs_qdss_stm, 1761 [SLAVE_TCU] = &xs_sys_tcu_cfg, 1762 }; 1763 1764 static const struct qcom_icc_desc sm8650_config_noc = { 1765 .config = &icc_regmap_config, 1766 .nodes = config_noc_nodes, 1767 .num_nodes = ARRAY_SIZE(config_noc_nodes), 1768 .bcms = config_noc_bcms, 1769 .num_bcms = ARRAY_SIZE(config_noc_bcms), 1770 }; 1771 1772 static struct qcom_icc_bcm * const cnoc_main_bcms[] = { 1773 &bcm_cn0, 1774 }; 1775 1776 static struct qcom_icc_node * const cnoc_main_nodes[] = { 1777 [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc, 1778 [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie, 1779 [SLAVE_AOSS] = &qhs_aoss, 1780 [SLAVE_IPA_CFG] = &qhs_ipa, 1781 [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router, 1782 [SLAVE_TME_CFG] = &qhs_tme_cfg, 1783 [SLAVE_APPSS] = &qss_apss, 1784 [SLAVE_CNOC_CFG] = &qss_cfg, 1785 [SLAVE_DDRSS_CFG] = &qss_ddrss_cfg, 1786 [SLAVE_IMEM] = &qxs_imem, 1787 [SLAVE_SERVICE_CNOC] = &srvc_cnoc_main, 1788 [SLAVE_PCIE_0] = &xs_pcie_0, 1789 [SLAVE_PCIE_1] = &xs_pcie_1, 1790 }; 1791 1792 static const struct qcom_icc_desc sm8650_cnoc_main = { 1793 .config = &icc_regmap_config, 1794 .nodes = cnoc_main_nodes, 1795 .num_nodes = ARRAY_SIZE(cnoc_main_nodes), 1796 .bcms = cnoc_main_bcms, 1797 .num_bcms = ARRAY_SIZE(cnoc_main_bcms), 1798 }; 1799 1800 static struct qcom_icc_bcm * const gem_noc_bcms[] = { 1801 &bcm_sh0, 1802 &bcm_sh1, 1803 }; 1804 1805 static struct qcom_icc_node * const gem_noc_nodes[] = { 1806 [MASTER_GPU_TCU] = &alm_gpu_tcu, 1807 [MASTER_SYS_TCU] = &alm_sys_tcu, 1808 [MASTER_UBWC_P_TCU] = &alm_ubwc_p_tcu, 1809 [MASTER_APPSS_PROC] = &chm_apps, 1810 [MASTER_GFX3D] = &qnm_gpu, 1811 [MASTER_LPASS_GEM_NOC] = &qnm_lpass_gemnoc, 1812 [MASTER_MSS_PROC] = &qnm_mdsp, 1813 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, 1814 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, 1815 [MASTER_COMPUTE_NOC] = &qnm_nsp_gemnoc, 1816 [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie, 1817 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, 1818 [MASTER_UBWC_P] = &qnm_ubwc_p, 1819 [MASTER_GIC] = &xm_gic, 1820 [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc, 1821 [SLAVE_LLCC] = &qns_llcc, 1822 [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie, 1823 }; 1824 1825 static const struct qcom_icc_desc sm8650_gem_noc = { 1826 .config = &icc_regmap_config, 1827 .nodes = gem_noc_nodes, 1828 .num_nodes = ARRAY_SIZE(gem_noc_nodes), 1829 .bcms = gem_noc_bcms, 1830 .num_bcms = ARRAY_SIZE(gem_noc_bcms), 1831 }; 1832 1833 static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { 1834 [MASTER_LPIAON_NOC] = &qnm_lpiaon_noc, 1835 [SLAVE_LPASS_GEM_NOC] = &qns_lpass_ag_noc_gemnoc, 1836 }; 1837 1838 static const struct qcom_icc_desc sm8650_lpass_ag_noc = { 1839 .config = &icc_regmap_config, 1840 .nodes = lpass_ag_noc_nodes, 1841 .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), 1842 }; 1843 1844 static struct qcom_icc_bcm * const lpass_lpiaon_noc_bcms[] = { 1845 &bcm_lp0, 1846 }; 1847 1848 static struct qcom_icc_node * const lpass_lpiaon_noc_nodes[] = { 1849 [MASTER_LPASS_LPINOC] = &qnm_lpass_lpinoc, 1850 [SLAVE_LPIAON_NOC_LPASS_AG_NOC] = &qns_lpass_aggnoc, 1851 }; 1852 1853 static const struct qcom_icc_desc sm8650_lpass_lpiaon_noc = { 1854 .config = &icc_regmap_config, 1855 .nodes = lpass_lpiaon_noc_nodes, 1856 .num_nodes = ARRAY_SIZE(lpass_lpiaon_noc_nodes), 1857 .bcms = lpass_lpiaon_noc_bcms, 1858 .num_bcms = ARRAY_SIZE(lpass_lpiaon_noc_bcms), 1859 }; 1860 1861 static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] = { 1862 [MASTER_LPASS_PROC] = &qxm_lpinoc_dsp_axim, 1863 [SLAVE_LPICX_NOC_LPIAON_NOC] = &qns_lpi_aon_noc, 1864 }; 1865 1866 static const struct qcom_icc_desc sm8650_lpass_lpicx_noc = { 1867 .config = &icc_regmap_config, 1868 .nodes = lpass_lpicx_noc_nodes, 1869 .num_nodes = ARRAY_SIZE(lpass_lpicx_noc_nodes), 1870 }; 1871 1872 static struct qcom_icc_bcm * const mc_virt_bcms[] = { 1873 &bcm_acv, 1874 &bcm_mc0, 1875 }; 1876 1877 static struct qcom_icc_node * const mc_virt_nodes[] = { 1878 [MASTER_LLCC] = &llcc_mc, 1879 [SLAVE_EBI1] = &ebi, 1880 }; 1881 1882 static const struct qcom_icc_desc sm8650_mc_virt = { 1883 .nodes = mc_virt_nodes, 1884 .num_nodes = ARRAY_SIZE(mc_virt_nodes), 1885 .bcms = mc_virt_bcms, 1886 .num_bcms = ARRAY_SIZE(mc_virt_bcms), 1887 }; 1888 1889 static struct qcom_icc_bcm * const mmss_noc_bcms[] = { 1890 &bcm_mm0, 1891 &bcm_mm1, 1892 }; 1893 1894 static struct qcom_icc_node * const mmss_noc_nodes[] = { 1895 [MASTER_CAMNOC_HF] = &qnm_camnoc_hf, 1896 [MASTER_CAMNOC_ICP] = &qnm_camnoc_icp, 1897 [MASTER_CAMNOC_SF] = &qnm_camnoc_sf, 1898 [MASTER_MDP] = &qnm_mdp, 1899 [MASTER_CDSP_HCP] = &qnm_vapss_hcp, 1900 [MASTER_VIDEO] = &qnm_video, 1901 [MASTER_VIDEO_CV_PROC] = &qnm_video_cv_cpu, 1902 [MASTER_VIDEO_PROC] = &qnm_video_cvp, 1903 [MASTER_VIDEO_V_PROC] = &qnm_video_v_cpu, 1904 [MASTER_CNOC_MNOC_CFG] = &qsm_mnoc_cfg, 1905 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, 1906 [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf, 1907 [SLAVE_SERVICE_MNOC] = &srvc_mnoc, 1908 }; 1909 1910 static const struct qcom_icc_desc sm8650_mmss_noc = { 1911 .config = &icc_regmap_config, 1912 .nodes = mmss_noc_nodes, 1913 .num_nodes = ARRAY_SIZE(mmss_noc_nodes), 1914 .bcms = mmss_noc_bcms, 1915 .num_bcms = ARRAY_SIZE(mmss_noc_bcms), 1916 }; 1917 1918 static struct qcom_icc_bcm * const nsp_noc_bcms[] = { 1919 &bcm_co0, 1920 }; 1921 1922 static struct qcom_icc_node * const nsp_noc_nodes[] = { 1923 [MASTER_CDSP_PROC] = &qnm_nsp, 1924 [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc, 1925 }; 1926 1927 static const struct qcom_icc_desc sm8650_nsp_noc = { 1928 .config = &icc_regmap_config, 1929 .nodes = nsp_noc_nodes, 1930 .num_nodes = ARRAY_SIZE(nsp_noc_nodes), 1931 .bcms = nsp_noc_bcms, 1932 .num_bcms = ARRAY_SIZE(nsp_noc_bcms), 1933 }; 1934 1935 static struct qcom_icc_bcm * const pcie_anoc_bcms[] = { 1936 &bcm_sn4, 1937 }; 1938 1939 static struct qcom_icc_node * const pcie_anoc_nodes[] = { 1940 [MASTER_PCIE_ANOC_CFG] = &qsm_pcie_anoc_cfg, 1941 [MASTER_PCIE_0] = &xm_pcie3_0, 1942 [MASTER_PCIE_1] = &xm_pcie3_1, 1943 [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc, 1944 [SLAVE_SERVICE_PCIE_ANOC] = &srvc_pcie_aggre_noc, 1945 }; 1946 1947 static const struct qcom_icc_desc sm8650_pcie_anoc = { 1948 .config = &icc_regmap_config, 1949 .nodes = pcie_anoc_nodes, 1950 .num_nodes = ARRAY_SIZE(pcie_anoc_nodes), 1951 .bcms = pcie_anoc_bcms, 1952 .num_bcms = ARRAY_SIZE(pcie_anoc_bcms), 1953 }; 1954 1955 static struct qcom_icc_bcm * const system_noc_bcms[] = { 1956 &bcm_sn0, 1957 &bcm_sn2, 1958 &bcm_sn3, 1959 }; 1960 1961 static struct qcom_icc_node * const system_noc_nodes[] = { 1962 [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc, 1963 [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc, 1964 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, 1965 [MASTER_APSS_NOC] = &qnm_apss_noc, 1966 }; 1967 1968 static const struct qcom_icc_desc sm8650_system_noc = { 1969 .config = &icc_regmap_config, 1970 .nodes = system_noc_nodes, 1971 .num_nodes = ARRAY_SIZE(system_noc_nodes), 1972 .bcms = system_noc_bcms, 1973 .num_bcms = ARRAY_SIZE(system_noc_bcms), 1974 }; 1975 1976 static const struct of_device_id qnoc_of_match[] = { 1977 { .compatible = "qcom,sm8650-aggre1-noc", .data = &sm8650_aggre1_noc }, 1978 { .compatible = "qcom,sm8650-aggre2-noc", .data = &sm8650_aggre2_noc }, 1979 { .compatible = "qcom,sm8650-clk-virt", .data = &sm8650_clk_virt }, 1980 { .compatible = "qcom,sm8650-config-noc", .data = &sm8650_config_noc }, 1981 { .compatible = "qcom,sm8650-cnoc-main", .data = &sm8650_cnoc_main }, 1982 { .compatible = "qcom,sm8650-gem-noc", .data = &sm8650_gem_noc }, 1983 { .compatible = "qcom,sm8650-lpass-ag-noc", .data = &sm8650_lpass_ag_noc }, 1984 { .compatible = "qcom,sm8650-lpass-lpiaon-noc", .data = &sm8650_lpass_lpiaon_noc }, 1985 { .compatible = "qcom,sm8650-lpass-lpicx-noc", .data = &sm8650_lpass_lpicx_noc }, 1986 { .compatible = "qcom,sm8650-mc-virt", .data = &sm8650_mc_virt }, 1987 { .compatible = "qcom,sm8650-mmss-noc", .data = &sm8650_mmss_noc }, 1988 { .compatible = "qcom,sm8650-nsp-noc", .data = &sm8650_nsp_noc }, 1989 { .compatible = "qcom,sm8650-pcie-anoc", .data = &sm8650_pcie_anoc }, 1990 { .compatible = "qcom,sm8650-system-noc", .data = &sm8650_system_noc }, 1991 { } 1992 }; 1993 MODULE_DEVICE_TABLE(of, qnoc_of_match); 1994 1995 static struct platform_driver qnoc_driver = { 1996 .probe = qcom_icc_rpmh_probe, 1997 .remove = qcom_icc_rpmh_remove, 1998 .driver = { 1999 .name = "qnoc-sm8650", 2000 .of_match_table = qnoc_of_match, 2001 .sync_state = icc_sync_state, 2002 }, 2003 }; 2004 2005 static int __init qnoc_driver_init(void) 2006 { 2007 return platform_driver_register(&qnoc_driver); 2008 } 2009 core_initcall(qnoc_driver_init); 2010 2011 static void __exit qnoc_driver_exit(void) 2012 { 2013 platform_driver_unregister(&qnoc_driver); 2014 } 2015 module_exit(qnoc_driver_exit); 2016 2017 MODULE_DESCRIPTION("sm8650 NoC driver"); 2018 MODULE_LICENSE("GPL"); 2019