1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 5 * Copyright (c) 2023, Linaro Limited 6 */ 7 8 #include <linux/device.h> 9 #include <linux/interconnect.h> 10 #include <linux/interconnect-provider.h> 11 #include <linux/module.h> 12 #include <linux/of_platform.h> 13 #include <dt-bindings/interconnect/qcom,sm8650-rpmh.h> 14 15 #include "bcm-voter.h" 16 #include "icc-common.h" 17 #include "icc-rpmh.h" 18 19 static struct qcom_icc_node qhm_qspi; 20 static struct qcom_icc_node qhm_qup1; 21 static struct qcom_icc_node qxm_qup02; 22 static struct qcom_icc_node xm_sdc4; 23 static struct qcom_icc_node xm_ufs_mem; 24 static struct qcom_icc_node xm_usb3_0; 25 static struct qcom_icc_node qhm_qdss_bam; 26 static struct qcom_icc_node qhm_qup2; 27 static struct qcom_icc_node qxm_crypto; 28 static struct qcom_icc_node qxm_ipa; 29 static struct qcom_icc_node qxm_sp; 30 static struct qcom_icc_node xm_qdss_etr_0; 31 static struct qcom_icc_node xm_qdss_etr_1; 32 static struct qcom_icc_node xm_sdc2; 33 static struct qcom_icc_node qup0_core_master; 34 static struct qcom_icc_node qup1_core_master; 35 static struct qcom_icc_node qup2_core_master; 36 static struct qcom_icc_node qsm_cfg; 37 static struct qcom_icc_node qnm_gemnoc_cnoc; 38 static struct qcom_icc_node qnm_gemnoc_pcie; 39 static struct qcom_icc_node alm_gpu_tcu; 40 static struct qcom_icc_node alm_sys_tcu; 41 static struct qcom_icc_node alm_ubwc_p_tcu; 42 static struct qcom_icc_node chm_apps; 43 static struct qcom_icc_node qnm_gpu; 44 static struct qcom_icc_node qnm_lpass_gemnoc; 45 static struct qcom_icc_node qnm_mdsp; 46 static struct qcom_icc_node qnm_mnoc_hf; 47 static struct qcom_icc_node qnm_mnoc_sf; 48 static struct qcom_icc_node qnm_nsp_gemnoc; 49 static struct qcom_icc_node qnm_pcie; 50 static struct qcom_icc_node qnm_snoc_sf; 51 static struct qcom_icc_node qnm_ubwc_p; 52 static struct qcom_icc_node xm_gic; 53 static struct qcom_icc_node qnm_lpiaon_noc; 54 static struct qcom_icc_node qnm_lpass_lpinoc; 55 static struct qcom_icc_node qxm_lpinoc_dsp_axim; 56 static struct qcom_icc_node llcc_mc; 57 static struct qcom_icc_node qnm_camnoc_hf; 58 static struct qcom_icc_node qnm_camnoc_icp; 59 static struct qcom_icc_node qnm_camnoc_sf; 60 static struct qcom_icc_node qnm_mdp; 61 static struct qcom_icc_node qnm_vapss_hcp; 62 static struct qcom_icc_node qnm_video; 63 static struct qcom_icc_node qnm_video_cv_cpu; 64 static struct qcom_icc_node qnm_video_cvp; 65 static struct qcom_icc_node qnm_video_v_cpu; 66 static struct qcom_icc_node qsm_mnoc_cfg; 67 static struct qcom_icc_node qnm_nsp; 68 static struct qcom_icc_node qsm_pcie_anoc_cfg; 69 static struct qcom_icc_node xm_pcie3_0; 70 static struct qcom_icc_node xm_pcie3_1; 71 static struct qcom_icc_node qnm_aggre1_noc; 72 static struct qcom_icc_node qnm_aggre2_noc; 73 static struct qcom_icc_node qnm_apss_noc; 74 static struct qcom_icc_node qns_a1noc_snoc; 75 static struct qcom_icc_node qns_a2noc_snoc; 76 static struct qcom_icc_node qup0_core_slave; 77 static struct qcom_icc_node qup1_core_slave; 78 static struct qcom_icc_node qup2_core_slave; 79 static struct qcom_icc_node qhs_ahb2phy0; 80 static struct qcom_icc_node qhs_ahb2phy1; 81 static struct qcom_icc_node qhs_camera_cfg; 82 static struct qcom_icc_node qhs_clk_ctl; 83 static struct qcom_icc_node qhs_cpr_cx; 84 static struct qcom_icc_node qhs_cpr_hmx; 85 static struct qcom_icc_node qhs_cpr_mmcx; 86 static struct qcom_icc_node qhs_cpr_mxa; 87 static struct qcom_icc_node qhs_cpr_mxc; 88 static struct qcom_icc_node qhs_cpr_nspcx; 89 static struct qcom_icc_node qhs_crypto0_cfg; 90 static struct qcom_icc_node qhs_cx_rdpm; 91 static struct qcom_icc_node qhs_display_cfg; 92 static struct qcom_icc_node qhs_gpuss_cfg; 93 static struct qcom_icc_node qhs_i2c; 94 static struct qcom_icc_node qhs_i3c_ibi0_cfg; 95 static struct qcom_icc_node qhs_i3c_ibi1_cfg; 96 static struct qcom_icc_node qhs_imem_cfg; 97 static struct qcom_icc_node qhs_mss_cfg; 98 static struct qcom_icc_node qhs_mx_2_rdpm; 99 static struct qcom_icc_node qhs_mx_rdpm; 100 static struct qcom_icc_node qhs_pcie0_cfg; 101 static struct qcom_icc_node qhs_pcie1_cfg; 102 static struct qcom_icc_node qhs_pcie_rscc; 103 static struct qcom_icc_node qhs_pdm; 104 static struct qcom_icc_node qhs_prng; 105 static struct qcom_icc_node qhs_qdss_cfg; 106 static struct qcom_icc_node qhs_qspi; 107 static struct qcom_icc_node qhs_qup02; 108 static struct qcom_icc_node qhs_qup1; 109 static struct qcom_icc_node qhs_qup2; 110 static struct qcom_icc_node qhs_sdc2; 111 static struct qcom_icc_node qhs_sdc4; 112 static struct qcom_icc_node qhs_spss_cfg; 113 static struct qcom_icc_node qhs_tcsr; 114 static struct qcom_icc_node qhs_tlmm; 115 static struct qcom_icc_node qhs_ufs_mem_cfg; 116 static struct qcom_icc_node qhs_usb3_0; 117 static struct qcom_icc_node qhs_venus_cfg; 118 static struct qcom_icc_node qhs_vsense_ctrl_cfg; 119 static struct qcom_icc_node qss_mnoc_cfg; 120 static struct qcom_icc_node qss_nsp_qtb_cfg; 121 static struct qcom_icc_node qss_pcie_anoc_cfg; 122 static struct qcom_icc_node srvc_cnoc_cfg; 123 static struct qcom_icc_node xs_qdss_stm; 124 static struct qcom_icc_node xs_sys_tcu_cfg; 125 static struct qcom_icc_node qhs_aoss; 126 static struct qcom_icc_node qhs_ipa; 127 static struct qcom_icc_node qhs_ipc_router; 128 static struct qcom_icc_node qhs_tme_cfg; 129 static struct qcom_icc_node qss_apss; 130 static struct qcom_icc_node qss_cfg; 131 static struct qcom_icc_node qss_ddrss_cfg; 132 static struct qcom_icc_node qxs_imem; 133 static struct qcom_icc_node srvc_cnoc_main; 134 static struct qcom_icc_node xs_pcie_0; 135 static struct qcom_icc_node xs_pcie_1; 136 static struct qcom_icc_node qns_gem_noc_cnoc; 137 static struct qcom_icc_node qns_llcc; 138 static struct qcom_icc_node qns_pcie; 139 static struct qcom_icc_node qns_lpass_ag_noc_gemnoc; 140 static struct qcom_icc_node qns_lpass_aggnoc; 141 static struct qcom_icc_node qns_lpi_aon_noc; 142 static struct qcom_icc_node ebi; 143 static struct qcom_icc_node qns_mem_noc_hf; 144 static struct qcom_icc_node qns_mem_noc_sf; 145 static struct qcom_icc_node srvc_mnoc; 146 static struct qcom_icc_node qns_nsp_gemnoc; 147 static struct qcom_icc_node qns_pcie_mem_noc; 148 static struct qcom_icc_node srvc_pcie_aggre_noc; 149 static struct qcom_icc_node qns_gemnoc_sf; 150 static const struct regmap_config icc_regmap_config = { 151 .reg_bits = 32, 152 .reg_stride = 4, 153 .val_bits = 32, 154 .fast_io = true, 155 }; 156 157 static struct qcom_icc_qosbox qhm_qspi_qos = { 158 .num_ports = 1, 159 .port_offsets = { 0xc000 }, 160 .prio = 2, 161 .urg_fwd = 0, 162 .prio_fwd_disable = 0, 163 }; 164 165 static struct qcom_icc_node qhm_qspi = { 166 .name = "qhm_qspi", 167 .channels = 1, 168 .buswidth = 4, 169 .qosbox = &qhm_qspi_qos, 170 .num_links = 1, 171 .link_nodes = { &qns_a1noc_snoc }, 172 }; 173 174 static struct qcom_icc_qosbox qhm_qup1_qos = { 175 .num_ports = 1, 176 .port_offsets = { 0xd000 }, 177 .prio = 2, 178 .urg_fwd = 0, 179 .prio_fwd_disable = 0, 180 }; 181 182 static struct qcom_icc_node qhm_qup1 = { 183 .name = "qhm_qup1", 184 .channels = 1, 185 .buswidth = 4, 186 .qosbox = &qhm_qup1_qos, 187 .num_links = 1, 188 .link_nodes = { &qns_a1noc_snoc }, 189 }; 190 191 static struct qcom_icc_node qxm_qup02 = { 192 .name = "qxm_qup02", 193 .channels = 1, 194 .buswidth = 8, 195 .num_links = 1, 196 .link_nodes = { &qns_a1noc_snoc }, 197 }; 198 199 static struct qcom_icc_qosbox xm_sdc4_qos = { 200 .num_ports = 1, 201 .port_offsets = { 0xe000 }, 202 .prio = 2, 203 .urg_fwd = 0, 204 .prio_fwd_disable = 0, 205 }; 206 207 static struct qcom_icc_node xm_sdc4 = { 208 .name = "xm_sdc4", 209 .channels = 1, 210 .buswidth = 8, 211 .qosbox = &xm_sdc4_qos, 212 .num_links = 1, 213 .link_nodes = { &qns_a1noc_snoc }, 214 }; 215 216 static struct qcom_icc_qosbox xm_ufs_mem_qos = { 217 .num_ports = 1, 218 .port_offsets = { 0xf000 }, 219 .prio = 2, 220 .urg_fwd = 0, 221 .prio_fwd_disable = 0, 222 }; 223 224 static struct qcom_icc_node xm_ufs_mem = { 225 .name = "xm_ufs_mem", 226 .channels = 1, 227 .buswidth = 16, 228 .qosbox = &xm_ufs_mem_qos, 229 .num_links = 1, 230 .link_nodes = { &qns_a1noc_snoc }, 231 }; 232 233 static struct qcom_icc_qosbox xm_usb3_0_qos = { 234 .num_ports = 1, 235 .port_offsets = { 0x10000 }, 236 .prio = 2, 237 .urg_fwd = 0, 238 .prio_fwd_disable = 0, 239 }; 240 241 static struct qcom_icc_node xm_usb3_0 = { 242 .name = "xm_usb3_0", 243 .channels = 1, 244 .buswidth = 8, 245 .qosbox = &xm_usb3_0_qos, 246 .num_links = 1, 247 .link_nodes = { &qns_a1noc_snoc }, 248 }; 249 250 static struct qcom_icc_qosbox qhm_qdss_bam_qos = { 251 .num_ports = 1, 252 .port_offsets = { 0x12000 }, 253 .prio = 2, 254 .urg_fwd = 0, 255 .prio_fwd_disable = 0, 256 }; 257 258 static struct qcom_icc_node qhm_qdss_bam = { 259 .name = "qhm_qdss_bam", 260 .channels = 1, 261 .buswidth = 4, 262 .qosbox = &qhm_qdss_bam_qos, 263 .num_links = 1, 264 .link_nodes = { &qns_a2noc_snoc }, 265 }; 266 267 static struct qcom_icc_qosbox qhm_qup2_qos = { 268 .num_ports = 1, 269 .port_offsets = { 0x13000 }, 270 .prio = 2, 271 .urg_fwd = 0, 272 .prio_fwd_disable = 0, 273 }; 274 275 static struct qcom_icc_node qhm_qup2 = { 276 .name = "qhm_qup2", 277 .channels = 1, 278 .buswidth = 4, 279 .qosbox = &qhm_qup2_qos, 280 .num_links = 1, 281 .link_nodes = { &qns_a2noc_snoc }, 282 }; 283 284 static struct qcom_icc_qosbox qxm_crypto_qos = { 285 .num_ports = 1, 286 .port_offsets = { 0x15000 }, 287 .prio = 2, 288 .urg_fwd = 1, 289 .prio_fwd_disable = 0, 290 }; 291 292 static struct qcom_icc_node qxm_crypto = { 293 .name = "qxm_crypto", 294 .channels = 1, 295 .buswidth = 8, 296 .qosbox = &qxm_crypto_qos, 297 .num_links = 1, 298 .link_nodes = { &qns_a2noc_snoc }, 299 }; 300 301 static struct qcom_icc_qosbox qxm_ipa_qos = { 302 .num_ports = 1, 303 .port_offsets = { 0x16000 }, 304 .prio = 2, 305 .urg_fwd = 1, 306 .prio_fwd_disable = 0, 307 }; 308 309 static struct qcom_icc_node qxm_ipa = { 310 .name = "qxm_ipa", 311 .channels = 1, 312 .buswidth = 8, 313 .qosbox = &qxm_ipa_qos, 314 .num_links = 1, 315 .link_nodes = { &qns_a2noc_snoc }, 316 }; 317 318 static struct qcom_icc_node qxm_sp = { 319 .name = "qxm_sp", 320 .channels = 1, 321 .buswidth = 8, 322 .num_links = 1, 323 .link_nodes = { &qns_a2noc_snoc }, 324 }; 325 326 static struct qcom_icc_qosbox xm_qdss_etr_0_qos = { 327 .num_ports = 1, 328 .port_offsets = { 0x17000 }, 329 .prio = 2, 330 .urg_fwd = 0, 331 .prio_fwd_disable = 0, 332 }; 333 334 static struct qcom_icc_node xm_qdss_etr_0 = { 335 .name = "xm_qdss_etr_0", 336 .channels = 1, 337 .buswidth = 8, 338 .qosbox = &xm_qdss_etr_0_qos, 339 .num_links = 1, 340 .link_nodes = { &qns_a2noc_snoc }, 341 }; 342 343 static struct qcom_icc_qosbox xm_qdss_etr_1_qos = { 344 .num_ports = 1, 345 .port_offsets = { 0x18000 }, 346 .prio = 2, 347 .urg_fwd = 0, 348 .prio_fwd_disable = 0, 349 }; 350 351 static struct qcom_icc_node xm_qdss_etr_1 = { 352 .name = "xm_qdss_etr_1", 353 .channels = 1, 354 .buswidth = 8, 355 .qosbox = &xm_qdss_etr_1_qos, 356 .num_links = 1, 357 .link_nodes = { &qns_a2noc_snoc }, 358 }; 359 360 static struct qcom_icc_qosbox xm_sdc2_qos = { 361 .num_ports = 1, 362 .port_offsets = { 0x19000 }, 363 .prio = 2, 364 .urg_fwd = 0, 365 .prio_fwd_disable = 0, 366 }; 367 368 static struct qcom_icc_node xm_sdc2 = { 369 .name = "xm_sdc2", 370 .channels = 1, 371 .buswidth = 8, 372 .qosbox = &xm_sdc2_qos, 373 .num_links = 1, 374 .link_nodes = { &qns_a2noc_snoc }, 375 }; 376 377 static struct qcom_icc_node qup0_core_master = { 378 .name = "qup0_core_master", 379 .channels = 1, 380 .buswidth = 4, 381 .num_links = 1, 382 .link_nodes = { &qup0_core_slave }, 383 }; 384 385 static struct qcom_icc_node qup1_core_master = { 386 .name = "qup1_core_master", 387 .channels = 1, 388 .buswidth = 4, 389 .num_links = 1, 390 .link_nodes = { &qup1_core_slave }, 391 }; 392 393 static struct qcom_icc_node qup2_core_master = { 394 .name = "qup2_core_master", 395 .channels = 1, 396 .buswidth = 4, 397 .num_links = 1, 398 .link_nodes = { &qup2_core_slave }, 399 }; 400 401 static struct qcom_icc_node qsm_cfg = { 402 .name = "qsm_cfg", 403 .channels = 1, 404 .buswidth = 4, 405 .num_links = 46, 406 .link_nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1, 407 &qhs_camera_cfg, &qhs_clk_ctl, 408 &qhs_cpr_cx, &qhs_cpr_hmx, 409 &qhs_cpr_mmcx, &qhs_cpr_mxa, 410 &qhs_cpr_mxc, &qhs_cpr_nspcx, 411 &qhs_crypto0_cfg, &qhs_cx_rdpm, 412 &qhs_display_cfg, &qhs_gpuss_cfg, 413 &qhs_i2c, &qhs_i3c_ibi0_cfg, 414 &qhs_i3c_ibi1_cfg, &qhs_imem_cfg, 415 &qhs_mss_cfg, &qhs_mx_2_rdpm, 416 &qhs_mx_rdpm, &qhs_pcie0_cfg, 417 &qhs_pcie1_cfg, &qhs_pcie_rscc, 418 &qhs_pdm, &qhs_prng, 419 &qhs_qdss_cfg, &qhs_qspi, 420 &qhs_qup02, &qhs_qup1, 421 &qhs_qup2, &qhs_sdc2, 422 &qhs_sdc4, &qhs_spss_cfg, 423 &qhs_tcsr, &qhs_tlmm, 424 &qhs_ufs_mem_cfg, &qhs_usb3_0, 425 &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, 426 &qss_mnoc_cfg, &qss_nsp_qtb_cfg, 427 &qss_pcie_anoc_cfg, &srvc_cnoc_cfg, 428 &xs_qdss_stm, &xs_sys_tcu_cfg }, 429 }; 430 431 static struct qcom_icc_node qnm_gemnoc_cnoc = { 432 .name = "qnm_gemnoc_cnoc", 433 .channels = 1, 434 .buswidth = 16, 435 .num_links = 9, 436 .link_nodes = { &qhs_aoss, &qhs_ipa, 437 &qhs_ipc_router, &qhs_tme_cfg, 438 &qss_apss, &qss_cfg, 439 &qss_ddrss_cfg, &qxs_imem, 440 &srvc_cnoc_main }, 441 }; 442 443 static struct qcom_icc_node qnm_gemnoc_pcie = { 444 .name = "qnm_gemnoc_pcie", 445 .channels = 1, 446 .buswidth = 16, 447 .num_links = 2, 448 .link_nodes = { &xs_pcie_0, &xs_pcie_1 }, 449 }; 450 451 static struct qcom_icc_qosbox alm_gpu_tcu_qos = { 452 .num_ports = 1, 453 .port_offsets = { 0xbf000 }, 454 .prio = 1, 455 .urg_fwd = 0, 456 .prio_fwd_disable = 1, 457 }; 458 459 static struct qcom_icc_node alm_gpu_tcu = { 460 .name = "alm_gpu_tcu", 461 .channels = 1, 462 .buswidth = 8, 463 .qosbox = &alm_gpu_tcu_qos, 464 .num_links = 2, 465 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 466 }; 467 468 static struct qcom_icc_qosbox alm_sys_tcu_qos = { 469 .num_ports = 1, 470 .port_offsets = { 0xc1000 }, 471 .prio = 6, 472 .urg_fwd = 0, 473 .prio_fwd_disable = 1, 474 }; 475 476 static struct qcom_icc_node alm_sys_tcu = { 477 .name = "alm_sys_tcu", 478 .channels = 1, 479 .buswidth = 8, 480 .qosbox = &alm_sys_tcu_qos, 481 .num_links = 2, 482 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 483 }; 484 485 static struct qcom_icc_qosbox alm_ubwc_p_tcu_qos = { 486 .num_ports = 1, 487 .port_offsets = { 0xc5000 }, 488 .prio = 1, 489 .urg_fwd = 0, 490 .prio_fwd_disable = 1, 491 }; 492 493 static struct qcom_icc_node alm_ubwc_p_tcu = { 494 .name = "alm_ubwc_p_tcu", 495 .channels = 1, 496 .buswidth = 8, 497 .qosbox = &alm_ubwc_p_tcu_qos, 498 .num_links = 2, 499 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 500 }; 501 502 static struct qcom_icc_node chm_apps = { 503 .name = "chm_apps", 504 .channels = 3, 505 .buswidth = 32, 506 .num_links = 3, 507 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, 508 &qns_pcie }, 509 }; 510 511 static struct qcom_icc_qosbox qnm_gpu_qos = { 512 .num_ports = 2, 513 .port_offsets = { 0x31000, 0x71000 }, 514 .prio = 0, 515 .urg_fwd = 1, 516 .prio_fwd_disable = 1, 517 }; 518 519 static struct qcom_icc_node qnm_gpu = { 520 .name = "qnm_gpu", 521 .channels = 2, 522 .buswidth = 32, 523 .qosbox = &qnm_gpu_qos, 524 .num_links = 2, 525 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 526 }; 527 528 static struct qcom_icc_qosbox qnm_lpass_gemnoc_qos = { 529 .num_ports = 1, 530 .port_offsets = { 0xb5000 }, 531 .prio = 0, 532 .urg_fwd = 1, 533 .prio_fwd_disable = 0, 534 }; 535 536 static struct qcom_icc_node qnm_lpass_gemnoc = { 537 .name = "qnm_lpass_gemnoc", 538 .channels = 1, 539 .buswidth = 16, 540 .qosbox = &qnm_lpass_gemnoc_qos, 541 .num_links = 3, 542 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, 543 &qns_pcie }, 544 }; 545 546 static struct qcom_icc_node qnm_mdsp = { 547 .name = "qnm_mdsp", 548 .channels = 1, 549 .buswidth = 16, 550 .num_links = 3, 551 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, 552 &qns_pcie }, 553 }; 554 555 static struct qcom_icc_qosbox qnm_mnoc_hf_qos = { 556 .num_ports = 2, 557 .port_offsets = { 0x33000, 0x73000 }, 558 .prio = 0, 559 .urg_fwd = 1, 560 .prio_fwd_disable = 0, 561 }; 562 563 static struct qcom_icc_node qnm_mnoc_hf = { 564 .name = "qnm_mnoc_hf", 565 .channels = 2, 566 .buswidth = 32, 567 .qosbox = &qnm_mnoc_hf_qos, 568 .num_links = 2, 569 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 570 }; 571 572 static struct qcom_icc_qosbox qnm_mnoc_sf_qos = { 573 .num_ports = 2, 574 .port_offsets = { 0x35000, 0x75000 }, 575 .prio = 0, 576 .urg_fwd = 0, 577 .prio_fwd_disable = 0, 578 }; 579 580 static struct qcom_icc_node qnm_mnoc_sf = { 581 .name = "qnm_mnoc_sf", 582 .channels = 2, 583 .buswidth = 32, 584 .qosbox = &qnm_mnoc_sf_qos, 585 .num_links = 2, 586 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 587 }; 588 589 static struct qcom_icc_qosbox qnm_nsp_gemnoc_qos = { 590 .num_ports = 2, 591 .port_offsets = { 0x37000, 0x77000 }, 592 .prio = 0, 593 .urg_fwd = 1, 594 .prio_fwd_disable = 1, 595 }; 596 597 static struct qcom_icc_node qnm_nsp_gemnoc = { 598 .name = "qnm_nsp_gemnoc", 599 .channels = 2, 600 .buswidth = 32, 601 .qosbox = &qnm_nsp_gemnoc_qos, 602 .num_links = 3, 603 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, 604 &qns_pcie }, 605 }; 606 607 static struct qcom_icc_qosbox qnm_pcie_qos = { 608 .num_ports = 1, 609 .port_offsets = { 0xb7000 }, 610 .prio = 2, 611 .urg_fwd = 1, 612 .prio_fwd_disable = 0, 613 }; 614 615 static struct qcom_icc_node qnm_pcie = { 616 .name = "qnm_pcie", 617 .channels = 1, 618 .buswidth = 16, 619 .qosbox = &qnm_pcie_qos, 620 .num_links = 2, 621 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 622 }; 623 624 static struct qcom_icc_qosbox qnm_snoc_sf_qos = { 625 .num_ports = 1, 626 .port_offsets = { 0xbb000 }, 627 .prio = 0, 628 .urg_fwd = 1, 629 .prio_fwd_disable = 0, 630 }; 631 632 static struct qcom_icc_node qnm_snoc_sf = { 633 .name = "qnm_snoc_sf", 634 .channels = 1, 635 .buswidth = 16, 636 .qosbox = &qnm_snoc_sf_qos, 637 .num_links = 3, 638 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, 639 &qns_pcie }, 640 }; 641 642 static struct qcom_icc_qosbox qnm_ubwc_p_qos = { 643 .num_ports = 1, 644 .port_offsets = { 0xc3000 }, 645 .prio = 1, 646 .urg_fwd = 1, 647 .prio_fwd_disable = 1, 648 }; 649 650 static struct qcom_icc_node qnm_ubwc_p = { 651 .name = "qnm_ubwc_p", 652 .channels = 1, 653 .buswidth = 32, 654 .qosbox = &qnm_ubwc_p_qos, 655 .num_links = 1, 656 .link_nodes = { &qns_llcc }, 657 }; 658 659 static struct qcom_icc_qosbox xm_gic_qos = { 660 .num_ports = 1, 661 .port_offsets = { 0xb9000 }, 662 .prio = 4, 663 .urg_fwd = 0, 664 .prio_fwd_disable = 1, 665 }; 666 667 static struct qcom_icc_node xm_gic = { 668 .name = "xm_gic", 669 .channels = 1, 670 .buswidth = 8, 671 .qosbox = &xm_gic_qos, 672 .num_links = 1, 673 .link_nodes = { &qns_llcc }, 674 }; 675 676 static struct qcom_icc_node qnm_lpiaon_noc = { 677 .name = "qnm_lpiaon_noc", 678 .channels = 1, 679 .buswidth = 16, 680 .num_links = 1, 681 .link_nodes = { &qns_lpass_ag_noc_gemnoc }, 682 }; 683 684 static struct qcom_icc_node qnm_lpass_lpinoc = { 685 .name = "qnm_lpass_lpinoc", 686 .channels = 1, 687 .buswidth = 16, 688 .num_links = 1, 689 .link_nodes = { &qns_lpass_aggnoc }, 690 }; 691 692 static struct qcom_icc_node qxm_lpinoc_dsp_axim = { 693 .name = "qxm_lpinoc_dsp_axim", 694 .channels = 1, 695 .buswidth = 16, 696 .num_links = 1, 697 .link_nodes = { &qns_lpi_aon_noc }, 698 }; 699 700 static struct qcom_icc_node llcc_mc = { 701 .name = "llcc_mc", 702 .channels = 4, 703 .buswidth = 4, 704 .num_links = 1, 705 .link_nodes = { &ebi }, 706 }; 707 708 static struct qcom_icc_qosbox qnm_camnoc_hf_qos = { 709 .num_ports = 2, 710 .port_offsets = { 0x28000, 0x29000 }, 711 .prio = 0, 712 .urg_fwd = 1, 713 .prio_fwd_disable = 0, 714 }; 715 716 static struct qcom_icc_node qnm_camnoc_hf = { 717 .name = "qnm_camnoc_hf", 718 .channels = 2, 719 .buswidth = 32, 720 .qosbox = &qnm_camnoc_hf_qos, 721 .num_links = 1, 722 .link_nodes = { &qns_mem_noc_hf }, 723 }; 724 725 static struct qcom_icc_qosbox qnm_camnoc_icp_qos = { 726 .num_ports = 1, 727 .port_offsets = { 0x2a000 }, 728 .prio = 4, 729 .urg_fwd = 1, 730 .prio_fwd_disable = 0, 731 }; 732 733 static struct qcom_icc_node qnm_camnoc_icp = { 734 .name = "qnm_camnoc_icp", 735 .channels = 1, 736 .buswidth = 8, 737 .qosbox = &qnm_camnoc_icp_qos, 738 .num_links = 1, 739 .link_nodes = { &qns_mem_noc_sf }, 740 }; 741 742 static struct qcom_icc_qosbox qnm_camnoc_sf_qos = { 743 .num_ports = 2, 744 .port_offsets = { 0x2b000, 0x2c000 }, 745 .prio = 0, 746 .urg_fwd = 1, 747 .prio_fwd_disable = 0, 748 }; 749 750 static struct qcom_icc_node qnm_camnoc_sf = { 751 .name = "qnm_camnoc_sf", 752 .channels = 2, 753 .buswidth = 32, 754 .qosbox = &qnm_camnoc_sf_qos, 755 .num_links = 1, 756 .link_nodes = { &qns_mem_noc_sf }, 757 }; 758 759 static struct qcom_icc_qosbox qnm_mdp_qos = { 760 .num_ports = 2, 761 .port_offsets = { 0x2d000, 0x2e000 }, 762 .prio = 0, 763 .urg_fwd = 1, 764 .prio_fwd_disable = 0, 765 }; 766 767 static struct qcom_icc_node qnm_mdp = { 768 .name = "qnm_mdp", 769 .channels = 2, 770 .buswidth = 32, 771 .qosbox = &qnm_mdp_qos, 772 .num_links = 1, 773 .link_nodes = { &qns_mem_noc_hf }, 774 }; 775 776 static struct qcom_icc_node qnm_vapss_hcp = { 777 .name = "qnm_vapss_hcp", 778 .channels = 1, 779 .buswidth = 32, 780 .num_links = 1, 781 .link_nodes = { &qns_mem_noc_sf }, 782 }; 783 784 static struct qcom_icc_qosbox qnm_video_qos = { 785 .num_ports = 2, 786 .port_offsets = { 0x30000, 0x31000 }, 787 .prio = 0, 788 .urg_fwd = 1, 789 .prio_fwd_disable = 0, 790 }; 791 792 static struct qcom_icc_node qnm_video = { 793 .name = "qnm_video", 794 .channels = 2, 795 .buswidth = 32, 796 .qosbox = &qnm_video_qos, 797 .num_links = 1, 798 .link_nodes = { &qns_mem_noc_sf }, 799 }; 800 801 static struct qcom_icc_qosbox qnm_video_cv_cpu_qos = { 802 .num_ports = 1, 803 .port_offsets = { 0x32000 }, 804 .prio = 4, 805 .urg_fwd = 1, 806 .prio_fwd_disable = 0, 807 }; 808 809 static struct qcom_icc_node qnm_video_cv_cpu = { 810 .name = "qnm_video_cv_cpu", 811 .channels = 1, 812 .buswidth = 8, 813 .qosbox = &qnm_video_cv_cpu_qos, 814 .num_links = 1, 815 .link_nodes = { &qns_mem_noc_sf }, 816 }; 817 818 static struct qcom_icc_qosbox qnm_video_cvp_qos = { 819 .num_ports = 2, 820 .port_offsets = { 0x33000, 0x34000 }, 821 .prio = 0, 822 .urg_fwd = 1, 823 .prio_fwd_disable = 0, 824 }; 825 826 static struct qcom_icc_node qnm_video_cvp = { 827 .name = "qnm_video_cvp", 828 .channels = 2, 829 .buswidth = 32, 830 .qosbox = &qnm_video_cvp_qos, 831 .num_links = 1, 832 .link_nodes = { &qns_mem_noc_sf }, 833 }; 834 835 static struct qcom_icc_qosbox qnm_video_v_cpu_qos = { 836 .num_ports = 1, 837 .port_offsets = { 0x35000 }, 838 .prio = 4, 839 .urg_fwd = 1, 840 .prio_fwd_disable = 0, 841 }; 842 843 static struct qcom_icc_node qnm_video_v_cpu = { 844 .name = "qnm_video_v_cpu", 845 .channels = 1, 846 .buswidth = 8, 847 .qosbox = &qnm_video_v_cpu_qos, 848 .num_links = 1, 849 .link_nodes = { &qns_mem_noc_sf }, 850 }; 851 852 static struct qcom_icc_node qsm_mnoc_cfg = { 853 .name = "qsm_mnoc_cfg", 854 .channels = 1, 855 .buswidth = 4, 856 .num_links = 1, 857 .link_nodes = { &srvc_mnoc }, 858 }; 859 860 static struct qcom_icc_node qnm_nsp = { 861 .name = "qnm_nsp", 862 .channels = 2, 863 .buswidth = 32, 864 .num_links = 1, 865 .link_nodes = { &qns_nsp_gemnoc }, 866 }; 867 868 static struct qcom_icc_node qsm_pcie_anoc_cfg = { 869 .name = "qsm_pcie_anoc_cfg", 870 .channels = 1, 871 .buswidth = 4, 872 .num_links = 1, 873 .link_nodes = { &srvc_pcie_aggre_noc }, 874 }; 875 876 static struct qcom_icc_qosbox xm_pcie3_0_qos = { 877 .num_ports = 1, 878 .port_offsets = { 0xb000 }, 879 .prio = 3, 880 .urg_fwd = 0, 881 .prio_fwd_disable = 0, 882 }; 883 884 static struct qcom_icc_node xm_pcie3_0 = { 885 .name = "xm_pcie3_0", 886 .channels = 1, 887 .buswidth = 8, 888 .qosbox = &xm_pcie3_0_qos, 889 .num_links = 1, 890 .link_nodes = { &qns_pcie_mem_noc }, 891 }; 892 893 static struct qcom_icc_qosbox xm_pcie3_1_qos = { 894 .num_ports = 1, 895 .port_offsets = { 0xc000 }, 896 .prio = 2, 897 .urg_fwd = 0, 898 .prio_fwd_disable = 0, 899 }; 900 901 static struct qcom_icc_node xm_pcie3_1 = { 902 .name = "xm_pcie3_1", 903 .channels = 1, 904 .buswidth = 16, 905 .qosbox = &xm_pcie3_1_qos, 906 .num_links = 1, 907 .link_nodes = { &qns_pcie_mem_noc }, 908 }; 909 910 static struct qcom_icc_node qnm_aggre1_noc = { 911 .name = "qnm_aggre1_noc", 912 .channels = 1, 913 .buswidth = 16, 914 .num_links = 1, 915 .link_nodes = { &qns_gemnoc_sf }, 916 }; 917 918 static struct qcom_icc_node qnm_aggre2_noc = { 919 .name = "qnm_aggre2_noc", 920 .channels = 1, 921 .buswidth = 16, 922 .num_links = 1, 923 .link_nodes = { &qns_gemnoc_sf }, 924 }; 925 926 static struct qcom_icc_qosbox qnm_apss_noc_qos = { 927 .num_ports = 1, 928 .port_offsets = { 0x1c000 }, 929 .prio = 2, 930 .urg_fwd = 0, 931 .prio_fwd_disable = 1, 932 }; 933 934 static struct qcom_icc_node qnm_apss_noc = { 935 .name = "qnm_apss_noc", 936 .channels = 1, 937 .buswidth = 4, 938 .qosbox = &qnm_apss_noc_qos, 939 .num_links = 1, 940 .link_nodes = { &qns_gemnoc_sf }, 941 }; 942 943 static struct qcom_icc_node qns_a1noc_snoc = { 944 .name = "qns_a1noc_snoc", 945 .channels = 1, 946 .buswidth = 16, 947 .num_links = 1, 948 .link_nodes = { &qnm_aggre1_noc }, 949 }; 950 951 static struct qcom_icc_node qns_a2noc_snoc = { 952 .name = "qns_a2noc_snoc", 953 .channels = 1, 954 .buswidth = 16, 955 .num_links = 1, 956 .link_nodes = { &qnm_aggre2_noc }, 957 }; 958 959 static struct qcom_icc_node qup0_core_slave = { 960 .name = "qup0_core_slave", 961 .channels = 1, 962 .buswidth = 4, 963 }; 964 965 static struct qcom_icc_node qup1_core_slave = { 966 .name = "qup1_core_slave", 967 .channels = 1, 968 .buswidth = 4, 969 }; 970 971 static struct qcom_icc_node qup2_core_slave = { 972 .name = "qup2_core_slave", 973 .channels = 1, 974 .buswidth = 4, 975 }; 976 977 static struct qcom_icc_node qhs_ahb2phy0 = { 978 .name = "qhs_ahb2phy0", 979 .channels = 1, 980 .buswidth = 4, 981 }; 982 983 static struct qcom_icc_node qhs_ahb2phy1 = { 984 .name = "qhs_ahb2phy1", 985 .channels = 1, 986 .buswidth = 4, 987 }; 988 989 static struct qcom_icc_node qhs_camera_cfg = { 990 .name = "qhs_camera_cfg", 991 .channels = 1, 992 .buswidth = 4, 993 }; 994 995 static struct qcom_icc_node qhs_clk_ctl = { 996 .name = "qhs_clk_ctl", 997 .channels = 1, 998 .buswidth = 4, 999 }; 1000 1001 static struct qcom_icc_node qhs_cpr_cx = { 1002 .name = "qhs_cpr_cx", 1003 .channels = 1, 1004 .buswidth = 4, 1005 }; 1006 1007 static struct qcom_icc_node qhs_cpr_hmx = { 1008 .name = "qhs_cpr_hmx", 1009 .channels = 1, 1010 .buswidth = 4, 1011 }; 1012 1013 static struct qcom_icc_node qhs_cpr_mmcx = { 1014 .name = "qhs_cpr_mmcx", 1015 .channels = 1, 1016 .buswidth = 4, 1017 }; 1018 1019 static struct qcom_icc_node qhs_cpr_mxa = { 1020 .name = "qhs_cpr_mxa", 1021 .channels = 1, 1022 .buswidth = 4, 1023 }; 1024 1025 static struct qcom_icc_node qhs_cpr_mxc = { 1026 .name = "qhs_cpr_mxc", 1027 .channels = 1, 1028 .buswidth = 4, 1029 }; 1030 1031 static struct qcom_icc_node qhs_cpr_nspcx = { 1032 .name = "qhs_cpr_nspcx", 1033 .channels = 1, 1034 .buswidth = 4, 1035 }; 1036 1037 static struct qcom_icc_node qhs_crypto0_cfg = { 1038 .name = "qhs_crypto0_cfg", 1039 .channels = 1, 1040 .buswidth = 4, 1041 }; 1042 1043 static struct qcom_icc_node qhs_cx_rdpm = { 1044 .name = "qhs_cx_rdpm", 1045 .channels = 1, 1046 .buswidth = 4, 1047 }; 1048 1049 static struct qcom_icc_node qhs_display_cfg = { 1050 .name = "qhs_display_cfg", 1051 .channels = 1, 1052 .buswidth = 4, 1053 }; 1054 1055 static struct qcom_icc_node qhs_gpuss_cfg = { 1056 .name = "qhs_gpuss_cfg", 1057 .channels = 1, 1058 .buswidth = 8, 1059 }; 1060 1061 static struct qcom_icc_node qhs_i2c = { 1062 .name = "qhs_i2c", 1063 .channels = 1, 1064 .buswidth = 4, 1065 }; 1066 1067 static struct qcom_icc_node qhs_i3c_ibi0_cfg = { 1068 .name = "qhs_i3c_ibi0_cfg", 1069 .channels = 1, 1070 .buswidth = 4, 1071 }; 1072 1073 static struct qcom_icc_node qhs_i3c_ibi1_cfg = { 1074 .name = "qhs_i3c_ibi1_cfg", 1075 .channels = 1, 1076 .buswidth = 4, 1077 }; 1078 1079 static struct qcom_icc_node qhs_imem_cfg = { 1080 .name = "qhs_imem_cfg", 1081 .channels = 1, 1082 .buswidth = 4, 1083 }; 1084 1085 static struct qcom_icc_node qhs_mss_cfg = { 1086 .name = "qhs_mss_cfg", 1087 .channels = 1, 1088 .buswidth = 4, 1089 }; 1090 1091 static struct qcom_icc_node qhs_mx_2_rdpm = { 1092 .name = "qhs_mx_2_rdpm", 1093 .channels = 1, 1094 .buswidth = 4, 1095 }; 1096 1097 static struct qcom_icc_node qhs_mx_rdpm = { 1098 .name = "qhs_mx_rdpm", 1099 .channels = 1, 1100 .buswidth = 4, 1101 }; 1102 1103 static struct qcom_icc_node qhs_pcie0_cfg = { 1104 .name = "qhs_pcie0_cfg", 1105 .channels = 1, 1106 .buswidth = 4, 1107 }; 1108 1109 static struct qcom_icc_node qhs_pcie1_cfg = { 1110 .name = "qhs_pcie1_cfg", 1111 .channels = 1, 1112 .buswidth = 4, 1113 }; 1114 1115 static struct qcom_icc_node qhs_pcie_rscc = { 1116 .name = "qhs_pcie_rscc", 1117 .channels = 1, 1118 .buswidth = 4, 1119 }; 1120 1121 static struct qcom_icc_node qhs_pdm = { 1122 .name = "qhs_pdm", 1123 .channels = 1, 1124 .buswidth = 4, 1125 }; 1126 1127 static struct qcom_icc_node qhs_prng = { 1128 .name = "qhs_prng", 1129 .channels = 1, 1130 .buswidth = 4, 1131 }; 1132 1133 static struct qcom_icc_node qhs_qdss_cfg = { 1134 .name = "qhs_qdss_cfg", 1135 .channels = 1, 1136 .buswidth = 4, 1137 }; 1138 1139 static struct qcom_icc_node qhs_qspi = { 1140 .name = "qhs_qspi", 1141 .channels = 1, 1142 .buswidth = 4, 1143 }; 1144 1145 static struct qcom_icc_node qhs_qup02 = { 1146 .name = "qhs_qup02", 1147 .channels = 1, 1148 .buswidth = 4, 1149 }; 1150 1151 static struct qcom_icc_node qhs_qup1 = { 1152 .name = "qhs_qup1", 1153 .channels = 1, 1154 .buswidth = 4, 1155 }; 1156 1157 static struct qcom_icc_node qhs_qup2 = { 1158 .name = "qhs_qup2", 1159 .channels = 1, 1160 .buswidth = 4, 1161 }; 1162 1163 static struct qcom_icc_node qhs_sdc2 = { 1164 .name = "qhs_sdc2", 1165 .channels = 1, 1166 .buswidth = 4, 1167 }; 1168 1169 static struct qcom_icc_node qhs_sdc4 = { 1170 .name = "qhs_sdc4", 1171 .channels = 1, 1172 .buswidth = 4, 1173 }; 1174 1175 static struct qcom_icc_node qhs_spss_cfg = { 1176 .name = "qhs_spss_cfg", 1177 .channels = 1, 1178 .buswidth = 4, 1179 }; 1180 1181 static struct qcom_icc_node qhs_tcsr = { 1182 .name = "qhs_tcsr", 1183 .channels = 1, 1184 .buswidth = 4, 1185 }; 1186 1187 static struct qcom_icc_node qhs_tlmm = { 1188 .name = "qhs_tlmm", 1189 .channels = 1, 1190 .buswidth = 4, 1191 }; 1192 1193 static struct qcom_icc_node qhs_ufs_mem_cfg = { 1194 .name = "qhs_ufs_mem_cfg", 1195 .channels = 1, 1196 .buswidth = 4, 1197 }; 1198 1199 static struct qcom_icc_node qhs_usb3_0 = { 1200 .name = "qhs_usb3_0", 1201 .channels = 1, 1202 .buswidth = 4, 1203 }; 1204 1205 static struct qcom_icc_node qhs_venus_cfg = { 1206 .name = "qhs_venus_cfg", 1207 .channels = 1, 1208 .buswidth = 4, 1209 }; 1210 1211 static struct qcom_icc_node qhs_vsense_ctrl_cfg = { 1212 .name = "qhs_vsense_ctrl_cfg", 1213 .channels = 1, 1214 .buswidth = 4, 1215 }; 1216 1217 static struct qcom_icc_node qss_mnoc_cfg = { 1218 .name = "qss_mnoc_cfg", 1219 .channels = 1, 1220 .buswidth = 4, 1221 .num_links = 1, 1222 .link_nodes = { &qsm_mnoc_cfg }, 1223 }; 1224 1225 static struct qcom_icc_node qss_nsp_qtb_cfg = { 1226 .name = "qss_nsp_qtb_cfg", 1227 .channels = 1, 1228 .buswidth = 4, 1229 }; 1230 1231 static struct qcom_icc_node qss_pcie_anoc_cfg = { 1232 .name = "qss_pcie_anoc_cfg", 1233 .channels = 1, 1234 .buswidth = 4, 1235 .num_links = 1, 1236 .link_nodes = { &qsm_pcie_anoc_cfg }, 1237 }; 1238 1239 static struct qcom_icc_node srvc_cnoc_cfg = { 1240 .name = "srvc_cnoc_cfg", 1241 .channels = 1, 1242 .buswidth = 4, 1243 }; 1244 1245 static struct qcom_icc_node xs_qdss_stm = { 1246 .name = "xs_qdss_stm", 1247 .channels = 1, 1248 .buswidth = 4, 1249 }; 1250 1251 static struct qcom_icc_node xs_sys_tcu_cfg = { 1252 .name = "xs_sys_tcu_cfg", 1253 .channels = 1, 1254 .buswidth = 8, 1255 }; 1256 1257 static struct qcom_icc_node qhs_aoss = { 1258 .name = "qhs_aoss", 1259 .channels = 1, 1260 .buswidth = 4, 1261 }; 1262 1263 static struct qcom_icc_node qhs_ipa = { 1264 .name = "qhs_ipa", 1265 .channels = 1, 1266 .buswidth = 4, 1267 }; 1268 1269 static struct qcom_icc_node qhs_ipc_router = { 1270 .name = "qhs_ipc_router", 1271 .channels = 1, 1272 .buswidth = 4, 1273 }; 1274 1275 static struct qcom_icc_node qhs_tme_cfg = { 1276 .name = "qhs_tme_cfg", 1277 .channels = 1, 1278 .buswidth = 4, 1279 }; 1280 1281 static struct qcom_icc_node qss_apss = { 1282 .name = "qss_apss", 1283 .channels = 1, 1284 .buswidth = 4, 1285 }; 1286 1287 static struct qcom_icc_node qss_cfg = { 1288 .name = "qss_cfg", 1289 .channels = 1, 1290 .buswidth = 4, 1291 .num_links = 1, 1292 .link_nodes = { &qsm_cfg }, 1293 }; 1294 1295 static struct qcom_icc_node qss_ddrss_cfg = { 1296 .name = "qss_ddrss_cfg", 1297 .channels = 1, 1298 .buswidth = 4, 1299 }; 1300 1301 static struct qcom_icc_node qxs_imem = { 1302 .name = "qxs_imem", 1303 .channels = 1, 1304 .buswidth = 8, 1305 }; 1306 1307 static struct qcom_icc_node srvc_cnoc_main = { 1308 .name = "srvc_cnoc_main", 1309 .channels = 1, 1310 .buswidth = 4, 1311 }; 1312 1313 static struct qcom_icc_node xs_pcie_0 = { 1314 .name = "xs_pcie_0", 1315 .channels = 1, 1316 .buswidth = 8, 1317 }; 1318 1319 static struct qcom_icc_node xs_pcie_1 = { 1320 .name = "xs_pcie_1", 1321 .channels = 1, 1322 .buswidth = 16, 1323 }; 1324 1325 static struct qcom_icc_node qns_gem_noc_cnoc = { 1326 .name = "qns_gem_noc_cnoc", 1327 .channels = 1, 1328 .buswidth = 16, 1329 .num_links = 1, 1330 .link_nodes = { &qnm_gemnoc_cnoc }, 1331 }; 1332 1333 static struct qcom_icc_node qns_llcc = { 1334 .name = "qns_llcc", 1335 .channels = 4, 1336 .buswidth = 16, 1337 .num_links = 1, 1338 .link_nodes = { &llcc_mc }, 1339 }; 1340 1341 static struct qcom_icc_node qns_pcie = { 1342 .name = "qns_pcie", 1343 .channels = 1, 1344 .buswidth = 8, 1345 .num_links = 1, 1346 .link_nodes = { &qnm_gemnoc_pcie }, 1347 }; 1348 1349 static struct qcom_icc_node qns_lpass_ag_noc_gemnoc = { 1350 .name = "qns_lpass_ag_noc_gemnoc", 1351 .channels = 1, 1352 .buswidth = 16, 1353 .num_links = 1, 1354 .link_nodes = { &qnm_lpass_gemnoc }, 1355 }; 1356 1357 static struct qcom_icc_node qns_lpass_aggnoc = { 1358 .name = "qns_lpass_aggnoc", 1359 .channels = 1, 1360 .buswidth = 16, 1361 .num_links = 1, 1362 .link_nodes = { &qnm_lpiaon_noc }, 1363 }; 1364 1365 static struct qcom_icc_node qns_lpi_aon_noc = { 1366 .name = "qns_lpi_aon_noc", 1367 .channels = 1, 1368 .buswidth = 16, 1369 .num_links = 1, 1370 .link_nodes = { &qnm_lpass_lpinoc }, 1371 }; 1372 1373 static struct qcom_icc_node ebi = { 1374 .name = "ebi", 1375 .channels = 4, 1376 .buswidth = 4, 1377 }; 1378 1379 static struct qcom_icc_node qns_mem_noc_hf = { 1380 .name = "qns_mem_noc_hf", 1381 .channels = 2, 1382 .buswidth = 32, 1383 .num_links = 1, 1384 .link_nodes = { &qnm_mnoc_hf }, 1385 }; 1386 1387 static struct qcom_icc_node qns_mem_noc_sf = { 1388 .name = "qns_mem_noc_sf", 1389 .channels = 2, 1390 .buswidth = 32, 1391 .num_links = 1, 1392 .link_nodes = { &qnm_mnoc_sf }, 1393 }; 1394 1395 static struct qcom_icc_node srvc_mnoc = { 1396 .name = "srvc_mnoc", 1397 .channels = 1, 1398 .buswidth = 4, 1399 }; 1400 1401 static struct qcom_icc_node qns_nsp_gemnoc = { 1402 .name = "qns_nsp_gemnoc", 1403 .channels = 2, 1404 .buswidth = 32, 1405 .num_links = 1, 1406 .link_nodes = { &qnm_nsp_gemnoc }, 1407 }; 1408 1409 static struct qcom_icc_node qns_pcie_mem_noc = { 1410 .name = "qns_pcie_mem_noc", 1411 .channels = 1, 1412 .buswidth = 16, 1413 .num_links = 1, 1414 .link_nodes = { &qnm_pcie }, 1415 }; 1416 1417 static struct qcom_icc_node srvc_pcie_aggre_noc = { 1418 .name = "srvc_pcie_aggre_noc", 1419 .channels = 1, 1420 .buswidth = 4, 1421 }; 1422 1423 static struct qcom_icc_node qns_gemnoc_sf = { 1424 .name = "qns_gemnoc_sf", 1425 .channels = 1, 1426 .buswidth = 16, 1427 .num_links = 1, 1428 .link_nodes = { &qnm_snoc_sf }, 1429 }; 1430 1431 static struct qcom_icc_bcm bcm_acv = { 1432 .name = "ACV", 1433 .enable_mask = BIT(0), 1434 .num_nodes = 1, 1435 .nodes = { &ebi }, 1436 }; 1437 1438 static struct qcom_icc_bcm bcm_ce0 = { 1439 .name = "CE0", 1440 .num_nodes = 1, 1441 .nodes = { &qxm_crypto }, 1442 }; 1443 1444 static struct qcom_icc_bcm bcm_cn0 = { 1445 .name = "CN0", 1446 .enable_mask = BIT(0), 1447 .keepalive = true, 1448 .num_nodes = 59, 1449 .nodes = { &qsm_cfg, &qhs_ahb2phy0, 1450 &qhs_ahb2phy1, &qhs_camera_cfg, 1451 &qhs_clk_ctl, &qhs_cpr_cx, 1452 &qhs_cpr_hmx, &qhs_cpr_mmcx, 1453 &qhs_cpr_mxa, &qhs_cpr_mxc, 1454 &qhs_cpr_nspcx, &qhs_crypto0_cfg, 1455 &qhs_cx_rdpm, &qhs_display_cfg, 1456 &qhs_gpuss_cfg, &qhs_i2c, 1457 &qhs_i3c_ibi0_cfg, &qhs_i3c_ibi1_cfg, 1458 &qhs_imem_cfg, &qhs_mss_cfg, 1459 &qhs_mx_2_rdpm, &qhs_mx_rdpm, 1460 &qhs_pcie0_cfg, &qhs_pcie1_cfg, 1461 &qhs_pcie_rscc, &qhs_pdm, 1462 &qhs_prng, &qhs_qdss_cfg, 1463 &qhs_qspi, &qhs_qup02, 1464 &qhs_qup1, &qhs_qup2, 1465 &qhs_sdc2, &qhs_sdc4, 1466 &qhs_spss_cfg, &qhs_tcsr, 1467 &qhs_tlmm, &qhs_ufs_mem_cfg, 1468 &qhs_usb3_0, &qhs_venus_cfg, 1469 &qhs_vsense_ctrl_cfg, &qss_mnoc_cfg, 1470 &qss_nsp_qtb_cfg, &qss_pcie_anoc_cfg, 1471 &srvc_cnoc_cfg, &xs_qdss_stm, 1472 &xs_sys_tcu_cfg, &qnm_gemnoc_cnoc, 1473 &qnm_gemnoc_pcie, &qhs_aoss, 1474 &qhs_ipa, &qhs_ipc_router, 1475 &qhs_tme_cfg, &qss_apss, 1476 &qss_cfg, &qss_ddrss_cfg, 1477 &qxs_imem, &srvc_cnoc_main, 1478 &xs_pcie_0, &xs_pcie_1 }, 1479 }; 1480 1481 static struct qcom_icc_bcm bcm_co0 = { 1482 .name = "CO0", 1483 .enable_mask = BIT(0), 1484 .num_nodes = 2, 1485 .nodes = { &qnm_nsp, &qns_nsp_gemnoc }, 1486 }; 1487 1488 static struct qcom_icc_bcm bcm_lp0 = { 1489 .name = "LP0", 1490 .num_nodes = 2, 1491 .nodes = { &qnm_lpass_lpinoc, &qns_lpass_aggnoc }, 1492 }; 1493 1494 static struct qcom_icc_bcm bcm_mc0 = { 1495 .name = "MC0", 1496 .keepalive = true, 1497 .num_nodes = 1, 1498 .nodes = { &ebi }, 1499 }; 1500 1501 static struct qcom_icc_bcm bcm_mm0 = { 1502 .name = "MM0", 1503 .num_nodes = 1, 1504 .nodes = { &qns_mem_noc_hf }, 1505 }; 1506 1507 static struct qcom_icc_bcm bcm_mm1 = { 1508 .name = "MM1", 1509 .enable_mask = BIT(0), 1510 .num_nodes = 8, 1511 .nodes = { &qnm_camnoc_hf, &qnm_camnoc_icp, 1512 &qnm_camnoc_sf, &qnm_vapss_hcp, 1513 &qnm_video_cv_cpu, &qnm_video_cvp, 1514 &qnm_video_v_cpu, &qns_mem_noc_sf }, 1515 }; 1516 1517 static struct qcom_icc_bcm bcm_qup0 = { 1518 .name = "QUP0", 1519 .keepalive = true, 1520 .vote_scale = 1, 1521 .num_nodes = 1, 1522 .nodes = { &qup0_core_slave }, 1523 }; 1524 1525 static struct qcom_icc_bcm bcm_qup1 = { 1526 .name = "QUP1", 1527 .keepalive = true, 1528 .vote_scale = 1, 1529 .num_nodes = 1, 1530 .nodes = { &qup1_core_slave }, 1531 }; 1532 1533 static struct qcom_icc_bcm bcm_qup2 = { 1534 .name = "QUP2", 1535 .keepalive = true, 1536 .vote_scale = 1, 1537 .num_nodes = 1, 1538 .nodes = { &qup2_core_slave }, 1539 }; 1540 1541 static struct qcom_icc_bcm bcm_sh0 = { 1542 .name = "SH0", 1543 .keepalive = true, 1544 .num_nodes = 1, 1545 .nodes = { &qns_llcc }, 1546 }; 1547 1548 static struct qcom_icc_bcm bcm_sh1 = { 1549 .name = "SH1", 1550 .enable_mask = BIT(0), 1551 .num_nodes = 15, 1552 .nodes = { &alm_gpu_tcu, &alm_sys_tcu, 1553 &alm_ubwc_p_tcu, &chm_apps, 1554 &qnm_gpu, &qnm_mdsp, 1555 &qnm_mnoc_hf, &qnm_mnoc_sf, 1556 &qnm_nsp_gemnoc, &qnm_pcie, 1557 &qnm_snoc_sf, &qnm_ubwc_p, 1558 &xm_gic, &qns_gem_noc_cnoc, 1559 &qns_pcie }, 1560 }; 1561 1562 static struct qcom_icc_bcm bcm_sn0 = { 1563 .name = "SN0", 1564 .keepalive = true, 1565 .num_nodes = 1, 1566 .nodes = { &qns_gemnoc_sf }, 1567 }; 1568 1569 static struct qcom_icc_bcm bcm_sn2 = { 1570 .name = "SN2", 1571 .num_nodes = 1, 1572 .nodes = { &qnm_aggre1_noc }, 1573 }; 1574 1575 static struct qcom_icc_bcm bcm_sn3 = { 1576 .name = "SN3", 1577 .num_nodes = 1, 1578 .nodes = { &qnm_aggre2_noc }, 1579 }; 1580 1581 static struct qcom_icc_bcm bcm_sn4 = { 1582 .name = "SN4", 1583 .num_nodes = 1, 1584 .nodes = { &qns_pcie_mem_noc }, 1585 }; 1586 1587 static struct qcom_icc_node * const aggre1_noc_nodes[] = { 1588 [MASTER_QSPI_0] = &qhm_qspi, 1589 [MASTER_QUP_1] = &qhm_qup1, 1590 [MASTER_QUP_3] = &qxm_qup02, 1591 [MASTER_SDCC_4] = &xm_sdc4, 1592 [MASTER_UFS_MEM] = &xm_ufs_mem, 1593 [MASTER_USB3_0] = &xm_usb3_0, 1594 [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc, 1595 }; 1596 1597 static const struct qcom_icc_desc sm8650_aggre1_noc = { 1598 .config = &icc_regmap_config, 1599 .nodes = aggre1_noc_nodes, 1600 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), 1601 }; 1602 1603 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { 1604 &bcm_ce0, 1605 }; 1606 1607 static struct qcom_icc_node * const aggre2_noc_nodes[] = { 1608 [MASTER_QDSS_BAM] = &qhm_qdss_bam, 1609 [MASTER_QUP_2] = &qhm_qup2, 1610 [MASTER_CRYPTO] = &qxm_crypto, 1611 [MASTER_IPA] = &qxm_ipa, 1612 [MASTER_SP] = &qxm_sp, 1613 [MASTER_QDSS_ETR] = &xm_qdss_etr_0, 1614 [MASTER_QDSS_ETR_1] = &xm_qdss_etr_1, 1615 [MASTER_SDCC_2] = &xm_sdc2, 1616 [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc, 1617 }; 1618 1619 static const struct qcom_icc_desc sm8650_aggre2_noc = { 1620 .config = &icc_regmap_config, 1621 .nodes = aggre2_noc_nodes, 1622 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), 1623 .bcms = aggre2_noc_bcms, 1624 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), 1625 }; 1626 1627 static struct qcom_icc_bcm * const clk_virt_bcms[] = { 1628 &bcm_qup0, 1629 &bcm_qup1, 1630 &bcm_qup2, 1631 }; 1632 1633 static struct qcom_icc_node * const clk_virt_nodes[] = { 1634 [MASTER_QUP_CORE_0] = &qup0_core_master, 1635 [MASTER_QUP_CORE_1] = &qup1_core_master, 1636 [MASTER_QUP_CORE_2] = &qup2_core_master, 1637 [SLAVE_QUP_CORE_0] = &qup0_core_slave, 1638 [SLAVE_QUP_CORE_1] = &qup1_core_slave, 1639 [SLAVE_QUP_CORE_2] = &qup2_core_slave, 1640 }; 1641 1642 static const struct qcom_icc_desc sm8650_clk_virt = { 1643 .nodes = clk_virt_nodes, 1644 .num_nodes = ARRAY_SIZE(clk_virt_nodes), 1645 .bcms = clk_virt_bcms, 1646 .num_bcms = ARRAY_SIZE(clk_virt_bcms), 1647 }; 1648 1649 static struct qcom_icc_bcm * const config_noc_bcms[] = { 1650 &bcm_cn0, 1651 }; 1652 1653 static struct qcom_icc_node * const config_noc_nodes[] = { 1654 [MASTER_CNOC_CFG] = &qsm_cfg, 1655 [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0, 1656 [SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1, 1657 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, 1658 [SLAVE_CLK_CTL] = &qhs_clk_ctl, 1659 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx, 1660 [SLAVE_CPR_HMX] = &qhs_cpr_hmx, 1661 [SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx, 1662 [SLAVE_RBCPR_MXA_CFG] = &qhs_cpr_mxa, 1663 [SLAVE_RBCPR_MXC_CFG] = &qhs_cpr_mxc, 1664 [SLAVE_CPR_NSPCX] = &qhs_cpr_nspcx, 1665 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, 1666 [SLAVE_CX_RDPM] = &qhs_cx_rdpm, 1667 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg, 1668 [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg, 1669 [SLAVE_I2C] = &qhs_i2c, 1670 [SLAVE_I3C_IBI0_CFG] = &qhs_i3c_ibi0_cfg, 1671 [SLAVE_I3C_IBI1_CFG] = &qhs_i3c_ibi1_cfg, 1672 [SLAVE_IMEM_CFG] = &qhs_imem_cfg, 1673 [SLAVE_CNOC_MSS] = &qhs_mss_cfg, 1674 [SLAVE_MX_2_RDPM] = &qhs_mx_2_rdpm, 1675 [SLAVE_MX_RDPM] = &qhs_mx_rdpm, 1676 [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg, 1677 [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg, 1678 [SLAVE_PCIE_RSCC] = &qhs_pcie_rscc, 1679 [SLAVE_PDM] = &qhs_pdm, 1680 [SLAVE_PRNG] = &qhs_prng, 1681 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, 1682 [SLAVE_QSPI_0] = &qhs_qspi, 1683 [SLAVE_QUP_3] = &qhs_qup02, 1684 [SLAVE_QUP_1] = &qhs_qup1, 1685 [SLAVE_QUP_2] = &qhs_qup2, 1686 [SLAVE_SDCC_2] = &qhs_sdc2, 1687 [SLAVE_SDCC_4] = &qhs_sdc4, 1688 [SLAVE_SPSS_CFG] = &qhs_spss_cfg, 1689 [SLAVE_TCSR] = &qhs_tcsr, 1690 [SLAVE_TLMM] = &qhs_tlmm, 1691 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, 1692 [SLAVE_USB3_0] = &qhs_usb3_0, 1693 [SLAVE_VENUS_CFG] = &qhs_venus_cfg, 1694 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, 1695 [SLAVE_CNOC_MNOC_CFG] = &qss_mnoc_cfg, 1696 [SLAVE_NSP_QTB_CFG] = &qss_nsp_qtb_cfg, 1697 [SLAVE_PCIE_ANOC_CFG] = &qss_pcie_anoc_cfg, 1698 [SLAVE_SERVICE_CNOC_CFG] = &srvc_cnoc_cfg, 1699 [SLAVE_QDSS_STM] = &xs_qdss_stm, 1700 [SLAVE_TCU] = &xs_sys_tcu_cfg, 1701 }; 1702 1703 static const struct qcom_icc_desc sm8650_config_noc = { 1704 .config = &icc_regmap_config, 1705 .nodes = config_noc_nodes, 1706 .num_nodes = ARRAY_SIZE(config_noc_nodes), 1707 .bcms = config_noc_bcms, 1708 .num_bcms = ARRAY_SIZE(config_noc_bcms), 1709 }; 1710 1711 static struct qcom_icc_bcm * const cnoc_main_bcms[] = { 1712 &bcm_cn0, 1713 }; 1714 1715 static struct qcom_icc_node * const cnoc_main_nodes[] = { 1716 [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc, 1717 [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie, 1718 [SLAVE_AOSS] = &qhs_aoss, 1719 [SLAVE_IPA_CFG] = &qhs_ipa, 1720 [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router, 1721 [SLAVE_TME_CFG] = &qhs_tme_cfg, 1722 [SLAVE_APPSS] = &qss_apss, 1723 [SLAVE_CNOC_CFG] = &qss_cfg, 1724 [SLAVE_DDRSS_CFG] = &qss_ddrss_cfg, 1725 [SLAVE_IMEM] = &qxs_imem, 1726 [SLAVE_SERVICE_CNOC] = &srvc_cnoc_main, 1727 [SLAVE_PCIE_0] = &xs_pcie_0, 1728 [SLAVE_PCIE_1] = &xs_pcie_1, 1729 }; 1730 1731 static const struct qcom_icc_desc sm8650_cnoc_main = { 1732 .config = &icc_regmap_config, 1733 .nodes = cnoc_main_nodes, 1734 .num_nodes = ARRAY_SIZE(cnoc_main_nodes), 1735 .bcms = cnoc_main_bcms, 1736 .num_bcms = ARRAY_SIZE(cnoc_main_bcms), 1737 }; 1738 1739 static struct qcom_icc_bcm * const gem_noc_bcms[] = { 1740 &bcm_sh0, 1741 &bcm_sh1, 1742 }; 1743 1744 static struct qcom_icc_node * const gem_noc_nodes[] = { 1745 [MASTER_GPU_TCU] = &alm_gpu_tcu, 1746 [MASTER_SYS_TCU] = &alm_sys_tcu, 1747 [MASTER_UBWC_P_TCU] = &alm_ubwc_p_tcu, 1748 [MASTER_APPSS_PROC] = &chm_apps, 1749 [MASTER_GFX3D] = &qnm_gpu, 1750 [MASTER_LPASS_GEM_NOC] = &qnm_lpass_gemnoc, 1751 [MASTER_MSS_PROC] = &qnm_mdsp, 1752 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, 1753 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, 1754 [MASTER_COMPUTE_NOC] = &qnm_nsp_gemnoc, 1755 [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie, 1756 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, 1757 [MASTER_UBWC_P] = &qnm_ubwc_p, 1758 [MASTER_GIC] = &xm_gic, 1759 [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc, 1760 [SLAVE_LLCC] = &qns_llcc, 1761 [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie, 1762 }; 1763 1764 static const struct qcom_icc_desc sm8650_gem_noc = { 1765 .config = &icc_regmap_config, 1766 .nodes = gem_noc_nodes, 1767 .num_nodes = ARRAY_SIZE(gem_noc_nodes), 1768 .bcms = gem_noc_bcms, 1769 .num_bcms = ARRAY_SIZE(gem_noc_bcms), 1770 }; 1771 1772 static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { 1773 [MASTER_LPIAON_NOC] = &qnm_lpiaon_noc, 1774 [SLAVE_LPASS_GEM_NOC] = &qns_lpass_ag_noc_gemnoc, 1775 }; 1776 1777 static const struct qcom_icc_desc sm8650_lpass_ag_noc = { 1778 .config = &icc_regmap_config, 1779 .nodes = lpass_ag_noc_nodes, 1780 .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), 1781 }; 1782 1783 static struct qcom_icc_bcm * const lpass_lpiaon_noc_bcms[] = { 1784 &bcm_lp0, 1785 }; 1786 1787 static struct qcom_icc_node * const lpass_lpiaon_noc_nodes[] = { 1788 [MASTER_LPASS_LPINOC] = &qnm_lpass_lpinoc, 1789 [SLAVE_LPIAON_NOC_LPASS_AG_NOC] = &qns_lpass_aggnoc, 1790 }; 1791 1792 static const struct qcom_icc_desc sm8650_lpass_lpiaon_noc = { 1793 .config = &icc_regmap_config, 1794 .nodes = lpass_lpiaon_noc_nodes, 1795 .num_nodes = ARRAY_SIZE(lpass_lpiaon_noc_nodes), 1796 .bcms = lpass_lpiaon_noc_bcms, 1797 .num_bcms = ARRAY_SIZE(lpass_lpiaon_noc_bcms), 1798 }; 1799 1800 static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] = { 1801 [MASTER_LPASS_PROC] = &qxm_lpinoc_dsp_axim, 1802 [SLAVE_LPICX_NOC_LPIAON_NOC] = &qns_lpi_aon_noc, 1803 }; 1804 1805 static const struct qcom_icc_desc sm8650_lpass_lpicx_noc = { 1806 .config = &icc_regmap_config, 1807 .nodes = lpass_lpicx_noc_nodes, 1808 .num_nodes = ARRAY_SIZE(lpass_lpicx_noc_nodes), 1809 }; 1810 1811 static struct qcom_icc_bcm * const mc_virt_bcms[] = { 1812 &bcm_acv, 1813 &bcm_mc0, 1814 }; 1815 1816 static struct qcom_icc_node * const mc_virt_nodes[] = { 1817 [MASTER_LLCC] = &llcc_mc, 1818 [SLAVE_EBI1] = &ebi, 1819 }; 1820 1821 static const struct qcom_icc_desc sm8650_mc_virt = { 1822 .nodes = mc_virt_nodes, 1823 .num_nodes = ARRAY_SIZE(mc_virt_nodes), 1824 .bcms = mc_virt_bcms, 1825 .num_bcms = ARRAY_SIZE(mc_virt_bcms), 1826 }; 1827 1828 static struct qcom_icc_bcm * const mmss_noc_bcms[] = { 1829 &bcm_mm0, 1830 &bcm_mm1, 1831 }; 1832 1833 static struct qcom_icc_node * const mmss_noc_nodes[] = { 1834 [MASTER_CAMNOC_HF] = &qnm_camnoc_hf, 1835 [MASTER_CAMNOC_ICP] = &qnm_camnoc_icp, 1836 [MASTER_CAMNOC_SF] = &qnm_camnoc_sf, 1837 [MASTER_MDP] = &qnm_mdp, 1838 [MASTER_CDSP_HCP] = &qnm_vapss_hcp, 1839 [MASTER_VIDEO] = &qnm_video, 1840 [MASTER_VIDEO_CV_PROC] = &qnm_video_cv_cpu, 1841 [MASTER_VIDEO_PROC] = &qnm_video_cvp, 1842 [MASTER_VIDEO_V_PROC] = &qnm_video_v_cpu, 1843 [MASTER_CNOC_MNOC_CFG] = &qsm_mnoc_cfg, 1844 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, 1845 [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf, 1846 [SLAVE_SERVICE_MNOC] = &srvc_mnoc, 1847 }; 1848 1849 static const struct qcom_icc_desc sm8650_mmss_noc = { 1850 .config = &icc_regmap_config, 1851 .nodes = mmss_noc_nodes, 1852 .num_nodes = ARRAY_SIZE(mmss_noc_nodes), 1853 .bcms = mmss_noc_bcms, 1854 .num_bcms = ARRAY_SIZE(mmss_noc_bcms), 1855 }; 1856 1857 static struct qcom_icc_bcm * const nsp_noc_bcms[] = { 1858 &bcm_co0, 1859 }; 1860 1861 static struct qcom_icc_node * const nsp_noc_nodes[] = { 1862 [MASTER_CDSP_PROC] = &qnm_nsp, 1863 [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc, 1864 }; 1865 1866 static const struct qcom_icc_desc sm8650_nsp_noc = { 1867 .config = &icc_regmap_config, 1868 .nodes = nsp_noc_nodes, 1869 .num_nodes = ARRAY_SIZE(nsp_noc_nodes), 1870 .bcms = nsp_noc_bcms, 1871 .num_bcms = ARRAY_SIZE(nsp_noc_bcms), 1872 }; 1873 1874 static struct qcom_icc_bcm * const pcie_anoc_bcms[] = { 1875 &bcm_sn4, 1876 }; 1877 1878 static struct qcom_icc_node * const pcie_anoc_nodes[] = { 1879 [MASTER_PCIE_ANOC_CFG] = &qsm_pcie_anoc_cfg, 1880 [MASTER_PCIE_0] = &xm_pcie3_0, 1881 [MASTER_PCIE_1] = &xm_pcie3_1, 1882 [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc, 1883 [SLAVE_SERVICE_PCIE_ANOC] = &srvc_pcie_aggre_noc, 1884 }; 1885 1886 static const struct qcom_icc_desc sm8650_pcie_anoc = { 1887 .config = &icc_regmap_config, 1888 .nodes = pcie_anoc_nodes, 1889 .num_nodes = ARRAY_SIZE(pcie_anoc_nodes), 1890 .bcms = pcie_anoc_bcms, 1891 .num_bcms = ARRAY_SIZE(pcie_anoc_bcms), 1892 }; 1893 1894 static struct qcom_icc_bcm * const system_noc_bcms[] = { 1895 &bcm_sn0, 1896 &bcm_sn2, 1897 &bcm_sn3, 1898 }; 1899 1900 static struct qcom_icc_node * const system_noc_nodes[] = { 1901 [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc, 1902 [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc, 1903 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, 1904 [MASTER_APSS_NOC] = &qnm_apss_noc, 1905 }; 1906 1907 static const struct qcom_icc_desc sm8650_system_noc = { 1908 .config = &icc_regmap_config, 1909 .nodes = system_noc_nodes, 1910 .num_nodes = ARRAY_SIZE(system_noc_nodes), 1911 .bcms = system_noc_bcms, 1912 .num_bcms = ARRAY_SIZE(system_noc_bcms), 1913 }; 1914 1915 static const struct of_device_id qnoc_of_match[] = { 1916 { .compatible = "qcom,sm8650-aggre1-noc", .data = &sm8650_aggre1_noc }, 1917 { .compatible = "qcom,sm8650-aggre2-noc", .data = &sm8650_aggre2_noc }, 1918 { .compatible = "qcom,sm8650-clk-virt", .data = &sm8650_clk_virt }, 1919 { .compatible = "qcom,sm8650-config-noc", .data = &sm8650_config_noc }, 1920 { .compatible = "qcom,sm8650-cnoc-main", .data = &sm8650_cnoc_main }, 1921 { .compatible = "qcom,sm8650-gem-noc", .data = &sm8650_gem_noc }, 1922 { .compatible = "qcom,sm8650-lpass-ag-noc", .data = &sm8650_lpass_ag_noc }, 1923 { .compatible = "qcom,sm8650-lpass-lpiaon-noc", .data = &sm8650_lpass_lpiaon_noc }, 1924 { .compatible = "qcom,sm8650-lpass-lpicx-noc", .data = &sm8650_lpass_lpicx_noc }, 1925 { .compatible = "qcom,sm8650-mc-virt", .data = &sm8650_mc_virt }, 1926 { .compatible = "qcom,sm8650-mmss-noc", .data = &sm8650_mmss_noc }, 1927 { .compatible = "qcom,sm8650-nsp-noc", .data = &sm8650_nsp_noc }, 1928 { .compatible = "qcom,sm8650-pcie-anoc", .data = &sm8650_pcie_anoc }, 1929 { .compatible = "qcom,sm8650-system-noc", .data = &sm8650_system_noc }, 1930 { } 1931 }; 1932 MODULE_DEVICE_TABLE(of, qnoc_of_match); 1933 1934 static struct platform_driver qnoc_driver = { 1935 .probe = qcom_icc_rpmh_probe, 1936 .remove = qcom_icc_rpmh_remove, 1937 .driver = { 1938 .name = "qnoc-sm8650", 1939 .of_match_table = qnoc_of_match, 1940 .sync_state = icc_sync_state, 1941 }, 1942 }; 1943 1944 static int __init qnoc_driver_init(void) 1945 { 1946 return platform_driver_register(&qnoc_driver); 1947 } 1948 core_initcall(qnoc_driver_init); 1949 1950 static void __exit qnoc_driver_exit(void) 1951 { 1952 platform_driver_unregister(&qnoc_driver); 1953 } 1954 module_exit(qnoc_driver_exit); 1955 1956 MODULE_DESCRIPTION("sm8650 NoC driver"); 1957 MODULE_LICENSE("GPL"); 1958