1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2021, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
5 * Copyright (c) 2022, Linaro Limited
6 *
7 */
8
9 #include <linux/device.h>
10 #include <linux/interconnect.h>
11 #include <linux/interconnect-provider.h>
12 #include <linux/module.h>
13 #include <linux/platform_device.h>
14 #include <linux/property.h>
15 #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
16
17 #include "bcm-voter.h"
18 #include "icc-common.h"
19 #include "icc-rpmh.h"
20
21 static struct qcom_icc_node qhm_qspi;
22 static struct qcom_icc_node qhm_qup1;
23 static struct qcom_icc_node xm_sdc4;
24 static struct qcom_icc_node xm_ufs_mem;
25 static struct qcom_icc_node xm_usb3_0;
26 static struct qcom_icc_node qhm_qdss_bam;
27 static struct qcom_icc_node qhm_qup2;
28 static struct qcom_icc_node qxm_crypto;
29 static struct qcom_icc_node qxm_ipa;
30 static struct qcom_icc_node qxm_sp;
31 static struct qcom_icc_node xm_qdss_etr_0;
32 static struct qcom_icc_node xm_qdss_etr_1;
33 static struct qcom_icc_node xm_sdc2;
34 static struct qcom_icc_node qup0_core_master;
35 static struct qcom_icc_node qup1_core_master;
36 static struct qcom_icc_node qup2_core_master;
37 static struct qcom_icc_node qsm_cfg;
38 static struct qcom_icc_node qnm_gemnoc_cnoc;
39 static struct qcom_icc_node qnm_gemnoc_pcie;
40 static struct qcom_icc_node alm_gpu_tcu;
41 static struct qcom_icc_node alm_sys_tcu;
42 static struct qcom_icc_node chm_apps;
43 static struct qcom_icc_node qnm_gpu;
44 static struct qcom_icc_node qnm_lpass_gemnoc;
45 static struct qcom_icc_node qnm_mdsp;
46 static struct qcom_icc_node qnm_mnoc_hf;
47 static struct qcom_icc_node qnm_mnoc_sf;
48 static struct qcom_icc_node qnm_nsp_gemnoc;
49 static struct qcom_icc_node qnm_pcie;
50 static struct qcom_icc_node qnm_snoc_gc;
51 static struct qcom_icc_node qnm_snoc_sf;
52 static struct qcom_icc_node qnm_lpiaon_noc;
53 static struct qcom_icc_node qnm_lpass_lpinoc;
54 static struct qcom_icc_node qxm_lpinoc_dsp_axim;
55 static struct qcom_icc_node llcc_mc;
56 static struct qcom_icc_node qnm_camnoc_hf;
57 static struct qcom_icc_node qnm_camnoc_icp;
58 static struct qcom_icc_node qnm_camnoc_sf;
59 static struct qcom_icc_node qnm_mdp;
60 static struct qcom_icc_node qnm_vapss_hcp;
61 static struct qcom_icc_node qnm_video;
62 static struct qcom_icc_node qnm_video_cv_cpu;
63 static struct qcom_icc_node qnm_video_cvp;
64 static struct qcom_icc_node qnm_video_v_cpu;
65 static struct qcom_icc_node qsm_mnoc_cfg;
66 static struct qcom_icc_node qxm_nsp;
67 static struct qcom_icc_node qsm_pcie_anoc_cfg;
68 static struct qcom_icc_node xm_pcie3_0;
69 static struct qcom_icc_node xm_pcie3_1;
70 static struct qcom_icc_node qhm_gic;
71 static struct qcom_icc_node qnm_aggre1_noc;
72 static struct qcom_icc_node qnm_aggre2_noc;
73 static struct qcom_icc_node xm_gic;
74 static struct qcom_icc_node qns_a1noc_snoc;
75 static struct qcom_icc_node qns_a2noc_snoc;
76 static struct qcom_icc_node qup0_core_slave;
77 static struct qcom_icc_node qup1_core_slave;
78 static struct qcom_icc_node qup2_core_slave;
79 static struct qcom_icc_node qhs_ahb2phy0;
80 static struct qcom_icc_node qhs_ahb2phy1;
81 static struct qcom_icc_node qhs_apss;
82 static struct qcom_icc_node qhs_camera_cfg;
83 static struct qcom_icc_node qhs_clk_ctl;
84 static struct qcom_icc_node qhs_cpr_cx;
85 static struct qcom_icc_node qhs_cpr_mmcx;
86 static struct qcom_icc_node qhs_cpr_mxa;
87 static struct qcom_icc_node qhs_cpr_mxc;
88 static struct qcom_icc_node qhs_cpr_nspcx;
89 static struct qcom_icc_node qhs_crypto0_cfg;
90 static struct qcom_icc_node qhs_cx_rdpm;
91 static struct qcom_icc_node qhs_display_cfg;
92 static struct qcom_icc_node qhs_gpuss_cfg;
93 static struct qcom_icc_node qhs_i2c;
94 static struct qcom_icc_node qhs_imem_cfg;
95 static struct qcom_icc_node qhs_ipa;
96 static struct qcom_icc_node qhs_ipc_router;
97 static struct qcom_icc_node qhs_mss_cfg;
98 static struct qcom_icc_node qhs_mx_rdpm;
99 static struct qcom_icc_node qhs_pcie0_cfg;
100 static struct qcom_icc_node qhs_pcie1_cfg;
101 static struct qcom_icc_node qhs_pdm;
102 static struct qcom_icc_node qhs_pimem_cfg;
103 static struct qcom_icc_node qhs_prng;
104 static struct qcom_icc_node qhs_qdss_cfg;
105 static struct qcom_icc_node qhs_qspi;
106 static struct qcom_icc_node qhs_qup1;
107 static struct qcom_icc_node qhs_qup2;
108 static struct qcom_icc_node qhs_sdc2;
109 static struct qcom_icc_node qhs_sdc4;
110 static struct qcom_icc_node qhs_spss_cfg;
111 static struct qcom_icc_node qhs_tcsr;
112 static struct qcom_icc_node qhs_tlmm;
113 static struct qcom_icc_node qhs_ufs_mem_cfg;
114 static struct qcom_icc_node qhs_usb3_0;
115 static struct qcom_icc_node qhs_venus_cfg;
116 static struct qcom_icc_node qhs_vsense_ctrl_cfg;
117 static struct qcom_icc_node qss_lpass_qtb_cfg;
118 static struct qcom_icc_node qss_mnoc_cfg;
119 static struct qcom_icc_node qss_nsp_qtb_cfg;
120 static struct qcom_icc_node qss_pcie_anoc_cfg;
121 static struct qcom_icc_node xs_qdss_stm;
122 static struct qcom_icc_node xs_sys_tcu_cfg;
123 static struct qcom_icc_node qhs_aoss;
124 static struct qcom_icc_node qhs_tme_cfg;
125 static struct qcom_icc_node qss_cfg;
126 static struct qcom_icc_node qss_ddrss_cfg;
127 static struct qcom_icc_node qxs_boot_imem;
128 static struct qcom_icc_node qxs_imem;
129 static struct qcom_icc_node xs_pcie_0;
130 static struct qcom_icc_node xs_pcie_1;
131 static struct qcom_icc_node qns_gem_noc_cnoc;
132 static struct qcom_icc_node qns_llcc;
133 static struct qcom_icc_node qns_pcie;
134 static struct qcom_icc_node qns_lpass_ag_noc_gemnoc;
135 static struct qcom_icc_node qns_lpass_aggnoc;
136 static struct qcom_icc_node qns_lpi_aon_noc;
137 static struct qcom_icc_node ebi;
138 static struct qcom_icc_node qns_mem_noc_hf;
139 static struct qcom_icc_node qns_mem_noc_sf;
140 static struct qcom_icc_node srvc_mnoc;
141 static struct qcom_icc_node qns_nsp_gemnoc;
142 static struct qcom_icc_node qns_pcie_mem_noc;
143 static struct qcom_icc_node srvc_pcie_aggre_noc;
144 static struct qcom_icc_node qns_gemnoc_gc;
145 static struct qcom_icc_node qns_gemnoc_sf;
146
147 static struct qcom_icc_node qhm_qspi = {
148 .name = "qhm_qspi",
149 .channels = 1,
150 .buswidth = 4,
151 .num_links = 1,
152 .link_nodes = { &qns_a1noc_snoc },
153 };
154
155 static struct qcom_icc_node qhm_qup1 = {
156 .name = "qhm_qup1",
157 .channels = 1,
158 .buswidth = 4,
159 .num_links = 1,
160 .link_nodes = { &qns_a1noc_snoc },
161 };
162
163 static struct qcom_icc_node xm_sdc4 = {
164 .name = "xm_sdc4",
165 .channels = 1,
166 .buswidth = 8,
167 .num_links = 1,
168 .link_nodes = { &qns_a1noc_snoc },
169 };
170
171 static struct qcom_icc_node xm_ufs_mem = {
172 .name = "xm_ufs_mem",
173 .channels = 1,
174 .buswidth = 16,
175 .num_links = 1,
176 .link_nodes = { &qns_a1noc_snoc },
177 };
178
179 static struct qcom_icc_node xm_usb3_0 = {
180 .name = "xm_usb3_0",
181 .channels = 1,
182 .buswidth = 8,
183 .num_links = 1,
184 .link_nodes = { &qns_a1noc_snoc },
185 };
186
187 static struct qcom_icc_node qhm_qdss_bam = {
188 .name = "qhm_qdss_bam",
189 .channels = 1,
190 .buswidth = 4,
191 .num_links = 1,
192 .link_nodes = { &qns_a2noc_snoc },
193 };
194
195 static struct qcom_icc_node qhm_qup2 = {
196 .name = "qhm_qup2",
197 .channels = 1,
198 .buswidth = 4,
199 .num_links = 1,
200 .link_nodes = { &qns_a2noc_snoc },
201 };
202
203 static struct qcom_icc_node qxm_crypto = {
204 .name = "qxm_crypto",
205 .channels = 1,
206 .buswidth = 8,
207 .num_links = 1,
208 .link_nodes = { &qns_a2noc_snoc },
209 };
210
211 static struct qcom_icc_node qxm_ipa = {
212 .name = "qxm_ipa",
213 .channels = 1,
214 .buswidth = 8,
215 .num_links = 1,
216 .link_nodes = { &qns_a2noc_snoc },
217 };
218
219 static struct qcom_icc_node qxm_sp = {
220 .name = "qxm_sp",
221 .channels = 1,
222 .buswidth = 8,
223 .num_links = 1,
224 .link_nodes = { &qns_a2noc_snoc },
225 };
226
227 static struct qcom_icc_node xm_qdss_etr_0 = {
228 .name = "xm_qdss_etr_0",
229 .channels = 1,
230 .buswidth = 8,
231 .num_links = 1,
232 .link_nodes = { &qns_a2noc_snoc },
233 };
234
235 static struct qcom_icc_node xm_qdss_etr_1 = {
236 .name = "xm_qdss_etr_1",
237 .channels = 1,
238 .buswidth = 8,
239 .num_links = 1,
240 .link_nodes = { &qns_a2noc_snoc },
241 };
242
243 static struct qcom_icc_node xm_sdc2 = {
244 .name = "xm_sdc2",
245 .channels = 1,
246 .buswidth = 8,
247 .num_links = 1,
248 .link_nodes = { &qns_a2noc_snoc },
249 };
250
251 static struct qcom_icc_node qup0_core_master = {
252 .name = "qup0_core_master",
253 .channels = 1,
254 .buswidth = 4,
255 .num_links = 1,
256 .link_nodes = { &qup0_core_slave },
257 };
258
259 static struct qcom_icc_node qup1_core_master = {
260 .name = "qup1_core_master",
261 .channels = 1,
262 .buswidth = 4,
263 .num_links = 1,
264 .link_nodes = { &qup1_core_slave },
265 };
266
267 static struct qcom_icc_node qup2_core_master = {
268 .name = "qup2_core_master",
269 .channels = 1,
270 .buswidth = 4,
271 .num_links = 1,
272 .link_nodes = { &qup2_core_slave },
273 };
274
275 static struct qcom_icc_node qsm_cfg = {
276 .name = "qsm_cfg",
277 .channels = 1,
278 .buswidth = 4,
279 .num_links = 44,
280 .link_nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1,
281 &qhs_apss, &qhs_camera_cfg,
282 &qhs_clk_ctl, &qhs_cpr_cx,
283 &qhs_cpr_mmcx, &qhs_cpr_mxa,
284 &qhs_cpr_mxc, &qhs_cpr_nspcx,
285 &qhs_crypto0_cfg, &qhs_cx_rdpm,
286 &qhs_display_cfg, &qhs_gpuss_cfg,
287 &qhs_i2c, &qhs_imem_cfg,
288 &qhs_ipa, &qhs_ipc_router,
289 &qhs_mss_cfg, &qhs_mx_rdpm,
290 &qhs_pcie0_cfg, &qhs_pcie1_cfg,
291 &qhs_pdm, &qhs_pimem_cfg,
292 &qhs_prng, &qhs_qdss_cfg,
293 &qhs_qspi, &qhs_qup1,
294 &qhs_qup2, &qhs_sdc2,
295 &qhs_sdc4, &qhs_spss_cfg,
296 &qhs_tcsr, &qhs_tlmm,
297 &qhs_ufs_mem_cfg, &qhs_usb3_0,
298 &qhs_venus_cfg, &qhs_vsense_ctrl_cfg,
299 &qss_lpass_qtb_cfg, &qss_mnoc_cfg,
300 &qss_nsp_qtb_cfg, &qss_pcie_anoc_cfg,
301 &xs_qdss_stm, &xs_sys_tcu_cfg },
302 };
303
304 static struct qcom_icc_node qnm_gemnoc_cnoc = {
305 .name = "qnm_gemnoc_cnoc",
306 .channels = 1,
307 .buswidth = 16,
308 .num_links = 6,
309 .link_nodes = { &qhs_aoss, &qhs_tme_cfg,
310 &qss_cfg, &qss_ddrss_cfg,
311 &qxs_boot_imem, &qxs_imem },
312 };
313
314 static struct qcom_icc_node qnm_gemnoc_pcie = {
315 .name = "qnm_gemnoc_pcie",
316 .channels = 1,
317 .buswidth = 8,
318 .num_links = 2,
319 .link_nodes = { &xs_pcie_0, &xs_pcie_1 },
320 };
321
322 static struct qcom_icc_node alm_gpu_tcu = {
323 .name = "alm_gpu_tcu",
324 .channels = 1,
325 .buswidth = 8,
326 .num_links = 2,
327 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
328 };
329
330 static struct qcom_icc_node alm_sys_tcu = {
331 .name = "alm_sys_tcu",
332 .channels = 1,
333 .buswidth = 8,
334 .num_links = 2,
335 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
336 };
337
338 static struct qcom_icc_node chm_apps = {
339 .name = "chm_apps",
340 .channels = 3,
341 .buswidth = 32,
342 .num_links = 3,
343 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
344 &qns_pcie },
345 };
346
347 static struct qcom_icc_node qnm_gpu = {
348 .name = "qnm_gpu",
349 .channels = 2,
350 .buswidth = 32,
351 .num_links = 2,
352 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
353 };
354
355 static struct qcom_icc_node qnm_lpass_gemnoc = {
356 .name = "qnm_lpass_gemnoc",
357 .channels = 1,
358 .buswidth = 16,
359 .num_links = 3,
360 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
361 &qns_pcie },
362 };
363
364 static struct qcom_icc_node qnm_mdsp = {
365 .name = "qnm_mdsp",
366 .channels = 1,
367 .buswidth = 16,
368 .num_links = 3,
369 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
370 &qns_pcie },
371 };
372
373 static struct qcom_icc_node qnm_mnoc_hf = {
374 .name = "qnm_mnoc_hf",
375 .channels = 2,
376 .buswidth = 32,
377 .num_links = 2,
378 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
379 };
380
381 static struct qcom_icc_node qnm_mnoc_sf = {
382 .name = "qnm_mnoc_sf",
383 .channels = 2,
384 .buswidth = 32,
385 .num_links = 2,
386 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
387 };
388
389 static struct qcom_icc_node qnm_nsp_gemnoc = {
390 .name = "qnm_nsp_gemnoc",
391 .channels = 2,
392 .buswidth = 32,
393 .num_links = 2,
394 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
395 };
396
397 static struct qcom_icc_node qnm_pcie = {
398 .name = "qnm_pcie",
399 .channels = 1,
400 .buswidth = 16,
401 .num_links = 2,
402 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
403 };
404
405 static struct qcom_icc_node qnm_snoc_gc = {
406 .name = "qnm_snoc_gc",
407 .channels = 1,
408 .buswidth = 8,
409 .num_links = 1,
410 .link_nodes = { &qns_llcc },
411 };
412
413 static struct qcom_icc_node qnm_snoc_sf = {
414 .name = "qnm_snoc_sf",
415 .channels = 1,
416 .buswidth = 16,
417 .num_links = 3,
418 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
419 &qns_pcie },
420 };
421
422 static struct qcom_icc_node qnm_lpiaon_noc = {
423 .name = "qnm_lpiaon_noc",
424 .channels = 1,
425 .buswidth = 16,
426 .num_links = 1,
427 .link_nodes = { &qns_lpass_ag_noc_gemnoc },
428 };
429
430 static struct qcom_icc_node qnm_lpass_lpinoc = {
431 .name = "qnm_lpass_lpinoc",
432 .channels = 1,
433 .buswidth = 16,
434 .num_links = 1,
435 .link_nodes = { &qns_lpass_aggnoc },
436 };
437
438 static struct qcom_icc_node qxm_lpinoc_dsp_axim = {
439 .name = "qxm_lpinoc_dsp_axim",
440 .channels = 1,
441 .buswidth = 16,
442 .num_links = 1,
443 .link_nodes = { &qns_lpi_aon_noc },
444 };
445
446 static struct qcom_icc_node llcc_mc = {
447 .name = "llcc_mc",
448 .channels = 4,
449 .buswidth = 4,
450 .num_links = 1,
451 .link_nodes = { &ebi },
452 };
453
454 static struct qcom_icc_node qnm_camnoc_hf = {
455 .name = "qnm_camnoc_hf",
456 .channels = 2,
457 .buswidth = 32,
458 .num_links = 1,
459 .link_nodes = { &qns_mem_noc_hf },
460 };
461
462 static struct qcom_icc_node qnm_camnoc_icp = {
463 .name = "qnm_camnoc_icp",
464 .channels = 1,
465 .buswidth = 8,
466 .num_links = 1,
467 .link_nodes = { &qns_mem_noc_sf },
468 };
469
470 static struct qcom_icc_node qnm_camnoc_sf = {
471 .name = "qnm_camnoc_sf",
472 .channels = 2,
473 .buswidth = 32,
474 .num_links = 1,
475 .link_nodes = { &qns_mem_noc_sf },
476 };
477
478 static struct qcom_icc_node qnm_mdp = {
479 .name = "qnm_mdp",
480 .channels = 2,
481 .buswidth = 32,
482 .num_links = 1,
483 .link_nodes = { &qns_mem_noc_hf },
484 };
485
486 static struct qcom_icc_node qnm_vapss_hcp = {
487 .name = "qnm_vapss_hcp",
488 .channels = 1,
489 .buswidth = 32,
490 .num_links = 1,
491 .link_nodes = { &qns_mem_noc_sf },
492 };
493
494 static struct qcom_icc_node qnm_video = {
495 .name = "qnm_video",
496 .channels = 2,
497 .buswidth = 32,
498 .num_links = 1,
499 .link_nodes = { &qns_mem_noc_sf },
500 };
501
502 static struct qcom_icc_node qnm_video_cv_cpu = {
503 .name = "qnm_video_cv_cpu",
504 .channels = 1,
505 .buswidth = 8,
506 .num_links = 1,
507 .link_nodes = { &qns_mem_noc_sf },
508 };
509
510 static struct qcom_icc_node qnm_video_cvp = {
511 .name = "qnm_video_cvp",
512 .channels = 1,
513 .buswidth = 32,
514 .num_links = 1,
515 .link_nodes = { &qns_mem_noc_sf },
516 };
517
518 static struct qcom_icc_node qnm_video_v_cpu = {
519 .name = "qnm_video_v_cpu",
520 .channels = 1,
521 .buswidth = 8,
522 .num_links = 1,
523 .link_nodes = { &qns_mem_noc_sf },
524 };
525
526 static struct qcom_icc_node qsm_mnoc_cfg = {
527 .name = "qsm_mnoc_cfg",
528 .channels = 1,
529 .buswidth = 4,
530 .num_links = 1,
531 .link_nodes = { &srvc_mnoc },
532 };
533
534 static struct qcom_icc_node qxm_nsp = {
535 .name = "qxm_nsp",
536 .channels = 2,
537 .buswidth = 32,
538 .num_links = 1,
539 .link_nodes = { &qns_nsp_gemnoc },
540 };
541
542 static struct qcom_icc_node qsm_pcie_anoc_cfg = {
543 .name = "qsm_pcie_anoc_cfg",
544 .channels = 1,
545 .buswidth = 4,
546 .num_links = 1,
547 .link_nodes = { &srvc_pcie_aggre_noc },
548 };
549
550 static struct qcom_icc_node xm_pcie3_0 = {
551 .name = "xm_pcie3_0",
552 .channels = 1,
553 .buswidth = 8,
554 .num_links = 1,
555 .link_nodes = { &qns_pcie_mem_noc },
556 };
557
558 static struct qcom_icc_node xm_pcie3_1 = {
559 .name = "xm_pcie3_1",
560 .channels = 1,
561 .buswidth = 16,
562 .num_links = 1,
563 .link_nodes = { &qns_pcie_mem_noc },
564 };
565
566 static struct qcom_icc_node qhm_gic = {
567 .name = "qhm_gic",
568 .channels = 1,
569 .buswidth = 4,
570 .num_links = 1,
571 .link_nodes = { &qns_gemnoc_sf },
572 };
573
574 static struct qcom_icc_node qnm_aggre1_noc = {
575 .name = "qnm_aggre1_noc",
576 .channels = 1,
577 .buswidth = 16,
578 .num_links = 1,
579 .link_nodes = { &qns_gemnoc_sf },
580 };
581
582 static struct qcom_icc_node qnm_aggre2_noc = {
583 .name = "qnm_aggre2_noc",
584 .channels = 1,
585 .buswidth = 16,
586 .num_links = 1,
587 .link_nodes = { &qns_gemnoc_sf },
588 };
589
590 static struct qcom_icc_node xm_gic = {
591 .name = "xm_gic",
592 .channels = 1,
593 .buswidth = 8,
594 .num_links = 1,
595 .link_nodes = { &qns_gemnoc_gc },
596 };
597
598 static struct qcom_icc_node qns_a1noc_snoc = {
599 .name = "qns_a1noc_snoc",
600 .channels = 1,
601 .buswidth = 16,
602 .num_links = 1,
603 .link_nodes = { &qnm_aggre1_noc },
604 };
605
606 static struct qcom_icc_node qns_a2noc_snoc = {
607 .name = "qns_a2noc_snoc",
608 .channels = 1,
609 .buswidth = 16,
610 .num_links = 1,
611 .link_nodes = { &qnm_aggre2_noc },
612 };
613
614 static struct qcom_icc_node qup0_core_slave = {
615 .name = "qup0_core_slave",
616 .channels = 1,
617 .buswidth = 4,
618 };
619
620 static struct qcom_icc_node qup1_core_slave = {
621 .name = "qup1_core_slave",
622 .channels = 1,
623 .buswidth = 4,
624 };
625
626 static struct qcom_icc_node qup2_core_slave = {
627 .name = "qup2_core_slave",
628 .channels = 1,
629 .buswidth = 4,
630 };
631
632 static struct qcom_icc_node qhs_ahb2phy0 = {
633 .name = "qhs_ahb2phy0",
634 .channels = 1,
635 .buswidth = 4,
636 };
637
638 static struct qcom_icc_node qhs_ahb2phy1 = {
639 .name = "qhs_ahb2phy1",
640 .channels = 1,
641 .buswidth = 4,
642 };
643
644 static struct qcom_icc_node qhs_apss = {
645 .name = "qhs_apss",
646 .channels = 1,
647 .buswidth = 8,
648 };
649
650 static struct qcom_icc_node qhs_camera_cfg = {
651 .name = "qhs_camera_cfg",
652 .channels = 1,
653 .buswidth = 4,
654 };
655
656 static struct qcom_icc_node qhs_clk_ctl = {
657 .name = "qhs_clk_ctl",
658 .channels = 1,
659 .buswidth = 4,
660 };
661
662 static struct qcom_icc_node qhs_cpr_cx = {
663 .name = "qhs_cpr_cx",
664 .channels = 1,
665 .buswidth = 4,
666 };
667
668 static struct qcom_icc_node qhs_cpr_mmcx = {
669 .name = "qhs_cpr_mmcx",
670 .channels = 1,
671 .buswidth = 4,
672 };
673
674 static struct qcom_icc_node qhs_cpr_mxa = {
675 .name = "qhs_cpr_mxa",
676 .channels = 1,
677 .buswidth = 4,
678 };
679
680 static struct qcom_icc_node qhs_cpr_mxc = {
681 .name = "qhs_cpr_mxc",
682 .channels = 1,
683 .buswidth = 4,
684 };
685
686 static struct qcom_icc_node qhs_cpr_nspcx = {
687 .name = "qhs_cpr_nspcx",
688 .channels = 1,
689 .buswidth = 4,
690 };
691
692 static struct qcom_icc_node qhs_crypto0_cfg = {
693 .name = "qhs_crypto0_cfg",
694 .channels = 1,
695 .buswidth = 4,
696 };
697
698 static struct qcom_icc_node qhs_cx_rdpm = {
699 .name = "qhs_cx_rdpm",
700 .channels = 1,
701 .buswidth = 4,
702 };
703
704 static struct qcom_icc_node qhs_display_cfg = {
705 .name = "qhs_display_cfg",
706 .channels = 1,
707 .buswidth = 4,
708 };
709
710 static struct qcom_icc_node qhs_gpuss_cfg = {
711 .name = "qhs_gpuss_cfg",
712 .channels = 1,
713 .buswidth = 8,
714 };
715
716 static struct qcom_icc_node qhs_i2c = {
717 .name = "qhs_i2c",
718 .channels = 1,
719 .buswidth = 4,
720 };
721
722 static struct qcom_icc_node qhs_imem_cfg = {
723 .name = "qhs_imem_cfg",
724 .channels = 1,
725 .buswidth = 4,
726 };
727
728 static struct qcom_icc_node qhs_ipa = {
729 .name = "qhs_ipa",
730 .channels = 1,
731 .buswidth = 4,
732 };
733
734 static struct qcom_icc_node qhs_ipc_router = {
735 .name = "qhs_ipc_router",
736 .channels = 1,
737 .buswidth = 4,
738 };
739
740 static struct qcom_icc_node qhs_mss_cfg = {
741 .name = "qhs_mss_cfg",
742 .channels = 1,
743 .buswidth = 4,
744 };
745
746 static struct qcom_icc_node qhs_mx_rdpm = {
747 .name = "qhs_mx_rdpm",
748 .channels = 1,
749 .buswidth = 4,
750 };
751
752 static struct qcom_icc_node qhs_pcie0_cfg = {
753 .name = "qhs_pcie0_cfg",
754 .channels = 1,
755 .buswidth = 4,
756 };
757
758 static struct qcom_icc_node qhs_pcie1_cfg = {
759 .name = "qhs_pcie1_cfg",
760 .channels = 1,
761 .buswidth = 4,
762 };
763
764 static struct qcom_icc_node qhs_pdm = {
765 .name = "qhs_pdm",
766 .channels = 1,
767 .buswidth = 4,
768 };
769
770 static struct qcom_icc_node qhs_pimem_cfg = {
771 .name = "qhs_pimem_cfg",
772 .channels = 1,
773 .buswidth = 4,
774 };
775
776 static struct qcom_icc_node qhs_prng = {
777 .name = "qhs_prng",
778 .channels = 1,
779 .buswidth = 4,
780 };
781
782 static struct qcom_icc_node qhs_qdss_cfg = {
783 .name = "qhs_qdss_cfg",
784 .channels = 1,
785 .buswidth = 4,
786 };
787
788 static struct qcom_icc_node qhs_qspi = {
789 .name = "qhs_qspi",
790 .channels = 1,
791 .buswidth = 4,
792 };
793
794 static struct qcom_icc_node qhs_qup1 = {
795 .name = "qhs_qup1",
796 .channels = 1,
797 .buswidth = 4,
798 };
799
800 static struct qcom_icc_node qhs_qup2 = {
801 .name = "qhs_qup2",
802 .channels = 1,
803 .buswidth = 4,
804 };
805
806 static struct qcom_icc_node qhs_sdc2 = {
807 .name = "qhs_sdc2",
808 .channels = 1,
809 .buswidth = 4,
810 };
811
812 static struct qcom_icc_node qhs_sdc4 = {
813 .name = "qhs_sdc4",
814 .channels = 1,
815 .buswidth = 4,
816 };
817
818 static struct qcom_icc_node qhs_spss_cfg = {
819 .name = "qhs_spss_cfg",
820 .channels = 1,
821 .buswidth = 4,
822 };
823
824 static struct qcom_icc_node qhs_tcsr = {
825 .name = "qhs_tcsr",
826 .channels = 1,
827 .buswidth = 4,
828 };
829
830 static struct qcom_icc_node qhs_tlmm = {
831 .name = "qhs_tlmm",
832 .channels = 1,
833 .buswidth = 4,
834 };
835
836 static struct qcom_icc_node qhs_ufs_mem_cfg = {
837 .name = "qhs_ufs_mem_cfg",
838 .channels = 1,
839 .buswidth = 4,
840 };
841
842 static struct qcom_icc_node qhs_usb3_0 = {
843 .name = "qhs_usb3_0",
844 .channels = 1,
845 .buswidth = 4,
846 };
847
848 static struct qcom_icc_node qhs_venus_cfg = {
849 .name = "qhs_venus_cfg",
850 .channels = 1,
851 .buswidth = 4,
852 };
853
854 static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
855 .name = "qhs_vsense_ctrl_cfg",
856 .channels = 1,
857 .buswidth = 4,
858 };
859
860 static struct qcom_icc_node qss_lpass_qtb_cfg = {
861 .name = "qss_lpass_qtb_cfg",
862 .channels = 1,
863 .buswidth = 4,
864 };
865
866 static struct qcom_icc_node qss_mnoc_cfg = {
867 .name = "qss_mnoc_cfg",
868 .channels = 1,
869 .buswidth = 4,
870 .num_links = 1,
871 .link_nodes = { &qsm_mnoc_cfg },
872 };
873
874 static struct qcom_icc_node qss_nsp_qtb_cfg = {
875 .name = "qss_nsp_qtb_cfg",
876 .channels = 1,
877 .buswidth = 4,
878 };
879
880 static struct qcom_icc_node qss_pcie_anoc_cfg = {
881 .name = "qss_pcie_anoc_cfg",
882 .channels = 1,
883 .buswidth = 4,
884 .num_links = 1,
885 .link_nodes = { &qsm_pcie_anoc_cfg },
886 };
887
888 static struct qcom_icc_node xs_qdss_stm = {
889 .name = "xs_qdss_stm",
890 .channels = 1,
891 .buswidth = 4,
892 };
893
894 static struct qcom_icc_node xs_sys_tcu_cfg = {
895 .name = "xs_sys_tcu_cfg",
896 .channels = 1,
897 .buswidth = 8,
898 };
899
900 static struct qcom_icc_node qhs_aoss = {
901 .name = "qhs_aoss",
902 .channels = 1,
903 .buswidth = 4,
904 };
905
906 static struct qcom_icc_node qhs_tme_cfg = {
907 .name = "qhs_tme_cfg",
908 .channels = 1,
909 .buswidth = 4,
910 };
911
912 static struct qcom_icc_node qss_cfg = {
913 .name = "qss_cfg",
914 .channels = 1,
915 .buswidth = 4,
916 .num_links = 1,
917 .link_nodes = { &qsm_cfg },
918 };
919
920 static struct qcom_icc_node qss_ddrss_cfg = {
921 .name = "qss_ddrss_cfg",
922 .channels = 1,
923 .buswidth = 4,
924 };
925
926 static struct qcom_icc_node qxs_boot_imem = {
927 .name = "qxs_boot_imem",
928 .channels = 1,
929 .buswidth = 8,
930 };
931
932 static struct qcom_icc_node qxs_imem = {
933 .name = "qxs_imem",
934 .channels = 1,
935 .buswidth = 8,
936 };
937
938 static struct qcom_icc_node xs_pcie_0 = {
939 .name = "xs_pcie_0",
940 .channels = 1,
941 .buswidth = 8,
942 };
943
944 static struct qcom_icc_node xs_pcie_1 = {
945 .name = "xs_pcie_1",
946 .channels = 1,
947 .buswidth = 16,
948 };
949
950 static struct qcom_icc_node qns_gem_noc_cnoc = {
951 .name = "qns_gem_noc_cnoc",
952 .channels = 1,
953 .buswidth = 16,
954 .num_links = 1,
955 .link_nodes = { &qnm_gemnoc_cnoc },
956 };
957
958 static struct qcom_icc_node qns_llcc = {
959 .name = "qns_llcc",
960 .channels = 4,
961 .buswidth = 16,
962 .num_links = 1,
963 .link_nodes = { &llcc_mc },
964 };
965
966 static struct qcom_icc_node qns_pcie = {
967 .name = "qns_pcie",
968 .channels = 1,
969 .buswidth = 8,
970 .num_links = 1,
971 .link_nodes = { &qnm_gemnoc_pcie },
972 };
973
974 static struct qcom_icc_node qns_lpass_ag_noc_gemnoc = {
975 .name = "qns_lpass_ag_noc_gemnoc",
976 .channels = 1,
977 .buswidth = 16,
978 .num_links = 1,
979 .link_nodes = { &qnm_lpass_gemnoc },
980 };
981
982 static struct qcom_icc_node qns_lpass_aggnoc = {
983 .name = "qns_lpass_aggnoc",
984 .channels = 1,
985 .buswidth = 16,
986 .num_links = 1,
987 .link_nodes = { &qnm_lpiaon_noc },
988 };
989
990 static struct qcom_icc_node qns_lpi_aon_noc = {
991 .name = "qns_lpi_aon_noc",
992 .channels = 1,
993 .buswidth = 16,
994 .num_links = 1,
995 .link_nodes = { &qnm_lpass_lpinoc },
996 };
997
998 static struct qcom_icc_node ebi = {
999 .name = "ebi",
1000 .channels = 4,
1001 .buswidth = 4,
1002 };
1003
1004 static struct qcom_icc_node qns_mem_noc_hf = {
1005 .name = "qns_mem_noc_hf",
1006 .channels = 2,
1007 .buswidth = 32,
1008 .num_links = 1,
1009 .link_nodes = { &qnm_mnoc_hf },
1010 };
1011
1012 static struct qcom_icc_node qns_mem_noc_sf = {
1013 .name = "qns_mem_noc_sf",
1014 .channels = 2,
1015 .buswidth = 32,
1016 .num_links = 1,
1017 .link_nodes = { &qnm_mnoc_sf },
1018 };
1019
1020 static struct qcom_icc_node srvc_mnoc = {
1021 .name = "srvc_mnoc",
1022 .channels = 1,
1023 .buswidth = 4,
1024 };
1025
1026 static struct qcom_icc_node qns_nsp_gemnoc = {
1027 .name = "qns_nsp_gemnoc",
1028 .channels = 2,
1029 .buswidth = 32,
1030 .num_links = 1,
1031 .link_nodes = { &qnm_nsp_gemnoc },
1032 };
1033
1034 static struct qcom_icc_node qns_pcie_mem_noc = {
1035 .name = "qns_pcie_mem_noc",
1036 .channels = 1,
1037 .buswidth = 16,
1038 .num_links = 1,
1039 .link_nodes = { &qnm_pcie },
1040 };
1041
1042 static struct qcom_icc_node srvc_pcie_aggre_noc = {
1043 .name = "srvc_pcie_aggre_noc",
1044 .channels = 1,
1045 .buswidth = 4,
1046 };
1047
1048 static struct qcom_icc_node qns_gemnoc_gc = {
1049 .name = "qns_gemnoc_gc",
1050 .channels = 1,
1051 .buswidth = 8,
1052 .num_links = 1,
1053 .link_nodes = { &qnm_snoc_gc },
1054 };
1055
1056 static struct qcom_icc_node qns_gemnoc_sf = {
1057 .name = "qns_gemnoc_sf",
1058 .channels = 1,
1059 .buswidth = 16,
1060 .num_links = 1,
1061 .link_nodes = { &qnm_snoc_sf },
1062 };
1063
1064 static struct qcom_icc_bcm bcm_acv = {
1065 .name = "ACV",
1066 .enable_mask = 0x8,
1067 .num_nodes = 1,
1068 .nodes = { &ebi },
1069 };
1070
1071 static struct qcom_icc_bcm bcm_ce0 = {
1072 .name = "CE0",
1073 .num_nodes = 1,
1074 .nodes = { &qxm_crypto },
1075 };
1076
1077 static struct qcom_icc_bcm bcm_cn0 = {
1078 .name = "CN0",
1079 .enable_mask = 0x1,
1080 .keepalive = true,
1081 .num_nodes = 54,
1082 .nodes = { &qsm_cfg, &qhs_ahb2phy0,
1083 &qhs_ahb2phy1, &qhs_apss,
1084 &qhs_camera_cfg, &qhs_clk_ctl,
1085 &qhs_cpr_cx, &qhs_cpr_mmcx,
1086 &qhs_cpr_mxa, &qhs_cpr_mxc,
1087 &qhs_cpr_nspcx, &qhs_crypto0_cfg,
1088 &qhs_cx_rdpm, &qhs_gpuss_cfg,
1089 &qhs_i2c, &qhs_imem_cfg,
1090 &qhs_ipa, &qhs_ipc_router,
1091 &qhs_mss_cfg, &qhs_mx_rdpm,
1092 &qhs_pcie0_cfg, &qhs_pcie1_cfg,
1093 &qhs_pdm, &qhs_pimem_cfg,
1094 &qhs_prng, &qhs_qdss_cfg,
1095 &qhs_qspi, &qhs_qup1,
1096 &qhs_qup2, &qhs_sdc2,
1097 &qhs_sdc4, &qhs_spss_cfg,
1098 &qhs_tcsr, &qhs_tlmm,
1099 &qhs_ufs_mem_cfg, &qhs_usb3_0,
1100 &qhs_venus_cfg, &qhs_vsense_ctrl_cfg,
1101 &qss_lpass_qtb_cfg, &qss_mnoc_cfg,
1102 &qss_nsp_qtb_cfg, &qss_pcie_anoc_cfg,
1103 &xs_qdss_stm, &xs_sys_tcu_cfg,
1104 &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie,
1105 &qhs_aoss, &qhs_tme_cfg,
1106 &qss_cfg, &qss_ddrss_cfg,
1107 &qxs_boot_imem, &qxs_imem,
1108 &xs_pcie_0, &xs_pcie_1 },
1109 };
1110
1111 static struct qcom_icc_bcm bcm_cn1 = {
1112 .name = "CN1",
1113 .num_nodes = 1,
1114 .nodes = { &qhs_display_cfg },
1115 };
1116
1117 static struct qcom_icc_bcm bcm_co0 = {
1118 .name = "CO0",
1119 .enable_mask = 0x1,
1120 .num_nodes = 2,
1121 .nodes = { &qxm_nsp, &qns_nsp_gemnoc },
1122 };
1123
1124 static struct qcom_icc_bcm bcm_lp0 = {
1125 .name = "LP0",
1126 .num_nodes = 2,
1127 .nodes = { &qnm_lpass_lpinoc, &qns_lpass_aggnoc },
1128 };
1129
1130 static struct qcom_icc_bcm bcm_mc0 = {
1131 .name = "MC0",
1132 .keepalive = true,
1133 .num_nodes = 1,
1134 .nodes = { &ebi },
1135 };
1136
1137 static struct qcom_icc_bcm bcm_mm0 = {
1138 .name = "MM0",
1139 .num_nodes = 1,
1140 .nodes = { &qns_mem_noc_hf },
1141 };
1142
1143 static struct qcom_icc_bcm bcm_mm1 = {
1144 .name = "MM1",
1145 .enable_mask = 0x1,
1146 .num_nodes = 8,
1147 .nodes = { &qnm_camnoc_hf, &qnm_camnoc_icp,
1148 &qnm_camnoc_sf, &qnm_vapss_hcp,
1149 &qnm_video_cv_cpu, &qnm_video_cvp,
1150 &qnm_video_v_cpu, &qns_mem_noc_sf },
1151 };
1152
1153 static struct qcom_icc_bcm bcm_qup0 = {
1154 .name = "QUP0",
1155 .keepalive = true,
1156 .vote_scale = 1,
1157 .num_nodes = 1,
1158 .nodes = { &qup0_core_slave },
1159 };
1160
1161 static struct qcom_icc_bcm bcm_qup1 = {
1162 .name = "QUP1",
1163 .keepalive = true,
1164 .vote_scale = 1,
1165 .num_nodes = 1,
1166 .nodes = { &qup1_core_slave },
1167 };
1168
1169 static struct qcom_icc_bcm bcm_qup2 = {
1170 .name = "QUP2",
1171 .keepalive = true,
1172 .vote_scale = 1,
1173 .num_nodes = 1,
1174 .nodes = { &qup2_core_slave },
1175 };
1176
1177 static struct qcom_icc_bcm bcm_sh0 = {
1178 .name = "SH0",
1179 .keepalive = true,
1180 .num_nodes = 1,
1181 .nodes = { &qns_llcc },
1182 };
1183
1184 static struct qcom_icc_bcm bcm_sh1 = {
1185 .name = "SH1",
1186 .enable_mask = 0x1,
1187 .num_nodes = 13,
1188 .nodes = { &alm_gpu_tcu, &alm_sys_tcu,
1189 &chm_apps, &qnm_gpu,
1190 &qnm_mdsp, &qnm_mnoc_hf,
1191 &qnm_mnoc_sf, &qnm_nsp_gemnoc,
1192 &qnm_pcie, &qnm_snoc_gc,
1193 &qnm_snoc_sf, &qns_gem_noc_cnoc,
1194 &qns_pcie },
1195 };
1196
1197 static struct qcom_icc_bcm bcm_sn0 = {
1198 .name = "SN0",
1199 .keepalive = true,
1200 .num_nodes = 1,
1201 .nodes = { &qns_gemnoc_sf },
1202 };
1203
1204 static struct qcom_icc_bcm bcm_sn1 = {
1205 .name = "SN1",
1206 .enable_mask = 0x1,
1207 .num_nodes = 3,
1208 .nodes = { &qhm_gic, &xm_gic,
1209 &qns_gemnoc_gc },
1210 };
1211
1212 static struct qcom_icc_bcm bcm_sn2 = {
1213 .name = "SN2",
1214 .num_nodes = 1,
1215 .nodes = { &qnm_aggre1_noc },
1216 };
1217
1218 static struct qcom_icc_bcm bcm_sn3 = {
1219 .name = "SN3",
1220 .num_nodes = 1,
1221 .nodes = { &qnm_aggre2_noc },
1222 };
1223
1224 static struct qcom_icc_bcm bcm_sn7 = {
1225 .name = "SN7",
1226 .num_nodes = 1,
1227 .nodes = { &qns_pcie_mem_noc },
1228 };
1229
1230 static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
1231 };
1232
1233 static struct qcom_icc_node * const aggre1_noc_nodes[] = {
1234 [MASTER_QSPI_0] = &qhm_qspi,
1235 [MASTER_QUP_1] = &qhm_qup1,
1236 [MASTER_SDCC_4] = &xm_sdc4,
1237 [MASTER_UFS_MEM] = &xm_ufs_mem,
1238 [MASTER_USB3_0] = &xm_usb3_0,
1239 [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
1240 };
1241
1242 static const struct qcom_icc_desc sm8550_aggre1_noc = {
1243 .nodes = aggre1_noc_nodes,
1244 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
1245 .bcms = aggre1_noc_bcms,
1246 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
1247 };
1248
1249 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
1250 &bcm_ce0,
1251 };
1252
1253 static struct qcom_icc_node * const aggre2_noc_nodes[] = {
1254 [MASTER_QDSS_BAM] = &qhm_qdss_bam,
1255 [MASTER_QUP_2] = &qhm_qup2,
1256 [MASTER_CRYPTO] = &qxm_crypto,
1257 [MASTER_IPA] = &qxm_ipa,
1258 [MASTER_SP] = &qxm_sp,
1259 [MASTER_QDSS_ETR] = &xm_qdss_etr_0,
1260 [MASTER_QDSS_ETR_1] = &xm_qdss_etr_1,
1261 [MASTER_SDCC_2] = &xm_sdc2,
1262 [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
1263 };
1264
1265 static const struct qcom_icc_desc sm8550_aggre2_noc = {
1266 .nodes = aggre2_noc_nodes,
1267 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
1268 .bcms = aggre2_noc_bcms,
1269 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
1270 };
1271
1272 static struct qcom_icc_bcm * const clk_virt_bcms[] = {
1273 &bcm_qup0,
1274 &bcm_qup1,
1275 &bcm_qup2,
1276 };
1277
1278 static struct qcom_icc_node * const clk_virt_nodes[] = {
1279 [MASTER_QUP_CORE_0] = &qup0_core_master,
1280 [MASTER_QUP_CORE_1] = &qup1_core_master,
1281 [MASTER_QUP_CORE_2] = &qup2_core_master,
1282 [SLAVE_QUP_CORE_0] = &qup0_core_slave,
1283 [SLAVE_QUP_CORE_1] = &qup1_core_slave,
1284 [SLAVE_QUP_CORE_2] = &qup2_core_slave,
1285 };
1286
1287 static const struct qcom_icc_desc sm8550_clk_virt = {
1288 .nodes = clk_virt_nodes,
1289 .num_nodes = ARRAY_SIZE(clk_virt_nodes),
1290 .bcms = clk_virt_bcms,
1291 .num_bcms = ARRAY_SIZE(clk_virt_bcms),
1292 };
1293
1294 static struct qcom_icc_bcm * const config_noc_bcms[] = {
1295 &bcm_cn0,
1296 &bcm_cn1,
1297 };
1298
1299 static struct qcom_icc_node * const config_noc_nodes[] = {
1300 [MASTER_CNOC_CFG] = &qsm_cfg,
1301 [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0,
1302 [SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1,
1303 [SLAVE_APPSS] = &qhs_apss,
1304 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
1305 [SLAVE_CLK_CTL] = &qhs_clk_ctl,
1306 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
1307 [SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx,
1308 [SLAVE_RBCPR_MXA_CFG] = &qhs_cpr_mxa,
1309 [SLAVE_RBCPR_MXC_CFG] = &qhs_cpr_mxc,
1310 [SLAVE_CPR_NSPCX] = &qhs_cpr_nspcx,
1311 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
1312 [SLAVE_CX_RDPM] = &qhs_cx_rdpm,
1313 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
1314 [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
1315 [SLAVE_I2C] = &qhs_i2c,
1316 [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
1317 [SLAVE_IPA_CFG] = &qhs_ipa,
1318 [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
1319 [SLAVE_CNOC_MSS] = &qhs_mss_cfg,
1320 [SLAVE_MX_RDPM] = &qhs_mx_rdpm,
1321 [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
1322 [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg,
1323 [SLAVE_PDM] = &qhs_pdm,
1324 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
1325 [SLAVE_PRNG] = &qhs_prng,
1326 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
1327 [SLAVE_QSPI_0] = &qhs_qspi,
1328 [SLAVE_QUP_1] = &qhs_qup1,
1329 [SLAVE_QUP_2] = &qhs_qup2,
1330 [SLAVE_SDCC_2] = &qhs_sdc2,
1331 [SLAVE_SDCC_4] = &qhs_sdc4,
1332 [SLAVE_SPSS_CFG] = &qhs_spss_cfg,
1333 [SLAVE_TCSR] = &qhs_tcsr,
1334 [SLAVE_TLMM] = &qhs_tlmm,
1335 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
1336 [SLAVE_USB3_0] = &qhs_usb3_0,
1337 [SLAVE_VENUS_CFG] = &qhs_venus_cfg,
1338 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
1339 [SLAVE_LPASS_QTB_CFG] = &qss_lpass_qtb_cfg,
1340 [SLAVE_CNOC_MNOC_CFG] = &qss_mnoc_cfg,
1341 [SLAVE_NSP_QTB_CFG] = &qss_nsp_qtb_cfg,
1342 [SLAVE_PCIE_ANOC_CFG] = &qss_pcie_anoc_cfg,
1343 [SLAVE_QDSS_STM] = &xs_qdss_stm,
1344 [SLAVE_TCU] = &xs_sys_tcu_cfg,
1345 };
1346
1347 static const struct qcom_icc_desc sm8550_config_noc = {
1348 .nodes = config_noc_nodes,
1349 .num_nodes = ARRAY_SIZE(config_noc_nodes),
1350 .bcms = config_noc_bcms,
1351 .num_bcms = ARRAY_SIZE(config_noc_bcms),
1352 };
1353
1354 static struct qcom_icc_bcm * const cnoc_main_bcms[] = {
1355 &bcm_cn0,
1356 };
1357
1358 static struct qcom_icc_node * const cnoc_main_nodes[] = {
1359 [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc,
1360 [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
1361 [SLAVE_AOSS] = &qhs_aoss,
1362 [SLAVE_TME_CFG] = &qhs_tme_cfg,
1363 [SLAVE_CNOC_CFG] = &qss_cfg,
1364 [SLAVE_DDRSS_CFG] = &qss_ddrss_cfg,
1365 [SLAVE_BOOT_IMEM] = &qxs_boot_imem,
1366 [SLAVE_IMEM] = &qxs_imem,
1367 [SLAVE_PCIE_0] = &xs_pcie_0,
1368 [SLAVE_PCIE_1] = &xs_pcie_1,
1369 };
1370
1371 static const struct qcom_icc_desc sm8550_cnoc_main = {
1372 .nodes = cnoc_main_nodes,
1373 .num_nodes = ARRAY_SIZE(cnoc_main_nodes),
1374 .bcms = cnoc_main_bcms,
1375 .num_bcms = ARRAY_SIZE(cnoc_main_bcms),
1376 };
1377
1378 static struct qcom_icc_bcm * const gem_noc_bcms[] = {
1379 &bcm_sh0,
1380 &bcm_sh1,
1381 };
1382
1383 static struct qcom_icc_node * const gem_noc_nodes[] = {
1384 [MASTER_GPU_TCU] = &alm_gpu_tcu,
1385 [MASTER_SYS_TCU] = &alm_sys_tcu,
1386 [MASTER_APPSS_PROC] = &chm_apps,
1387 [MASTER_GFX3D] = &qnm_gpu,
1388 [MASTER_LPASS_GEM_NOC] = &qnm_lpass_gemnoc,
1389 [MASTER_MSS_PROC] = &qnm_mdsp,
1390 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
1391 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
1392 [MASTER_COMPUTE_NOC] = &qnm_nsp_gemnoc,
1393 [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
1394 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
1395 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
1396 [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc,
1397 [SLAVE_LLCC] = &qns_llcc,
1398 [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie,
1399 };
1400
1401 static const struct qcom_icc_desc sm8550_gem_noc = {
1402 .nodes = gem_noc_nodes,
1403 .num_nodes = ARRAY_SIZE(gem_noc_nodes),
1404 .bcms = gem_noc_bcms,
1405 .num_bcms = ARRAY_SIZE(gem_noc_bcms),
1406 };
1407
1408 static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = {
1409 };
1410
1411 static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
1412 [MASTER_LPIAON_NOC] = &qnm_lpiaon_noc,
1413 [SLAVE_LPASS_GEM_NOC] = &qns_lpass_ag_noc_gemnoc,
1414 };
1415
1416 static const struct qcom_icc_desc sm8550_lpass_ag_noc = {
1417 .nodes = lpass_ag_noc_nodes,
1418 .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
1419 .bcms = lpass_ag_noc_bcms,
1420 .num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms),
1421 };
1422
1423 static struct qcom_icc_bcm * const lpass_lpiaon_noc_bcms[] = {
1424 &bcm_lp0,
1425 };
1426
1427 static struct qcom_icc_node * const lpass_lpiaon_noc_nodes[] = {
1428 [MASTER_LPASS_LPINOC] = &qnm_lpass_lpinoc,
1429 [SLAVE_LPIAON_NOC_LPASS_AG_NOC] = &qns_lpass_aggnoc,
1430 };
1431
1432 static const struct qcom_icc_desc sm8550_lpass_lpiaon_noc = {
1433 .nodes = lpass_lpiaon_noc_nodes,
1434 .num_nodes = ARRAY_SIZE(lpass_lpiaon_noc_nodes),
1435 .bcms = lpass_lpiaon_noc_bcms,
1436 .num_bcms = ARRAY_SIZE(lpass_lpiaon_noc_bcms),
1437 };
1438
1439 static struct qcom_icc_bcm * const lpass_lpicx_noc_bcms[] = {
1440 };
1441
1442 static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] = {
1443 [MASTER_LPASS_PROC] = &qxm_lpinoc_dsp_axim,
1444 [SLAVE_LPICX_NOC_LPIAON_NOC] = &qns_lpi_aon_noc,
1445 };
1446
1447 static const struct qcom_icc_desc sm8550_lpass_lpicx_noc = {
1448 .nodes = lpass_lpicx_noc_nodes,
1449 .num_nodes = ARRAY_SIZE(lpass_lpicx_noc_nodes),
1450 .bcms = lpass_lpicx_noc_bcms,
1451 .num_bcms = ARRAY_SIZE(lpass_lpicx_noc_bcms),
1452 };
1453
1454 static struct qcom_icc_bcm * const mc_virt_bcms[] = {
1455 &bcm_acv,
1456 &bcm_mc0,
1457 };
1458
1459 static struct qcom_icc_node * const mc_virt_nodes[] = {
1460 [MASTER_LLCC] = &llcc_mc,
1461 [SLAVE_EBI1] = &ebi,
1462 };
1463
1464 static const struct qcom_icc_desc sm8550_mc_virt = {
1465 .nodes = mc_virt_nodes,
1466 .num_nodes = ARRAY_SIZE(mc_virt_nodes),
1467 .bcms = mc_virt_bcms,
1468 .num_bcms = ARRAY_SIZE(mc_virt_bcms),
1469 };
1470
1471 static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
1472 &bcm_mm0,
1473 &bcm_mm1,
1474 };
1475
1476 static struct qcom_icc_node * const mmss_noc_nodes[] = {
1477 [MASTER_CAMNOC_HF] = &qnm_camnoc_hf,
1478 [MASTER_CAMNOC_ICP] = &qnm_camnoc_icp,
1479 [MASTER_CAMNOC_SF] = &qnm_camnoc_sf,
1480 [MASTER_MDP] = &qnm_mdp,
1481 [MASTER_CDSP_HCP] = &qnm_vapss_hcp,
1482 [MASTER_VIDEO] = &qnm_video,
1483 [MASTER_VIDEO_CV_PROC] = &qnm_video_cv_cpu,
1484 [MASTER_VIDEO_PROC] = &qnm_video_cvp,
1485 [MASTER_VIDEO_V_PROC] = &qnm_video_v_cpu,
1486 [MASTER_CNOC_MNOC_CFG] = &qsm_mnoc_cfg,
1487 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
1488 [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
1489 [SLAVE_SERVICE_MNOC] = &srvc_mnoc,
1490 };
1491
1492 static const struct qcom_icc_desc sm8550_mmss_noc = {
1493 .nodes = mmss_noc_nodes,
1494 .num_nodes = ARRAY_SIZE(mmss_noc_nodes),
1495 .bcms = mmss_noc_bcms,
1496 .num_bcms = ARRAY_SIZE(mmss_noc_bcms),
1497 };
1498
1499 static struct qcom_icc_bcm * const nsp_noc_bcms[] = {
1500 &bcm_co0,
1501 };
1502
1503 static struct qcom_icc_node * const nsp_noc_nodes[] = {
1504 [MASTER_CDSP_PROC] = &qxm_nsp,
1505 [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc,
1506 };
1507
1508 static const struct qcom_icc_desc sm8550_nsp_noc = {
1509 .nodes = nsp_noc_nodes,
1510 .num_nodes = ARRAY_SIZE(nsp_noc_nodes),
1511 .bcms = nsp_noc_bcms,
1512 .num_bcms = ARRAY_SIZE(nsp_noc_bcms),
1513 };
1514
1515 static struct qcom_icc_bcm * const pcie_anoc_bcms[] = {
1516 &bcm_sn7,
1517 };
1518
1519 static struct qcom_icc_node * const pcie_anoc_nodes[] = {
1520 [MASTER_PCIE_ANOC_CFG] = &qsm_pcie_anoc_cfg,
1521 [MASTER_PCIE_0] = &xm_pcie3_0,
1522 [MASTER_PCIE_1] = &xm_pcie3_1,
1523 [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
1524 [SLAVE_SERVICE_PCIE_ANOC] = &srvc_pcie_aggre_noc,
1525 };
1526
1527 static const struct qcom_icc_desc sm8550_pcie_anoc = {
1528 .nodes = pcie_anoc_nodes,
1529 .num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
1530 .bcms = pcie_anoc_bcms,
1531 .num_bcms = ARRAY_SIZE(pcie_anoc_bcms),
1532 };
1533
1534 static struct qcom_icc_bcm * const system_noc_bcms[] = {
1535 &bcm_sn0,
1536 &bcm_sn1,
1537 &bcm_sn2,
1538 &bcm_sn3,
1539 };
1540
1541 static struct qcom_icc_node * const system_noc_nodes[] = {
1542 [MASTER_GIC_AHB] = &qhm_gic,
1543 [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
1544 [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
1545 [MASTER_GIC] = &xm_gic,
1546 [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
1547 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
1548 };
1549
1550 static const struct qcom_icc_desc sm8550_system_noc = {
1551 .nodes = system_noc_nodes,
1552 .num_nodes = ARRAY_SIZE(system_noc_nodes),
1553 .bcms = system_noc_bcms,
1554 .num_bcms = ARRAY_SIZE(system_noc_bcms),
1555 };
1556
1557 static const struct of_device_id qnoc_of_match[] = {
1558 { .compatible = "qcom,sm8550-aggre1-noc",
1559 .data = &sm8550_aggre1_noc},
1560 { .compatible = "qcom,sm8550-aggre2-noc",
1561 .data = &sm8550_aggre2_noc},
1562 { .compatible = "qcom,sm8550-clk-virt",
1563 .data = &sm8550_clk_virt},
1564 { .compatible = "qcom,sm8550-config-noc",
1565 .data = &sm8550_config_noc},
1566 { .compatible = "qcom,sm8550-cnoc-main",
1567 .data = &sm8550_cnoc_main},
1568 { .compatible = "qcom,sm8550-gem-noc",
1569 .data = &sm8550_gem_noc},
1570 { .compatible = "qcom,sm8550-lpass-ag-noc",
1571 .data = &sm8550_lpass_ag_noc},
1572 { .compatible = "qcom,sm8550-lpass-lpiaon-noc",
1573 .data = &sm8550_lpass_lpiaon_noc},
1574 { .compatible = "qcom,sm8550-lpass-lpicx-noc",
1575 .data = &sm8550_lpass_lpicx_noc},
1576 { .compatible = "qcom,sm8550-mc-virt",
1577 .data = &sm8550_mc_virt},
1578 { .compatible = "qcom,sm8550-mmss-noc",
1579 .data = &sm8550_mmss_noc},
1580 { .compatible = "qcom,sm8550-nsp-noc",
1581 .data = &sm8550_nsp_noc},
1582 { .compatible = "qcom,sm8550-pcie-anoc",
1583 .data = &sm8550_pcie_anoc},
1584 { .compatible = "qcom,sm8550-system-noc",
1585 .data = &sm8550_system_noc},
1586 { }
1587 };
1588 MODULE_DEVICE_TABLE(of, qnoc_of_match);
1589
1590 static struct platform_driver qnoc_driver = {
1591 .probe = qcom_icc_rpmh_probe,
1592 .remove = qcom_icc_rpmh_remove,
1593 .driver = {
1594 .name = "qnoc-sm8550",
1595 .of_match_table = qnoc_of_match,
1596 .sync_state = icc_sync_state,
1597 },
1598 };
1599
qnoc_driver_init(void)1600 static int __init qnoc_driver_init(void)
1601 {
1602 return platform_driver_register(&qnoc_driver);
1603 }
1604 core_initcall(qnoc_driver_init);
1605
qnoc_driver_exit(void)1606 static void __exit qnoc_driver_exit(void)
1607 {
1608 platform_driver_unregister(&qnoc_driver);
1609 }
1610 module_exit(qnoc_driver_exit);
1611
1612 MODULE_DESCRIPTION("sm8550 NoC driver");
1613 MODULE_LICENSE("GPL");
1614