1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021, Linaro Limited 5 */ 6 7 #include <linux/device.h> 8 #include <linux/interconnect.h> 9 #include <linux/interconnect-provider.h> 10 #include <linux/module.h> 11 #include <linux/platform_device.h> 12 #include <linux/property.h> 13 #include <dt-bindings/interconnect/qcom,sm8450.h> 14 15 #include "bcm-voter.h" 16 #include "icc-common.h" 17 #include "icc-rpmh.h" 18 19 static struct qcom_icc_node qhm_qspi; 20 static struct qcom_icc_node qhm_qup1; 21 static struct qcom_icc_node qnm_a1noc_cfg; 22 static struct qcom_icc_node xm_sdc4; 23 static struct qcom_icc_node xm_ufs_mem; 24 static struct qcom_icc_node xm_usb3_0; 25 static struct qcom_icc_node qhm_qdss_bam; 26 static struct qcom_icc_node qhm_qup0; 27 static struct qcom_icc_node qhm_qup2; 28 static struct qcom_icc_node qnm_a2noc_cfg; 29 static struct qcom_icc_node qxm_crypto; 30 static struct qcom_icc_node qxm_ipa; 31 static struct qcom_icc_node qxm_sensorss_q6; 32 static struct qcom_icc_node qxm_sp; 33 static struct qcom_icc_node xm_qdss_etr_0; 34 static struct qcom_icc_node xm_qdss_etr_1; 35 static struct qcom_icc_node xm_sdc2; 36 static struct qcom_icc_node qup0_core_master; 37 static struct qcom_icc_node qup1_core_master; 38 static struct qcom_icc_node qup2_core_master; 39 static struct qcom_icc_node qnm_gemnoc_cnoc; 40 static struct qcom_icc_node qnm_gemnoc_pcie; 41 static struct qcom_icc_node alm_gpu_tcu; 42 static struct qcom_icc_node alm_sys_tcu; 43 static struct qcom_icc_node chm_apps; 44 static struct qcom_icc_node qnm_gpu; 45 static struct qcom_icc_node qnm_mdsp; 46 static struct qcom_icc_node qnm_mnoc_hf; 47 static struct qcom_icc_node qnm_mnoc_sf; 48 static struct qcom_icc_node qnm_nsp_gemnoc; 49 static struct qcom_icc_node qnm_pcie; 50 static struct qcom_icc_node qnm_snoc_gc; 51 static struct qcom_icc_node qnm_snoc_sf; 52 static struct qcom_icc_node qhm_config_noc; 53 static struct qcom_icc_node qxm_lpass_dsp; 54 static struct qcom_icc_node llcc_mc; 55 static struct qcom_icc_node qnm_camnoc_hf; 56 static struct qcom_icc_node qnm_camnoc_icp; 57 static struct qcom_icc_node qnm_camnoc_sf; 58 static struct qcom_icc_node qnm_mdp; 59 static struct qcom_icc_node qnm_mnoc_cfg; 60 static struct qcom_icc_node qnm_rot; 61 static struct qcom_icc_node qnm_vapss_hcp; 62 static struct qcom_icc_node qnm_video; 63 static struct qcom_icc_node qnm_video_cv_cpu; 64 static struct qcom_icc_node qnm_video_cvp; 65 static struct qcom_icc_node qnm_video_v_cpu; 66 static struct qcom_icc_node qhm_nsp_noc_config; 67 static struct qcom_icc_node qxm_nsp; 68 static struct qcom_icc_node qnm_pcie_anoc_cfg; 69 static struct qcom_icc_node xm_pcie3_0; 70 static struct qcom_icc_node xm_pcie3_1; 71 static struct qcom_icc_node qhm_gic; 72 static struct qcom_icc_node qnm_aggre1_noc; 73 static struct qcom_icc_node qnm_aggre2_noc; 74 static struct qcom_icc_node qnm_lpass_noc; 75 static struct qcom_icc_node qnm_snoc_cfg; 76 static struct qcom_icc_node qxm_pimem; 77 static struct qcom_icc_node xm_gic; 78 static struct qcom_icc_node qnm_mnoc_hf_disp; 79 static struct qcom_icc_node qnm_mnoc_sf_disp; 80 static struct qcom_icc_node qnm_pcie_disp; 81 static struct qcom_icc_node llcc_mc_disp; 82 static struct qcom_icc_node qnm_mdp_disp; 83 static struct qcom_icc_node qnm_rot_disp; 84 static struct qcom_icc_node qns_a1noc_snoc; 85 static struct qcom_icc_node srvc_aggre1_noc; 86 static struct qcom_icc_node qns_a2noc_snoc; 87 static struct qcom_icc_node srvc_aggre2_noc; 88 static struct qcom_icc_node qup0_core_slave; 89 static struct qcom_icc_node qup1_core_slave; 90 static struct qcom_icc_node qup2_core_slave; 91 static struct qcom_icc_node qhs_ahb2phy0; 92 static struct qcom_icc_node qhs_ahb2phy1; 93 static struct qcom_icc_node qhs_aoss; 94 static struct qcom_icc_node qhs_camera_cfg; 95 static struct qcom_icc_node qhs_clk_ctl; 96 static struct qcom_icc_node qhs_compute_cfg; 97 static struct qcom_icc_node qhs_cpr_cx; 98 static struct qcom_icc_node qhs_cpr_mmcx; 99 static struct qcom_icc_node qhs_cpr_mxa; 100 static struct qcom_icc_node qhs_cpr_mxc; 101 static struct qcom_icc_node qhs_crypto0_cfg; 102 static struct qcom_icc_node qhs_cx_rdpm; 103 static struct qcom_icc_node qhs_display_cfg; 104 static struct qcom_icc_node qhs_gpuss_cfg; 105 static struct qcom_icc_node qhs_imem_cfg; 106 static struct qcom_icc_node qhs_ipa; 107 static struct qcom_icc_node qhs_ipc_router; 108 static struct qcom_icc_node qhs_lpass_cfg; 109 static struct qcom_icc_node qhs_mss_cfg; 110 static struct qcom_icc_node qhs_mx_rdpm; 111 static struct qcom_icc_node qhs_pcie0_cfg; 112 static struct qcom_icc_node qhs_pcie1_cfg; 113 static struct qcom_icc_node qhs_pdm; 114 static struct qcom_icc_node qhs_pimem_cfg; 115 static struct qcom_icc_node qhs_prng; 116 static struct qcom_icc_node qhs_qdss_cfg; 117 static struct qcom_icc_node qhs_qspi; 118 static struct qcom_icc_node qhs_qup0; 119 static struct qcom_icc_node qhs_qup1; 120 static struct qcom_icc_node qhs_qup2; 121 static struct qcom_icc_node qhs_sdc2; 122 static struct qcom_icc_node qhs_sdc4; 123 static struct qcom_icc_node qhs_spss_cfg; 124 static struct qcom_icc_node qhs_tcsr; 125 static struct qcom_icc_node qhs_tlmm; 126 static struct qcom_icc_node qhs_tme_cfg; 127 static struct qcom_icc_node qhs_ufs_mem_cfg; 128 static struct qcom_icc_node qhs_usb3_0; 129 static struct qcom_icc_node qhs_venus_cfg; 130 static struct qcom_icc_node qhs_vsense_ctrl_cfg; 131 static struct qcom_icc_node qns_a1_noc_cfg; 132 static struct qcom_icc_node qns_a2_noc_cfg; 133 static struct qcom_icc_node qns_ddrss_cfg; 134 static struct qcom_icc_node qns_mnoc_cfg; 135 static struct qcom_icc_node qns_pcie_anoc_cfg; 136 static struct qcom_icc_node qns_snoc_cfg; 137 static struct qcom_icc_node qxs_imem; 138 static struct qcom_icc_node qxs_pimem; 139 static struct qcom_icc_node srvc_cnoc; 140 static struct qcom_icc_node xs_pcie_0; 141 static struct qcom_icc_node xs_pcie_1; 142 static struct qcom_icc_node xs_qdss_stm; 143 static struct qcom_icc_node xs_sys_tcu_cfg; 144 static struct qcom_icc_node qns_gem_noc_cnoc; 145 static struct qcom_icc_node qns_llcc; 146 static struct qcom_icc_node qns_pcie; 147 static struct qcom_icc_node qhs_lpass_core; 148 static struct qcom_icc_node qhs_lpass_lpi; 149 static struct qcom_icc_node qhs_lpass_mpu; 150 static struct qcom_icc_node qhs_lpass_top; 151 static struct qcom_icc_node qns_sysnoc; 152 static struct qcom_icc_node srvc_niu_aml_noc; 153 static struct qcom_icc_node srvc_niu_lpass_agnoc; 154 static struct qcom_icc_node ebi; 155 static struct qcom_icc_node qns_mem_noc_hf; 156 static struct qcom_icc_node qns_mem_noc_sf; 157 static struct qcom_icc_node srvc_mnoc; 158 static struct qcom_icc_node qns_nsp_gemnoc; 159 static struct qcom_icc_node service_nsp_noc; 160 static struct qcom_icc_node qns_pcie_mem_noc; 161 static struct qcom_icc_node srvc_pcie_aggre_noc; 162 static struct qcom_icc_node qns_gemnoc_gc; 163 static struct qcom_icc_node qns_gemnoc_sf; 164 static struct qcom_icc_node srvc_snoc; 165 static struct qcom_icc_node qns_llcc_disp; 166 static struct qcom_icc_node ebi_disp; 167 static struct qcom_icc_node qns_mem_noc_hf_disp; 168 static struct qcom_icc_node qns_mem_noc_sf_disp; 169 170 static struct qcom_icc_node qhm_qspi = { 171 .name = "qhm_qspi", 172 .channels = 1, 173 .buswidth = 4, 174 .num_links = 1, 175 .link_nodes = { &qns_a1noc_snoc }, 176 }; 177 178 static struct qcom_icc_node qhm_qup1 = { 179 .name = "qhm_qup1", 180 .channels = 1, 181 .buswidth = 4, 182 .num_links = 1, 183 .link_nodes = { &qns_a1noc_snoc }, 184 }; 185 186 static struct qcom_icc_node qnm_a1noc_cfg = { 187 .name = "qnm_a1noc_cfg", 188 .channels = 1, 189 .buswidth = 4, 190 .num_links = 1, 191 .link_nodes = { &srvc_aggre1_noc }, 192 }; 193 194 static struct qcom_icc_node xm_sdc4 = { 195 .name = "xm_sdc4", 196 .channels = 1, 197 .buswidth = 8, 198 .num_links = 1, 199 .link_nodes = { &qns_a1noc_snoc }, 200 }; 201 202 static struct qcom_icc_node xm_ufs_mem = { 203 .name = "xm_ufs_mem", 204 .channels = 1, 205 .buswidth = 8, 206 .num_links = 1, 207 .link_nodes = { &qns_a1noc_snoc }, 208 }; 209 210 static struct qcom_icc_node xm_usb3_0 = { 211 .name = "xm_usb3_0", 212 .channels = 1, 213 .buswidth = 8, 214 .num_links = 1, 215 .link_nodes = { &qns_a1noc_snoc }, 216 }; 217 218 static struct qcom_icc_node qhm_qdss_bam = { 219 .name = "qhm_qdss_bam", 220 .channels = 1, 221 .buswidth = 4, 222 .num_links = 1, 223 .link_nodes = { &qns_a2noc_snoc }, 224 }; 225 226 static struct qcom_icc_node qhm_qup0 = { 227 .name = "qhm_qup0", 228 .channels = 1, 229 .buswidth = 4, 230 .num_links = 1, 231 .link_nodes = { &qns_a2noc_snoc }, 232 }; 233 234 static struct qcom_icc_node qhm_qup2 = { 235 .name = "qhm_qup2", 236 .channels = 1, 237 .buswidth = 4, 238 .num_links = 1, 239 .link_nodes = { &qns_a2noc_snoc }, 240 }; 241 242 static struct qcom_icc_node qnm_a2noc_cfg = { 243 .name = "qnm_a2noc_cfg", 244 .channels = 1, 245 .buswidth = 4, 246 .num_links = 1, 247 .link_nodes = { &srvc_aggre2_noc }, 248 }; 249 250 static struct qcom_icc_node qxm_crypto = { 251 .name = "qxm_crypto", 252 .channels = 1, 253 .buswidth = 8, 254 .num_links = 1, 255 .link_nodes = { &qns_a2noc_snoc }, 256 }; 257 258 static struct qcom_icc_node qxm_ipa = { 259 .name = "qxm_ipa", 260 .channels = 1, 261 .buswidth = 8, 262 .num_links = 1, 263 .link_nodes = { &qns_a2noc_snoc }, 264 }; 265 266 static struct qcom_icc_node qxm_sensorss_q6 = { 267 .name = "qxm_sensorss_q6", 268 .channels = 1, 269 .buswidth = 8, 270 .num_links = 1, 271 .link_nodes = { &qns_a2noc_snoc }, 272 }; 273 274 static struct qcom_icc_node qxm_sp = { 275 .name = "qxm_sp", 276 .channels = 1, 277 .buswidth = 8, 278 .num_links = 1, 279 .link_nodes = { &qns_a2noc_snoc }, 280 }; 281 282 static struct qcom_icc_node xm_qdss_etr_0 = { 283 .name = "xm_qdss_etr_0", 284 .channels = 1, 285 .buswidth = 8, 286 .num_links = 1, 287 .link_nodes = { &qns_a2noc_snoc }, 288 }; 289 290 static struct qcom_icc_node xm_qdss_etr_1 = { 291 .name = "xm_qdss_etr_1", 292 .channels = 1, 293 .buswidth = 8, 294 .num_links = 1, 295 .link_nodes = { &qns_a2noc_snoc }, 296 }; 297 298 static struct qcom_icc_node xm_sdc2 = { 299 .name = "xm_sdc2", 300 .channels = 1, 301 .buswidth = 8, 302 .num_links = 1, 303 .link_nodes = { &qns_a2noc_snoc }, 304 }; 305 306 static struct qcom_icc_node qup0_core_master = { 307 .name = "qup0_core_master", 308 .channels = 1, 309 .buswidth = 4, 310 .num_links = 1, 311 .link_nodes = { &qup0_core_slave }, 312 }; 313 314 static struct qcom_icc_node qup1_core_master = { 315 .name = "qup1_core_master", 316 .channels = 1, 317 .buswidth = 4, 318 .num_links = 1, 319 .link_nodes = { &qup1_core_slave }, 320 }; 321 322 static struct qcom_icc_node qup2_core_master = { 323 .name = "qup2_core_master", 324 .channels = 1, 325 .buswidth = 4, 326 .num_links = 1, 327 .link_nodes = { &qup2_core_slave }, 328 }; 329 330 static struct qcom_icc_node qnm_gemnoc_cnoc = { 331 .name = "qnm_gemnoc_cnoc", 332 .channels = 1, 333 .buswidth = 16, 334 .num_links = 51, 335 .link_nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1, 336 &qhs_aoss, &qhs_camera_cfg, 337 &qhs_clk_ctl, &qhs_compute_cfg, 338 &qhs_cpr_cx, &qhs_cpr_mmcx, 339 &qhs_cpr_mxa, &qhs_cpr_mxc, 340 &qhs_crypto0_cfg, &qhs_cx_rdpm, 341 &qhs_display_cfg, &qhs_gpuss_cfg, 342 &qhs_imem_cfg, &qhs_ipa, 343 &qhs_ipc_router, &qhs_lpass_cfg, 344 &qhs_mss_cfg, &qhs_mx_rdpm, 345 &qhs_pcie0_cfg, &qhs_pcie1_cfg, 346 &qhs_pdm, &qhs_pimem_cfg, 347 &qhs_prng, &qhs_qdss_cfg, 348 &qhs_qspi, &qhs_qup0, 349 &qhs_qup1, &qhs_qup2, 350 &qhs_sdc2, &qhs_sdc4, 351 &qhs_spss_cfg, &qhs_tcsr, 352 &qhs_tlmm, &qhs_tme_cfg, 353 &qhs_ufs_mem_cfg, &qhs_usb3_0, 354 &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, 355 &qns_a1_noc_cfg, &qns_a2_noc_cfg, 356 &qns_ddrss_cfg, &qns_mnoc_cfg, 357 &qns_pcie_anoc_cfg, &qns_snoc_cfg, 358 &qxs_imem, &qxs_pimem, 359 &srvc_cnoc, &xs_qdss_stm, 360 &xs_sys_tcu_cfg }, 361 }; 362 363 static struct qcom_icc_node qnm_gemnoc_pcie = { 364 .name = "qnm_gemnoc_pcie", 365 .channels = 1, 366 .buswidth = 8, 367 .num_links = 2, 368 .link_nodes = { &xs_pcie_0, &xs_pcie_1 }, 369 }; 370 371 static struct qcom_icc_node alm_gpu_tcu = { 372 .name = "alm_gpu_tcu", 373 .channels = 1, 374 .buswidth = 8, 375 .num_links = 2, 376 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 377 }; 378 379 static struct qcom_icc_node alm_sys_tcu = { 380 .name = "alm_sys_tcu", 381 .channels = 1, 382 .buswidth = 8, 383 .num_links = 2, 384 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 385 }; 386 387 static struct qcom_icc_node chm_apps = { 388 .name = "chm_apps", 389 .channels = 3, 390 .buswidth = 32, 391 .num_links = 3, 392 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, 393 &qns_pcie }, 394 }; 395 396 static struct qcom_icc_node qnm_gpu = { 397 .name = "qnm_gpu", 398 .channels = 2, 399 .buswidth = 32, 400 .num_links = 2, 401 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 402 }; 403 404 static struct qcom_icc_node qnm_mdsp = { 405 .name = "qnm_mdsp", 406 .channels = 1, 407 .buswidth = 16, 408 .num_links = 3, 409 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, 410 &qns_pcie }, 411 }; 412 413 static struct qcom_icc_node qnm_mnoc_hf = { 414 .name = "qnm_mnoc_hf", 415 .channels = 2, 416 .buswidth = 32, 417 .num_links = 1, 418 .link_nodes = { &qns_llcc }, 419 }; 420 421 static struct qcom_icc_node qnm_mnoc_sf = { 422 .name = "qnm_mnoc_sf", 423 .channels = 2, 424 .buswidth = 32, 425 .num_links = 2, 426 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 427 }; 428 429 static struct qcom_icc_node qnm_nsp_gemnoc = { 430 .name = "qnm_nsp_gemnoc", 431 .channels = 2, 432 .buswidth = 32, 433 .num_links = 2, 434 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 435 }; 436 437 static struct qcom_icc_node qnm_pcie = { 438 .name = "qnm_pcie", 439 .channels = 1, 440 .buswidth = 16, 441 .num_links = 2, 442 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 443 }; 444 445 static struct qcom_icc_node qnm_snoc_gc = { 446 .name = "qnm_snoc_gc", 447 .channels = 1, 448 .buswidth = 8, 449 .num_links = 1, 450 .link_nodes = { &qns_llcc }, 451 }; 452 453 static struct qcom_icc_node qnm_snoc_sf = { 454 .name = "qnm_snoc_sf", 455 .channels = 1, 456 .buswidth = 16, 457 .num_links = 3, 458 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, 459 &qns_pcie }, 460 }; 461 462 static struct qcom_icc_node qhm_config_noc = { 463 .name = "qhm_config_noc", 464 .channels = 1, 465 .buswidth = 4, 466 .num_links = 6, 467 .link_nodes = { &qhs_lpass_core, &qhs_lpass_lpi, 468 &qhs_lpass_mpu, &qhs_lpass_top, 469 &srvc_niu_aml_noc, &srvc_niu_lpass_agnoc }, 470 }; 471 472 static struct qcom_icc_node qxm_lpass_dsp = { 473 .name = "qxm_lpass_dsp", 474 .channels = 1, 475 .buswidth = 8, 476 .num_links = 4, 477 .link_nodes = { &qhs_lpass_top, &qns_sysnoc, 478 &srvc_niu_aml_noc, &srvc_niu_lpass_agnoc }, 479 }; 480 481 static struct qcom_icc_node llcc_mc = { 482 .name = "llcc_mc", 483 .channels = 4, 484 .buswidth = 4, 485 .num_links = 1, 486 .link_nodes = { &ebi }, 487 }; 488 489 static struct qcom_icc_node qnm_camnoc_hf = { 490 .name = "qnm_camnoc_hf", 491 .channels = 2, 492 .buswidth = 32, 493 .num_links = 1, 494 .link_nodes = { &qns_mem_noc_hf }, 495 }; 496 497 static struct qcom_icc_node qnm_camnoc_icp = { 498 .name = "qnm_camnoc_icp", 499 .channels = 1, 500 .buswidth = 8, 501 .num_links = 1, 502 .link_nodes = { &qns_mem_noc_sf }, 503 }; 504 505 static struct qcom_icc_node qnm_camnoc_sf = { 506 .name = "qnm_camnoc_sf", 507 .channels = 2, 508 .buswidth = 32, 509 .num_links = 1, 510 .link_nodes = { &qns_mem_noc_sf }, 511 }; 512 513 static struct qcom_icc_node qnm_mdp = { 514 .name = "qnm_mdp", 515 .channels = 2, 516 .buswidth = 32, 517 .num_links = 1, 518 .link_nodes = { &qns_mem_noc_hf }, 519 }; 520 521 static struct qcom_icc_node qnm_mnoc_cfg = { 522 .name = "qnm_mnoc_cfg", 523 .channels = 1, 524 .buswidth = 4, 525 .num_links = 1, 526 .link_nodes = { &srvc_mnoc }, 527 }; 528 529 static struct qcom_icc_node qnm_rot = { 530 .name = "qnm_rot", 531 .channels = 1, 532 .buswidth = 32, 533 .num_links = 1, 534 .link_nodes = { &qns_mem_noc_sf }, 535 }; 536 537 static struct qcom_icc_node qnm_vapss_hcp = { 538 .name = "qnm_vapss_hcp", 539 .channels = 1, 540 .buswidth = 32, 541 .num_links = 1, 542 .link_nodes = { &qns_mem_noc_sf }, 543 }; 544 545 static struct qcom_icc_node qnm_video = { 546 .name = "qnm_video", 547 .channels = 2, 548 .buswidth = 32, 549 .num_links = 1, 550 .link_nodes = { &qns_mem_noc_sf }, 551 }; 552 553 static struct qcom_icc_node qnm_video_cv_cpu = { 554 .name = "qnm_video_cv_cpu", 555 .channels = 1, 556 .buswidth = 8, 557 .num_links = 1, 558 .link_nodes = { &qns_mem_noc_sf }, 559 }; 560 561 static struct qcom_icc_node qnm_video_cvp = { 562 .name = "qnm_video_cvp", 563 .channels = 1, 564 .buswidth = 32, 565 .num_links = 1, 566 .link_nodes = { &qns_mem_noc_sf }, 567 }; 568 569 static struct qcom_icc_node qnm_video_v_cpu = { 570 .name = "qnm_video_v_cpu", 571 .channels = 1, 572 .buswidth = 8, 573 .num_links = 1, 574 .link_nodes = { &qns_mem_noc_sf }, 575 }; 576 577 static struct qcom_icc_node qhm_nsp_noc_config = { 578 .name = "qhm_nsp_noc_config", 579 .channels = 1, 580 .buswidth = 4, 581 .num_links = 1, 582 .link_nodes = { &service_nsp_noc }, 583 }; 584 585 static struct qcom_icc_node qxm_nsp = { 586 .name = "qxm_nsp", 587 .channels = 2, 588 .buswidth = 32, 589 .num_links = 1, 590 .link_nodes = { &qns_nsp_gemnoc }, 591 }; 592 593 static struct qcom_icc_node qnm_pcie_anoc_cfg = { 594 .name = "qnm_pcie_anoc_cfg", 595 .channels = 1, 596 .buswidth = 4, 597 .num_links = 1, 598 .link_nodes = { &srvc_pcie_aggre_noc }, 599 }; 600 601 static struct qcom_icc_node xm_pcie3_0 = { 602 .name = "xm_pcie3_0", 603 .channels = 1, 604 .buswidth = 8, 605 .num_links = 1, 606 .link_nodes = { &qns_pcie_mem_noc }, 607 }; 608 609 static struct qcom_icc_node xm_pcie3_1 = { 610 .name = "xm_pcie3_1", 611 .channels = 1, 612 .buswidth = 8, 613 .num_links = 1, 614 .link_nodes = { &qns_pcie_mem_noc }, 615 }; 616 617 static struct qcom_icc_node qhm_gic = { 618 .name = "qhm_gic", 619 .channels = 1, 620 .buswidth = 4, 621 .num_links = 1, 622 .link_nodes = { &qns_gemnoc_sf }, 623 }; 624 625 static struct qcom_icc_node qnm_aggre1_noc = { 626 .name = "qnm_aggre1_noc", 627 .channels = 1, 628 .buswidth = 16, 629 .num_links = 1, 630 .link_nodes = { &qns_gemnoc_sf }, 631 }; 632 633 static struct qcom_icc_node qnm_aggre2_noc = { 634 .name = "qnm_aggre2_noc", 635 .channels = 1, 636 .buswidth = 16, 637 .num_links = 1, 638 .link_nodes = { &qns_gemnoc_sf }, 639 }; 640 641 static struct qcom_icc_node qnm_lpass_noc = { 642 .name = "qnm_lpass_noc", 643 .channels = 1, 644 .buswidth = 16, 645 .num_links = 1, 646 .link_nodes = { &qns_gemnoc_sf }, 647 }; 648 649 static struct qcom_icc_node qnm_snoc_cfg = { 650 .name = "qnm_snoc_cfg", 651 .channels = 1, 652 .buswidth = 4, 653 .num_links = 1, 654 .link_nodes = { &srvc_snoc }, 655 }; 656 657 static struct qcom_icc_node qxm_pimem = { 658 .name = "qxm_pimem", 659 .channels = 1, 660 .buswidth = 8, 661 .num_links = 1, 662 .link_nodes = { &qns_gemnoc_gc }, 663 }; 664 665 static struct qcom_icc_node xm_gic = { 666 .name = "xm_gic", 667 .channels = 1, 668 .buswidth = 8, 669 .num_links = 1, 670 .link_nodes = { &qns_gemnoc_gc }, 671 }; 672 673 static struct qcom_icc_node qnm_mnoc_hf_disp = { 674 .name = "qnm_mnoc_hf_disp", 675 .channels = 2, 676 .buswidth = 32, 677 .num_links = 1, 678 .link_nodes = { &qns_llcc_disp }, 679 }; 680 681 static struct qcom_icc_node qnm_mnoc_sf_disp = { 682 .name = "qnm_mnoc_sf_disp", 683 .channels = 2, 684 .buswidth = 32, 685 .num_links = 1, 686 .link_nodes = { &qns_llcc_disp }, 687 }; 688 689 static struct qcom_icc_node qnm_pcie_disp = { 690 .name = "qnm_pcie_disp", 691 .channels = 1, 692 .buswidth = 16, 693 .num_links = 1, 694 .link_nodes = { &qns_llcc_disp }, 695 }; 696 697 static struct qcom_icc_node llcc_mc_disp = { 698 .name = "llcc_mc_disp", 699 .channels = 4, 700 .buswidth = 4, 701 .num_links = 1, 702 .link_nodes = { &ebi_disp }, 703 }; 704 705 static struct qcom_icc_node qnm_mdp_disp = { 706 .name = "qnm_mdp_disp", 707 .channels = 2, 708 .buswidth = 32, 709 .num_links = 1, 710 .link_nodes = { &qns_mem_noc_hf_disp }, 711 }; 712 713 static struct qcom_icc_node qnm_rot_disp = { 714 .name = "qnm_rot_disp", 715 .channels = 1, 716 .buswidth = 32, 717 .num_links = 1, 718 .link_nodes = { &qns_mem_noc_sf_disp }, 719 }; 720 721 static struct qcom_icc_node qns_a1noc_snoc = { 722 .name = "qns_a1noc_snoc", 723 .channels = 1, 724 .buswidth = 16, 725 .num_links = 1, 726 .link_nodes = { &qnm_aggre1_noc }, 727 }; 728 729 static struct qcom_icc_node srvc_aggre1_noc = { 730 .name = "srvc_aggre1_noc", 731 .channels = 1, 732 .buswidth = 4, 733 }; 734 735 static struct qcom_icc_node qns_a2noc_snoc = { 736 .name = "qns_a2noc_snoc", 737 .channels = 1, 738 .buswidth = 16, 739 .num_links = 1, 740 .link_nodes = { &qnm_aggre2_noc }, 741 }; 742 743 static struct qcom_icc_node srvc_aggre2_noc = { 744 .name = "srvc_aggre2_noc", 745 .channels = 1, 746 .buswidth = 4, 747 }; 748 749 static struct qcom_icc_node qup0_core_slave = { 750 .name = "qup0_core_slave", 751 .channels = 1, 752 .buswidth = 4, 753 }; 754 755 static struct qcom_icc_node qup1_core_slave = { 756 .name = "qup1_core_slave", 757 .channels = 1, 758 .buswidth = 4, 759 }; 760 761 static struct qcom_icc_node qup2_core_slave = { 762 .name = "qup2_core_slave", 763 .channels = 1, 764 .buswidth = 4, 765 }; 766 767 static struct qcom_icc_node qhs_ahb2phy0 = { 768 .name = "qhs_ahb2phy0", 769 .channels = 1, 770 .buswidth = 4, 771 }; 772 773 static struct qcom_icc_node qhs_ahb2phy1 = { 774 .name = "qhs_ahb2phy1", 775 .channels = 1, 776 .buswidth = 4, 777 }; 778 779 static struct qcom_icc_node qhs_aoss = { 780 .name = "qhs_aoss", 781 .channels = 1, 782 .buswidth = 4, 783 }; 784 785 static struct qcom_icc_node qhs_camera_cfg = { 786 .name = "qhs_camera_cfg", 787 .channels = 1, 788 .buswidth = 4, 789 }; 790 791 static struct qcom_icc_node qhs_clk_ctl = { 792 .name = "qhs_clk_ctl", 793 .channels = 1, 794 .buswidth = 4, 795 }; 796 797 static struct qcom_icc_node qhs_compute_cfg = { 798 .name = "qhs_compute_cfg", 799 .channels = 1, 800 .buswidth = 4, 801 .num_links = 1, 802 .link_nodes = { &qhm_nsp_noc_config }, 803 }; 804 805 static struct qcom_icc_node qhs_cpr_cx = { 806 .name = "qhs_cpr_cx", 807 .channels = 1, 808 .buswidth = 4, 809 }; 810 811 static struct qcom_icc_node qhs_cpr_mmcx = { 812 .name = "qhs_cpr_mmcx", 813 .channels = 1, 814 .buswidth = 4, 815 }; 816 817 static struct qcom_icc_node qhs_cpr_mxa = { 818 .name = "qhs_cpr_mxa", 819 .channels = 1, 820 .buswidth = 4, 821 }; 822 823 static struct qcom_icc_node qhs_cpr_mxc = { 824 .name = "qhs_cpr_mxc", 825 .channels = 1, 826 .buswidth = 4, 827 }; 828 829 static struct qcom_icc_node qhs_crypto0_cfg = { 830 .name = "qhs_crypto0_cfg", 831 .channels = 1, 832 .buswidth = 4, 833 }; 834 835 static struct qcom_icc_node qhs_cx_rdpm = { 836 .name = "qhs_cx_rdpm", 837 .channels = 1, 838 .buswidth = 4, 839 }; 840 841 static struct qcom_icc_node qhs_display_cfg = { 842 .name = "qhs_display_cfg", 843 .channels = 1, 844 .buswidth = 4, 845 }; 846 847 static struct qcom_icc_node qhs_gpuss_cfg = { 848 .name = "qhs_gpuss_cfg", 849 .channels = 1, 850 .buswidth = 8, 851 }; 852 853 static struct qcom_icc_node qhs_imem_cfg = { 854 .name = "qhs_imem_cfg", 855 .channels = 1, 856 .buswidth = 4, 857 }; 858 859 static struct qcom_icc_node qhs_ipa = { 860 .name = "qhs_ipa", 861 .channels = 1, 862 .buswidth = 4, 863 }; 864 865 static struct qcom_icc_node qhs_ipc_router = { 866 .name = "qhs_ipc_router", 867 .channels = 1, 868 .buswidth = 4, 869 }; 870 871 static struct qcom_icc_node qhs_lpass_cfg = { 872 .name = "qhs_lpass_cfg", 873 .channels = 1, 874 .buswidth = 4, 875 .num_links = 1, 876 .link_nodes = { &qhm_config_noc }, 877 }; 878 879 static struct qcom_icc_node qhs_mss_cfg = { 880 .name = "qhs_mss_cfg", 881 .channels = 1, 882 .buswidth = 4, 883 }; 884 885 static struct qcom_icc_node qhs_mx_rdpm = { 886 .name = "qhs_mx_rdpm", 887 .channels = 1, 888 .buswidth = 4, 889 }; 890 891 static struct qcom_icc_node qhs_pcie0_cfg = { 892 .name = "qhs_pcie0_cfg", 893 .channels = 1, 894 .buswidth = 4, 895 }; 896 897 static struct qcom_icc_node qhs_pcie1_cfg = { 898 .name = "qhs_pcie1_cfg", 899 .channels = 1, 900 .buswidth = 4, 901 }; 902 903 static struct qcom_icc_node qhs_pdm = { 904 .name = "qhs_pdm", 905 .channels = 1, 906 .buswidth = 4, 907 }; 908 909 static struct qcom_icc_node qhs_pimem_cfg = { 910 .name = "qhs_pimem_cfg", 911 .channels = 1, 912 .buswidth = 4, 913 }; 914 915 static struct qcom_icc_node qhs_prng = { 916 .name = "qhs_prng", 917 .channels = 1, 918 .buswidth = 4, 919 }; 920 921 static struct qcom_icc_node qhs_qdss_cfg = { 922 .name = "qhs_qdss_cfg", 923 .channels = 1, 924 .buswidth = 4, 925 }; 926 927 static struct qcom_icc_node qhs_qspi = { 928 .name = "qhs_qspi", 929 .channels = 1, 930 .buswidth = 4, 931 }; 932 933 static struct qcom_icc_node qhs_qup0 = { 934 .name = "qhs_qup0", 935 .channels = 1, 936 .buswidth = 4, 937 }; 938 939 static struct qcom_icc_node qhs_qup1 = { 940 .name = "qhs_qup1", 941 .channels = 1, 942 .buswidth = 4, 943 }; 944 945 static struct qcom_icc_node qhs_qup2 = { 946 .name = "qhs_qup2", 947 .channels = 1, 948 .buswidth = 4, 949 }; 950 951 static struct qcom_icc_node qhs_sdc2 = { 952 .name = "qhs_sdc2", 953 .channels = 1, 954 .buswidth = 4, 955 }; 956 957 static struct qcom_icc_node qhs_sdc4 = { 958 .name = "qhs_sdc4", 959 .channels = 1, 960 .buswidth = 4, 961 }; 962 963 static struct qcom_icc_node qhs_spss_cfg = { 964 .name = "qhs_spss_cfg", 965 .channels = 1, 966 .buswidth = 4, 967 }; 968 969 static struct qcom_icc_node qhs_tcsr = { 970 .name = "qhs_tcsr", 971 .channels = 1, 972 .buswidth = 4, 973 }; 974 975 static struct qcom_icc_node qhs_tlmm = { 976 .name = "qhs_tlmm", 977 .channels = 1, 978 .buswidth = 4, 979 }; 980 981 static struct qcom_icc_node qhs_tme_cfg = { 982 .name = "qhs_tme_cfg", 983 .channels = 1, 984 .buswidth = 4, 985 }; 986 987 static struct qcom_icc_node qhs_ufs_mem_cfg = { 988 .name = "qhs_ufs_mem_cfg", 989 .channels = 1, 990 .buswidth = 4, 991 }; 992 993 static struct qcom_icc_node qhs_usb3_0 = { 994 .name = "qhs_usb3_0", 995 .channels = 1, 996 .buswidth = 4, 997 }; 998 999 static struct qcom_icc_node qhs_venus_cfg = { 1000 .name = "qhs_venus_cfg", 1001 .channels = 1, 1002 .buswidth = 4, 1003 }; 1004 1005 static struct qcom_icc_node qhs_vsense_ctrl_cfg = { 1006 .name = "qhs_vsense_ctrl_cfg", 1007 .channels = 1, 1008 .buswidth = 4, 1009 }; 1010 1011 static struct qcom_icc_node qns_a1_noc_cfg = { 1012 .name = "qns_a1_noc_cfg", 1013 .channels = 1, 1014 .buswidth = 4, 1015 .num_links = 1, 1016 .link_nodes = { &qnm_a1noc_cfg }, 1017 }; 1018 1019 static struct qcom_icc_node qns_a2_noc_cfg = { 1020 .name = "qns_a2_noc_cfg", 1021 .channels = 1, 1022 .buswidth = 4, 1023 .num_links = 1, 1024 .link_nodes = { &qnm_a2noc_cfg }, 1025 }; 1026 1027 static struct qcom_icc_node qns_ddrss_cfg = { 1028 .name = "qns_ddrss_cfg", 1029 .channels = 1, 1030 .buswidth = 4, 1031 //FIXME where is link 1032 }; 1033 1034 static struct qcom_icc_node qns_mnoc_cfg = { 1035 .name = "qns_mnoc_cfg", 1036 .channels = 1, 1037 .buswidth = 4, 1038 .num_links = 1, 1039 .link_nodes = { &qnm_mnoc_cfg }, 1040 }; 1041 1042 static struct qcom_icc_node qns_pcie_anoc_cfg = { 1043 .name = "qns_pcie_anoc_cfg", 1044 .channels = 1, 1045 .buswidth = 4, 1046 .num_links = 1, 1047 .link_nodes = { &qnm_pcie_anoc_cfg }, 1048 }; 1049 1050 static struct qcom_icc_node qns_snoc_cfg = { 1051 .name = "qns_snoc_cfg", 1052 .channels = 1, 1053 .buswidth = 4, 1054 .num_links = 1, 1055 .link_nodes = { &qnm_snoc_cfg }, 1056 }; 1057 1058 static struct qcom_icc_node qxs_imem = { 1059 .name = "qxs_imem", 1060 .channels = 1, 1061 .buswidth = 8, 1062 }; 1063 1064 static struct qcom_icc_node qxs_pimem = { 1065 .name = "qxs_pimem", 1066 .channels = 1, 1067 .buswidth = 8, 1068 }; 1069 1070 static struct qcom_icc_node srvc_cnoc = { 1071 .name = "srvc_cnoc", 1072 .channels = 1, 1073 .buswidth = 4, 1074 }; 1075 1076 static struct qcom_icc_node xs_pcie_0 = { 1077 .name = "xs_pcie_0", 1078 .channels = 1, 1079 .buswidth = 8, 1080 }; 1081 1082 static struct qcom_icc_node xs_pcie_1 = { 1083 .name = "xs_pcie_1", 1084 .channels = 1, 1085 .buswidth = 8, 1086 }; 1087 1088 static struct qcom_icc_node xs_qdss_stm = { 1089 .name = "xs_qdss_stm", 1090 .channels = 1, 1091 .buswidth = 4, 1092 }; 1093 1094 static struct qcom_icc_node xs_sys_tcu_cfg = { 1095 .name = "xs_sys_tcu_cfg", 1096 .channels = 1, 1097 .buswidth = 8, 1098 }; 1099 1100 static struct qcom_icc_node qns_gem_noc_cnoc = { 1101 .name = "qns_gem_noc_cnoc", 1102 .channels = 1, 1103 .buswidth = 16, 1104 .num_links = 1, 1105 .link_nodes = { &qnm_gemnoc_cnoc }, 1106 }; 1107 1108 static struct qcom_icc_node qns_llcc = { 1109 .name = "qns_llcc", 1110 .channels = 4, 1111 .buswidth = 16, 1112 .num_links = 1, 1113 .link_nodes = { &llcc_mc }, 1114 }; 1115 1116 static struct qcom_icc_node qns_pcie = { 1117 .name = "qns_pcie", 1118 .channels = 1, 1119 .buswidth = 8, 1120 .num_links = 1, 1121 .link_nodes = { &qnm_gemnoc_pcie }, 1122 }; 1123 1124 static struct qcom_icc_node qhs_lpass_core = { 1125 .name = "qhs_lpass_core", 1126 .channels = 1, 1127 .buswidth = 4, 1128 }; 1129 1130 static struct qcom_icc_node qhs_lpass_lpi = { 1131 .name = "qhs_lpass_lpi", 1132 .channels = 1, 1133 .buswidth = 4, 1134 }; 1135 1136 static struct qcom_icc_node qhs_lpass_mpu = { 1137 .name = "qhs_lpass_mpu", 1138 .channels = 1, 1139 .buswidth = 4, 1140 }; 1141 1142 static struct qcom_icc_node qhs_lpass_top = { 1143 .name = "qhs_lpass_top", 1144 .channels = 1, 1145 .buswidth = 4, 1146 }; 1147 1148 static struct qcom_icc_node qns_sysnoc = { 1149 .name = "qns_sysnoc", 1150 .channels = 1, 1151 .buswidth = 16, 1152 .num_links = 1, 1153 .link_nodes = { &qnm_lpass_noc }, 1154 }; 1155 1156 static struct qcom_icc_node srvc_niu_aml_noc = { 1157 .name = "srvc_niu_aml_noc", 1158 .channels = 1, 1159 .buswidth = 4, 1160 }; 1161 1162 static struct qcom_icc_node srvc_niu_lpass_agnoc = { 1163 .name = "srvc_niu_lpass_agnoc", 1164 .channels = 1, 1165 .buswidth = 4, 1166 }; 1167 1168 static struct qcom_icc_node ebi = { 1169 .name = "ebi", 1170 .channels = 4, 1171 .buswidth = 4, 1172 }; 1173 1174 static struct qcom_icc_node qns_mem_noc_hf = { 1175 .name = "qns_mem_noc_hf", 1176 .channels = 2, 1177 .buswidth = 32, 1178 .num_links = 1, 1179 .link_nodes = { &qnm_mnoc_hf }, 1180 }; 1181 1182 static struct qcom_icc_node qns_mem_noc_sf = { 1183 .name = "qns_mem_noc_sf", 1184 .channels = 2, 1185 .buswidth = 32, 1186 .num_links = 1, 1187 .link_nodes = { &qnm_mnoc_sf }, 1188 }; 1189 1190 static struct qcom_icc_node srvc_mnoc = { 1191 .name = "srvc_mnoc", 1192 .channels = 1, 1193 .buswidth = 4, 1194 }; 1195 1196 static struct qcom_icc_node qns_nsp_gemnoc = { 1197 .name = "qns_nsp_gemnoc", 1198 .channels = 2, 1199 .buswidth = 32, 1200 .num_links = 1, 1201 .link_nodes = { &qnm_nsp_gemnoc }, 1202 }; 1203 1204 static struct qcom_icc_node service_nsp_noc = { 1205 .name = "service_nsp_noc", 1206 .channels = 1, 1207 .buswidth = 4, 1208 }; 1209 1210 static struct qcom_icc_node qns_pcie_mem_noc = { 1211 .name = "qns_pcie_mem_noc", 1212 .channels = 1, 1213 .buswidth = 16, 1214 .num_links = 1, 1215 .link_nodes = { &qnm_pcie }, 1216 }; 1217 1218 static struct qcom_icc_node srvc_pcie_aggre_noc = { 1219 .name = "srvc_pcie_aggre_noc", 1220 .channels = 1, 1221 .buswidth = 4, 1222 }; 1223 1224 static struct qcom_icc_node qns_gemnoc_gc = { 1225 .name = "qns_gemnoc_gc", 1226 .channels = 1, 1227 .buswidth = 8, 1228 .num_links = 1, 1229 .link_nodes = { &qnm_snoc_gc }, 1230 }; 1231 1232 static struct qcom_icc_node qns_gemnoc_sf = { 1233 .name = "qns_gemnoc_sf", 1234 .channels = 1, 1235 .buswidth = 16, 1236 .num_links = 1, 1237 .link_nodes = { &qnm_snoc_sf }, 1238 }; 1239 1240 static struct qcom_icc_node srvc_snoc = { 1241 .name = "srvc_snoc", 1242 .channels = 1, 1243 .buswidth = 4, 1244 }; 1245 1246 static struct qcom_icc_node qns_llcc_disp = { 1247 .name = "qns_llcc_disp", 1248 .channels = 4, 1249 .buswidth = 16, 1250 .num_links = 1, 1251 .link_nodes = { &llcc_mc_disp }, 1252 }; 1253 1254 static struct qcom_icc_node ebi_disp = { 1255 .name = "ebi_disp", 1256 .channels = 4, 1257 .buswidth = 4, 1258 }; 1259 1260 static struct qcom_icc_node qns_mem_noc_hf_disp = { 1261 .name = "qns_mem_noc_hf_disp", 1262 .channels = 2, 1263 .buswidth = 32, 1264 .num_links = 1, 1265 .link_nodes = { &qnm_mnoc_hf_disp }, 1266 }; 1267 1268 static struct qcom_icc_node qns_mem_noc_sf_disp = { 1269 .name = "qns_mem_noc_sf_disp", 1270 .channels = 2, 1271 .buswidth = 32, 1272 .num_links = 1, 1273 .link_nodes = { &qnm_mnoc_sf_disp }, 1274 }; 1275 1276 static struct qcom_icc_bcm bcm_acv = { 1277 .name = "ACV", 1278 .enable_mask = 0x8, 1279 .num_nodes = 1, 1280 .nodes = { &ebi }, 1281 }; 1282 1283 static struct qcom_icc_bcm bcm_ce0 = { 1284 .name = "CE0", 1285 .num_nodes = 1, 1286 .nodes = { &qxm_crypto }, 1287 }; 1288 1289 static struct qcom_icc_bcm bcm_cn0 = { 1290 .name = "CN0", 1291 .enable_mask = 0x1, 1292 .keepalive = true, 1293 .num_nodes = 55, 1294 .nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie, 1295 &qhs_ahb2phy0, &qhs_ahb2phy1, 1296 &qhs_aoss, &qhs_camera_cfg, 1297 &qhs_clk_ctl, &qhs_compute_cfg, 1298 &qhs_cpr_cx, &qhs_cpr_mmcx, 1299 &qhs_cpr_mxa, &qhs_cpr_mxc, 1300 &qhs_crypto0_cfg, &qhs_cx_rdpm, 1301 &qhs_display_cfg, &qhs_gpuss_cfg, 1302 &qhs_imem_cfg, &qhs_ipa, 1303 &qhs_ipc_router, &qhs_lpass_cfg, 1304 &qhs_mss_cfg, &qhs_mx_rdpm, 1305 &qhs_pcie0_cfg, &qhs_pcie1_cfg, 1306 &qhs_pdm, &qhs_pimem_cfg, 1307 &qhs_prng, &qhs_qdss_cfg, 1308 &qhs_qspi, &qhs_qup0, 1309 &qhs_qup1, &qhs_qup2, 1310 &qhs_sdc2, &qhs_sdc4, 1311 &qhs_spss_cfg, &qhs_tcsr, 1312 &qhs_tlmm, &qhs_tme_cfg, 1313 &qhs_ufs_mem_cfg, &qhs_usb3_0, 1314 &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, 1315 &qns_a1_noc_cfg, &qns_a2_noc_cfg, 1316 &qns_ddrss_cfg, &qns_mnoc_cfg, 1317 &qns_pcie_anoc_cfg, &qns_snoc_cfg, 1318 &qxs_imem, &qxs_pimem, 1319 &srvc_cnoc, &xs_pcie_0, 1320 &xs_pcie_1, &xs_qdss_stm, 1321 &xs_sys_tcu_cfg }, 1322 }; 1323 1324 static struct qcom_icc_bcm bcm_co0 = { 1325 .name = "CO0", 1326 .enable_mask = 0x1, 1327 .num_nodes = 2, 1328 .nodes = { &qxm_nsp, &qns_nsp_gemnoc }, 1329 }; 1330 1331 static struct qcom_icc_bcm bcm_mc0 = { 1332 .name = "MC0", 1333 .keepalive = true, 1334 .num_nodes = 1, 1335 .nodes = { &ebi }, 1336 }; 1337 1338 static struct qcom_icc_bcm bcm_mm0 = { 1339 .name = "MM0", 1340 .keepalive = true, 1341 .num_nodes = 1, 1342 .nodes = { &qns_mem_noc_hf }, 1343 }; 1344 1345 static struct qcom_icc_bcm bcm_mm1 = { 1346 .name = "MM1", 1347 .enable_mask = 0x1, 1348 .num_nodes = 12, 1349 .nodes = { &qnm_camnoc_hf, &qnm_camnoc_icp, 1350 &qnm_camnoc_sf, &qnm_mdp, 1351 &qnm_mnoc_cfg, &qnm_rot, 1352 &qnm_vapss_hcp, &qnm_video, 1353 &qnm_video_cv_cpu, &qnm_video_cvp, 1354 &qnm_video_v_cpu, &qns_mem_noc_sf }, 1355 }; 1356 1357 static struct qcom_icc_bcm bcm_qup0 = { 1358 .name = "QUP0", 1359 .keepalive = true, 1360 .vote_scale = 1, 1361 .num_nodes = 1, 1362 .nodes = { &qup0_core_slave }, 1363 }; 1364 1365 static struct qcom_icc_bcm bcm_qup1 = { 1366 .name = "QUP1", 1367 .keepalive = true, 1368 .vote_scale = 1, 1369 .num_nodes = 1, 1370 .nodes = { &qup1_core_slave }, 1371 }; 1372 1373 static struct qcom_icc_bcm bcm_qup2 = { 1374 .name = "QUP2", 1375 .keepalive = true, 1376 .vote_scale = 1, 1377 .num_nodes = 1, 1378 .nodes = { &qup2_core_slave }, 1379 }; 1380 1381 static struct qcom_icc_bcm bcm_sh0 = { 1382 .name = "SH0", 1383 .keepalive = true, 1384 .num_nodes = 1, 1385 .nodes = { &qns_llcc }, 1386 }; 1387 1388 static struct qcom_icc_bcm bcm_sh1 = { 1389 .name = "SH1", 1390 .enable_mask = 0x1, 1391 .num_nodes = 7, 1392 .nodes = { &alm_gpu_tcu, &alm_sys_tcu, 1393 &qnm_nsp_gemnoc, &qnm_pcie, 1394 &qnm_snoc_gc, &qns_gem_noc_cnoc, 1395 &qns_pcie }, 1396 }; 1397 1398 static struct qcom_icc_bcm bcm_sn0 = { 1399 .name = "SN0", 1400 .keepalive = true, 1401 .num_nodes = 1, 1402 .nodes = { &qns_gemnoc_sf }, 1403 }; 1404 1405 static struct qcom_icc_bcm bcm_sn1 = { 1406 .name = "SN1", 1407 .enable_mask = 0x1, 1408 .num_nodes = 4, 1409 .nodes = { &qhm_gic, &qxm_pimem, 1410 &xm_gic, &qns_gemnoc_gc }, 1411 }; 1412 1413 static struct qcom_icc_bcm bcm_sn2 = { 1414 .name = "SN2", 1415 .num_nodes = 1, 1416 .nodes = { &qnm_aggre1_noc }, 1417 }; 1418 1419 static struct qcom_icc_bcm bcm_sn3 = { 1420 .name = "SN3", 1421 .num_nodes = 1, 1422 .nodes = { &qnm_aggre2_noc }, 1423 }; 1424 1425 static struct qcom_icc_bcm bcm_sn4 = { 1426 .name = "SN4", 1427 .num_nodes = 1, 1428 .nodes = { &qnm_lpass_noc }, 1429 }; 1430 1431 static struct qcom_icc_bcm bcm_sn7 = { 1432 .name = "SN7", 1433 .num_nodes = 1, 1434 .nodes = { &qns_pcie_mem_noc }, 1435 }; 1436 1437 static struct qcom_icc_bcm bcm_acv_disp = { 1438 .name = "ACV", 1439 .enable_mask = 0x1, 1440 .num_nodes = 1, 1441 .nodes = { &ebi_disp }, 1442 }; 1443 1444 static struct qcom_icc_bcm bcm_mc0_disp = { 1445 .name = "MC0", 1446 .num_nodes = 1, 1447 .nodes = { &ebi_disp }, 1448 }; 1449 1450 static struct qcom_icc_bcm bcm_mm0_disp = { 1451 .name = "MM0", 1452 .num_nodes = 1, 1453 .nodes = { &qns_mem_noc_hf_disp }, 1454 }; 1455 1456 static struct qcom_icc_bcm bcm_mm1_disp = { 1457 .name = "MM1", 1458 .enable_mask = 0x1, 1459 .num_nodes = 3, 1460 .nodes = { &qnm_mdp_disp, &qnm_rot_disp, 1461 &qns_mem_noc_sf_disp }, 1462 }; 1463 1464 static struct qcom_icc_bcm bcm_sh0_disp = { 1465 .name = "SH0", 1466 .num_nodes = 1, 1467 .nodes = { &qns_llcc_disp }, 1468 }; 1469 1470 static struct qcom_icc_bcm bcm_sh1_disp = { 1471 .name = "SH1", 1472 .enable_mask = 0x1, 1473 .num_nodes = 1, 1474 .nodes = { &qnm_pcie_disp }, 1475 }; 1476 1477 static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { 1478 }; 1479 1480 static struct qcom_icc_node * const aggre1_noc_nodes[] = { 1481 [MASTER_QSPI_0] = &qhm_qspi, 1482 [MASTER_QUP_1] = &qhm_qup1, 1483 [MASTER_A1NOC_CFG] = &qnm_a1noc_cfg, 1484 [MASTER_SDCC_4] = &xm_sdc4, 1485 [MASTER_UFS_MEM] = &xm_ufs_mem, 1486 [MASTER_USB3_0] = &xm_usb3_0, 1487 [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc, 1488 [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc, 1489 }; 1490 1491 static const struct qcom_icc_desc sm8450_aggre1_noc = { 1492 .nodes = aggre1_noc_nodes, 1493 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), 1494 .bcms = aggre1_noc_bcms, 1495 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), 1496 }; 1497 1498 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { 1499 &bcm_ce0, 1500 }; 1501 1502 static struct qcom_icc_node * const aggre2_noc_nodes[] = { 1503 [MASTER_QDSS_BAM] = &qhm_qdss_bam, 1504 [MASTER_QUP_0] = &qhm_qup0, 1505 [MASTER_QUP_2] = &qhm_qup2, 1506 [MASTER_A2NOC_CFG] = &qnm_a2noc_cfg, 1507 [MASTER_CRYPTO] = &qxm_crypto, 1508 [MASTER_IPA] = &qxm_ipa, 1509 [MASTER_SENSORS_PROC] = &qxm_sensorss_q6, 1510 [MASTER_SP] = &qxm_sp, 1511 [MASTER_QDSS_ETR] = &xm_qdss_etr_0, 1512 [MASTER_QDSS_ETR_1] = &xm_qdss_etr_1, 1513 [MASTER_SDCC_2] = &xm_sdc2, 1514 [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc, 1515 [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc, 1516 }; 1517 1518 static const struct qcom_icc_desc sm8450_aggre2_noc = { 1519 .nodes = aggre2_noc_nodes, 1520 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), 1521 .bcms = aggre2_noc_bcms, 1522 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), 1523 }; 1524 1525 static struct qcom_icc_bcm * const clk_virt_bcms[] = { 1526 &bcm_qup0, 1527 &bcm_qup1, 1528 &bcm_qup2, 1529 }; 1530 1531 static struct qcom_icc_node * const clk_virt_nodes[] = { 1532 [MASTER_QUP_CORE_0] = &qup0_core_master, 1533 [MASTER_QUP_CORE_1] = &qup1_core_master, 1534 [MASTER_QUP_CORE_2] = &qup2_core_master, 1535 [SLAVE_QUP_CORE_0] = &qup0_core_slave, 1536 [SLAVE_QUP_CORE_1] = &qup1_core_slave, 1537 [SLAVE_QUP_CORE_2] = &qup2_core_slave, 1538 }; 1539 1540 static const struct qcom_icc_desc sm8450_clk_virt = { 1541 .nodes = clk_virt_nodes, 1542 .num_nodes = ARRAY_SIZE(clk_virt_nodes), 1543 .bcms = clk_virt_bcms, 1544 .num_bcms = ARRAY_SIZE(clk_virt_bcms), 1545 }; 1546 1547 static struct qcom_icc_bcm * const config_noc_bcms[] = { 1548 &bcm_cn0, 1549 }; 1550 1551 static struct qcom_icc_node * const config_noc_nodes[] = { 1552 [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc, 1553 [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie, 1554 [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0, 1555 [SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1, 1556 [SLAVE_AOSS] = &qhs_aoss, 1557 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, 1558 [SLAVE_CLK_CTL] = &qhs_clk_ctl, 1559 [SLAVE_CDSP_CFG] = &qhs_compute_cfg, 1560 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx, 1561 [SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx, 1562 [SLAVE_RBCPR_MXA_CFG] = &qhs_cpr_mxa, 1563 [SLAVE_RBCPR_MXC_CFG] = &qhs_cpr_mxc, 1564 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, 1565 [SLAVE_CX_RDPM] = &qhs_cx_rdpm, 1566 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg, 1567 [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg, 1568 [SLAVE_IMEM_CFG] = &qhs_imem_cfg, 1569 [SLAVE_IPA_CFG] = &qhs_ipa, 1570 [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router, 1571 [SLAVE_LPASS] = &qhs_lpass_cfg, 1572 [SLAVE_CNOC_MSS] = &qhs_mss_cfg, 1573 [SLAVE_MX_RDPM] = &qhs_mx_rdpm, 1574 [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg, 1575 [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg, 1576 [SLAVE_PDM] = &qhs_pdm, 1577 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg, 1578 [SLAVE_PRNG] = &qhs_prng, 1579 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, 1580 [SLAVE_QSPI_0] = &qhs_qspi, 1581 [SLAVE_QUP_0] = &qhs_qup0, 1582 [SLAVE_QUP_1] = &qhs_qup1, 1583 [SLAVE_QUP_2] = &qhs_qup2, 1584 [SLAVE_SDCC_2] = &qhs_sdc2, 1585 [SLAVE_SDCC_4] = &qhs_sdc4, 1586 [SLAVE_SPSS_CFG] = &qhs_spss_cfg, 1587 [SLAVE_TCSR] = &qhs_tcsr, 1588 [SLAVE_TLMM] = &qhs_tlmm, 1589 [SLAVE_TME_CFG] = &qhs_tme_cfg, 1590 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, 1591 [SLAVE_USB3_0] = &qhs_usb3_0, 1592 [SLAVE_VENUS_CFG] = &qhs_venus_cfg, 1593 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, 1594 [SLAVE_A1NOC_CFG] = &qns_a1_noc_cfg, 1595 [SLAVE_A2NOC_CFG] = &qns_a2_noc_cfg, 1596 [SLAVE_DDRSS_CFG] = &qns_ddrss_cfg, 1597 [SLAVE_CNOC_MNOC_CFG] = &qns_mnoc_cfg, 1598 [SLAVE_PCIE_ANOC_CFG] = &qns_pcie_anoc_cfg, 1599 [SLAVE_SNOC_CFG] = &qns_snoc_cfg, 1600 [SLAVE_IMEM] = &qxs_imem, 1601 [SLAVE_PIMEM] = &qxs_pimem, 1602 [SLAVE_SERVICE_CNOC] = &srvc_cnoc, 1603 [SLAVE_PCIE_0] = &xs_pcie_0, 1604 [SLAVE_PCIE_1] = &xs_pcie_1, 1605 [SLAVE_QDSS_STM] = &xs_qdss_stm, 1606 [SLAVE_TCU] = &xs_sys_tcu_cfg, 1607 }; 1608 1609 static const struct qcom_icc_desc sm8450_config_noc = { 1610 .nodes = config_noc_nodes, 1611 .num_nodes = ARRAY_SIZE(config_noc_nodes), 1612 .bcms = config_noc_bcms, 1613 .num_bcms = ARRAY_SIZE(config_noc_bcms), 1614 }; 1615 1616 static struct qcom_icc_bcm * const gem_noc_bcms[] = { 1617 &bcm_sh0, 1618 &bcm_sh1, 1619 &bcm_sh0_disp, 1620 &bcm_sh1_disp, 1621 }; 1622 1623 static struct qcom_icc_node * const gem_noc_nodes[] = { 1624 [MASTER_GPU_TCU] = &alm_gpu_tcu, 1625 [MASTER_SYS_TCU] = &alm_sys_tcu, 1626 [MASTER_APPSS_PROC] = &chm_apps, 1627 [MASTER_GFX3D] = &qnm_gpu, 1628 [MASTER_MSS_PROC] = &qnm_mdsp, 1629 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, 1630 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, 1631 [MASTER_COMPUTE_NOC] = &qnm_nsp_gemnoc, 1632 [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie, 1633 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc, 1634 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, 1635 [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc, 1636 [SLAVE_LLCC] = &qns_llcc, 1637 [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie, 1638 [MASTER_MNOC_HF_MEM_NOC_DISP] = &qnm_mnoc_hf_disp, 1639 [MASTER_MNOC_SF_MEM_NOC_DISP] = &qnm_mnoc_sf_disp, 1640 [MASTER_ANOC_PCIE_GEM_NOC_DISP] = &qnm_pcie_disp, 1641 [SLAVE_LLCC_DISP] = &qns_llcc_disp, 1642 }; 1643 1644 static const struct qcom_icc_desc sm8450_gem_noc = { 1645 .nodes = gem_noc_nodes, 1646 .num_nodes = ARRAY_SIZE(gem_noc_nodes), 1647 .bcms = gem_noc_bcms, 1648 .num_bcms = ARRAY_SIZE(gem_noc_bcms), 1649 }; 1650 1651 static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = { 1652 }; 1653 1654 static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { 1655 [MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc, 1656 [MASTER_LPASS_PROC] = &qxm_lpass_dsp, 1657 [SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core, 1658 [SLAVE_LPASS_LPI_CFG] = &qhs_lpass_lpi, 1659 [SLAVE_LPASS_MPU_CFG] = &qhs_lpass_mpu, 1660 [SLAVE_LPASS_TOP_CFG] = &qhs_lpass_top, 1661 [SLAVE_LPASS_SNOC] = &qns_sysnoc, 1662 [SLAVE_SERVICES_LPASS_AML_NOC] = &srvc_niu_aml_noc, 1663 [SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc, 1664 }; 1665 1666 static const struct qcom_icc_desc sm8450_lpass_ag_noc = { 1667 .nodes = lpass_ag_noc_nodes, 1668 .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), 1669 .bcms = lpass_ag_noc_bcms, 1670 .num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms), 1671 }; 1672 1673 static struct qcom_icc_bcm * const mc_virt_bcms[] = { 1674 &bcm_acv, 1675 &bcm_mc0, 1676 &bcm_acv_disp, 1677 &bcm_mc0_disp, 1678 }; 1679 1680 static struct qcom_icc_node * const mc_virt_nodes[] = { 1681 [MASTER_LLCC] = &llcc_mc, 1682 [SLAVE_EBI1] = &ebi, 1683 [MASTER_LLCC_DISP] = &llcc_mc_disp, 1684 [SLAVE_EBI1_DISP] = &ebi_disp, 1685 }; 1686 1687 static const struct qcom_icc_desc sm8450_mc_virt = { 1688 .nodes = mc_virt_nodes, 1689 .num_nodes = ARRAY_SIZE(mc_virt_nodes), 1690 .bcms = mc_virt_bcms, 1691 .num_bcms = ARRAY_SIZE(mc_virt_bcms), 1692 }; 1693 1694 static struct qcom_icc_bcm * const mmss_noc_bcms[] = { 1695 &bcm_mm0, 1696 &bcm_mm1, 1697 &bcm_mm0_disp, 1698 &bcm_mm1_disp, 1699 }; 1700 1701 static struct qcom_icc_node * const mmss_noc_nodes[] = { 1702 [MASTER_CAMNOC_HF] = &qnm_camnoc_hf, 1703 [MASTER_CAMNOC_ICP] = &qnm_camnoc_icp, 1704 [MASTER_CAMNOC_SF] = &qnm_camnoc_sf, 1705 [MASTER_MDP] = &qnm_mdp, 1706 [MASTER_CNOC_MNOC_CFG] = &qnm_mnoc_cfg, 1707 [MASTER_ROTATOR] = &qnm_rot, 1708 [MASTER_CDSP_HCP] = &qnm_vapss_hcp, 1709 [MASTER_VIDEO] = &qnm_video, 1710 [MASTER_VIDEO_CV_PROC] = &qnm_video_cv_cpu, 1711 [MASTER_VIDEO_PROC] = &qnm_video_cvp, 1712 [MASTER_VIDEO_V_PROC] = &qnm_video_v_cpu, 1713 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, 1714 [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf, 1715 [SLAVE_SERVICE_MNOC] = &srvc_mnoc, 1716 [MASTER_MDP_DISP] = &qnm_mdp_disp, 1717 [MASTER_ROTATOR_DISP] = &qnm_rot_disp, 1718 [SLAVE_MNOC_HF_MEM_NOC_DISP] = &qns_mem_noc_hf_disp, 1719 [SLAVE_MNOC_SF_MEM_NOC_DISP] = &qns_mem_noc_sf_disp, 1720 }; 1721 1722 static const struct qcom_icc_desc sm8450_mmss_noc = { 1723 .nodes = mmss_noc_nodes, 1724 .num_nodes = ARRAY_SIZE(mmss_noc_nodes), 1725 .bcms = mmss_noc_bcms, 1726 .num_bcms = ARRAY_SIZE(mmss_noc_bcms), 1727 }; 1728 1729 static struct qcom_icc_bcm * const nsp_noc_bcms[] = { 1730 &bcm_co0, 1731 }; 1732 1733 static struct qcom_icc_node * const nsp_noc_nodes[] = { 1734 [MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config, 1735 [MASTER_CDSP_PROC] = &qxm_nsp, 1736 [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc, 1737 [SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc, 1738 }; 1739 1740 static const struct qcom_icc_desc sm8450_nsp_noc = { 1741 .nodes = nsp_noc_nodes, 1742 .num_nodes = ARRAY_SIZE(nsp_noc_nodes), 1743 .bcms = nsp_noc_bcms, 1744 .num_bcms = ARRAY_SIZE(nsp_noc_bcms), 1745 }; 1746 1747 static struct qcom_icc_bcm * const pcie_anoc_bcms[] = { 1748 &bcm_sn7, 1749 }; 1750 1751 static struct qcom_icc_node * const pcie_anoc_nodes[] = { 1752 [MASTER_PCIE_ANOC_CFG] = &qnm_pcie_anoc_cfg, 1753 [MASTER_PCIE_0] = &xm_pcie3_0, 1754 [MASTER_PCIE_1] = &xm_pcie3_1, 1755 [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc, 1756 [SLAVE_SERVICE_PCIE_ANOC] = &srvc_pcie_aggre_noc, 1757 }; 1758 1759 static const struct qcom_icc_desc sm8450_pcie_anoc = { 1760 .nodes = pcie_anoc_nodes, 1761 .num_nodes = ARRAY_SIZE(pcie_anoc_nodes), 1762 .bcms = pcie_anoc_bcms, 1763 .num_bcms = ARRAY_SIZE(pcie_anoc_bcms), 1764 }; 1765 1766 static struct qcom_icc_bcm * const system_noc_bcms[] = { 1767 &bcm_sn0, 1768 &bcm_sn1, 1769 &bcm_sn2, 1770 &bcm_sn3, 1771 &bcm_sn4, 1772 }; 1773 1774 static struct qcom_icc_node * const system_noc_nodes[] = { 1775 [MASTER_GIC_AHB] = &qhm_gic, 1776 [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc, 1777 [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc, 1778 [MASTER_LPASS_ANOC] = &qnm_lpass_noc, 1779 [MASTER_SNOC_CFG] = &qnm_snoc_cfg, 1780 [MASTER_PIMEM] = &qxm_pimem, 1781 [MASTER_GIC] = &xm_gic, 1782 [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc, 1783 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, 1784 [SLAVE_SERVICE_SNOC] = &srvc_snoc, 1785 }; 1786 1787 static const struct qcom_icc_desc sm8450_system_noc = { 1788 .nodes = system_noc_nodes, 1789 .num_nodes = ARRAY_SIZE(system_noc_nodes), 1790 .bcms = system_noc_bcms, 1791 .num_bcms = ARRAY_SIZE(system_noc_bcms), 1792 }; 1793 1794 static const struct of_device_id qnoc_of_match[] = { 1795 { .compatible = "qcom,sm8450-aggre1-noc", 1796 .data = &sm8450_aggre1_noc}, 1797 { .compatible = "qcom,sm8450-aggre2-noc", 1798 .data = &sm8450_aggre2_noc}, 1799 { .compatible = "qcom,sm8450-clk-virt", 1800 .data = &sm8450_clk_virt}, 1801 { .compatible = "qcom,sm8450-config-noc", 1802 .data = &sm8450_config_noc}, 1803 { .compatible = "qcom,sm8450-gem-noc", 1804 .data = &sm8450_gem_noc}, 1805 { .compatible = "qcom,sm8450-lpass-ag-noc", 1806 .data = &sm8450_lpass_ag_noc}, 1807 { .compatible = "qcom,sm8450-mc-virt", 1808 .data = &sm8450_mc_virt}, 1809 { .compatible = "qcom,sm8450-mmss-noc", 1810 .data = &sm8450_mmss_noc}, 1811 { .compatible = "qcom,sm8450-nsp-noc", 1812 .data = &sm8450_nsp_noc}, 1813 { .compatible = "qcom,sm8450-pcie-anoc", 1814 .data = &sm8450_pcie_anoc}, 1815 { .compatible = "qcom,sm8450-system-noc", 1816 .data = &sm8450_system_noc}, 1817 { } 1818 }; 1819 MODULE_DEVICE_TABLE(of, qnoc_of_match); 1820 1821 static struct platform_driver qnoc_driver = { 1822 .probe = qcom_icc_rpmh_probe, 1823 .remove = qcom_icc_rpmh_remove, 1824 .driver = { 1825 .name = "qnoc-sm8450", 1826 .of_match_table = qnoc_of_match, 1827 .sync_state = icc_sync_state, 1828 }, 1829 }; 1830 1831 static int __init qnoc_driver_init(void) 1832 { 1833 return platform_driver_register(&qnoc_driver); 1834 } 1835 core_initcall(qnoc_driver_init); 1836 1837 static void __exit qnoc_driver_exit(void) 1838 { 1839 platform_driver_unregister(&qnoc_driver); 1840 } 1841 module_exit(qnoc_driver_exit); 1842 1843 MODULE_DESCRIPTION("sm8450 NoC driver"); 1844 MODULE_LICENSE("GPL v2"); 1845