1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021, Linaro Limited 5 * 6 */ 7 8 #include <linux/interconnect-provider.h> 9 #include <linux/module.h> 10 #include <linux/mod_devicetable.h> 11 #include <linux/platform_device.h> 12 #include <dt-bindings/interconnect/qcom,sm8350.h> 13 14 #include "bcm-voter.h" 15 #include "icc-rpmh.h" 16 #include "sm8350.h" 17 18 static struct qcom_icc_node qhm_qspi = { 19 .name = "qhm_qspi", 20 .id = SM8350_MASTER_QSPI_0, 21 .channels = 1, 22 .buswidth = 4, 23 .num_links = 1, 24 .links = { SM8350_SLAVE_A1NOC_SNOC }, 25 }; 26 27 static struct qcom_icc_node qhm_qup0 = { 28 .name = "qhm_qup0", 29 .id = SM8350_MASTER_QUP_0, 30 .channels = 1, 31 .buswidth = 4, 32 .num_links = 1, 33 .links = { SM8350_SLAVE_A2NOC_SNOC }, 34 }; 35 36 static struct qcom_icc_node qhm_qup1 = { 37 .name = "qhm_qup1", 38 .id = SM8350_MASTER_QUP_1, 39 .channels = 1, 40 .buswidth = 4, 41 .num_links = 1, 42 .links = { SM8350_SLAVE_A1NOC_SNOC }, 43 }; 44 45 static struct qcom_icc_node qhm_qup2 = { 46 .name = "qhm_qup2", 47 .id = SM8350_MASTER_QUP_2, 48 .channels = 1, 49 .buswidth = 4, 50 .num_links = 1, 51 .links = { SM8350_SLAVE_A2NOC_SNOC }, 52 }; 53 54 static struct qcom_icc_node qnm_a1noc_cfg = { 55 .name = "qnm_a1noc_cfg", 56 .id = SM8350_MASTER_A1NOC_CFG, 57 .channels = 1, 58 .buswidth = 4, 59 .num_links = 1, 60 .links = { SM8350_SLAVE_SERVICE_A1NOC }, 61 }; 62 63 static struct qcom_icc_node xm_sdc4 = { 64 .name = "xm_sdc4", 65 .id = SM8350_MASTER_SDCC_4, 66 .channels = 1, 67 .buswidth = 8, 68 .num_links = 1, 69 .links = { SM8350_SLAVE_A1NOC_SNOC }, 70 }; 71 72 static struct qcom_icc_node xm_ufs_mem = { 73 .name = "xm_ufs_mem", 74 .id = SM8350_MASTER_UFS_MEM, 75 .channels = 1, 76 .buswidth = 8, 77 .num_links = 1, 78 .links = { SM8350_SLAVE_A1NOC_SNOC }, 79 }; 80 81 static struct qcom_icc_node xm_usb3_0 = { 82 .name = "xm_usb3_0", 83 .id = SM8350_MASTER_USB3_0, 84 .channels = 1, 85 .buswidth = 8, 86 .num_links = 1, 87 .links = { SM8350_SLAVE_A1NOC_SNOC }, 88 }; 89 90 static struct qcom_icc_node xm_usb3_1 = { 91 .name = "xm_usb3_1", 92 .id = SM8350_MASTER_USB3_1, 93 .channels = 1, 94 .buswidth = 8, 95 .num_links = 1, 96 .links = { SM8350_SLAVE_A1NOC_SNOC }, 97 }; 98 99 static struct qcom_icc_node qhm_qdss_bam = { 100 .name = "qhm_qdss_bam", 101 .id = SM8350_MASTER_QDSS_BAM, 102 .channels = 1, 103 .buswidth = 4, 104 .num_links = 1, 105 .links = { SM8350_SLAVE_A2NOC_SNOC }, 106 }; 107 108 static struct qcom_icc_node qnm_a2noc_cfg = { 109 .name = "qnm_a2noc_cfg", 110 .id = SM8350_MASTER_A2NOC_CFG, 111 .channels = 1, 112 .buswidth = 4, 113 .num_links = 1, 114 .links = { SM8350_SLAVE_SERVICE_A2NOC }, 115 }; 116 117 static struct qcom_icc_node qxm_crypto = { 118 .name = "qxm_crypto", 119 .id = SM8350_MASTER_CRYPTO, 120 .channels = 1, 121 .buswidth = 8, 122 .num_links = 1, 123 .links = { SM8350_SLAVE_A2NOC_SNOC }, 124 }; 125 126 static struct qcom_icc_node qxm_ipa = { 127 .name = "qxm_ipa", 128 .id = SM8350_MASTER_IPA, 129 .channels = 1, 130 .buswidth = 8, 131 .num_links = 1, 132 .links = { SM8350_SLAVE_A2NOC_SNOC }, 133 }; 134 135 static struct qcom_icc_node xm_pcie3_0 = { 136 .name = "xm_pcie3_0", 137 .id = SM8350_MASTER_PCIE_0, 138 .channels = 1, 139 .buswidth = 8, 140 .num_links = 1, 141 .links = { SM8350_SLAVE_ANOC_PCIE_GEM_NOC }, 142 }; 143 144 static struct qcom_icc_node xm_pcie3_1 = { 145 .name = "xm_pcie3_1", 146 .id = SM8350_MASTER_PCIE_1, 147 .channels = 1, 148 .buswidth = 8, 149 .num_links = 1, 150 .links = { SM8350_SLAVE_ANOC_PCIE_GEM_NOC }, 151 }; 152 153 static struct qcom_icc_node xm_qdss_etr = { 154 .name = "xm_qdss_etr", 155 .id = SM8350_MASTER_QDSS_ETR, 156 .channels = 1, 157 .buswidth = 8, 158 .num_links = 1, 159 .links = { SM8350_SLAVE_A2NOC_SNOC }, 160 }; 161 162 static struct qcom_icc_node xm_sdc2 = { 163 .name = "xm_sdc2", 164 .id = SM8350_MASTER_SDCC_2, 165 .channels = 1, 166 .buswidth = 8, 167 .num_links = 1, 168 .links = { SM8350_SLAVE_A2NOC_SNOC }, 169 }; 170 171 static struct qcom_icc_node xm_ufs_card = { 172 .name = "xm_ufs_card", 173 .id = SM8350_MASTER_UFS_CARD, 174 .channels = 1, 175 .buswidth = 8, 176 .num_links = 1, 177 .links = { SM8350_SLAVE_A2NOC_SNOC }, 178 }; 179 180 static struct qcom_icc_node qnm_gemnoc_cnoc = { 181 .name = "qnm_gemnoc_cnoc", 182 .id = SM8350_MASTER_GEM_NOC_CNOC, 183 .channels = 1, 184 .buswidth = 16, 185 .num_links = 56, 186 .links = { SM8350_SLAVE_AHB2PHY_SOUTH, 187 SM8350_SLAVE_AHB2PHY_NORTH, 188 SM8350_SLAVE_AOSS, 189 SM8350_SLAVE_APPSS, 190 SM8350_SLAVE_CAMERA_CFG, 191 SM8350_SLAVE_CLK_CTL, 192 SM8350_SLAVE_CDSP_CFG, 193 SM8350_SLAVE_RBCPR_CX_CFG, 194 SM8350_SLAVE_RBCPR_MMCX_CFG, 195 SM8350_SLAVE_RBCPR_MX_CFG, 196 SM8350_SLAVE_CRYPTO_0_CFG, 197 SM8350_SLAVE_CX_RDPM, 198 SM8350_SLAVE_DCC_CFG, 199 SM8350_SLAVE_DISPLAY_CFG, 200 SM8350_SLAVE_GFX3D_CFG, 201 SM8350_SLAVE_HWKM, 202 SM8350_SLAVE_IMEM_CFG, 203 SM8350_SLAVE_IPA_CFG, 204 SM8350_SLAVE_IPC_ROUTER_CFG, 205 SM8350_SLAVE_LPASS, 206 SM8350_SLAVE_CNOC_MSS, 207 SM8350_SLAVE_MX_RDPM, 208 SM8350_SLAVE_PCIE_0_CFG, 209 SM8350_SLAVE_PCIE_1_CFG, 210 SM8350_SLAVE_PDM, 211 SM8350_SLAVE_PIMEM_CFG, 212 SM8350_SLAVE_PKA_WRAPPER_CFG, 213 SM8350_SLAVE_PMU_WRAPPER_CFG, 214 SM8350_SLAVE_QDSS_CFG, 215 SM8350_SLAVE_QSPI_0, 216 SM8350_SLAVE_QUP_0, 217 SM8350_SLAVE_QUP_1, 218 SM8350_SLAVE_QUP_2, 219 SM8350_SLAVE_SDCC_2, 220 SM8350_SLAVE_SDCC_4, 221 SM8350_SLAVE_SECURITY, 222 SM8350_SLAVE_SPSS_CFG, 223 SM8350_SLAVE_TCSR, 224 SM8350_SLAVE_TLMM, 225 SM8350_SLAVE_UFS_CARD_CFG, 226 SM8350_SLAVE_UFS_MEM_CFG, 227 SM8350_SLAVE_USB3_0, 228 SM8350_SLAVE_USB3_1, 229 SM8350_SLAVE_VENUS_CFG, 230 SM8350_SLAVE_VSENSE_CTRL_CFG, 231 SM8350_SLAVE_A1NOC_CFG, 232 SM8350_SLAVE_A2NOC_CFG, 233 SM8350_SLAVE_DDRSS_CFG, 234 SM8350_SLAVE_CNOC_MNOC_CFG, 235 SM8350_SLAVE_SNOC_CFG, 236 SM8350_SLAVE_BOOT_IMEM, 237 SM8350_SLAVE_IMEM, 238 SM8350_SLAVE_PIMEM, 239 SM8350_SLAVE_SERVICE_CNOC, 240 SM8350_SLAVE_QDSS_STM, 241 SM8350_SLAVE_TCU 242 }, 243 }; 244 245 static struct qcom_icc_node qnm_gemnoc_pcie = { 246 .name = "qnm_gemnoc_pcie", 247 .id = SM8350_MASTER_GEM_NOC_PCIE_SNOC, 248 .channels = 1, 249 .buswidth = 8, 250 .num_links = 2, 251 .links = { SM8350_SLAVE_PCIE_0, 252 SM8350_SLAVE_PCIE_1 253 }, 254 }; 255 256 static struct qcom_icc_node xm_qdss_dap = { 257 .name = "xm_qdss_dap", 258 .id = SM8350_MASTER_QDSS_DAP, 259 .channels = 1, 260 .buswidth = 8, 261 .num_links = 56, 262 .links = { SM8350_SLAVE_AHB2PHY_SOUTH, 263 SM8350_SLAVE_AHB2PHY_NORTH, 264 SM8350_SLAVE_AOSS, 265 SM8350_SLAVE_APPSS, 266 SM8350_SLAVE_CAMERA_CFG, 267 SM8350_SLAVE_CLK_CTL, 268 SM8350_SLAVE_CDSP_CFG, 269 SM8350_SLAVE_RBCPR_CX_CFG, 270 SM8350_SLAVE_RBCPR_MMCX_CFG, 271 SM8350_SLAVE_RBCPR_MX_CFG, 272 SM8350_SLAVE_CRYPTO_0_CFG, 273 SM8350_SLAVE_CX_RDPM, 274 SM8350_SLAVE_DCC_CFG, 275 SM8350_SLAVE_DISPLAY_CFG, 276 SM8350_SLAVE_GFX3D_CFG, 277 SM8350_SLAVE_HWKM, 278 SM8350_SLAVE_IMEM_CFG, 279 SM8350_SLAVE_IPA_CFG, 280 SM8350_SLAVE_IPC_ROUTER_CFG, 281 SM8350_SLAVE_LPASS, 282 SM8350_SLAVE_CNOC_MSS, 283 SM8350_SLAVE_MX_RDPM, 284 SM8350_SLAVE_PCIE_0_CFG, 285 SM8350_SLAVE_PCIE_1_CFG, 286 SM8350_SLAVE_PDM, 287 SM8350_SLAVE_PIMEM_CFG, 288 SM8350_SLAVE_PKA_WRAPPER_CFG, 289 SM8350_SLAVE_PMU_WRAPPER_CFG, 290 SM8350_SLAVE_QDSS_CFG, 291 SM8350_SLAVE_QSPI_0, 292 SM8350_SLAVE_QUP_0, 293 SM8350_SLAVE_QUP_1, 294 SM8350_SLAVE_QUP_2, 295 SM8350_SLAVE_SDCC_2, 296 SM8350_SLAVE_SDCC_4, 297 SM8350_SLAVE_SECURITY, 298 SM8350_SLAVE_SPSS_CFG, 299 SM8350_SLAVE_TCSR, 300 SM8350_SLAVE_TLMM, 301 SM8350_SLAVE_UFS_CARD_CFG, 302 SM8350_SLAVE_UFS_MEM_CFG, 303 SM8350_SLAVE_USB3_0, 304 SM8350_SLAVE_USB3_1, 305 SM8350_SLAVE_VENUS_CFG, 306 SM8350_SLAVE_VSENSE_CTRL_CFG, 307 SM8350_SLAVE_A1NOC_CFG, 308 SM8350_SLAVE_A2NOC_CFG, 309 SM8350_SLAVE_DDRSS_CFG, 310 SM8350_SLAVE_CNOC_MNOC_CFG, 311 SM8350_SLAVE_SNOC_CFG, 312 SM8350_SLAVE_BOOT_IMEM, 313 SM8350_SLAVE_IMEM, 314 SM8350_SLAVE_PIMEM, 315 SM8350_SLAVE_SERVICE_CNOC, 316 SM8350_SLAVE_QDSS_STM, 317 SM8350_SLAVE_TCU 318 }, 319 }; 320 321 static struct qcom_icc_node qnm_cnoc_dc_noc = { 322 .name = "qnm_cnoc_dc_noc", 323 .id = SM8350_MASTER_CNOC_DC_NOC, 324 .channels = 1, 325 .buswidth = 4, 326 .num_links = 2, 327 .links = { SM8350_SLAVE_LLCC_CFG, 328 SM8350_SLAVE_GEM_NOC_CFG 329 }, 330 }; 331 332 static struct qcom_icc_node alm_gpu_tcu = { 333 .name = "alm_gpu_tcu", 334 .id = SM8350_MASTER_GPU_TCU, 335 .channels = 1, 336 .buswidth = 8, 337 .num_links = 2, 338 .links = { SM8350_SLAVE_GEM_NOC_CNOC, 339 SM8350_SLAVE_LLCC 340 }, 341 }; 342 343 static struct qcom_icc_node alm_sys_tcu = { 344 .name = "alm_sys_tcu", 345 .id = SM8350_MASTER_SYS_TCU, 346 .channels = 1, 347 .buswidth = 8, 348 .num_links = 2, 349 .links = { SM8350_SLAVE_GEM_NOC_CNOC, 350 SM8350_SLAVE_LLCC 351 }, 352 }; 353 354 static struct qcom_icc_node chm_apps = { 355 .name = "chm_apps", 356 .id = SM8350_MASTER_APPSS_PROC, 357 .channels = 2, 358 .buswidth = 32, 359 .num_links = 3, 360 .links = { SM8350_SLAVE_GEM_NOC_CNOC, 361 SM8350_SLAVE_LLCC, 362 SM8350_SLAVE_MEM_NOC_PCIE_SNOC 363 }, 364 }; 365 366 static struct qcom_icc_node qnm_cmpnoc = { 367 .name = "qnm_cmpnoc", 368 .id = SM8350_MASTER_COMPUTE_NOC, 369 .channels = 2, 370 .buswidth = 32, 371 .num_links = 2, 372 .links = { SM8350_SLAVE_GEM_NOC_CNOC, 373 SM8350_SLAVE_LLCC 374 }, 375 }; 376 377 static struct qcom_icc_node qnm_gemnoc_cfg = { 378 .name = "qnm_gemnoc_cfg", 379 .id = SM8350_MASTER_GEM_NOC_CFG, 380 .channels = 1, 381 .buswidth = 4, 382 .num_links = 5, 383 .links = { SM8350_SLAVE_MSS_PROC_MS_MPU_CFG, 384 SM8350_SLAVE_MCDMA_MS_MPU_CFG, 385 SM8350_SLAVE_SERVICE_GEM_NOC_1, 386 SM8350_SLAVE_SERVICE_GEM_NOC_2, 387 SM8350_SLAVE_SERVICE_GEM_NOC 388 }, 389 }; 390 391 static struct qcom_icc_node qnm_gpu = { 392 .name = "qnm_gpu", 393 .id = SM8350_MASTER_GFX3D, 394 .channels = 2, 395 .buswidth = 32, 396 .num_links = 2, 397 .links = { SM8350_SLAVE_GEM_NOC_CNOC, 398 SM8350_SLAVE_LLCC 399 }, 400 }; 401 402 static struct qcom_icc_node qnm_mnoc_hf = { 403 .name = "qnm_mnoc_hf", 404 .id = SM8350_MASTER_MNOC_HF_MEM_NOC, 405 .channels = 2, 406 .buswidth = 32, 407 .num_links = 1, 408 .links = { SM8350_SLAVE_LLCC }, 409 }; 410 411 static struct qcom_icc_node qnm_mnoc_sf = { 412 .name = "qnm_mnoc_sf", 413 .id = SM8350_MASTER_MNOC_SF_MEM_NOC, 414 .channels = 2, 415 .buswidth = 32, 416 .num_links = 2, 417 .links = { SM8350_SLAVE_GEM_NOC_CNOC, 418 SM8350_SLAVE_LLCC 419 }, 420 }; 421 422 static struct qcom_icc_node qnm_pcie = { 423 .name = "qnm_pcie", 424 .id = SM8350_MASTER_ANOC_PCIE_GEM_NOC, 425 .channels = 1, 426 .buswidth = 16, 427 .num_links = 2, 428 .links = { SM8350_SLAVE_GEM_NOC_CNOC, 429 SM8350_SLAVE_LLCC 430 }, 431 }; 432 433 static struct qcom_icc_node qnm_snoc_gc = { 434 .name = "qnm_snoc_gc", 435 .id = SM8350_MASTER_SNOC_GC_MEM_NOC, 436 .channels = 1, 437 .buswidth = 8, 438 .num_links = 1, 439 .links = { SM8350_SLAVE_LLCC }, 440 }; 441 442 static struct qcom_icc_node qnm_snoc_sf = { 443 .name = "qnm_snoc_sf", 444 .id = SM8350_MASTER_SNOC_SF_MEM_NOC, 445 .channels = 1, 446 .buswidth = 16, 447 .num_links = 3, 448 .links = { SM8350_SLAVE_GEM_NOC_CNOC, 449 SM8350_SLAVE_LLCC, 450 SM8350_SLAVE_MEM_NOC_PCIE_SNOC 451 }, 452 }; 453 454 static struct qcom_icc_node qhm_config_noc = { 455 .name = "qhm_config_noc", 456 .id = SM8350_MASTER_CNOC_LPASS_AG_NOC, 457 .channels = 1, 458 .buswidth = 4, 459 .num_links = 6, 460 .links = { SM8350_SLAVE_LPASS_CORE_CFG, 461 SM8350_SLAVE_LPASS_LPI_CFG, 462 SM8350_SLAVE_LPASS_MPU_CFG, 463 SM8350_SLAVE_LPASS_TOP_CFG, 464 SM8350_SLAVE_SERVICES_LPASS_AML_NOC, 465 SM8350_SLAVE_SERVICE_LPASS_AG_NOC 466 }, 467 }; 468 469 static struct qcom_icc_node llcc_mc = { 470 .name = "llcc_mc", 471 .id = SM8350_MASTER_LLCC, 472 .channels = 4, 473 .buswidth = 4, 474 .num_links = 1, 475 .links = { SM8350_SLAVE_EBI1 }, 476 }; 477 478 static struct qcom_icc_node qnm_camnoc_hf = { 479 .name = "qnm_camnoc_hf", 480 .id = SM8350_MASTER_CAMNOC_HF, 481 .channels = 2, 482 .buswidth = 32, 483 .num_links = 1, 484 .links = { SM8350_SLAVE_MNOC_HF_MEM_NOC }, 485 }; 486 487 static struct qcom_icc_node qnm_camnoc_icp = { 488 .name = "qnm_camnoc_icp", 489 .id = SM8350_MASTER_CAMNOC_ICP, 490 .channels = 1, 491 .buswidth = 8, 492 .num_links = 1, 493 .links = { SM8350_SLAVE_MNOC_SF_MEM_NOC }, 494 }; 495 496 static struct qcom_icc_node qnm_camnoc_sf = { 497 .name = "qnm_camnoc_sf", 498 .id = SM8350_MASTER_CAMNOC_SF, 499 .channels = 2, 500 .buswidth = 32, 501 .num_links = 1, 502 .links = { SM8350_SLAVE_MNOC_SF_MEM_NOC }, 503 }; 504 505 static struct qcom_icc_node qnm_mnoc_cfg = { 506 .name = "qnm_mnoc_cfg", 507 .id = SM8350_MASTER_CNOC_MNOC_CFG, 508 .channels = 1, 509 .buswidth = 4, 510 .num_links = 1, 511 .links = { SM8350_SLAVE_SERVICE_MNOC }, 512 }; 513 514 static struct qcom_icc_node qnm_video0 = { 515 .name = "qnm_video0", 516 .id = SM8350_MASTER_VIDEO_P0, 517 .channels = 1, 518 .buswidth = 32, 519 .num_links = 1, 520 .links = { SM8350_SLAVE_MNOC_SF_MEM_NOC }, 521 }; 522 523 static struct qcom_icc_node qnm_video1 = { 524 .name = "qnm_video1", 525 .id = SM8350_MASTER_VIDEO_P1, 526 .channels = 1, 527 .buswidth = 32, 528 .num_links = 1, 529 .links = { SM8350_SLAVE_MNOC_SF_MEM_NOC }, 530 }; 531 532 static struct qcom_icc_node qnm_video_cvp = { 533 .name = "qnm_video_cvp", 534 .id = SM8350_MASTER_VIDEO_PROC, 535 .channels = 1, 536 .buswidth = 32, 537 .num_links = 1, 538 .links = { SM8350_SLAVE_MNOC_SF_MEM_NOC }, 539 }; 540 541 static struct qcom_icc_node qxm_mdp0 = { 542 .name = "qxm_mdp0", 543 .id = SM8350_MASTER_MDP0, 544 .channels = 1, 545 .buswidth = 32, 546 .num_links = 1, 547 .links = { SM8350_SLAVE_MNOC_HF_MEM_NOC }, 548 }; 549 550 static struct qcom_icc_node qxm_mdp1 = { 551 .name = "qxm_mdp1", 552 .id = SM8350_MASTER_MDP1, 553 .channels = 1, 554 .buswidth = 32, 555 .num_links = 1, 556 .links = { SM8350_SLAVE_MNOC_HF_MEM_NOC }, 557 }; 558 559 static struct qcom_icc_node qxm_rot = { 560 .name = "qxm_rot", 561 .id = SM8350_MASTER_ROTATOR, 562 .channels = 1, 563 .buswidth = 32, 564 .num_links = 1, 565 .links = { SM8350_SLAVE_MNOC_SF_MEM_NOC }, 566 }; 567 568 static struct qcom_icc_node qhm_nsp_noc_config = { 569 .name = "qhm_nsp_noc_config", 570 .id = SM8350_MASTER_CDSP_NOC_CFG, 571 .channels = 1, 572 .buswidth = 4, 573 .num_links = 1, 574 .links = { SM8350_SLAVE_SERVICE_NSP_NOC }, 575 }; 576 577 static struct qcom_icc_node qxm_nsp = { 578 .name = "qxm_nsp", 579 .id = SM8350_MASTER_CDSP_PROC, 580 .channels = 2, 581 .buswidth = 32, 582 .num_links = 1, 583 .links = { SM8350_SLAVE_CDSP_MEM_NOC }, 584 }; 585 586 static struct qcom_icc_node qnm_aggre1_noc = { 587 .name = "qnm_aggre1_noc", 588 .id = SM8350_MASTER_A1NOC_SNOC, 589 .channels = 1, 590 .buswidth = 16, 591 .num_links = 1, 592 .links = { SM8350_SLAVE_SNOC_GEM_NOC_SF }, 593 }; 594 595 static struct qcom_icc_node qnm_aggre2_noc = { 596 .name = "qnm_aggre2_noc", 597 .id = SM8350_MASTER_A2NOC_SNOC, 598 .channels = 1, 599 .buswidth = 16, 600 .num_links = 1, 601 .links = { SM8350_SLAVE_SNOC_GEM_NOC_SF }, 602 }; 603 604 static struct qcom_icc_node qnm_snoc_cfg = { 605 .name = "qnm_snoc_cfg", 606 .id = SM8350_MASTER_SNOC_CFG, 607 .channels = 1, 608 .buswidth = 4, 609 .num_links = 1, 610 .links = { SM8350_SLAVE_SERVICE_SNOC }, 611 }; 612 613 static struct qcom_icc_node qxm_pimem = { 614 .name = "qxm_pimem", 615 .id = SM8350_MASTER_PIMEM, 616 .channels = 1, 617 .buswidth = 8, 618 .num_links = 1, 619 .links = { SM8350_SLAVE_SNOC_GEM_NOC_GC }, 620 }; 621 622 static struct qcom_icc_node xm_gic = { 623 .name = "xm_gic", 624 .id = SM8350_MASTER_GIC, 625 .channels = 1, 626 .buswidth = 8, 627 .num_links = 1, 628 .links = { SM8350_SLAVE_SNOC_GEM_NOC_GC }, 629 }; 630 631 static struct qcom_icc_node qns_a1noc_snoc = { 632 .name = "qns_a1noc_snoc", 633 .id = SM8350_SLAVE_A1NOC_SNOC, 634 .channels = 1, 635 .buswidth = 16, 636 .num_links = 1, 637 .links = { SM8350_MASTER_A1NOC_SNOC }, 638 }; 639 640 static struct qcom_icc_node srvc_aggre1_noc = { 641 .name = "srvc_aggre1_noc", 642 .id = SM8350_SLAVE_SERVICE_A1NOC, 643 .channels = 1, 644 .buswidth = 4, 645 }; 646 647 static struct qcom_icc_node qns_a2noc_snoc = { 648 .name = "qns_a2noc_snoc", 649 .id = SM8350_SLAVE_A2NOC_SNOC, 650 .channels = 1, 651 .buswidth = 16, 652 .num_links = 1, 653 .links = { SM8350_MASTER_A2NOC_SNOC }, 654 }; 655 656 static struct qcom_icc_node qns_pcie_mem_noc = { 657 .name = "qns_pcie_mem_noc", 658 .id = SM8350_SLAVE_ANOC_PCIE_GEM_NOC, 659 .channels = 1, 660 .buswidth = 16, 661 .num_links = 1, 662 .links = { SM8350_MASTER_ANOC_PCIE_GEM_NOC }, 663 }; 664 665 static struct qcom_icc_node srvc_aggre2_noc = { 666 .name = "srvc_aggre2_noc", 667 .id = SM8350_SLAVE_SERVICE_A2NOC, 668 .channels = 1, 669 .buswidth = 4, 670 }; 671 672 static struct qcom_icc_node qhs_ahb2phy0 = { 673 .name = "qhs_ahb2phy0", 674 .id = SM8350_SLAVE_AHB2PHY_SOUTH, 675 .channels = 1, 676 .buswidth = 4, 677 }; 678 679 static struct qcom_icc_node qhs_ahb2phy1 = { 680 .name = "qhs_ahb2phy1", 681 .id = SM8350_SLAVE_AHB2PHY_NORTH, 682 .channels = 1, 683 .buswidth = 4, 684 }; 685 686 static struct qcom_icc_node qhs_aoss = { 687 .name = "qhs_aoss", 688 .id = SM8350_SLAVE_AOSS, 689 .channels = 1, 690 .buswidth = 4, 691 }; 692 693 static struct qcom_icc_node qhs_apss = { 694 .name = "qhs_apss", 695 .id = SM8350_SLAVE_APPSS, 696 .channels = 1, 697 .buswidth = 8, 698 }; 699 700 static struct qcom_icc_node qhs_camera_cfg = { 701 .name = "qhs_camera_cfg", 702 .id = SM8350_SLAVE_CAMERA_CFG, 703 .channels = 1, 704 .buswidth = 4, 705 }; 706 707 static struct qcom_icc_node qhs_clk_ctl = { 708 .name = "qhs_clk_ctl", 709 .id = SM8350_SLAVE_CLK_CTL, 710 .channels = 1, 711 .buswidth = 4, 712 }; 713 714 static struct qcom_icc_node qhs_compute_cfg = { 715 .name = "qhs_compute_cfg", 716 .id = SM8350_SLAVE_CDSP_CFG, 717 .channels = 1, 718 .buswidth = 4, 719 }; 720 721 static struct qcom_icc_node qhs_cpr_cx = { 722 .name = "qhs_cpr_cx", 723 .id = SM8350_SLAVE_RBCPR_CX_CFG, 724 .channels = 1, 725 .buswidth = 4, 726 }; 727 728 static struct qcom_icc_node qhs_cpr_mmcx = { 729 .name = "qhs_cpr_mmcx", 730 .id = SM8350_SLAVE_RBCPR_MMCX_CFG, 731 .channels = 1, 732 .buswidth = 4, 733 }; 734 735 static struct qcom_icc_node qhs_cpr_mx = { 736 .name = "qhs_cpr_mx", 737 .id = SM8350_SLAVE_RBCPR_MX_CFG, 738 .channels = 1, 739 .buswidth = 4, 740 }; 741 742 static struct qcom_icc_node qhs_crypto0_cfg = { 743 .name = "qhs_crypto0_cfg", 744 .id = SM8350_SLAVE_CRYPTO_0_CFG, 745 .channels = 1, 746 .buswidth = 4, 747 }; 748 749 static struct qcom_icc_node qhs_cx_rdpm = { 750 .name = "qhs_cx_rdpm", 751 .id = SM8350_SLAVE_CX_RDPM, 752 .channels = 1, 753 .buswidth = 4, 754 }; 755 756 static struct qcom_icc_node qhs_dcc_cfg = { 757 .name = "qhs_dcc_cfg", 758 .id = SM8350_SLAVE_DCC_CFG, 759 .channels = 1, 760 .buswidth = 4, 761 }; 762 763 static struct qcom_icc_node qhs_display_cfg = { 764 .name = "qhs_display_cfg", 765 .id = SM8350_SLAVE_DISPLAY_CFG, 766 .channels = 1, 767 .buswidth = 4, 768 }; 769 770 static struct qcom_icc_node qhs_gpuss_cfg = { 771 .name = "qhs_gpuss_cfg", 772 .id = SM8350_SLAVE_GFX3D_CFG, 773 .channels = 1, 774 .buswidth = 8, 775 }; 776 777 static struct qcom_icc_node qhs_hwkm = { 778 .name = "qhs_hwkm", 779 .id = SM8350_SLAVE_HWKM, 780 .channels = 1, 781 .buswidth = 4, 782 }; 783 784 static struct qcom_icc_node qhs_imem_cfg = { 785 .name = "qhs_imem_cfg", 786 .id = SM8350_SLAVE_IMEM_CFG, 787 .channels = 1, 788 .buswidth = 4, 789 }; 790 791 static struct qcom_icc_node qhs_ipa = { 792 .name = "qhs_ipa", 793 .id = SM8350_SLAVE_IPA_CFG, 794 .channels = 1, 795 .buswidth = 4, 796 }; 797 798 static struct qcom_icc_node qhs_ipc_router = { 799 .name = "qhs_ipc_router", 800 .id = SM8350_SLAVE_IPC_ROUTER_CFG, 801 .channels = 1, 802 .buswidth = 4, 803 }; 804 805 static struct qcom_icc_node qhs_lpass_cfg = { 806 .name = "qhs_lpass_cfg", 807 .id = SM8350_SLAVE_LPASS, 808 .channels = 1, 809 .buswidth = 4, 810 .num_links = 1, 811 .links = { SM8350_MASTER_CNOC_LPASS_AG_NOC }, 812 }; 813 814 static struct qcom_icc_node qhs_mss_cfg = { 815 .name = "qhs_mss_cfg", 816 .id = SM8350_SLAVE_CNOC_MSS, 817 .channels = 1, 818 .buswidth = 4, 819 }; 820 821 static struct qcom_icc_node qhs_mx_rdpm = { 822 .name = "qhs_mx_rdpm", 823 .id = SM8350_SLAVE_MX_RDPM, 824 .channels = 1, 825 .buswidth = 4, 826 }; 827 828 static struct qcom_icc_node qhs_pcie0_cfg = { 829 .name = "qhs_pcie0_cfg", 830 .id = SM8350_SLAVE_PCIE_0_CFG, 831 .channels = 1, 832 .buswidth = 4, 833 }; 834 835 static struct qcom_icc_node qhs_pcie1_cfg = { 836 .name = "qhs_pcie1_cfg", 837 .id = SM8350_SLAVE_PCIE_1_CFG, 838 .channels = 1, 839 .buswidth = 4, 840 }; 841 842 static struct qcom_icc_node qhs_pdm = { 843 .name = "qhs_pdm", 844 .id = SM8350_SLAVE_PDM, 845 .channels = 1, 846 .buswidth = 4, 847 }; 848 849 static struct qcom_icc_node qhs_pimem_cfg = { 850 .name = "qhs_pimem_cfg", 851 .id = SM8350_SLAVE_PIMEM_CFG, 852 .channels = 1, 853 .buswidth = 4, 854 }; 855 856 static struct qcom_icc_node qhs_pka_wrapper_cfg = { 857 .name = "qhs_pka_wrapper_cfg", 858 .id = SM8350_SLAVE_PKA_WRAPPER_CFG, 859 .channels = 1, 860 .buswidth = 4, 861 }; 862 863 static struct qcom_icc_node qhs_pmu_wrapper_cfg = { 864 .name = "qhs_pmu_wrapper_cfg", 865 .id = SM8350_SLAVE_PMU_WRAPPER_CFG, 866 .channels = 1, 867 .buswidth = 4, 868 }; 869 870 static struct qcom_icc_node qhs_qdss_cfg = { 871 .name = "qhs_qdss_cfg", 872 .id = SM8350_SLAVE_QDSS_CFG, 873 .channels = 1, 874 .buswidth = 4, 875 }; 876 877 static struct qcom_icc_node qhs_qspi = { 878 .name = "qhs_qspi", 879 .id = SM8350_SLAVE_QSPI_0, 880 .channels = 1, 881 .buswidth = 4, 882 }; 883 884 static struct qcom_icc_node qhs_qup0 = { 885 .name = "qhs_qup0", 886 .id = SM8350_SLAVE_QUP_0, 887 .channels = 1, 888 .buswidth = 4, 889 }; 890 891 static struct qcom_icc_node qhs_qup1 = { 892 .name = "qhs_qup1", 893 .id = SM8350_SLAVE_QUP_1, 894 .channels = 1, 895 .buswidth = 4, 896 }; 897 898 static struct qcom_icc_node qhs_qup2 = { 899 .name = "qhs_qup2", 900 .id = SM8350_SLAVE_QUP_2, 901 .channels = 1, 902 .buswidth = 4, 903 }; 904 905 static struct qcom_icc_node qhs_sdc2 = { 906 .name = "qhs_sdc2", 907 .id = SM8350_SLAVE_SDCC_2, 908 .channels = 1, 909 .buswidth = 4, 910 }; 911 912 static struct qcom_icc_node qhs_sdc4 = { 913 .name = "qhs_sdc4", 914 .id = SM8350_SLAVE_SDCC_4, 915 .channels = 1, 916 .buswidth = 4, 917 }; 918 919 static struct qcom_icc_node qhs_security = { 920 .name = "qhs_security", 921 .id = SM8350_SLAVE_SECURITY, 922 .channels = 1, 923 .buswidth = 4, 924 }; 925 926 static struct qcom_icc_node qhs_spss_cfg = { 927 .name = "qhs_spss_cfg", 928 .id = SM8350_SLAVE_SPSS_CFG, 929 .channels = 1, 930 .buswidth = 4, 931 }; 932 933 static struct qcom_icc_node qhs_tcsr = { 934 .name = "qhs_tcsr", 935 .id = SM8350_SLAVE_TCSR, 936 .channels = 1, 937 .buswidth = 4, 938 }; 939 940 static struct qcom_icc_node qhs_tlmm = { 941 .name = "qhs_tlmm", 942 .id = SM8350_SLAVE_TLMM, 943 .channels = 1, 944 .buswidth = 4, 945 }; 946 947 static struct qcom_icc_node qhs_ufs_card_cfg = { 948 .name = "qhs_ufs_card_cfg", 949 .id = SM8350_SLAVE_UFS_CARD_CFG, 950 .channels = 1, 951 .buswidth = 4, 952 }; 953 954 static struct qcom_icc_node qhs_ufs_mem_cfg = { 955 .name = "qhs_ufs_mem_cfg", 956 .id = SM8350_SLAVE_UFS_MEM_CFG, 957 .channels = 1, 958 .buswidth = 4, 959 }; 960 961 static struct qcom_icc_node qhs_usb3_0 = { 962 .name = "qhs_usb3_0", 963 .id = SM8350_SLAVE_USB3_0, 964 .channels = 1, 965 .buswidth = 4, 966 }; 967 968 static struct qcom_icc_node qhs_usb3_1 = { 969 .name = "qhs_usb3_1", 970 .id = SM8350_SLAVE_USB3_1, 971 .channels = 1, 972 .buswidth = 4, 973 }; 974 975 static struct qcom_icc_node qhs_venus_cfg = { 976 .name = "qhs_venus_cfg", 977 .id = SM8350_SLAVE_VENUS_CFG, 978 .channels = 1, 979 .buswidth = 4, 980 }; 981 982 static struct qcom_icc_node qhs_vsense_ctrl_cfg = { 983 .name = "qhs_vsense_ctrl_cfg", 984 .id = SM8350_SLAVE_VSENSE_CTRL_CFG, 985 .channels = 1, 986 .buswidth = 4, 987 }; 988 989 static struct qcom_icc_node qns_a1_noc_cfg = { 990 .name = "qns_a1_noc_cfg", 991 .id = SM8350_SLAVE_A1NOC_CFG, 992 .channels = 1, 993 .buswidth = 4, 994 }; 995 996 static struct qcom_icc_node qns_a2_noc_cfg = { 997 .name = "qns_a2_noc_cfg", 998 .id = SM8350_SLAVE_A2NOC_CFG, 999 .channels = 1, 1000 .buswidth = 4, 1001 }; 1002 1003 static struct qcom_icc_node qns_ddrss_cfg = { 1004 .name = "qns_ddrss_cfg", 1005 .id = SM8350_SLAVE_DDRSS_CFG, 1006 .channels = 1, 1007 .buswidth = 4, 1008 }; 1009 1010 static struct qcom_icc_node qns_mnoc_cfg = { 1011 .name = "qns_mnoc_cfg", 1012 .id = SM8350_SLAVE_CNOC_MNOC_CFG, 1013 .channels = 1, 1014 .buswidth = 4, 1015 }; 1016 1017 static struct qcom_icc_node qns_snoc_cfg = { 1018 .name = "qns_snoc_cfg", 1019 .id = SM8350_SLAVE_SNOC_CFG, 1020 .channels = 1, 1021 .buswidth = 4, 1022 }; 1023 1024 static struct qcom_icc_node qxs_boot_imem = { 1025 .name = "qxs_boot_imem", 1026 .id = SM8350_SLAVE_BOOT_IMEM, 1027 .channels = 1, 1028 .buswidth = 8, 1029 }; 1030 1031 static struct qcom_icc_node qxs_imem = { 1032 .name = "qxs_imem", 1033 .id = SM8350_SLAVE_IMEM, 1034 .channels = 1, 1035 .buswidth = 8, 1036 }; 1037 1038 static struct qcom_icc_node qxs_pimem = { 1039 .name = "qxs_pimem", 1040 .id = SM8350_SLAVE_PIMEM, 1041 .channels = 1, 1042 .buswidth = 8, 1043 }; 1044 1045 static struct qcom_icc_node srvc_cnoc = { 1046 .name = "srvc_cnoc", 1047 .id = SM8350_SLAVE_SERVICE_CNOC, 1048 .channels = 1, 1049 .buswidth = 4, 1050 }; 1051 1052 static struct qcom_icc_node xs_pcie_0 = { 1053 .name = "xs_pcie_0", 1054 .id = SM8350_SLAVE_PCIE_0, 1055 .channels = 1, 1056 .buswidth = 8, 1057 }; 1058 1059 static struct qcom_icc_node xs_pcie_1 = { 1060 .name = "xs_pcie_1", 1061 .id = SM8350_SLAVE_PCIE_1, 1062 .channels = 1, 1063 .buswidth = 8, 1064 }; 1065 1066 static struct qcom_icc_node xs_qdss_stm = { 1067 .name = "xs_qdss_stm", 1068 .id = SM8350_SLAVE_QDSS_STM, 1069 .channels = 1, 1070 .buswidth = 4, 1071 }; 1072 1073 static struct qcom_icc_node xs_sys_tcu_cfg = { 1074 .name = "xs_sys_tcu_cfg", 1075 .id = SM8350_SLAVE_TCU, 1076 .channels = 1, 1077 .buswidth = 8, 1078 }; 1079 1080 static struct qcom_icc_node qhs_llcc = { 1081 .name = "qhs_llcc", 1082 .id = SM8350_SLAVE_LLCC_CFG, 1083 .channels = 1, 1084 .buswidth = 4, 1085 }; 1086 1087 static struct qcom_icc_node qns_gemnoc = { 1088 .name = "qns_gemnoc", 1089 .id = SM8350_SLAVE_GEM_NOC_CFG, 1090 .channels = 1, 1091 .buswidth = 4, 1092 }; 1093 1094 static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = { 1095 .name = "qhs_mdsp_ms_mpu_cfg", 1096 .id = SM8350_SLAVE_MSS_PROC_MS_MPU_CFG, 1097 .channels = 1, 1098 .buswidth = 4, 1099 }; 1100 1101 static struct qcom_icc_node qhs_modem_ms_mpu_cfg = { 1102 .name = "qhs_modem_ms_mpu_cfg", 1103 .id = SM8350_SLAVE_MCDMA_MS_MPU_CFG, 1104 .channels = 1, 1105 .buswidth = 4, 1106 }; 1107 1108 static struct qcom_icc_node qns_gem_noc_cnoc = { 1109 .name = "qns_gem_noc_cnoc", 1110 .id = SM8350_SLAVE_GEM_NOC_CNOC, 1111 .channels = 1, 1112 .buswidth = 16, 1113 .num_links = 1, 1114 .links = { SM8350_MASTER_GEM_NOC_CNOC }, 1115 }; 1116 1117 static struct qcom_icc_node qns_llcc = { 1118 .name = "qns_llcc", 1119 .id = SM8350_SLAVE_LLCC, 1120 .channels = 4, 1121 .buswidth = 16, 1122 .num_links = 1, 1123 .links = { SM8350_MASTER_LLCC }, 1124 }; 1125 1126 static struct qcom_icc_node qns_pcie = { 1127 .name = "qns_pcie", 1128 .id = SM8350_SLAVE_MEM_NOC_PCIE_SNOC, 1129 .channels = 1, 1130 .buswidth = 8, 1131 }; 1132 1133 static struct qcom_icc_node srvc_even_gemnoc = { 1134 .name = "srvc_even_gemnoc", 1135 .id = SM8350_SLAVE_SERVICE_GEM_NOC_1, 1136 .channels = 1, 1137 .buswidth = 4, 1138 }; 1139 1140 static struct qcom_icc_node srvc_odd_gemnoc = { 1141 .name = "srvc_odd_gemnoc", 1142 .id = SM8350_SLAVE_SERVICE_GEM_NOC_2, 1143 .channels = 1, 1144 .buswidth = 4, 1145 }; 1146 1147 static struct qcom_icc_node srvc_sys_gemnoc = { 1148 .name = "srvc_sys_gemnoc", 1149 .id = SM8350_SLAVE_SERVICE_GEM_NOC, 1150 .channels = 1, 1151 .buswidth = 4, 1152 }; 1153 1154 static struct qcom_icc_node qhs_lpass_core = { 1155 .name = "qhs_lpass_core", 1156 .id = SM8350_SLAVE_LPASS_CORE_CFG, 1157 .channels = 1, 1158 .buswidth = 4, 1159 }; 1160 1161 static struct qcom_icc_node qhs_lpass_lpi = { 1162 .name = "qhs_lpass_lpi", 1163 .id = SM8350_SLAVE_LPASS_LPI_CFG, 1164 .channels = 1, 1165 .buswidth = 4, 1166 }; 1167 1168 static struct qcom_icc_node qhs_lpass_mpu = { 1169 .name = "qhs_lpass_mpu", 1170 .id = SM8350_SLAVE_LPASS_MPU_CFG, 1171 .channels = 1, 1172 .buswidth = 4, 1173 }; 1174 1175 static struct qcom_icc_node qhs_lpass_top = { 1176 .name = "qhs_lpass_top", 1177 .id = SM8350_SLAVE_LPASS_TOP_CFG, 1178 .channels = 1, 1179 .buswidth = 4, 1180 }; 1181 1182 static struct qcom_icc_node srvc_niu_aml_noc = { 1183 .name = "srvc_niu_aml_noc", 1184 .id = SM8350_SLAVE_SERVICES_LPASS_AML_NOC, 1185 .channels = 1, 1186 .buswidth = 4, 1187 }; 1188 1189 static struct qcom_icc_node srvc_niu_lpass_agnoc = { 1190 .name = "srvc_niu_lpass_agnoc", 1191 .id = SM8350_SLAVE_SERVICE_LPASS_AG_NOC, 1192 .channels = 1, 1193 .buswidth = 4, 1194 }; 1195 1196 static struct qcom_icc_node ebi = { 1197 .name = "ebi", 1198 .id = SM8350_SLAVE_EBI1, 1199 .channels = 4, 1200 .buswidth = 4, 1201 }; 1202 1203 static struct qcom_icc_node qns_mem_noc_hf = { 1204 .name = "qns_mem_noc_hf", 1205 .id = SM8350_SLAVE_MNOC_HF_MEM_NOC, 1206 .channels = 2, 1207 .buswidth = 32, 1208 .num_links = 1, 1209 .links = { SM8350_MASTER_MNOC_HF_MEM_NOC }, 1210 }; 1211 1212 static struct qcom_icc_node qns_mem_noc_sf = { 1213 .name = "qns_mem_noc_sf", 1214 .id = SM8350_SLAVE_MNOC_SF_MEM_NOC, 1215 .channels = 2, 1216 .buswidth = 32, 1217 .num_links = 1, 1218 .links = { SM8350_MASTER_MNOC_SF_MEM_NOC }, 1219 }; 1220 1221 static struct qcom_icc_node srvc_mnoc = { 1222 .name = "srvc_mnoc", 1223 .id = SM8350_SLAVE_SERVICE_MNOC, 1224 .channels = 1, 1225 .buswidth = 4, 1226 }; 1227 1228 static struct qcom_icc_node qns_nsp_gemnoc = { 1229 .name = "qns_nsp_gemnoc", 1230 .id = SM8350_SLAVE_CDSP_MEM_NOC, 1231 .channels = 2, 1232 .buswidth = 32, 1233 .num_links = 1, 1234 .links = { SM8350_MASTER_COMPUTE_NOC }, 1235 }; 1236 1237 static struct qcom_icc_node service_nsp_noc = { 1238 .name = "service_nsp_noc", 1239 .id = SM8350_SLAVE_SERVICE_NSP_NOC, 1240 .channels = 1, 1241 .buswidth = 4, 1242 }; 1243 1244 static struct qcom_icc_node qns_gemnoc_gc = { 1245 .name = "qns_gemnoc_gc", 1246 .id = SM8350_SLAVE_SNOC_GEM_NOC_GC, 1247 .channels = 1, 1248 .buswidth = 8, 1249 .num_links = 1, 1250 .links = { SM8350_MASTER_SNOC_GC_MEM_NOC }, 1251 }; 1252 1253 static struct qcom_icc_node qns_gemnoc_sf = { 1254 .name = "qns_gemnoc_sf", 1255 .id = SM8350_SLAVE_SNOC_GEM_NOC_SF, 1256 .channels = 1, 1257 .buswidth = 16, 1258 .num_links = 1, 1259 .links = { SM8350_MASTER_SNOC_SF_MEM_NOC }, 1260 }; 1261 1262 static struct qcom_icc_node srvc_snoc = { 1263 .name = "srvc_snoc", 1264 .id = SM8350_SLAVE_SERVICE_SNOC, 1265 .channels = 1, 1266 .buswidth = 4, 1267 }; 1268 1269 static struct qcom_icc_bcm bcm_acv = { 1270 .name = "ACV", 1271 .enable_mask = BIT(3), 1272 .keepalive = false, 1273 .num_nodes = 1, 1274 .nodes = { &ebi }, 1275 }; 1276 1277 static struct qcom_icc_bcm bcm_ce0 = { 1278 .name = "CE0", 1279 .keepalive = false, 1280 .num_nodes = 1, 1281 .nodes = { &qxm_crypto }, 1282 }; 1283 1284 static struct qcom_icc_bcm bcm_cn0 = { 1285 .name = "CN0", 1286 .keepalive = true, 1287 .num_nodes = 2, 1288 .nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie }, 1289 }; 1290 1291 static struct qcom_icc_bcm bcm_cn1 = { 1292 .name = "CN1", 1293 .keepalive = false, 1294 .num_nodes = 47, 1295 .nodes = { &xm_qdss_dap, 1296 &qhs_ahb2phy0, 1297 &qhs_ahb2phy1, 1298 &qhs_aoss, 1299 &qhs_apss, 1300 &qhs_camera_cfg, 1301 &qhs_clk_ctl, 1302 &qhs_compute_cfg, 1303 &qhs_cpr_cx, 1304 &qhs_cpr_mmcx, 1305 &qhs_cpr_mx, 1306 &qhs_crypto0_cfg, 1307 &qhs_cx_rdpm, 1308 &qhs_dcc_cfg, 1309 &qhs_display_cfg, 1310 &qhs_gpuss_cfg, 1311 &qhs_hwkm, 1312 &qhs_imem_cfg, 1313 &qhs_ipa, 1314 &qhs_ipc_router, 1315 &qhs_mss_cfg, 1316 &qhs_mx_rdpm, 1317 &qhs_pcie0_cfg, 1318 &qhs_pcie1_cfg, 1319 &qhs_pimem_cfg, 1320 &qhs_pka_wrapper_cfg, 1321 &qhs_pmu_wrapper_cfg, 1322 &qhs_qdss_cfg, 1323 &qhs_qup0, 1324 &qhs_qup1, 1325 &qhs_qup2, 1326 &qhs_security, 1327 &qhs_spss_cfg, 1328 &qhs_tcsr, 1329 &qhs_tlmm, 1330 &qhs_ufs_card_cfg, 1331 &qhs_ufs_mem_cfg, 1332 &qhs_usb3_0, 1333 &qhs_usb3_1, 1334 &qhs_venus_cfg, 1335 &qhs_vsense_ctrl_cfg, 1336 &qns_a1_noc_cfg, 1337 &qns_a2_noc_cfg, 1338 &qns_ddrss_cfg, 1339 &qns_mnoc_cfg, 1340 &qns_snoc_cfg, 1341 &srvc_cnoc 1342 }, 1343 }; 1344 1345 static struct qcom_icc_bcm bcm_cn2 = { 1346 .name = "CN2", 1347 .keepalive = false, 1348 .num_nodes = 5, 1349 .nodes = { &qhs_lpass_cfg, &qhs_pdm, &qhs_qspi, &qhs_sdc2, &qhs_sdc4 }, 1350 }; 1351 1352 static struct qcom_icc_bcm bcm_co0 = { 1353 .name = "CO0", 1354 .keepalive = false, 1355 .num_nodes = 1, 1356 .nodes = { &qns_nsp_gemnoc }, 1357 }; 1358 1359 static struct qcom_icc_bcm bcm_co3 = { 1360 .name = "CO3", 1361 .keepalive = false, 1362 .num_nodes = 1, 1363 .nodes = { &qxm_nsp }, 1364 }; 1365 1366 static struct qcom_icc_bcm bcm_mc0 = { 1367 .name = "MC0", 1368 .keepalive = true, 1369 .num_nodes = 1, 1370 .nodes = { &ebi }, 1371 }; 1372 1373 static struct qcom_icc_bcm bcm_mm0 = { 1374 .name = "MM0", 1375 .keepalive = true, 1376 .num_nodes = 1, 1377 .nodes = { &qns_mem_noc_hf }, 1378 }; 1379 1380 static struct qcom_icc_bcm bcm_mm1 = { 1381 .name = "MM1", 1382 .keepalive = false, 1383 .num_nodes = 3, 1384 .nodes = { &qnm_camnoc_hf, &qxm_mdp0, &qxm_mdp1 }, 1385 }; 1386 1387 static struct qcom_icc_bcm bcm_mm4 = { 1388 .name = "MM4", 1389 .keepalive = false, 1390 .num_nodes = 1, 1391 .nodes = { &qns_mem_noc_sf }, 1392 }; 1393 1394 static struct qcom_icc_bcm bcm_mm5 = { 1395 .name = "MM5", 1396 .keepalive = false, 1397 .num_nodes = 6, 1398 .nodes = { &qnm_camnoc_icp, 1399 &qnm_camnoc_sf, 1400 &qnm_video0, 1401 &qnm_video1, 1402 &qnm_video_cvp, 1403 &qxm_rot 1404 }, 1405 }; 1406 1407 static struct qcom_icc_bcm bcm_sh0 = { 1408 .name = "SH0", 1409 .keepalive = true, 1410 .num_nodes = 1, 1411 .nodes = { &qns_llcc }, 1412 }; 1413 1414 static struct qcom_icc_bcm bcm_sh2 = { 1415 .name = "SH2", 1416 .keepalive = false, 1417 .num_nodes = 2, 1418 .nodes = { &alm_gpu_tcu, &alm_sys_tcu }, 1419 }; 1420 1421 static struct qcom_icc_bcm bcm_sh3 = { 1422 .name = "SH3", 1423 .keepalive = false, 1424 .num_nodes = 1, 1425 .nodes = { &qnm_cmpnoc }, 1426 }; 1427 1428 static struct qcom_icc_bcm bcm_sh4 = { 1429 .name = "SH4", 1430 .keepalive = false, 1431 .num_nodes = 1, 1432 .nodes = { &chm_apps }, 1433 }; 1434 1435 static struct qcom_icc_bcm bcm_sn0 = { 1436 .name = "SN0", 1437 .keepalive = true, 1438 .num_nodes = 1, 1439 .nodes = { &qns_gemnoc_sf }, 1440 }; 1441 1442 static struct qcom_icc_bcm bcm_sn2 = { 1443 .name = "SN2", 1444 .keepalive = false, 1445 .num_nodes = 1, 1446 .nodes = { &qns_gemnoc_gc }, 1447 }; 1448 1449 static struct qcom_icc_bcm bcm_sn3 = { 1450 .name = "SN3", 1451 .keepalive = false, 1452 .num_nodes = 1, 1453 .nodes = { &qxs_pimem }, 1454 }; 1455 1456 static struct qcom_icc_bcm bcm_sn4 = { 1457 .name = "SN4", 1458 .keepalive = false, 1459 .num_nodes = 1, 1460 .nodes = { &xs_qdss_stm }, 1461 }; 1462 1463 static struct qcom_icc_bcm bcm_sn5 = { 1464 .name = "SN5", 1465 .keepalive = false, 1466 .num_nodes = 1, 1467 .nodes = { &xm_pcie3_0 }, 1468 }; 1469 1470 static struct qcom_icc_bcm bcm_sn6 = { 1471 .name = "SN6", 1472 .keepalive = false, 1473 .num_nodes = 1, 1474 .nodes = { &xm_pcie3_1 }, 1475 }; 1476 1477 static struct qcom_icc_bcm bcm_sn7 = { 1478 .name = "SN7", 1479 .keepalive = false, 1480 .num_nodes = 1, 1481 .nodes = { &qnm_aggre1_noc }, 1482 }; 1483 1484 static struct qcom_icc_bcm bcm_sn8 = { 1485 .name = "SN8", 1486 .keepalive = false, 1487 .num_nodes = 1, 1488 .nodes = { &qnm_aggre2_noc }, 1489 }; 1490 1491 static struct qcom_icc_bcm bcm_sn14 = { 1492 .name = "SN14", 1493 .keepalive = false, 1494 .num_nodes = 1, 1495 .nodes = { &qns_pcie_mem_noc }, 1496 }; 1497 1498 static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { 1499 }; 1500 1501 static struct qcom_icc_node * const aggre1_noc_nodes[] = { 1502 [MASTER_QSPI_0] = &qhm_qspi, 1503 [MASTER_QUP_1] = &qhm_qup1, 1504 [MASTER_A1NOC_CFG] = &qnm_a1noc_cfg, 1505 [MASTER_SDCC_4] = &xm_sdc4, 1506 [MASTER_UFS_MEM] = &xm_ufs_mem, 1507 [MASTER_USB3_0] = &xm_usb3_0, 1508 [MASTER_USB3_1] = &xm_usb3_1, 1509 [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc, 1510 [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc, 1511 }; 1512 1513 static const struct qcom_icc_desc sm8350_aggre1_noc = { 1514 .nodes = aggre1_noc_nodes, 1515 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), 1516 .bcms = aggre1_noc_bcms, 1517 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), 1518 }; 1519 1520 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { 1521 &bcm_ce0, 1522 &bcm_sn5, 1523 &bcm_sn6, 1524 &bcm_sn14, 1525 }; 1526 1527 static struct qcom_icc_node * const aggre2_noc_nodes[] = { 1528 [MASTER_QDSS_BAM] = &qhm_qdss_bam, 1529 [MASTER_QUP_0] = &qhm_qup0, 1530 [MASTER_QUP_2] = &qhm_qup2, 1531 [MASTER_A2NOC_CFG] = &qnm_a2noc_cfg, 1532 [MASTER_CRYPTO] = &qxm_crypto, 1533 [MASTER_IPA] = &qxm_ipa, 1534 [MASTER_PCIE_0] = &xm_pcie3_0, 1535 [MASTER_PCIE_1] = &xm_pcie3_1, 1536 [MASTER_QDSS_ETR] = &xm_qdss_etr, 1537 [MASTER_SDCC_2] = &xm_sdc2, 1538 [MASTER_UFS_CARD] = &xm_ufs_card, 1539 [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc, 1540 [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc, 1541 [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc, 1542 }; 1543 1544 static const struct qcom_icc_desc sm8350_aggre2_noc = { 1545 .nodes = aggre2_noc_nodes, 1546 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), 1547 .bcms = aggre2_noc_bcms, 1548 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), 1549 }; 1550 1551 static struct qcom_icc_bcm * const config_noc_bcms[] = { 1552 &bcm_cn0, 1553 &bcm_cn1, 1554 &bcm_cn2, 1555 &bcm_sn3, 1556 &bcm_sn4, 1557 }; 1558 1559 static struct qcom_icc_node * const config_noc_nodes[] = { 1560 [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc, 1561 [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie, 1562 [MASTER_QDSS_DAP] = &xm_qdss_dap, 1563 [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0, 1564 [SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1, 1565 [SLAVE_AOSS] = &qhs_aoss, 1566 [SLAVE_APPSS] = &qhs_apss, 1567 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, 1568 [SLAVE_CLK_CTL] = &qhs_clk_ctl, 1569 [SLAVE_CDSP_CFG] = &qhs_compute_cfg, 1570 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx, 1571 [SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx, 1572 [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx, 1573 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, 1574 [SLAVE_CX_RDPM] = &qhs_cx_rdpm, 1575 [SLAVE_DCC_CFG] = &qhs_dcc_cfg, 1576 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg, 1577 [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg, 1578 [SLAVE_HWKM] = &qhs_hwkm, 1579 [SLAVE_IMEM_CFG] = &qhs_imem_cfg, 1580 [SLAVE_IPA_CFG] = &qhs_ipa, 1581 [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router, 1582 [SLAVE_LPASS] = &qhs_lpass_cfg, 1583 [SLAVE_CNOC_MSS] = &qhs_mss_cfg, 1584 [SLAVE_MX_RDPM] = &qhs_mx_rdpm, 1585 [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg, 1586 [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg, 1587 [SLAVE_PDM] = &qhs_pdm, 1588 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg, 1589 [SLAVE_PKA_WRAPPER_CFG] = &qhs_pka_wrapper_cfg, 1590 [SLAVE_PMU_WRAPPER_CFG] = &qhs_pmu_wrapper_cfg, 1591 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, 1592 [SLAVE_QSPI_0] = &qhs_qspi, 1593 [SLAVE_QUP_0] = &qhs_qup0, 1594 [SLAVE_QUP_1] = &qhs_qup1, 1595 [SLAVE_QUP_2] = &qhs_qup2, 1596 [SLAVE_SDCC_2] = &qhs_sdc2, 1597 [SLAVE_SDCC_4] = &qhs_sdc4, 1598 [SLAVE_SECURITY] = &qhs_security, 1599 [SLAVE_SPSS_CFG] = &qhs_spss_cfg, 1600 [SLAVE_TCSR] = &qhs_tcsr, 1601 [SLAVE_TLMM] = &qhs_tlmm, 1602 [SLAVE_UFS_CARD_CFG] = &qhs_ufs_card_cfg, 1603 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, 1604 [SLAVE_USB3_0] = &qhs_usb3_0, 1605 [SLAVE_USB3_1] = &qhs_usb3_1, 1606 [SLAVE_VENUS_CFG] = &qhs_venus_cfg, 1607 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, 1608 [SLAVE_A1NOC_CFG] = &qns_a1_noc_cfg, 1609 [SLAVE_A2NOC_CFG] = &qns_a2_noc_cfg, 1610 [SLAVE_DDRSS_CFG] = &qns_ddrss_cfg, 1611 [SLAVE_CNOC_MNOC_CFG] = &qns_mnoc_cfg, 1612 [SLAVE_SNOC_CFG] = &qns_snoc_cfg, 1613 [SLAVE_BOOT_IMEM] = &qxs_boot_imem, 1614 [SLAVE_IMEM] = &qxs_imem, 1615 [SLAVE_PIMEM] = &qxs_pimem, 1616 [SLAVE_SERVICE_CNOC] = &srvc_cnoc, 1617 [SLAVE_PCIE_0] = &xs_pcie_0, 1618 [SLAVE_PCIE_1] = &xs_pcie_1, 1619 [SLAVE_QDSS_STM] = &xs_qdss_stm, 1620 [SLAVE_TCU] = &xs_sys_tcu_cfg, 1621 }; 1622 1623 static const struct qcom_icc_desc sm8350_config_noc = { 1624 .nodes = config_noc_nodes, 1625 .num_nodes = ARRAY_SIZE(config_noc_nodes), 1626 .bcms = config_noc_bcms, 1627 .num_bcms = ARRAY_SIZE(config_noc_bcms), 1628 }; 1629 1630 static struct qcom_icc_bcm * const dc_noc_bcms[] = { 1631 }; 1632 1633 static struct qcom_icc_node * const dc_noc_nodes[] = { 1634 [MASTER_CNOC_DC_NOC] = &qnm_cnoc_dc_noc, 1635 [SLAVE_LLCC_CFG] = &qhs_llcc, 1636 [SLAVE_GEM_NOC_CFG] = &qns_gemnoc, 1637 }; 1638 1639 static const struct qcom_icc_desc sm8350_dc_noc = { 1640 .nodes = dc_noc_nodes, 1641 .num_nodes = ARRAY_SIZE(dc_noc_nodes), 1642 .bcms = dc_noc_bcms, 1643 .num_bcms = ARRAY_SIZE(dc_noc_bcms), 1644 }; 1645 1646 static struct qcom_icc_bcm * const gem_noc_bcms[] = { 1647 &bcm_sh0, 1648 &bcm_sh2, 1649 &bcm_sh3, 1650 &bcm_sh4, 1651 }; 1652 1653 static struct qcom_icc_node * const gem_noc_nodes[] = { 1654 [MASTER_GPU_TCU] = &alm_gpu_tcu, 1655 [MASTER_SYS_TCU] = &alm_sys_tcu, 1656 [MASTER_APPSS_PROC] = &chm_apps, 1657 [MASTER_COMPUTE_NOC] = &qnm_cmpnoc, 1658 [MASTER_GEM_NOC_CFG] = &qnm_gemnoc_cfg, 1659 [MASTER_GFX3D] = &qnm_gpu, 1660 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, 1661 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, 1662 [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie, 1663 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc, 1664 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, 1665 [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg, 1666 [SLAVE_MCDMA_MS_MPU_CFG] = &qhs_modem_ms_mpu_cfg, 1667 [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc, 1668 [SLAVE_LLCC] = &qns_llcc, 1669 [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie, 1670 [SLAVE_SERVICE_GEM_NOC_1] = &srvc_even_gemnoc, 1671 [SLAVE_SERVICE_GEM_NOC_2] = &srvc_odd_gemnoc, 1672 [SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc, 1673 }; 1674 1675 static const struct qcom_icc_desc sm8350_gem_noc = { 1676 .nodes = gem_noc_nodes, 1677 .num_nodes = ARRAY_SIZE(gem_noc_nodes), 1678 .bcms = gem_noc_bcms, 1679 .num_bcms = ARRAY_SIZE(gem_noc_bcms), 1680 }; 1681 1682 static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = { 1683 }; 1684 1685 static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { 1686 [MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc, 1687 [SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core, 1688 [SLAVE_LPASS_LPI_CFG] = &qhs_lpass_lpi, 1689 [SLAVE_LPASS_MPU_CFG] = &qhs_lpass_mpu, 1690 [SLAVE_LPASS_TOP_CFG] = &qhs_lpass_top, 1691 [SLAVE_SERVICES_LPASS_AML_NOC] = &srvc_niu_aml_noc, 1692 [SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc, 1693 }; 1694 1695 static const struct qcom_icc_desc sm8350_lpass_ag_noc = { 1696 .nodes = lpass_ag_noc_nodes, 1697 .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), 1698 .bcms = lpass_ag_noc_bcms, 1699 .num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms), 1700 }; 1701 1702 static struct qcom_icc_bcm * const mc_virt_bcms[] = { 1703 &bcm_acv, 1704 &bcm_mc0, 1705 }; 1706 1707 static struct qcom_icc_node * const mc_virt_nodes[] = { 1708 [MASTER_LLCC] = &llcc_mc, 1709 [SLAVE_EBI1] = &ebi, 1710 }; 1711 1712 static const struct qcom_icc_desc sm8350_mc_virt = { 1713 .nodes = mc_virt_nodes, 1714 .num_nodes = ARRAY_SIZE(mc_virt_nodes), 1715 .bcms = mc_virt_bcms, 1716 .num_bcms = ARRAY_SIZE(mc_virt_bcms), 1717 }; 1718 1719 static struct qcom_icc_bcm * const mmss_noc_bcms[] = { 1720 &bcm_mm0, 1721 &bcm_mm1, 1722 &bcm_mm4, 1723 &bcm_mm5, 1724 }; 1725 1726 static struct qcom_icc_node * const mmss_noc_nodes[] = { 1727 [MASTER_CAMNOC_HF] = &qnm_camnoc_hf, 1728 [MASTER_CAMNOC_ICP] = &qnm_camnoc_icp, 1729 [MASTER_CAMNOC_SF] = &qnm_camnoc_sf, 1730 [MASTER_CNOC_MNOC_CFG] = &qnm_mnoc_cfg, 1731 [MASTER_VIDEO_P0] = &qnm_video0, 1732 [MASTER_VIDEO_P1] = &qnm_video1, 1733 [MASTER_VIDEO_PROC] = &qnm_video_cvp, 1734 [MASTER_MDP0] = &qxm_mdp0, 1735 [MASTER_MDP1] = &qxm_mdp1, 1736 [MASTER_ROTATOR] = &qxm_rot, 1737 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, 1738 [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf, 1739 [SLAVE_SERVICE_MNOC] = &srvc_mnoc, 1740 }; 1741 1742 static const struct qcom_icc_desc sm8350_mmss_noc = { 1743 .nodes = mmss_noc_nodes, 1744 .num_nodes = ARRAY_SIZE(mmss_noc_nodes), 1745 .bcms = mmss_noc_bcms, 1746 .num_bcms = ARRAY_SIZE(mmss_noc_bcms), 1747 }; 1748 1749 static struct qcom_icc_bcm * const nsp_noc_bcms[] = { 1750 &bcm_co0, 1751 &bcm_co3, 1752 }; 1753 1754 static struct qcom_icc_node * const nsp_noc_nodes[] = { 1755 [MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config, 1756 [MASTER_CDSP_PROC] = &qxm_nsp, 1757 [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc, 1758 [SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc, 1759 }; 1760 1761 static const struct qcom_icc_desc sm8350_compute_noc = { 1762 .nodes = nsp_noc_nodes, 1763 .num_nodes = ARRAY_SIZE(nsp_noc_nodes), 1764 .bcms = nsp_noc_bcms, 1765 .num_bcms = ARRAY_SIZE(nsp_noc_bcms), 1766 }; 1767 1768 static struct qcom_icc_bcm * const system_noc_bcms[] = { 1769 &bcm_sn0, 1770 &bcm_sn2, 1771 &bcm_sn7, 1772 &bcm_sn8, 1773 }; 1774 1775 static struct qcom_icc_node * const system_noc_nodes[] = { 1776 [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc, 1777 [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc, 1778 [MASTER_SNOC_CFG] = &qnm_snoc_cfg, 1779 [MASTER_PIMEM] = &qxm_pimem, 1780 [MASTER_GIC] = &xm_gic, 1781 [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc, 1782 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, 1783 [SLAVE_SERVICE_SNOC] = &srvc_snoc, 1784 }; 1785 1786 static const struct qcom_icc_desc sm8350_system_noc = { 1787 .nodes = system_noc_nodes, 1788 .num_nodes = ARRAY_SIZE(system_noc_nodes), 1789 .bcms = system_noc_bcms, 1790 .num_bcms = ARRAY_SIZE(system_noc_bcms), 1791 }; 1792 1793 static const struct of_device_id qnoc_of_match[] = { 1794 { .compatible = "qcom,sm8350-aggre1-noc", .data = &sm8350_aggre1_noc}, 1795 { .compatible = "qcom,sm8350-aggre2-noc", .data = &sm8350_aggre2_noc}, 1796 { .compatible = "qcom,sm8350-config-noc", .data = &sm8350_config_noc}, 1797 { .compatible = "qcom,sm8350-dc-noc", .data = &sm8350_dc_noc}, 1798 { .compatible = "qcom,sm8350-gem-noc", .data = &sm8350_gem_noc}, 1799 { .compatible = "qcom,sm8350-lpass-ag-noc", .data = &sm8350_lpass_ag_noc}, 1800 { .compatible = "qcom,sm8350-mc-virt", .data = &sm8350_mc_virt}, 1801 { .compatible = "qcom,sm8350-mmss-noc", .data = &sm8350_mmss_noc}, 1802 { .compatible = "qcom,sm8350-compute-noc", .data = &sm8350_compute_noc}, 1803 { .compatible = "qcom,sm8350-system-noc", .data = &sm8350_system_noc}, 1804 { } 1805 }; 1806 MODULE_DEVICE_TABLE(of, qnoc_of_match); 1807 1808 static struct platform_driver qnoc_driver = { 1809 .probe = qcom_icc_rpmh_probe, 1810 .remove_new = qcom_icc_rpmh_remove, 1811 .driver = { 1812 .name = "qnoc-sm8350", 1813 .of_match_table = qnoc_of_match, 1814 .sync_state = icc_sync_state, 1815 }, 1816 }; 1817 module_platform_driver(qnoc_driver); 1818 1819 MODULE_DESCRIPTION("SM8350 NoC driver"); 1820 MODULE_LICENSE("GPL v2"); 1821